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MIPS: Allow storing pgd in C0_CONTEXT for MIPSr6
[linux-2.6-block.git] / arch / mips / mm / tlbex.c
CommitLineData
1da177e4
LT		 1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Synthesize TLB refill handlers at runtime.
7 *
70342287
RB		 8 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
9 * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki
41c594ab 10 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
fd062c84 11 * Copyright (C) 2008, 2009 Cavium Networks, Inc.
113c62d9 12 * Copyright (C) 2011 MIPS Technologies, Inc.
41c594ab
RB		 13 *
14 * ... and the days got worse and worse and now you see
92a76f6d 15 * I've gone completely out of my mind.
41c594ab
RB		 16 *
17 * They're coming to take me a away haha
18 * they're coming to take me a away hoho hihi haha
19 * to the funny farm where code is beautiful all the time ...
20 *
21 * (Condolences to Napoleon XIV)
1da177e4
LT		 22 */
23
95affdda 24#include <linux/bug.h>
ccf01516 25#include <linux/export.h>
1da177e4
LT		 26#include <linux/kernel.h>
27#include <linux/types.h>
631330f5 28#include <linux/smp.h>
1da177e4 29#include <linux/string.h>
3d8bfdd0 30#include <linux/cache.h>
1da177e4 31
3d8bfdd0 32#include <asm/cacheflush.h>
69f24d17 33#include <asm/cpu-type.h>
3d8bfdd0 34#include <asm/pgtable.h>
1da177e4 35#include <asm/war.h>
3482d713 36#include <asm/uasm.h>
b81947c6 37#include <asm/setup.h>
722b4544 38#include <asm/tlbex.h>
e30ec452 39
a2d25e63 40static int mips_xpa_disabled;
c5b36783
SH		 41
42static int __init xpa_disable(char *s)
43{
44 mips_xpa_disabled = 1;
45
46 return 1;
47}
48
49__setup("noxpa", xpa_disable);
50
1ec56329
DD		 51/*
52 * TLB load/store/modify handlers.
53 *
54 * Only the fastpath gets synthesized at runtime, the slowpath for
55 * do_page_fault remains normal asm.
56 */
57extern void tlb_do_page_fault_0(void);
58extern void tlb_do_page_fault_1(void);
59
bf28607f
DD		 60struct work_registers {
61 int r1;
62 int r2;
63 int r3;
64};
65
66struct tlb_reg_save {
67 unsigned long a;
68 unsigned long b;
69} ____cacheline_aligned_in_smp;
70
71static struct tlb_reg_save handler_reg_save[NR_CPUS];
1ec56329 72
aeffdbba 73static inline int r45k_bvahwbug(void)
1da177e4
LT		 74{
75 /* XXX: We should probe for the presence of this bug, but we don't. */
76 return 0;
77}
78
aeffdbba 79static inline int r4k_250MHZhwbug(void)
1da177e4
LT		 80{
81 /* XXX: We should probe for the presence of this bug, but we don't. */
82 return 0;
83}
84
aeffdbba 85static inline int __maybe_unused bcm1250_m3_war(void)
1da177e4
LT		 86{
87 return BCM1250_M3_WAR;
88}
89
aeffdbba 90static inline int __maybe_unused r10000_llsc_war(void)
1da177e4
LT		 91{
92 return R10000_LLSC_WAR;
93}
94
cc33ae43
DD		 95static int use_bbit_insns(void)
96{
97 switch (current_cpu_type()) {
98 case CPU_CAVIUM_OCTEON:
99 case CPU_CAVIUM_OCTEON_PLUS:
100 case CPU_CAVIUM_OCTEON2:
4723b20a 101 case CPU_CAVIUM_OCTEON3:
cc33ae43
DD		 102 return 1;
103 default:
104 return 0;
105 }
106}
107
2c8c53e2
DD		 108static int use_lwx_insns(void)
109{
110 switch (current_cpu_type()) {
111 case CPU_CAVIUM_OCTEON2:
4723b20a 112 case CPU_CAVIUM_OCTEON3:
2c8c53e2
DD		 113 return 1;
114 default:
115 return 0;
116 }
117}
118#if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \
119 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
120static bool scratchpad_available(void)
121{
122 return true;
123}
124static int scratchpad_offset(int i)
125{
126 /*
127 * CVMSEG starts at address -32768 and extends for
128 * CAVIUM_OCTEON_CVMSEG_SIZE 128 byte cache lines.
129 */
130 i += 1; /* Kernel use starts at the top and works down. */
131 return CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128 - (8 * i) - 32768;
132}
133#else
134static bool scratchpad_available(void)
135{
136 return false;
137}
138static int scratchpad_offset(int i)
139{
140 BUG();
e1c87d2a
DD		 141 /* Really unreachable, but evidently some GCC want this. */
142 return 0;
2c8c53e2
DD		 143}
144#endif
8df5beac
MR		 145/*
146 * Found by experiment: At least some revisions of the 4kc throw under
147 * some circumstances a machine check exception, triggered by invalid
148 * values in the index register. Delaying the tlbp instruction until
149 * after the next branch, plus adding an additional nop in front of
150 * tlbwi/tlbwr avoids the invalid index register values. Nobody knows
151 * why; it's not an issue caused by the core RTL.
152 *
153 */
078a55fc 154static int m4kc_tlbp_war(void)
8df5beac
MR		 155{
156 return (current_cpu_data.processor_id & 0xffff00) ==
157 (PRID_COMP_MIPS | PRID_IMP_4KC);
158}
159
e30ec452 160/* Handle labels (which must be positive integers). */
1da177e4 161enum label_id {
e30ec452 162 label_second_part = 1,
1da177e4
LT		 163 label_leave,
164 label_vmalloc,
165 label_vmalloc_done,
02a54177
RB		 166 label_tlbw_hazard_0,
167 label_split = label_tlbw_hazard_0 + 8,
6dd9344c
DD		 168 label_tlbl_goaround1,
169 label_tlbl_goaround2,
1da177e4
LT		 170 label_nopage_tlbl,
171 label_nopage_tlbs,
172 label_nopage_tlbm,
173 label_smp_pgtable_change,
174 label_r3000_write_probe_fail,
1ec56329 175 label_large_segbits_fault,
aa1762f4 176#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
fd062c84
DD		 177 label_tlb_huge_update,
178#endif
1da177e4
LT		 179};
180
e30ec452
TS		 181UASM_L_LA(_second_part)
182UASM_L_LA(_leave)
e30ec452
TS		 183UASM_L_LA(_vmalloc)
184UASM_L_LA(_vmalloc_done)
02a54177 185/* _tlbw_hazard_x is handled differently. */
e30ec452 186UASM_L_LA(_split)
6dd9344c
DD		 187UASM_L_LA(_tlbl_goaround1)
188UASM_L_LA(_tlbl_goaround2)
e30ec452
TS		 189UASM_L_LA(_nopage_tlbl)
190UASM_L_LA(_nopage_tlbs)
191UASM_L_LA(_nopage_tlbm)
192UASM_L_LA(_smp_pgtable_change)
193UASM_L_LA(_r3000_write_probe_fail)
1ec56329 194UASM_L_LA(_large_segbits_fault)
aa1762f4 195#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
fd062c84
DD		 196UASM_L_LA(_tlb_huge_update)
197#endif
656be92f 198
078a55fc 199static int hazard_instance;
02a54177 200
078a55fc 201static void uasm_bgezl_hazard(u32 **p, struct uasm_reloc **r, int instance)
02a54177
RB		 202{
203 switch (instance) {
204 case 0 ... 7:
205 uasm_il_bgezl(p, r, 0, label_tlbw_hazard_0 + instance);
206 return;
207 default:
208 BUG();
209 }
210}
211
078a55fc 212static void uasm_bgezl_label(struct uasm_label **l, u32 **p, int instance)
02a54177
RB		 213{
214 switch (instance) {
215 case 0 ... 7:
216 uasm_build_label(l, *p, label_tlbw_hazard_0 + instance);
217 break;
218 default:
219 BUG();
220 }
221}
222
92b1e6a6 223/*
a2c763e0
RB		 224 * pgtable bits are assigned dynamically depending on processor feature
225 * and statically based on kernel configuration. This spits out the actual
70342287 226 * values the kernel is using. Required to make sense from disassembled
a2c763e0 227 * TLB exception handlers.
92b1e6a6 228 */
a2c763e0
RB		 229static void output_pgtable_bits_defines(void)
230{
231#define pr_define(fmt, ...) \
232 pr_debug("#define " fmt, ##__VA_ARGS__)
233
234 pr_debug("#include <asm/asm.h>\n");
235 pr_debug("#include <asm/regdef.h>\n");
236 pr_debug("\n");
237
238 pr_define("_PAGE_PRESENT_SHIFT %d\n", _PAGE_PRESENT_SHIFT);
780602d7 239 pr_define("_PAGE_NO_READ_SHIFT %d\n", _PAGE_NO_READ_SHIFT);
a2c763e0
RB		 240 pr_define("_PAGE_WRITE_SHIFT %d\n", _PAGE_WRITE_SHIFT);
241 pr_define("_PAGE_ACCESSED_SHIFT %d\n", _PAGE_ACCESSED_SHIFT);
242 pr_define("_PAGE_MODIFIED_SHIFT %d\n", _PAGE_MODIFIED_SHIFT);
970d032f 243#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
a2c763e0
RB		 244 pr_define("_PAGE_HUGE_SHIFT %d\n", _PAGE_HUGE_SHIFT);
245#endif
a2c763e0 246#ifdef _PAGE_NO_EXEC_SHIFT
780602d7 247 if (cpu_has_rixi)
a2c763e0 248 pr_define("_PAGE_NO_EXEC_SHIFT %d\n", _PAGE_NO_EXEC_SHIFT);
be0c37c9 249#endif
a2c763e0
RB		 250 pr_define("_PAGE_GLOBAL_SHIFT %d\n", _PAGE_GLOBAL_SHIFT);
251 pr_define("_PAGE_VALID_SHIFT %d\n", _PAGE_VALID_SHIFT);
252 pr_define("_PAGE_DIRTY_SHIFT %d\n", _PAGE_DIRTY_SHIFT);
253 pr_define("_PFN_SHIFT %d\n", _PFN_SHIFT);
254 pr_debug("\n");
255}
256
257static inline void dump_handler(const char *symbol, const u32 *handler, int count)
92b1e6a6
FBH		 258{
259 int i;
260
a2c763e0
RB		 261 pr_debug("LEAF(%s)\n", symbol);
262
92b1e6a6
FBH		 263 pr_debug("\t.set push\n");
264 pr_debug("\t.set noreorder\n");
265
266 for (i = 0; i < count; i++)
a2c763e0 267 pr_debug("\t.word\t0x%08x\t\t# %p\n", handler[i], &handler[i]);
92b1e6a6 268
a2c763e0
RB		 269 pr_debug("\t.set\tpop\n");
270
271 pr_debug("\tEND(%s)\n", symbol);
92b1e6a6
FBH		 272}
273
1da177e4
LT		 274/* The only general purpose registers allowed in TLB handlers. */
275#define K0 26
276#define K1 27
277
278/* Some CP0 registers */
41c594ab
RB		 279#define C0_INDEX 0, 0
280#define C0_ENTRYLO0 2, 0
281#define C0_TCBIND 2, 2
282#define C0_ENTRYLO1 3, 0
283#define C0_CONTEXT 4, 0
fd062c84 284#define C0_PAGEMASK 5, 0
380cd582
HC		 285#define C0_PWBASE 5, 5
286#define C0_PWFIELD 5, 6
287#define C0_PWSIZE 5, 7
288#define C0_PWCTL 6, 6
41c594ab 289#define C0_BADVADDR 8, 0
380cd582 290#define C0_PGD 9, 7
41c594ab
RB		 291#define C0_ENTRYHI 10, 0
292#define C0_EPC 14, 0
293#define C0_XCONTEXT 20, 0
1da177e4 294
875d43e7 295#ifdef CONFIG_64BIT
e30ec452 296# define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT)
1da177e4 297#else
e30ec452 298# define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT)
1da177e4
LT		 299#endif
300
301/* The worst case length of the handler is around 18 instructions for
302 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs.
303 * Maximum space available is 32 instructions for R3000 and 64
304 * instructions for R4000.
305 *
306 * We deliberately chose a buffer size of 128, so we won't scribble
307 * over anything important on overflow before we panic.
308 */
078a55fc 309static u32 tlb_handler[128];
1da177e4
LT		 310
311/* simply assume worst case size for labels and relocs */
078a55fc
PG		 312static struct uasm_label labels[128];
313static struct uasm_reloc relocs[128];
1da177e4 314
078a55fc 315static int check_for_high_segbits;
00bf1c69 316static bool fill_includes_sw_bits;
3d8bfdd0 317
078a55fc 318static unsigned int kscratch_used_mask;
3d8bfdd0 319
7777b939
J		 320static inline int __maybe_unused c0_kscratch(void)
321{
322 switch (current_cpu_type()) {
323 case CPU_XLP:
324 case CPU_XLR:
325 return 22;
326 default:
327 return 31;
328 }
329}
330
078a55fc 331static int allocate_kscratch(void)
3d8bfdd0
DD		 332{
333 int r;
334 unsigned int a = cpu_data[0].kscratch_mask & ~kscratch_used_mask;
335
336 r = ffs(a);
337
338 if (r == 0)
339 return -1;
340
341 r--; /* make it zero based */
342
343 kscratch_used_mask |= (1 << r);
344
345 return r;
346}
347
078a55fc 348static int scratch_reg;
722b4544
JH		 349int pgd_reg;
350EXPORT_SYMBOL_GPL(pgd_reg);
2c8c53e2
DD		 351enum vmalloc64_mode {not_refill, refill_scratch, refill_noscratch};
352
078a55fc 353static struct work_registers build_get_work_registers(u32 **p)
bf28607f
DD		 354{
355 struct work_registers r;
356
0e6ecc1a 357 if (scratch_reg >= 0) {
bf28607f 358 /* Save in CPU local C0_KScratch? */
7777b939 359 UASM_i_MTC0(p, 1, c0_kscratch(), scratch_reg);
bf28607f
DD		 360 r.r1 = K0;
361 r.r2 = K1;
362 r.r3 = 1;
363 return r;
364 }
365
366 if (num_possible_cpus() > 1) {
bf28607f 367 /* Get smp_processor_id */
c2377a42
J		 368 UASM_i_CPUID_MFC0(p, K0, SMP_CPUID_REG);
369 UASM_i_SRL_SAFE(p, K0, K0, SMP_CPUID_REGSHIFT);
bf28607f
DD		 370
371 /* handler_reg_save index in K0 */
372 UASM_i_SLL(p, K0, K0, ilog2(sizeof(struct tlb_reg_save)));
373
374 UASM_i_LA(p, K1, (long)&handler_reg_save);
375 UASM_i_ADDU(p, K0, K0, K1);
376 } else {
377 UASM_i_LA(p, K0, (long)&handler_reg_save);
378 }
379 /* K0 now points to save area, save $1 and $2 */
380 UASM_i_SW(p, 1, offsetof(struct tlb_reg_save, a), K0);
381 UASM_i_SW(p, 2, offsetof(struct tlb_reg_save, b), K0);
382
383 r.r1 = K1;
384 r.r2 = 1;
385 r.r3 = 2;
386 return r;
387}
388
078a55fc 389static void build_restore_work_registers(u32 **p)
bf28607f 390{
0e6ecc1a 391 if (scratch_reg >= 0) {
7777b939 392 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg);
bf28607f
DD		 393 return;
394 }
395 /* K0 already points to save area, restore $1 and $2 */
396 UASM_i_LW(p, 1, offsetof(struct tlb_reg_save, a), K0);
397 UASM_i_LW(p, 2, offsetof(struct tlb_reg_save, b), K0);
398}
399
2c8c53e2 400#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
3d8bfdd0 401
82622284
DD		 402/*
403 * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current,
404 * we cannot do r3000 under these circumstances.
3d8bfdd0
DD		 405 *
406 * Declare pgd_current here instead of including mmu_context.h to avoid type
407 * conflicts for tlbmiss_handler_setup_pgd
82622284 408 */
3d8bfdd0 409extern unsigned long pgd_current[];
82622284 410
1da177e4
LT		 411/*
412 * The R3000 TLB handler is simple.
413 */
078a55fc 414static void build_r3000_tlb_refill_handler(void)
1da177e4
LT		 415{
416 long pgdc = (long)pgd_current;
417 u32 *p;
418
419 memset(tlb_handler, 0, sizeof(tlb_handler));
420 p = tlb_handler;
421
e30ec452
TS		 422 uasm_i_mfc0(&p, K0, C0_BADVADDR);
423 uasm_i_lui(&p, K1, uasm_rel_hi(pgdc)); /* cp0 delay */
424 uasm_i_lw(&p, K1, uasm_rel_lo(pgdc), K1);
425 uasm_i_srl(&p, K0, K0, 22); /* load delay */
426 uasm_i_sll(&p, K0, K0, 2);
427 uasm_i_addu(&p, K1, K1, K0);
428 uasm_i_mfc0(&p, K0, C0_CONTEXT);
429 uasm_i_lw(&p, K1, 0, K1); /* cp0 delay */
430 uasm_i_andi(&p, K0, K0, 0xffc); /* load delay */
431 uasm_i_addu(&p, K1, K1, K0);
432 uasm_i_lw(&p, K0, 0, K1);
433 uasm_i_nop(&p); /* load delay */
434 uasm_i_mtc0(&p, K0, C0_ENTRYLO0);
435 uasm_i_mfc0(&p, K1, C0_EPC); /* cp0 delay */
436 uasm_i_tlbwr(&p); /* cp0 delay */
437 uasm_i_jr(&p, K1);
438 uasm_i_rfe(&p); /* branch delay */
1da177e4
LT		 439
440 if (p > tlb_handler + 32)
441 panic("TLB refill handler space exceeded");
442
e30ec452
TS		 443 pr_debug("Wrote TLB refill handler (%u instructions).\n",
444 (unsigned int)(p - tlb_handler));
1da177e4 445
91b05e67 446 memcpy((void *)ebase, tlb_handler, 0x80);
1062080a 447 local_flush_icache_range(ebase, ebase + 0x80);
92b1e6a6 448
a2c763e0 449 dump_handler("r3000_tlb_refill", (u32 *)ebase, 32);
1da177e4 450}
82622284 451#endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
1da177e4
LT		 452
453/*
454 * The R4000 TLB handler is much more complicated. We have two
455 * consecutive handler areas with 32 instructions space each.
456 * Since they aren't used at the same time, we can overflow in the
457 * other one.To keep things simple, we first assume linear space,
458 * then we relocate it to the final handler layout as needed.
459 */
078a55fc 460static u32 final_handler[64];
1da177e4
LT		 461
462/*
463 * Hazards
464 *
465 * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0:
466 * 2. A timing hazard exists for the TLBP instruction.
467 *
70342287
RB		 468 * stalling_instruction
469 * TLBP
1da177e4
LT		 470 *
471 * The JTLB is being read for the TLBP throughout the stall generated by the
472 * previous instruction. This is not really correct as the stalling instruction
473 * can modify the address used to access the JTLB. The failure symptom is that
474 * the TLBP instruction will use an address created for the stalling instruction
475 * and not the address held in C0_ENHI and thus report the wrong results.
476 *
477 * The software work-around is to not allow the instruction preceding the TLBP
478 * to stall - make it an NOP or some other instruction guaranteed not to stall.
479 *
70342287 480 * Errata 2 will not be fixed. This errata is also on the R5000.
1da177e4
LT		 481 *
482 * As if we MIPS hackers wouldn't know how to nop pipelines happy ...
483 */
078a55fc 484static void __maybe_unused build_tlb_probe_entry(u32 **p)
1da177e4 485{
10cc3529 486 switch (current_cpu_type()) {
326e2e1a 487 /* Found by experiment: R4600 v2.0/R4700 needs this, too. */
f5b4d956 488 case CPU_R4600:
326e2e1a 489 case CPU_R4700:
1da177e4 490 case CPU_R5000:
1da177e4 491 case CPU_NEVADA:
e30ec452
TS		 492 uasm_i_nop(p);
493 uasm_i_tlbp(p);
1da177e4
LT		 494 break;
495
496 default:
e30ec452 497 uasm_i_tlbp(p);
1da177e4
LT		 498 break;
499 }
500}
501
722b4544
JH		 502void build_tlb_write_entry(u32 **p, struct uasm_label **l,
503 struct uasm_reloc **r,
504 enum tlb_write_entry wmode)
1da177e4
LT		 505{
506 void(*tlbw)(u32 **) = NULL;
507
508 switch (wmode) {
e30ec452
TS		 509 case tlb_random: tlbw = uasm_i_tlbwr; break;
510 case tlb_indexed: tlbw = uasm_i_tlbwi; break;
1da177e4
LT		 511 }
512
9eaffa84
RB		 513 if (cpu_has_mips_r2_r6) {
514 if (cpu_has_mips_r2_exec_hazard)
41f0e4d0 515 uasm_i_ehb(p);
161548bf
RB		 516 tlbw(p);
517 return;
518 }
519
10cc3529 520 switch (current_cpu_type()) {
1da177e4
LT		 521 case CPU_R4000PC:
522 case CPU_R4000SC:
523 case CPU_R4000MC:
524 case CPU_R4400PC:
525 case CPU_R4400SC:
526 case CPU_R4400MC:
527 /*
528 * This branch uses up a mtc0 hazard nop slot and saves
529 * two nops after the tlbw instruction.
530 */
02a54177 531 uasm_bgezl_hazard(p, r, hazard_instance);
1da177e4 532 tlbw(p);
02a54177
RB		 533 uasm_bgezl_label(l, p, hazard_instance);
534 hazard_instance++;
e30ec452 535 uasm_i_nop(p);
1da177e4
LT		 536 break;
537
538 case CPU_R4600:
539 case CPU_R4700:
e30ec452 540 uasm_i_nop(p);
2c93e12c 541 tlbw(p);
e30ec452 542 uasm_i_nop(p);
2c93e12c
MR		 543 break;
544
359187d6 545 case CPU_R5000:
359187d6
RB		 546 case CPU_NEVADA:
547 uasm_i_nop(p); /* QED specifies 2 nops hazard */
548 uasm_i_nop(p); /* QED specifies 2 nops hazard */
549 tlbw(p);
550 break;
551
2c93e12c 552 case CPU_R4300:
1da177e4
LT		 553 case CPU_5KC:
554 case CPU_TX49XX:
bdf21b18 555 case CPU_PR4450:
efa0f81c 556 case CPU_XLR:
e30ec452 557 uasm_i_nop(p);
1da177e4
LT		 558 tlbw(p);
559 break;
560
561 case CPU_R10000:
562 case CPU_R12000:
44d921b2 563 case CPU_R14000:
30577391 564 case CPU_R16000:
1da177e4 565 case CPU_4KC:
b1ec4c8e 566 case CPU_4KEC:
113c62d9 567 case CPU_M14KC:
f8fa4811 568 case CPU_M14KEC:
1da177e4 569 case CPU_SB1:
93ce2f52 570 case CPU_SB1A:
1da177e4
LT		 571 case CPU_4KSC:
572 case CPU_20KC:
573 case CPU_25KF:
602977b0
KC		 574 case CPU_BMIPS32:
575 case CPU_BMIPS3300:
576 case CPU_BMIPS4350:
577 case CPU_BMIPS4380:
578 case CPU_BMIPS5000:
2a21c730 579 case CPU_LOONGSON2:
c579d310 580 case CPU_LOONGSON3:
a644b277 581 case CPU_R5500:
8df5beac 582 if (m4kc_tlbp_war())
e30ec452 583 uasm_i_nop(p);
2f794d09 584 case CPU_ALCHEMY:
1da177e4
LT		 585 tlbw(p);
586 break;
587
1da177e4 588 case CPU_RM7000:
e30ec452
TS		 589 uasm_i_nop(p);
590 uasm_i_nop(p);
591 uasm_i_nop(p);
592 uasm_i_nop(p);
1da177e4
LT		 593 tlbw(p);
594 break;
595
1da177e4
LT		 596 case CPU_VR4111:
597 case CPU_VR4121:
598 case CPU_VR4122:
599 case CPU_VR4181:
600 case CPU_VR4181A:
e30ec452
TS		 601 uasm_i_nop(p);
602 uasm_i_nop(p);
1da177e4 603 tlbw(p);
e30ec452
TS		 604 uasm_i_nop(p);
605 uasm_i_nop(p);
1da177e4
LT		 606 break;
607
608 case CPU_VR4131:
609 case CPU_VR4133:
7623debf 610 case CPU_R5432:
e30ec452
TS		 611 uasm_i_nop(p);
612 uasm_i_nop(p);
1da177e4
LT		 613 tlbw(p);
614 break;
615
83ccf69d
LPC		 616 case CPU_JZRISC:
617 tlbw(p);
618 uasm_i_nop(p);
619 break;
620
1da177e4
LT		 621 default:
622 panic("No TLB refill handler yet (CPU type: %d)",
d7b12056 623 current_cpu_type());
1da177e4
LT		 624 break;
625 }
626}
722b4544 627EXPORT_SYMBOL_GPL(build_tlb_write_entry);
1da177e4 628
078a55fc
PG		 629static __maybe_unused void build_convert_pte_to_entrylo(u32 **p,
630 unsigned int reg)
fd062c84 631{
2caa89b4
PB		 632 if (_PAGE_GLOBAL_SHIFT == 0) {
633 /* pte_t is already in EntryLo format */
634 return;
635 }
636
00bf1c69
PB		 637 if (cpu_has_rixi && _PAGE_NO_EXEC) {
638 if (fill_includes_sw_bits) {
639 UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL));
640 } else {
641 UASM_i_SRL(p, reg, reg, ilog2(_PAGE_NO_EXEC));
642 UASM_i_ROTR(p, reg, reg,
643 ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
644 }
6dd9344c 645 } else {
34adb28d 646#ifdef CONFIG_PHYS_ADDR_T_64BIT
3be6022c 647 uasm_i_dsrl_safe(p, reg, reg, ilog2(_PAGE_GLOBAL));
6dd9344c
DD		 648#else
649 UASM_i_SRL(p, reg, reg, ilog2(_PAGE_GLOBAL));
650#endif
651 }
652}
fd062c84 653
aa1762f4 654#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
fd062c84 655
078a55fc
PG		 656static void build_restore_pagemask(u32 **p, struct uasm_reloc **r,
657 unsigned int tmp, enum label_id lid,
658 int restore_scratch)
6dd9344c 659{
2c8c53e2
DD		 660 if (restore_scratch) {
661 /* Reset default page size */
662 if (PM_DEFAULT_MASK >> 16) {
663 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16);
664 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff);
665 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
666 uasm_il_b(p, r, lid);
667 } else if (PM_DEFAULT_MASK) {
668 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK);
669 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
670 uasm_il_b(p, r, lid);
671 } else {
672 uasm_i_mtc0(p, 0, C0_PAGEMASK);
673 uasm_il_b(p, r, lid);
674 }
0e6ecc1a 675 if (scratch_reg >= 0)
7777b939 676 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg);
2c8c53e2
DD		 677 else
678 UASM_i_LW(p, 1, scratchpad_offset(0), 0);
fd062c84 679 } else {
2c8c53e2
DD		 680 /* Reset default page size */
681 if (PM_DEFAULT_MASK >> 16) {
682 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16);
683 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff);
684 uasm_il_b(p, r, lid);
685 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
686 } else if (PM_DEFAULT_MASK) {
687 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK);
688 uasm_il_b(p, r, lid);
689 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
690 } else {
691 uasm_il_b(p, r, lid);
692 uasm_i_mtc0(p, 0, C0_PAGEMASK);
693 }
fd062c84
DD		 694 }
695}
696
078a55fc
PG		 697static void build_huge_tlb_write_entry(u32 **p, struct uasm_label **l,
698 struct uasm_reloc **r,
699 unsigned int tmp,
700 enum tlb_write_entry wmode,
701 int restore_scratch)
6dd9344c
DD		 702{
703 /* Set huge page tlb entry size */
704 uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16);
705 uasm_i_ori(p, tmp, tmp, PM_HUGE_MASK & 0xffff);
706 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
707
708 build_tlb_write_entry(p, l, r, wmode);
709
2c8c53e2 710 build_restore_pagemask(p, r, tmp, label_leave, restore_scratch);
6dd9344c
DD		 711}
712
fd062c84
DD		 713/*
714 * Check if Huge PTE is present, if so then jump to LABEL.
715 */
078a55fc 716static void
fd062c84 717build_is_huge_pte(u32 **p, struct uasm_reloc **r, unsigned int tmp,
078a55fc 718 unsigned int pmd, int lid)
fd062c84
DD		 719{
720 UASM_i_LW(p, tmp, 0, pmd);
cc33ae43
DD		 721 if (use_bbit_insns()) {
722 uasm_il_bbit1(p, r, tmp, ilog2(_PAGE_HUGE), lid);
723 } else {
724 uasm_i_andi(p, tmp, tmp, _PAGE_HUGE);
725 uasm_il_bnez(p, r, tmp, lid);
726 }
fd062c84
DD		 727}
728
078a55fc
PG		 729static void build_huge_update_entries(u32 **p, unsigned int pte,
730 unsigned int tmp)
fd062c84
DD		 731{
732 int small_sequence;
733
734 /*
735 * A huge PTE describes an area the size of the
736 * configured huge page size. This is twice the
737 * of the large TLB entry size we intend to use.
738 * A TLB entry half the size of the configured
739 * huge page size is configured into entrylo0
740 * and entrylo1 to cover the contiguous huge PTE
741 * address space.
742 */
743 small_sequence = (HPAGE_SIZE >> 7) < 0x10000;
744
70342287 745 /* We can clobber tmp. It isn't used after this.*/
fd062c84
DD		 746 if (!small_sequence)
747 uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16));
748
6dd9344c 749 build_convert_pte_to_entrylo(p, pte);
9b8c3891 750 UASM_i_MTC0(p, pte, C0_ENTRYLO0); /* load it */
fd062c84
DD		 751 /* convert to entrylo1 */
752 if (small_sequence)
753 UASM_i_ADDIU(p, pte, pte, HPAGE_SIZE >> 7);
754 else
755 UASM_i_ADDU(p, pte, pte, tmp);
756
9b8c3891 757 UASM_i_MTC0(p, pte, C0_ENTRYLO1); /* load it */
fd062c84
DD		 758}
759
078a55fc
PG		 760static void build_huge_handler_tail(u32 **p, struct uasm_reloc **r,
761 struct uasm_label **l,
762 unsigned int pte,
0115f6cb
HC		 763 unsigned int ptr,
764 unsigned int flush)
fd062c84
DD		 765{
766#ifdef CONFIG_SMP
767 UASM_i_SC(p, pte, 0, ptr);
768 uasm_il_beqz(p, r, pte, label_tlb_huge_update);
769 UASM_i_LW(p, pte, 0, ptr); /* Needed because SC killed our PTE */
770#else
771 UASM_i_SW(p, pte, 0, ptr);
772#endif
0115f6cb
HC		 773 if (cpu_has_ftlb && flush) {
774 BUG_ON(!cpu_has_tlbinv);
775
776 UASM_i_MFC0(p, ptr, C0_ENTRYHI);
777 uasm_i_ori(p, ptr, ptr, MIPS_ENTRYHI_EHINV);
778 UASM_i_MTC0(p, ptr, C0_ENTRYHI);
779 build_tlb_write_entry(p, l, r, tlb_indexed);
780
781 uasm_i_xori(p, ptr, ptr, MIPS_ENTRYHI_EHINV);
782 UASM_i_MTC0(p, ptr, C0_ENTRYHI);
783 build_huge_update_entries(p, pte, ptr);
784 build_huge_tlb_write_entry(p, l, r, pte, tlb_random, 0);
785
786 return;
787 }
788
fd062c84 789 build_huge_update_entries(p, pte, ptr);
2c8c53e2 790 build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed, 0);
fd062c84 791}
aa1762f4 792#endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
fd062c84 793
875d43e7 794#ifdef CONFIG_64BIT
1da177e4
LT		 795/*
796 * TMP and PTR are scratch.
797 * TMP will be clobbered, PTR will hold the pmd entry.
798 */
722b4544
JH		 799void build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
800 unsigned int tmp, unsigned int ptr)
1da177e4 801{
82622284 802#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
1da177e4 803 long pgdc = (long)pgd_current;
82622284 804#endif
1da177e4
LT		 805 /*
806 * The vmalloc handling is not in the hotpath.
807 */
e30ec452 808 uasm_i_dmfc0(p, tmp, C0_BADVADDR);
1ec56329
DD		 809
810 if (check_for_high_segbits) {
811 /*
812 * The kernel currently implicitely assumes that the
813 * MIPS SEGBITS parameter for the processor is
814 * (PGDIR_SHIFT+PGDIR_BITS) or less, and will never
815 * allocate virtual addresses outside the maximum
816 * range for SEGBITS = (PGDIR_SHIFT+PGDIR_BITS). But
817 * that doesn't prevent user code from accessing the
818 * higher xuseg addresses. Here, we make sure that
819 * everything but the lower xuseg addresses goes down
820 * the module_alloc/vmalloc path.
821 */
822 uasm_i_dsrl_safe(p, ptr, tmp, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
823 uasm_il_bnez(p, r, ptr, label_vmalloc);
824 } else {
825 uasm_il_bltz(p, r, tmp, label_vmalloc);
826 }
e30ec452 827 /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */
1da177e4 828
3d8bfdd0
DD		 829 if (pgd_reg != -1) {
830 /* pgd is in pgd_reg */
380cd582
HC		 831 if (cpu_has_ldpte)
832 UASM_i_MFC0(p, ptr, C0_PWBASE);
833 else
834 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg);
3d8bfdd0 835 } else {
f4ae17aa 836#if defined(CONFIG_MIPS_PGD_C0_CONTEXT)
3d8bfdd0
DD		 837 /*
838 * &pgd << 11 stored in CONTEXT [23..63].
839 */
840 UASM_i_MFC0(p, ptr, C0_CONTEXT);
841
842 /* Clear lower 23 bits of context. */
843 uasm_i_dins(p, ptr, 0, 0, 23);
844
70342287 845 /* 1 0 1 0 1 << 6 xkphys cached */
3d8bfdd0
DD		 846 uasm_i_ori(p, ptr, ptr, 0x540);
847 uasm_i_drotr(p, ptr, ptr, 11);
82622284 848#elif defined(CONFIG_SMP)
f4ae17aa
J		 849 UASM_i_CPUID_MFC0(p, ptr, SMP_CPUID_REG);
850 uasm_i_dsrl_safe(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
851 UASM_i_LA_mostly(p, tmp, pgdc);
852 uasm_i_daddu(p, ptr, ptr, tmp);
853 uasm_i_dmfc0(p, tmp, C0_BADVADDR);
854 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
1da177e4 855#else
f4ae17aa
J		 856 UASM_i_LA_mostly(p, ptr, pgdc);
857 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr);
1da177e4 858#endif
f4ae17aa 859 }
1da177e4 860
e30ec452 861 uasm_l_vmalloc_done(l, *p);
242954b5 862
3be6022c
DD		 863 /* get pgd offset in bytes */
864 uasm_i_dsrl_safe(p, tmp, tmp, PGDIR_SHIFT - 3);
e30ec452
TS		 865
866 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3);
867 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */
3377e227
AB		 868#ifndef __PAGETABLE_PUD_FOLDED
869 uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */
870 uasm_i_ld(p, ptr, 0, ptr); /* get pud pointer */
871 uasm_i_dsrl_safe(p, tmp, tmp, PUD_SHIFT - 3); /* get pud offset in bytes */
872 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PUD - 1) << 3);
873 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pud offset */
874#endif
325f8a0a 875#ifndef __PAGETABLE_PMD_FOLDED
e30ec452
TS		 876 uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */
877 uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */
3be6022c 878 uasm_i_dsrl_safe(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */
e30ec452
TS		 879 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3);
880 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */
325f8a0a 881#endif
1da177e4 882}
722b4544 883EXPORT_SYMBOL_GPL(build_get_pmde64);
1da177e4
LT		 884
885/*
886 * BVADDR is the faulting address, PTR is scratch.
887 * PTR will hold the pgd for vmalloc.
888 */
078a55fc 889static void
e30ec452 890build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
1ec56329
DD		 891 unsigned int bvaddr, unsigned int ptr,
892 enum vmalloc64_mode mode)
1da177e4
LT		 893{
894 long swpd = (long)swapper_pg_dir;
1ec56329
DD		 895 int single_insn_swpd;
896 int did_vmalloc_branch = 0;
897
898 single_insn_swpd = uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd);
1da177e4 899
e30ec452 900 uasm_l_vmalloc(l, *p);
1da177e4 901
2c8c53e2 902 if (mode != not_refill && check_for_high_segbits) {
1ec56329
DD		 903 if (single_insn_swpd) {
904 uasm_il_bltz(p, r, bvaddr, label_vmalloc_done);
905 uasm_i_lui(p, ptr, uasm_rel_hi(swpd));
906 did_vmalloc_branch = 1;
907 /* fall through */
908 } else {
909 uasm_il_bgez(p, r, bvaddr, label_large_segbits_fault);
910 }
911 }
912 if (!did_vmalloc_branch) {
2f8f8c04 913 if (single_insn_swpd) {
1ec56329
DD		 914 uasm_il_b(p, r, label_vmalloc_done);
915 uasm_i_lui(p, ptr, uasm_rel_hi(swpd));
916 } else {
917 UASM_i_LA_mostly(p, ptr, swpd);
918 uasm_il_b(p, r, label_vmalloc_done);
919 if (uasm_in_compat_space_p(swpd))
920 uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd));
921 else
922 uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd));
923 }
924 }
2c8c53e2 925 if (mode != not_refill && check_for_high_segbits) {
1ec56329
DD		 926 uasm_l_large_segbits_fault(l, *p);
927 /*
928 * We get here if we are an xsseg address, or if we are
929 * an xuseg address above (PGDIR_SHIFT+PGDIR_BITS) boundary.
930 *
931 * Ignoring xsseg (assume disabled so would generate
932 * (address errors?), the only remaining possibility
933 * is the upper xuseg addresses. On processors with
934 * TLB_SEGBITS <= PGDIR_SHIFT+PGDIR_BITS, these
935 * addresses would have taken an address error. We try
936 * to mimic that here by taking a load/istream page
937 * fault.
938 */
939 UASM_i_LA(p, ptr, (unsigned long)tlb_do_page_fault_0);
940 uasm_i_jr(p, ptr);
2c8c53e2
DD		 941
942 if (mode == refill_scratch) {
0e6ecc1a 943 if (scratch_reg >= 0)
7777b939 944 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg);
2c8c53e2
DD		 945 else
946 UASM_i_LW(p, 1, scratchpad_offset(0), 0);
947 } else {
948 uasm_i_nop(p);
949 }
1da177e4
LT		 950 }
951}
952
875d43e7 953#else /* !CONFIG_64BIT */
1da177e4
LT		 954
955/*
956 * TMP and PTR are scratch.
957 * TMP will be clobbered, PTR will hold the pgd entry.
958 */
722b4544 959void build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
1da177e4 960{
f4ae17aa
J		 961 if (pgd_reg != -1) {
962 /* pgd is in pgd_reg */
963 uasm_i_mfc0(p, ptr, c0_kscratch(), pgd_reg);
964 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
965 } else {
966 long pgdc = (long)pgd_current;
1da177e4 967
f4ae17aa 968 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */
1da177e4 969#ifdef CONFIG_SMP
f4ae17aa
J		 970 uasm_i_mfc0(p, ptr, SMP_CPUID_REG);
971 UASM_i_LA_mostly(p, tmp, pgdc);
972 uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
973 uasm_i_addu(p, ptr, tmp, ptr);
1da177e4 974#else
f4ae17aa 975 UASM_i_LA_mostly(p, ptr, pgdc);
1da177e4 976#endif
f4ae17aa
J		 977 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
978 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
979 }
e30ec452
TS		 980 uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */
981 uasm_i_sll(p, tmp, tmp, PGD_T_LOG2);
982 uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */
1da177e4 983}
722b4544 984EXPORT_SYMBOL_GPL(build_get_pgde32);
1da177e4 985
875d43e7 986#endif /* !CONFIG_64BIT */
1da177e4 987
078a55fc 988static void build_adjust_context(u32 **p, unsigned int ctx)
1da177e4 989{
242954b5 990 unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12;
1da177e4
LT		 991 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1);
992
10cc3529 993 switch (current_cpu_type()) {
1da177e4
LT		 994 case CPU_VR41XX:
995 case CPU_VR4111:
996 case CPU_VR4121:
997 case CPU_VR4122:
998 case CPU_VR4131:
999 case CPU_VR4181:
1000 case CPU_VR4181A:
1001 case CPU_VR4133:
1002 shift += 2;
1003 break;
1004
1005 default:
1006 break;
1007 }
1008
1009 if (shift)
e30ec452
TS		 1010 UASM_i_SRL(p, ctx, ctx, shift);
1011 uasm_i_andi(p, ctx, ctx, mask);
1da177e4
LT		 1012}
1013
722b4544 1014void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr)
1da177e4
LT		 1015{
1016 /*
1017 * Bug workaround for the Nevada. It seems as if under certain
1018 * circumstances the move from cp0_context might produce a
1019 * bogus result when the mfc0 instruction and its consumer are
1020 * in a different cacheline or a load instruction, probably any
1021 * memory reference, is between them.
1022 */
10cc3529 1023 switch (current_cpu_type()) {
1da177e4 1024 case CPU_NEVADA:
e30ec452 1025 UASM_i_LW(p, ptr, 0, ptr);
1da177e4
LT		 1026 GET_CONTEXT(p, tmp); /* get context reg */
1027 break;
1028
1029 default:
1030 GET_CONTEXT(p, tmp); /* get context reg */
e30ec452 1031 UASM_i_LW(p, ptr, 0, ptr);
1da177e4
LT		 1032 break;
1033 }
1034
1035 build_adjust_context(p, tmp);
e30ec452 1036 UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */
1da177e4 1037}
722b4544 1038EXPORT_SYMBOL_GPL(build_get_ptep);
1da177e4 1039
722b4544 1040void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep)
1da177e4 1041{
2caa89b4
PB		 1042 int pte_off_even = 0;
1043 int pte_off_odd = sizeof(pte_t);
7b2cb64f 1044
2caa89b4
PB		 1045#if defined(CONFIG_CPU_MIPS32) && defined(CONFIG_PHYS_ADDR_T_64BIT)
1046 /* The low 32 bits of EntryLo is stored in pte_high */
1047 pte_off_even += offsetof(pte_t, pte_high);
1048 pte_off_odd += offsetof(pte_t, pte_high);
1049#endif
1050
97f2645f 1051 if (IS_ENABLED(CONFIG_XPA)) {
c5b36783 1052 uasm_i_lw(p, tmp, pte_off_even, ptep); /* even pte */
c5b36783 1053 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL));
c5b36783 1054 UASM_i_MTC0(p, tmp, C0_ENTRYLO0);
7b2cb64f 1055
4b6f99d3
JH		 1056 if (cpu_has_xpa && !mips_xpa_disabled) {
1057 uasm_i_lw(p, tmp, 0, ptep);
1058 uasm_i_ext(p, tmp, tmp, 0, 24);
1059 uasm_i_mthc0(p, tmp, C0_ENTRYLO0);
1060 }
f3832196
JH		 1061
1062 uasm_i_lw(p, tmp, pte_off_odd, ptep); /* odd pte */
1063 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL));
1064 UASM_i_MTC0(p, tmp, C0_ENTRYLO1);
1065
4b6f99d3
JH		 1066 if (cpu_has_xpa && !mips_xpa_disabled) {
1067 uasm_i_lw(p, tmp, sizeof(pte_t), ptep);
1068 uasm_i_ext(p, tmp, tmp, 0, 24);
1069 uasm_i_mthc0(p, tmp, C0_ENTRYLO1);
1070 }
7b2cb64f
PB		 1071 return;
1072 }
1073
2caa89b4
PB		 1074 UASM_i_LW(p, tmp, pte_off_even, ptep); /* get even pte */
1075 UASM_i_LW(p, ptep, pte_off_odd, ptep); /* get odd pte */
1da177e4
LT		 1076 if (r45k_bvahwbug())
1077 build_tlb_probe_entry(p);
974a0b6a
PB		 1078 build_convert_pte_to_entrylo(p, tmp);
1079 if (r4k_250MHZhwbug())
1080 UASM_i_MTC0(p, 0, C0_ENTRYLO0);
1081 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
1082 build_convert_pte_to_entrylo(p, ptep);
1083 if (r45k_bvahwbug())
1084 uasm_i_mfc0(p, tmp, C0_INDEX);
1da177e4 1085 if (r4k_250MHZhwbug())
9b8c3891
DD		 1086 UASM_i_MTC0(p, 0, C0_ENTRYLO1);
1087 UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */
1da177e4 1088}
722b4544 1089EXPORT_SYMBOL_GPL(build_update_entries);
1da177e4 1090
2c8c53e2
DD		 1091struct mips_huge_tlb_info {
1092 int huge_pte;
1093 int restore_scratch;
9e0f162a 1094 bool need_reload_pte;
2c8c53e2
DD		 1095};
1096
078a55fc 1097static struct mips_huge_tlb_info
2c8c53e2
DD		 1098build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l,
1099 struct uasm_reloc **r, unsigned int tmp,
7777b939 1100 unsigned int ptr, int c0_scratch_reg)
2c8c53e2
DD		 1101{
1102 struct mips_huge_tlb_info rv;
1103 unsigned int even, odd;
1104 int vmalloc_branch_delay_filled = 0;
1105 const int scratch = 1; /* Our extra working register */
1106
1107 rv.huge_pte = scratch;
1108 rv.restore_scratch = 0;
9e0f162a 1109 rv.need_reload_pte = false;
2c8c53e2
DD		 1110
1111 if (check_for_high_segbits) {
1112 UASM_i_MFC0(p, tmp, C0_BADVADDR);
1113
1114 if (pgd_reg != -1)
7777b939 1115 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg);
2c8c53e2
DD		 1116 else
1117 UASM_i_MFC0(p, ptr, C0_CONTEXT);
1118
7777b939
J		 1119 if (c0_scratch_reg >= 0)
1120 UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg);
2c8c53e2
DD		 1121 else
1122 UASM_i_SW(p, scratch, scratchpad_offset(0), 0);
1123
1124 uasm_i_dsrl_safe(p, scratch, tmp,
1125 PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
1126 uasm_il_bnez(p, r, scratch, label_vmalloc);
1127
1128 if (pgd_reg == -1) {
1129 vmalloc_branch_delay_filled = 1;
1130 /* Clear lower 23 bits of context. */
1131 uasm_i_dins(p, ptr, 0, 0, 23);
1132 }
1133 } else {
1134 if (pgd_reg != -1)
7777b939 1135 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg);
2c8c53e2
DD		 1136 else
1137 UASM_i_MFC0(p, ptr, C0_CONTEXT);
1138
1139 UASM_i_MFC0(p, tmp, C0_BADVADDR);
1140
7777b939
J		 1141 if (c0_scratch_reg >= 0)
1142 UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg);
2c8c53e2
DD		 1143 else
1144 UASM_i_SW(p, scratch, scratchpad_offset(0), 0);
1145
1146 if (pgd_reg == -1)
1147 /* Clear lower 23 bits of context. */
1148 uasm_i_dins(p, ptr, 0, 0, 23);
1149
1150 uasm_il_bltz(p, r, tmp, label_vmalloc);
1151 }
1152
1153 if (pgd_reg == -1) {
1154 vmalloc_branch_delay_filled = 1;
70342287 1155 /* 1 0 1 0 1 << 6 xkphys cached */
2c8c53e2
DD		 1156 uasm_i_ori(p, ptr, ptr, 0x540);
1157 uasm_i_drotr(p, ptr, ptr, 11);
1158 }
1159
1160#ifdef __PAGETABLE_PMD_FOLDED
1161#define LOC_PTEP scratch
1162#else
1163#define LOC_PTEP ptr
1164#endif
1165
1166 if (!vmalloc_branch_delay_filled)
1167 /* get pgd offset in bytes */
1168 uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3);
1169
1170 uasm_l_vmalloc_done(l, *p);
1171
1172 /*
70342287
RB		 1173 * tmp ptr
1174 * fall-through case = badvaddr *pgd_current
1175 * vmalloc case = badvaddr swapper_pg_dir
2c8c53e2
DD		 1176 */
1177
1178 if (vmalloc_branch_delay_filled)
1179 /* get pgd offset in bytes */
1180 uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3);
1181
1182#ifdef __PAGETABLE_PMD_FOLDED
1183 GET_CONTEXT(p, tmp); /* get context reg */
1184#endif
1185 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PGD - 1) << 3);
1186
1187 if (use_lwx_insns()) {
1188 UASM_i_LWX(p, LOC_PTEP, scratch, ptr);
1189 } else {
1190 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pgd offset */
1191 uasm_i_ld(p, LOC_PTEP, 0, ptr); /* get pmd pointer */
1192 }
1193
3377e227
AB		 1194#ifndef __PAGETABLE_PUD_FOLDED
1195 /* get pud offset in bytes */
1196 uasm_i_dsrl_safe(p, scratch, tmp, PUD_SHIFT - 3);
1197 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PUD - 1) << 3);
1198
1199 if (use_lwx_insns()) {
1200 UASM_i_LWX(p, ptr, scratch, ptr);
1201 } else {
1202 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */
1203 UASM_i_LW(p, ptr, 0, ptr);
1204 }
1205 /* ptr contains a pointer to PMD entry */
1206 /* tmp contains the address */
1207#endif
1208
2c8c53e2
DD		 1209#ifndef __PAGETABLE_PMD_FOLDED
1210 /* get pmd offset in bytes */
1211 uasm_i_dsrl_safe(p, scratch, tmp, PMD_SHIFT - 3);
1212 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PMD - 1) << 3);
1213 GET_CONTEXT(p, tmp); /* get context reg */
1214
1215 if (use_lwx_insns()) {
1216 UASM_i_LWX(p, scratch, scratch, ptr);
1217 } else {
1218 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */
1219 UASM_i_LW(p, scratch, 0, ptr);
1220 }
1221#endif
1222 /* Adjust the context during the load latency. */
1223 build_adjust_context(p, tmp);
1224
aa1762f4 1225#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
2c8c53e2
DD		 1226 uasm_il_bbit1(p, r, scratch, ilog2(_PAGE_HUGE), label_tlb_huge_update);
1227 /*
1228 * The in the LWX case we don't want to do the load in the
70342287 1229 * delay slot. It cannot issue in the same cycle and may be
2c8c53e2
DD		 1230 * speculative and unneeded.
1231 */
1232 if (use_lwx_insns())
1233 uasm_i_nop(p);
aa1762f4 1234#endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
2c8c53e2
DD		 1235
1236
1237 /* build_update_entries */
1238 if (use_lwx_insns()) {
1239 even = ptr;
1240 odd = tmp;
1241 UASM_i_LWX(p, even, scratch, tmp);
1242 UASM_i_ADDIU(p, tmp, tmp, sizeof(pte_t));
1243 UASM_i_LWX(p, odd, scratch, tmp);
1244 } else {
1245 UASM_i_ADDU(p, ptr, scratch, tmp); /* add in offset */
1246 even = tmp;
1247 odd = ptr;
1248 UASM_i_LW(p, even, 0, ptr); /* get even pte */
1249 UASM_i_LW(p, odd, sizeof(pte_t), ptr); /* get odd pte */
1250 }
05857c64 1251 if (cpu_has_rixi) {
748e787e 1252 uasm_i_drotr(p, even, even, ilog2(_PAGE_GLOBAL));
2c8c53e2 1253 UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */
748e787e 1254 uasm_i_drotr(p, odd, odd, ilog2(_PAGE_GLOBAL));
2c8c53e2
DD		 1255 } else {
1256 uasm_i_dsrl_safe(p, even, even, ilog2(_PAGE_GLOBAL));
1257 UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */
1258 uasm_i_dsrl_safe(p, odd, odd, ilog2(_PAGE_GLOBAL));
1259 }
1260 UASM_i_MTC0(p, odd, C0_ENTRYLO1); /* load it */
1261
7777b939
J		 1262 if (c0_scratch_reg >= 0) {
1263 UASM_i_MFC0(p, scratch, c0_kscratch(), c0_scratch_reg);
2c8c53e2
DD		 1264 build_tlb_write_entry(p, l, r, tlb_random);
1265 uasm_l_leave(l, *p);
1266 rv.restore_scratch = 1;
1267 } else if (PAGE_SHIFT == 14 || PAGE_SHIFT == 13) {
1268 build_tlb_write_entry(p, l, r, tlb_random);
1269 uasm_l_leave(l, *p);
1270 UASM_i_LW(p, scratch, scratchpad_offset(0), 0);
1271 } else {
1272 UASM_i_LW(p, scratch, scratchpad_offset(0), 0);
1273 build_tlb_write_entry(p, l, r, tlb_random);
1274 uasm_l_leave(l, *p);
1275 rv.restore_scratch = 1;
1276 }
1277
1278 uasm_i_eret(p); /* return from trap */
1279
1280 return rv;
1281}
1282
e6f72d3a
DD		 1283/*
1284 * For a 64-bit kernel, we are using the 64-bit XTLB refill exception
1285 * because EXL == 0. If we wrap, we can also use the 32 instruction
1286 * slots before the XTLB refill exception handler which belong to the
1287 * unused TLB refill exception.
1288 */
1289#define MIPS64_REFILL_INSNS 32
1290
078a55fc 1291static void build_r4000_tlb_refill_handler(void)
1da177e4
LT		 1292{
1293 u32 *p = tlb_handler;
e30ec452
TS		 1294 struct uasm_label *l = labels;
1295 struct uasm_reloc *r = relocs;
1da177e4
LT		 1296 u32 *f;
1297 unsigned int final_len;
4a9040f4
RB		 1298 struct mips_huge_tlb_info htlb_info __maybe_unused;
1299 enum vmalloc64_mode vmalloc_mode __maybe_unused;
18280eda 1300
1da177e4
LT		 1301 memset(tlb_handler, 0, sizeof(tlb_handler));
1302 memset(labels, 0, sizeof(labels));
1303 memset(relocs, 0, sizeof(relocs));
1304 memset(final_handler, 0, sizeof(final_handler));
1305
18280eda 1306 if (IS_ENABLED(CONFIG_64BIT) && (scratch_reg >= 0 || scratchpad_available()) && use_bbit_insns()) {
2c8c53e2
DD		 1307 htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1,
1308 scratch_reg);
1309 vmalloc_mode = refill_scratch;
1310 } else {
1311 htlb_info.huge_pte = K0;
1312 htlb_info.restore_scratch = 0;
9e0f162a 1313 htlb_info.need_reload_pte = true;
2c8c53e2
DD		 1314 vmalloc_mode = refill_noscratch;
1315 /*
1316 * create the plain linear handler
1317 */
1318 if (bcm1250_m3_war()) {
1319 unsigned int segbits = 44;
1320
1321 uasm_i_dmfc0(&p, K0, C0_BADVADDR);
1322 uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
1323 uasm_i_xor(&p, K0, K0, K1);
1324 uasm_i_dsrl_safe(&p, K1, K0, 62);
1325 uasm_i_dsrl_safe(&p, K0, K0, 12 + 1);
1326 uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits);
1327 uasm_i_or(&p, K0, K0, K1);
1328 uasm_il_bnez(&p, &r, K0, label_leave);
1329 /* No need for uasm_i_nop */
1330 }
1da177e4 1331
875d43e7 1332#ifdef CONFIG_64BIT
2c8c53e2 1333 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
1da177e4 1334#else
2c8c53e2 1335 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
1da177e4
LT		 1336#endif
1337
aa1762f4 1338#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
2c8c53e2 1339 build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update);
fd062c84
DD		 1340#endif
1341
2c8c53e2
DD		 1342 build_get_ptep(&p, K0, K1);
1343 build_update_entries(&p, K0, K1);
1344 build_tlb_write_entry(&p, &l, &r, tlb_random);
1345 uasm_l_leave(&l, p);
1346 uasm_i_eret(&p); /* return from trap */
1347 }
aa1762f4 1348#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
fd062c84 1349 uasm_l_tlb_huge_update(&l, p);
9e0f162a
DD		 1350 if (htlb_info.need_reload_pte)
1351 UASM_i_LW(&p, htlb_info.huge_pte, 0, K1);
2c8c53e2
DD		 1352 build_huge_update_entries(&p, htlb_info.huge_pte, K1);
1353 build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random,
1354 htlb_info.restore_scratch);
fd062c84
DD		 1355#endif
1356
875d43e7 1357#ifdef CONFIG_64BIT
2c8c53e2 1358 build_get_pgd_vmalloc64(&p, &l, &r, K0, K1, vmalloc_mode);
1da177e4
LT		 1359#endif
1360
1361 /*
1362 * Overflow check: For the 64bit handler, we need at least one
1363 * free instruction slot for the wrap-around branch. In worst
1364 * case, if the intended insertion point is a delay slot, we
4b3f686d 1365 * need three, with the second nop'ed and the third being
1da177e4
LT		 1366 * unused.
1367 */
14bd8c08
RB		 1368 switch (boot_cpu_type()) {
1369 default:
1370 if (sizeof(long) == 4) {
1371 case CPU_LOONGSON2:
1372 /* Loongson2 ebase is different than r4k, we have more space */
1373 if ((p - tlb_handler) > 64)
1374 panic("TLB refill handler space exceeded");
95affdda 1375 /*
14bd8c08 1376 * Now fold the handler in the TLB refill handler space.
95affdda 1377 */
14bd8c08
RB		 1378 f = final_handler;
1379 /* Simplest case, just copy the handler. */
1380 uasm_copy_handler(relocs, labels, tlb_handler, p, f);
1381 final_len = p - tlb_handler;
1382 break;
1383 } else {
1384 if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1)
1385 || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3)
1386 && uasm_insn_has_bdelay(relocs,
1387 tlb_handler + MIPS64_REFILL_INSNS - 3)))
1388 panic("TLB refill handler space exceeded");
95affdda 1389 /*
14bd8c08 1390 * Now fold the handler in the TLB refill handler space.
95affdda 1391 */
14bd8c08
RB		 1392 f = final_handler + MIPS64_REFILL_INSNS;
1393 if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) {
1394 /* Just copy the handler. */
1395 uasm_copy_handler(relocs, labels, tlb_handler, p, f);
1396 final_len = p - tlb_handler;
1397 } else {
1398#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1399 const enum label_id ls = label_tlb_huge_update;
1400#else
1401 const enum label_id ls = label_vmalloc;
1402#endif
1403 u32 *split;
1404 int ov = 0;
1405 int i;
1406
1407 for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++)
1408 ;
1409 BUG_ON(i == ARRAY_SIZE(labels));
1410 split = labels[i].addr;
1411
1412 /*
1413 * See if we have overflown one way or the other.
1414 */
1415 if (split > tlb_handler + MIPS64_REFILL_INSNS ||
1416 split < p - MIPS64_REFILL_INSNS)
1417 ov = 1;
1418
1419 if (ov) {
1420 /*
1421 * Split two instructions before the end. One
1422 * for the branch and one for the instruction
1423 * in the delay slot.
1424 */
1425 split = tlb_handler + MIPS64_REFILL_INSNS - 2;
1426
1427 /*
1428 * If the branch would fall in a delay slot,
1429 * we must back up an additional instruction
1430 * so that it is no longer in a delay slot.
1431 */
1432 if (uasm_insn_has_bdelay(relocs, split - 1))
1433 split--;
1434 }
1435 /* Copy first part of the handler. */
1436 uasm_copy_handler(relocs, labels, tlb_handler, split, f);
1437 f += split - tlb_handler;
1438
1439 if (ov) {
1440 /* Insert branch. */
1441 uasm_l_split(&l, final_handler);
1442 uasm_il_b(&f, &r, label_split);
1443 if (uasm_insn_has_bdelay(relocs, split))
1444 uasm_i_nop(&f);
1445 else {
1446 uasm_copy_handler(relocs, labels,
1447 split, split + 1, f);
1448 uasm_move_labels(labels, f, f + 1, -1);
1449 f++;
1450 split++;
1451 }
1452 }
1453
1454 /* Copy the rest of the handler. */
1455 uasm_copy_handler(relocs, labels, split, p, final_handler);
1456 final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) +
1457 (p - split);
95affdda 1458 }
1da177e4 1459 }
14bd8c08 1460 break;
1da177e4 1461 }
1da177e4 1462
e30ec452
TS		 1463 uasm_resolve_relocs(relocs, labels);
1464 pr_debug("Wrote TLB refill handler (%u instructions).\n",
1465 final_len);
1da177e4 1466
91b05e67 1467 memcpy((void *)ebase, final_handler, 0x100);
1062080a 1468 local_flush_icache_range(ebase, ebase + 0x100);
92b1e6a6 1469
a2c763e0 1470 dump_handler("r4000_tlb_refill", (u32 *)ebase, 64);
1da177e4
LT		 1471}
1472
380cd582
HC		 1473static void setup_pw(void)
1474{
1475 unsigned long pgd_i, pgd_w;
1476#ifndef __PAGETABLE_PMD_FOLDED
1477 unsigned long pmd_i, pmd_w;
1478#endif
1479 unsigned long pt_i, pt_w;
1480 unsigned long pte_i, pte_w;
1481#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1482 unsigned long psn;
1483
1484 psn = ilog2(_PAGE_HUGE); /* bit used to indicate huge page */
1485#endif
1486 pgd_i = PGDIR_SHIFT; /* 1st level PGD */
1487#ifndef __PAGETABLE_PMD_FOLDED
1488 pgd_w = PGDIR_SHIFT - PMD_SHIFT + PGD_ORDER;
1489
1490 pmd_i = PMD_SHIFT; /* 2nd level PMD */
1491 pmd_w = PMD_SHIFT - PAGE_SHIFT;
1492#else
1493 pgd_w = PGDIR_SHIFT - PAGE_SHIFT + PGD_ORDER;
1494#endif
1495
1496 pt_i = PAGE_SHIFT; /* 3rd level PTE */
1497 pt_w = PAGE_SHIFT - 3;
1498
1499 pte_i = ilog2(_PAGE_GLOBAL);
1500 pte_w = 0;
1501
1502#ifndef __PAGETABLE_PMD_FOLDED
1503 write_c0_pwfield(pgd_i << 24 | pmd_i << 12 | pt_i << 6 | pte_i);
1504 write_c0_pwsize(1 << 30 | pgd_w << 24 | pmd_w << 12 | pt_w << 6 | pte_w);
1505#else
1506 write_c0_pwfield(pgd_i << 24 | pt_i << 6 | pte_i);
1507 write_c0_pwsize(1 << 30 | pgd_w << 24 | pt_w << 6 | pte_w);
1508#endif
1509
1510#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
1511 write_c0_pwctl(1 << 6 | psn);
1512#endif
1513 write_c0_kpgd(swapper_pg_dir);
1514 kscratch_used_mask |= (1 << 7); /* KScratch6 is used for KPGD */
1515}
1516
1517static void build_loongson3_tlb_refill_handler(void)
1518{
1519 u32 *p = tlb_handler;
1520 struct uasm_label *l = labels;
1521 struct uasm_reloc *r = relocs;
1522
1523 memset(labels, 0, sizeof(labels));
1524 memset(relocs, 0, sizeof(relocs));
1525 memset(tlb_handler, 0, sizeof(tlb_handler));
1526
1527 if (check_for_high_segbits) {
1528 uasm_i_dmfc0(&p, K0, C0_BADVADDR);
1529 uasm_i_dsrl_safe(&p, K1, K0, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
1530 uasm_il_beqz(&p, &r, K1, label_vmalloc);
1531 uasm_i_nop(&p);
1532
1533 uasm_il_bgez(&p, &r, K0, label_large_segbits_fault);
1534 uasm_i_nop(&p);
1535 uasm_l_vmalloc(&l, p);
1536 }
1537
1538 uasm_i_dmfc0(&p, K1, C0_PGD);
1539
1540 uasm_i_lddir(&p, K0, K1, 3); /* global page dir */
1541#ifndef __PAGETABLE_PMD_FOLDED
1542 uasm_i_lddir(&p, K1, K0, 1); /* middle page dir */
1543#endif
1544 uasm_i_ldpte(&p, K1, 0); /* even */
1545 uasm_i_ldpte(&p, K1, 1); /* odd */
1546 uasm_i_tlbwr(&p);
1547
1548 /* restore page mask */
1549 if (PM_DEFAULT_MASK >> 16) {
1550 uasm_i_lui(&p, K0, PM_DEFAULT_MASK >> 16);
1551 uasm_i_ori(&p, K0, K0, PM_DEFAULT_MASK & 0xffff);
1552 uasm_i_mtc0(&p, K0, C0_PAGEMASK);
1553 } else if (PM_DEFAULT_MASK) {
1554 uasm_i_ori(&p, K0, 0, PM_DEFAULT_MASK);
1555 uasm_i_mtc0(&p, K0, C0_PAGEMASK);
1556 } else {
1557 uasm_i_mtc0(&p, 0, C0_PAGEMASK);
1558 }
1559
1560 uasm_i_eret(&p);
1561
1562 if (check_for_high_segbits) {
1563 uasm_l_large_segbits_fault(&l, p);
1564 UASM_i_LA(&p, K1, (unsigned long)tlb_do_page_fault_0);
1565 uasm_i_jr(&p, K1);
1566 uasm_i_nop(&p);
1567 }
1568
1569 uasm_resolve_relocs(relocs, labels);
1570 memcpy((void *)(ebase + 0x80), tlb_handler, 0x80);
1571 local_flush_icache_range(ebase + 0x80, ebase + 0x100);
1572 dump_handler("loongson3_tlb_refill", (u32 *)(ebase + 0x80), 32);
1573}
1574
6ba045f9
J		 1575extern u32 handle_tlbl[], handle_tlbl_end[];
1576extern u32 handle_tlbs[], handle_tlbs_end[];
1577extern u32 handle_tlbm[], handle_tlbm_end[];
ccf01516
JH		 1578extern u32 tlbmiss_handler_setup_pgd_start[];
1579extern u32 tlbmiss_handler_setup_pgd[];
1580EXPORT_SYMBOL_GPL(tlbmiss_handler_setup_pgd);
7bb39409 1581extern u32 tlbmiss_handler_setup_pgd_end[];
3d8bfdd0 1582
f4ae17aa 1583static void build_setup_pgd(void)
3d8bfdd0
DD		 1584{
1585 const int a0 = 4;
f4ae17aa
J		 1586 const int __maybe_unused a1 = 5;
1587 const int __maybe_unused a2 = 6;
7bb39409 1588 u32 *p = tlbmiss_handler_setup_pgd_start;
6ba045f9 1589 const int tlbmiss_handler_setup_pgd_size =
7bb39409 1590 tlbmiss_handler_setup_pgd_end - tlbmiss_handler_setup_pgd_start;
f4ae17aa
J		 1591#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
1592 long pgdc = (long)pgd_current;
1593#endif
3d8bfdd0 1594
6ba045f9
J		 1595 memset(tlbmiss_handler_setup_pgd, 0, tlbmiss_handler_setup_pgd_size *
1596 sizeof(tlbmiss_handler_setup_pgd[0]));
3d8bfdd0
DD		 1597 memset(labels, 0, sizeof(labels));
1598 memset(relocs, 0, sizeof(relocs));
3d8bfdd0 1599 pgd_reg = allocate_kscratch();
f4ae17aa 1600#ifdef CONFIG_MIPS_PGD_C0_CONTEXT
3d8bfdd0 1601 if (pgd_reg == -1) {
f4ae17aa
J		 1602 struct uasm_label *l = labels;
1603 struct uasm_reloc *r = relocs;
1604
3d8bfdd0
DD		 1605 /* PGD << 11 in c0_Context */
1606 /*
1607 * If it is a ckseg0 address, convert to a physical
1608 * address. Shifting right by 29 and adding 4 will
1609 * result in zero for these addresses.
1610 *
1611 */
1612 UASM_i_SRA(&p, a1, a0, 29);
1613 UASM_i_ADDIU(&p, a1, a1, 4);
1614 uasm_il_bnez(&p, &r, a1, label_tlbl_goaround1);
1615 uasm_i_nop(&p);
1616 uasm_i_dinsm(&p, a0, 0, 29, 64 - 29);
1617 uasm_l_tlbl_goaround1(&l, p);
1618 UASM_i_SLL(&p, a0, a0, 11);
1619 uasm_i_jr(&p, 31);
1620 UASM_i_MTC0(&p, a0, C0_CONTEXT);
1621 } else {
1622 /* PGD in c0_KScratch */
1623 uasm_i_jr(&p, 31);
380cd582
HC		 1624 if (cpu_has_ldpte)
1625 UASM_i_MTC0(&p, a0, C0_PWBASE);
1626 else
1627 UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg);
3d8bfdd0 1628 }
f4ae17aa
J		 1629#else
1630#ifdef CONFIG_SMP
1631 /* Save PGD to pgd_current[smp_processor_id()] */
1632 UASM_i_CPUID_MFC0(&p, a1, SMP_CPUID_REG);
1633 UASM_i_SRL_SAFE(&p, a1, a1, SMP_CPUID_PTRSHIFT);
1634 UASM_i_LA_mostly(&p, a2, pgdc);
1635 UASM_i_ADDU(&p, a2, a2, a1);
1636 UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2);
1637#else
1638 UASM_i_LA_mostly(&p, a2, pgdc);
1639 UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2);
1640#endif /* SMP */
1641 uasm_i_jr(&p, 31);
1642
1643 /* if pgd_reg is allocated, save PGD also to scratch register */
1644 if (pgd_reg != -1)
1645 UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg);
1646 else
1647 uasm_i_nop(&p);
1648#endif
6ba045f9
J		 1649 if (p >= tlbmiss_handler_setup_pgd_end)
1650 panic("tlbmiss_handler_setup_pgd space exceeded");
1651
3d8bfdd0 1652 uasm_resolve_relocs(relocs, labels);
6ba045f9
J		 1653 pr_debug("Wrote tlbmiss_handler_setup_pgd (%u instructions).\n",
1654 (unsigned int)(p - tlbmiss_handler_setup_pgd));
3d8bfdd0 1655
6ba045f9
J		 1656 dump_handler("tlbmiss_handler", tlbmiss_handler_setup_pgd,
1657 tlbmiss_handler_setup_pgd_size);
3d8bfdd0 1658}
1da177e4 1659
078a55fc 1660static void
bd1437e4 1661iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr)
1da177e4
LT		 1662{
1663#ifdef CONFIG_SMP
34adb28d 1664# ifdef CONFIG_PHYS_ADDR_T_64BIT
1da177e4 1665 if (cpu_has_64bits)
e30ec452 1666 uasm_i_lld(p, pte, 0, ptr);
1da177e4
LT		 1667 else
1668# endif
e30ec452 1669 UASM_i_LL(p, pte, 0, ptr);
1da177e4 1670#else
34adb28d 1671# ifdef CONFIG_PHYS_ADDR_T_64BIT
1da177e4 1672 if (cpu_has_64bits)
e30ec452 1673 uasm_i_ld(p, pte, 0, ptr);
1da177e4
LT		 1674 else
1675# endif
e30ec452 1676 UASM_i_LW(p, pte, 0, ptr);
1da177e4
LT		 1677#endif
1678}
1679
078a55fc 1680static void
e30ec452 1681iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr,
bbeeffec 1682 unsigned int mode, unsigned int scratch)
1da177e4 1683{
63b2d2f4 1684 unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY);
b4ebbb87 1685 unsigned int swmode = mode & ~hwmode;
63b2d2f4 1686
97f2645f 1687 if (IS_ENABLED(CONFIG_XPA) && !cpu_has_64bits) {
b4ebbb87 1688 uasm_i_lui(p, scratch, swmode >> 16);
c5b36783 1689 uasm_i_or(p, pte, pte, scratch);
b4ebbb87
PB		 1690 BUG_ON(swmode & 0xffff);
1691 } else {
1692 uasm_i_ori(p, pte, pte, mode);
1693 }
1694
1da177e4 1695#ifdef CONFIG_SMP
34adb28d 1696# ifdef CONFIG_PHYS_ADDR_T_64BIT
1da177e4 1697 if (cpu_has_64bits)
e30ec452 1698 uasm_i_scd(p, pte, 0, ptr);
1da177e4
LT		 1699 else
1700# endif
e30ec452 1701 UASM_i_SC(p, pte, 0, ptr);
1da177e4
LT		 1702
1703 if (r10000_llsc_war())
e30ec452 1704 uasm_il_beqzl(p, r, pte, label_smp_pgtable_change);
1da177e4 1705 else
e30ec452 1706 uasm_il_beqz(p, r, pte, label_smp_pgtable_change);
1da177e4 1707
34adb28d 1708# ifdef CONFIG_PHYS_ADDR_T_64BIT
1da177e4 1709 if (!cpu_has_64bits) {
e30ec452
TS		 1710 /* no uasm_i_nop needed */
1711 uasm_i_ll(p, pte, sizeof(pte_t) / 2, ptr);
1712 uasm_i_ori(p, pte, pte, hwmode);
b4ebbb87 1713 BUG_ON(hwmode & ~0xffff);
e30ec452
TS		 1714 uasm_i_sc(p, pte, sizeof(pte_t) / 2, ptr);
1715 uasm_il_beqz(p, r, pte, label_smp_pgtable_change);
1716 /* no uasm_i_nop needed */
1717 uasm_i_lw(p, pte, 0, ptr);
1da177e4 1718 } else
e30ec452 1719 uasm_i_nop(p);
1da177e4 1720# else
e30ec452 1721 uasm_i_nop(p);
1da177e4
LT		 1722# endif
1723#else
34adb28d 1724# ifdef CONFIG_PHYS_ADDR_T_64BIT
1da177e4 1725 if (cpu_has_64bits)
e30ec452 1726 uasm_i_sd(p, pte, 0, ptr);
1da177e4
LT		 1727 else
1728# endif
e30ec452 1729 UASM_i_SW(p, pte, 0, ptr);
1da177e4 1730
34adb28d 1731# ifdef CONFIG_PHYS_ADDR_T_64BIT
1da177e4 1732 if (!cpu_has_64bits) {
e30ec452
TS		 1733 uasm_i_lw(p, pte, sizeof(pte_t) / 2, ptr);
1734 uasm_i_ori(p, pte, pte, hwmode);
b4ebbb87 1735 BUG_ON(hwmode & ~0xffff);
e30ec452
TS		 1736 uasm_i_sw(p, pte, sizeof(pte_t) / 2, ptr);
1737 uasm_i_lw(p, pte, 0, ptr);
1da177e4
LT		 1738 }
1739# endif
1740#endif
1741}
1742
1743/*
1744 * Check if PTE is present, if not then jump to LABEL. PTR points to
1745 * the page table where this PTE is located, PTE will be re-loaded
1746 * with it's original value.
1747 */
078a55fc 1748static void
bd1437e4 1749build_pte_present(u32 **p, struct uasm_reloc **r,
bf28607f 1750 int pte, int ptr, int scratch, enum label_id lid)
1da177e4 1751{
bf28607f 1752 int t = scratch >= 0 ? scratch : pte;
8fe4908b 1753 int cur = pte;
bf28607f 1754
05857c64 1755 if (cpu_has_rixi) {
cc33ae43
DD		 1756 if (use_bbit_insns()) {
1757 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid);
1758 uasm_i_nop(p);
1759 } else {
8fe4908b
JH		 1760 if (_PAGE_PRESENT_SHIFT) {
1761 uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT);
1762 cur = t;
1763 }
1764 uasm_i_andi(p, t, cur, 1);
bf28607f
DD		 1765 uasm_il_beqz(p, r, t, lid);
1766 if (pte == t)
1767 /* You lose the SMP race :-(*/
1768 iPTE_LW(p, pte, ptr);
cc33ae43 1769 }
6dd9344c 1770 } else {
8fe4908b
JH		 1771 if (_PAGE_PRESENT_SHIFT) {
1772 uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT);
1773 cur = t;
1774 }
1775 uasm_i_andi(p, t, cur,
780602d7
PB		 1776 (_PAGE_PRESENT | _PAGE_NO_READ) >> _PAGE_PRESENT_SHIFT);
1777 uasm_i_xori(p, t, t, _PAGE_PRESENT >> _PAGE_PRESENT_SHIFT);
bf28607f
DD		 1778 uasm_il_bnez(p, r, t, lid);
1779 if (pte == t)
1780 /* You lose the SMP race :-(*/
1781 iPTE_LW(p, pte, ptr);
6dd9344c 1782 }
1da177e4
LT		 1783}
1784
1785/* Make PTE valid, store result in PTR. */
078a55fc 1786static void
e30ec452 1787build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte,
bbeeffec 1788 unsigned int ptr, unsigned int scratch)
1da177e4 1789{
63b2d2f4
TS		 1790 unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED;
1791
bbeeffec 1792 iPTE_SW(p, r, pte, ptr, mode, scratch);
1da177e4
LT		 1793}
1794
1795/*
1796 * Check if PTE can be written to, if not branch to LABEL. Regardless
1797 * restore PTE with value from PTR when done.
1798 */
078a55fc 1799static void
bd1437e4 1800build_pte_writable(u32 **p, struct uasm_reloc **r,
bf28607f
DD		 1801 unsigned int pte, unsigned int ptr, int scratch,
1802 enum label_id lid)
1da177e4 1803{
bf28607f 1804 int t = scratch >= 0 ? scratch : pte;
8fe4908b 1805 int cur = pte;
bf28607f 1806
8fe4908b
JH		 1807 if (_PAGE_PRESENT_SHIFT) {
1808 uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT);
1809 cur = t;
1810 }
1811 uasm_i_andi(p, t, cur,
a3ae565a
JH		 1812 (_PAGE_PRESENT | _PAGE_WRITE) >> _PAGE_PRESENT_SHIFT);
1813 uasm_i_xori(p, t, t,
1814 (_PAGE_PRESENT | _PAGE_WRITE) >> _PAGE_PRESENT_SHIFT);
bf28607f
DD		 1815 uasm_il_bnez(p, r, t, lid);
1816 if (pte == t)
1817 /* You lose the SMP race :-(*/
cc33ae43 1818 iPTE_LW(p, pte, ptr);
bf28607f
DD		 1819 else
1820 uasm_i_nop(p);
1da177e4
LT		 1821}
1822
1823/* Make PTE writable, update software status bits as well, then store
1824 * at PTR.
1825 */
078a55fc 1826static void
e30ec452 1827build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte,
bbeeffec 1828 unsigned int ptr, unsigned int scratch)
1da177e4 1829{
63b2d2f4
TS		 1830 unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID
1831 | _PAGE_DIRTY);
1832
bbeeffec 1833 iPTE_SW(p, r, pte, ptr, mode, scratch);
1da177e4
LT		 1834}
1835
1836/*
1837 * Check if PTE can be modified, if not branch to LABEL. Regardless
1838 * restore PTE with value from PTR when done.
1839 */
078a55fc 1840static void
bd1437e4 1841build_pte_modifiable(u32 **p, struct uasm_reloc **r,
bf28607f
DD		 1842 unsigned int pte, unsigned int ptr, int scratch,
1843 enum label_id lid)
1da177e4 1844{
cc33ae43
DD		 1845 if (use_bbit_insns()) {
1846 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_WRITE), lid);
1847 uasm_i_nop(p);
1848 } else {
bf28607f 1849 int t = scratch >= 0 ? scratch : pte;
c5b36783
SH		 1850 uasm_i_srl(p, t, pte, _PAGE_WRITE_SHIFT);
1851 uasm_i_andi(p, t, t, 1);
bf28607f
DD		 1852 uasm_il_beqz(p, r, t, lid);
1853 if (pte == t)
1854 /* You lose the SMP race :-(*/
1855 iPTE_LW(p, pte, ptr);
cc33ae43 1856 }
1da177e4
LT		 1857}
1858
82622284 1859#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
3d8bfdd0
DD		 1860
1861
1da177e4
LT		 1862/*
1863 * R3000 style TLB load/store/modify handlers.
1864 */
1865
fded2e50
MR		 1866/*
1867 * This places the pte into ENTRYLO0 and writes it with tlbwi.
1868 * Then it returns.
1869 */
078a55fc 1870static void
fded2e50 1871build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp)
1da177e4 1872{
e30ec452
TS		 1873 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
1874 uasm_i_mfc0(p, tmp, C0_EPC); /* cp0 delay */
1875 uasm_i_tlbwi(p);
1876 uasm_i_jr(p, tmp);
1877 uasm_i_rfe(p); /* branch delay */
1da177e4
LT		 1878}
1879
1880/*
fded2e50
MR		 1881 * This places the pte into ENTRYLO0 and writes it with tlbwi
1882 * or tlbwr as appropriate. This is because the index register
1883 * may have the probe fail bit set as a result of a trap on a
1884 * kseg2 access, i.e. without refill. Then it returns.
1da177e4 1885 */
078a55fc 1886static void
e30ec452
TS		 1887build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l,
1888 struct uasm_reloc **r, unsigned int pte,
1889 unsigned int tmp)
1890{
1891 uasm_i_mfc0(p, tmp, C0_INDEX);
1892 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */
1893 uasm_il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */
1894 uasm_i_mfc0(p, tmp, C0_EPC); /* branch delay */
1895 uasm_i_tlbwi(p); /* cp0 delay */
1896 uasm_i_jr(p, tmp);
1897 uasm_i_rfe(p); /* branch delay */
1898 uasm_l_r3000_write_probe_fail(l, *p);
1899 uasm_i_tlbwr(p); /* cp0 delay */
1900 uasm_i_jr(p, tmp);
1901 uasm_i_rfe(p); /* branch delay */
1da177e4
LT		 1902}
1903
078a55fc 1904static void
1da177e4
LT		 1905build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte,
1906 unsigned int ptr)
1907{
1908 long pgdc = (long)pgd_current;
1909
e30ec452
TS		 1910 uasm_i_mfc0(p, pte, C0_BADVADDR);
1911 uasm_i_lui(p, ptr, uasm_rel_hi(pgdc)); /* cp0 delay */
1912 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr);
1913 uasm_i_srl(p, pte, pte, 22); /* load delay */
1914 uasm_i_sll(p, pte, pte, 2);
1915 uasm_i_addu(p, ptr, ptr, pte);
1916 uasm_i_mfc0(p, pte, C0_CONTEXT);
1917 uasm_i_lw(p, ptr, 0, ptr); /* cp0 delay */
1918 uasm_i_andi(p, pte, pte, 0xffc); /* load delay */
1919 uasm_i_addu(p, ptr, ptr, pte);
1920 uasm_i_lw(p, pte, 0, ptr);
1921 uasm_i_tlbp(p); /* load delay */
1da177e4
LT		 1922}
1923
078a55fc 1924static void build_r3000_tlb_load_handler(void)
1da177e4
LT		 1925{
1926 u32 *p = handle_tlbl;
6ba045f9 1927 const int handle_tlbl_size = handle_tlbl_end - handle_tlbl;
e30ec452
TS		 1928 struct uasm_label *l = labels;
1929 struct uasm_reloc *r = relocs;
1da177e4 1930
6ba045f9 1931 memset(handle_tlbl, 0, handle_tlbl_size * sizeof(handle_tlbl[0]));
1da177e4
LT		 1932 memset(labels, 0, sizeof(labels));
1933 memset(relocs, 0, sizeof(relocs));
1934
1935 build_r3000_tlbchange_handler_head(&p, K0, K1);
bf28607f 1936 build_pte_present(&p, &r, K0, K1, -1, label_nopage_tlbl);
e30ec452 1937 uasm_i_nop(&p); /* load delay */
bbeeffec 1938 build_make_valid(&p, &r, K0, K1, -1);
fded2e50 1939 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
1da177e4 1940
e30ec452
TS		 1941 uasm_l_nopage_tlbl(&l, p);
1942 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
1943 uasm_i_nop(&p);
1da177e4 1944
6ba045f9 1945 if (p >= handle_tlbl_end)
1da177e4
LT		 1946 panic("TLB load handler fastpath space exceeded");
1947
e30ec452
TS		 1948 uasm_resolve_relocs(relocs, labels);
1949 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
1950 (unsigned int)(p - handle_tlbl));
1da177e4 1951
6ba045f9 1952 dump_handler("r3000_tlb_load", handle_tlbl, handle_tlbl_size);
1da177e4
LT		 1953}
1954
078a55fc 1955static void build_r3000_tlb_store_handler(void)
1da177e4
LT		 1956{
1957 u32 *p = handle_tlbs;
6ba045f9 1958 const int handle_tlbs_size = handle_tlbs_end - handle_tlbs;
e30ec452
TS		 1959 struct uasm_label *l = labels;
1960 struct uasm_reloc *r = relocs;
1da177e4 1961
6ba045f9 1962 memset(handle_tlbs, 0, handle_tlbs_size * sizeof(handle_tlbs[0]));
1da177e4
LT		 1963 memset(labels, 0, sizeof(labels));
1964 memset(relocs, 0, sizeof(relocs));
1965
1966 build_r3000_tlbchange_handler_head(&p, K0, K1);
bf28607f 1967 build_pte_writable(&p, &r, K0, K1, -1, label_nopage_tlbs);
e30ec452 1968 uasm_i_nop(&p); /* load delay */
bbeeffec 1969 build_make_write(&p, &r, K0, K1, -1);
fded2e50 1970 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
1da177e4 1971
e30ec452
TS		 1972 uasm_l_nopage_tlbs(&l, p);
1973 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1974 uasm_i_nop(&p);
1da177e4 1975
afc813ae 1976 if (p >= handle_tlbs_end)
1da177e4
LT		 1977 panic("TLB store handler fastpath space exceeded");
1978
e30ec452
TS		 1979 uasm_resolve_relocs(relocs, labels);
1980 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
1981 (unsigned int)(p - handle_tlbs));
1da177e4 1982
6ba045f9 1983 dump_handler("r3000_tlb_store", handle_tlbs, handle_tlbs_size);
1da177e4
LT		 1984}
1985
078a55fc 1986static void build_r3000_tlb_modify_handler(void)
1da177e4
LT		 1987{
1988 u32 *p = handle_tlbm;
6ba045f9 1989 const int handle_tlbm_size = handle_tlbm_end - handle_tlbm;
e30ec452
TS		 1990 struct uasm_label *l = labels;
1991 struct uasm_reloc *r = relocs;
1da177e4 1992
6ba045f9 1993 memset(handle_tlbm, 0, handle_tlbm_size * sizeof(handle_tlbm[0]));
1da177e4
LT		 1994 memset(labels, 0, sizeof(labels));
1995 memset(relocs, 0, sizeof(relocs));
1996
1997 build_r3000_tlbchange_handler_head(&p, K0, K1);
d954ffe3 1998 build_pte_modifiable(&p, &r, K0, K1, -1, label_nopage_tlbm);
e30ec452 1999 uasm_i_nop(&p); /* load delay */
bbeeffec 2000 build_make_write(&p, &r, K0, K1, -1);
fded2e50 2001 build_r3000_pte_reload_tlbwi(&p, K0, K1);
1da177e4 2002
e30ec452
TS		 2003 uasm_l_nopage_tlbm(&l, p);
2004 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
2005 uasm_i_nop(&p);
1da177e4 2006
6ba045f9 2007 if (p >= handle_tlbm_end)
1da177e4
LT		 2008 panic("TLB modify handler fastpath space exceeded");
2009
e30ec452
TS		 2010 uasm_resolve_relocs(relocs, labels);
2011 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
2012 (unsigned int)(p - handle_tlbm));
1da177e4 2013
6ba045f9 2014 dump_handler("r3000_tlb_modify", handle_tlbm, handle_tlbm_size);
1da177e4 2015}
82622284 2016#endif /* CONFIG_MIPS_PGD_C0_CONTEXT */
1da177e4 2017
f39878cc
PB		 2018static bool cpu_has_tlbex_tlbp_race(void)
2019{
2020 /*
2021 * When a Hardware Table Walker is running it can replace TLB entries
2022 * at any time, leading to a race between it & the CPU.
2023 */
2024 if (cpu_has_htw)
2025 return true;
2026
2027 /*
2028 * If the CPU shares FTLB RAM with its siblings then our entry may be
2029 * replaced at any time by a sibling performing a write to the FTLB.
2030 */
2031 if (cpu_has_shared_ftlb_ram)
2032 return true;
2033
2034 /* In all other cases there ought to be no race condition to handle */
2035 return false;
2036}
2037
1da177e4
LT		 2038/*
2039 * R4000 style TLB load/store/modify handlers.
2040 */
078a55fc 2041static struct work_registers
e30ec452 2042build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l,
bf28607f 2043 struct uasm_reloc **r)
1da177e4 2044{
bf28607f
DD		 2045 struct work_registers wr = build_get_work_registers(p);
2046
875d43e7 2047#ifdef CONFIG_64BIT
bf28607f 2048 build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */
1da177e4 2049#else
bf28607f 2050 build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */
1da177e4
LT		 2051#endif
2052
aa1762f4 2053#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
fd062c84
DD		 2054 /*
2055 * For huge tlb entries, pmd doesn't contain an address but
2056 * instead contains the tlb pte. Check the PAGE_HUGE bit and
2057 * see if we need to jump to huge tlb processing.
2058 */
bf28607f 2059 build_is_huge_pte(p, r, wr.r1, wr.r2, label_tlb_huge_update);
fd062c84
DD		 2060#endif
2061
bf28607f
DD		 2062 UASM_i_MFC0(p, wr.r1, C0_BADVADDR);
2063 UASM_i_LW(p, wr.r2, 0, wr.r2);
2064 UASM_i_SRL(p, wr.r1, wr.r1, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2);
2065 uasm_i_andi(p, wr.r1, wr.r1, (PTRS_PER_PTE - 1) << PTE_T_LOG2);
2066 UASM_i_ADDU(p, wr.r2, wr.r2, wr.r1);
1da177e4
LT		 2067
2068#ifdef CONFIG_SMP
e30ec452
TS		 2069 uasm_l_smp_pgtable_change(l, *p);
2070#endif
bf28607f 2071 iPTE_LW(p, wr.r1, wr.r2); /* get even pte */
070e76cb 2072 if (!m4kc_tlbp_war()) {
8df5beac 2073 build_tlb_probe_entry(p);
f39878cc 2074 if (cpu_has_tlbex_tlbp_race()) {
070e76cb
LY		 2075 /* race condition happens, leaving */
2076 uasm_i_ehb(p);
2077 uasm_i_mfc0(p, wr.r3, C0_INDEX);
2078 uasm_il_bltz(p, r, wr.r3, label_leave);
2079 uasm_i_nop(p);
2080 }
2081 }
bf28607f 2082 return wr;
1da177e4
LT		 2083}
2084
078a55fc 2085static void
e30ec452
TS		 2086build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l,
2087 struct uasm_reloc **r, unsigned int tmp,
1da177e4
LT		 2088 unsigned int ptr)
2089{
e30ec452
TS		 2090 uasm_i_ori(p, ptr, ptr, sizeof(pte_t));
2091 uasm_i_xori(p, ptr, ptr, sizeof(pte_t));
1da177e4
LT		 2092 build_update_entries(p, tmp, ptr);
2093 build_tlb_write_entry(p, l, r, tlb_indexed);
e30ec452 2094 uasm_l_leave(l, *p);
bf28607f 2095 build_restore_work_registers(p);
e30ec452 2096 uasm_i_eret(p); /* return from trap */
1da177e4 2097
875d43e7 2098#ifdef CONFIG_64BIT
1ec56329 2099 build_get_pgd_vmalloc64(p, l, r, tmp, ptr, not_refill);
1da177e4
LT		 2100#endif
2101}
2102
078a55fc 2103static void build_r4000_tlb_load_handler(void)
1da177e4 2104{
2c0e57ea 2105 u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbl);
6ba045f9 2106 const int handle_tlbl_size = handle_tlbl_end - handle_tlbl;
e30ec452
TS		 2107 struct uasm_label *l = labels;
2108 struct uasm_reloc *r = relocs;
bf28607f 2109 struct work_registers wr;
1da177e4 2110
6ba045f9 2111 memset(handle_tlbl, 0, handle_tlbl_size * sizeof(handle_tlbl[0]));
1da177e4
LT		 2112 memset(labels, 0, sizeof(labels));
2113 memset(relocs, 0, sizeof(relocs));
2114
2115 if (bcm1250_m3_war()) {
3d45285d
RB		 2116 unsigned int segbits = 44;
2117
2118 uasm_i_dmfc0(&p, K0, C0_BADVADDR);
2119 uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
e30ec452 2120 uasm_i_xor(&p, K0, K0, K1);
3be6022c
DD		 2121 uasm_i_dsrl_safe(&p, K1, K0, 62);
2122 uasm_i_dsrl_safe(&p, K0, K0, 12 + 1);
2123 uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits);
3d45285d 2124 uasm_i_or(&p, K0, K0, K1);
e30ec452
TS		 2125 uasm_il_bnez(&p, &r, K0, label_leave);
2126 /* No need for uasm_i_nop */
1da177e4
LT		 2127 }
2128
bf28607f
DD		 2129 wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
2130 build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl);
8df5beac
MR		 2131 if (m4kc_tlbp_war())
2132 build_tlb_probe_entry(&p);
6dd9344c 2133
5890f70f 2134 if (cpu_has_rixi && !cpu_has_rixiex) {
6dd9344c
DD		 2135 /*
2136 * If the page is not _PAGE_VALID, RI or XI could not
2137 * have triggered it. Skip the expensive test..
2138 */
cc33ae43 2139 if (use_bbit_insns()) {
bf28607f 2140 uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID),
cc33ae43
DD		 2141 label_tlbl_goaround1);
2142 } else {
bf28607f
DD		 2143 uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID);
2144 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround1);
cc33ae43 2145 }
6dd9344c
DD		 2146 uasm_i_nop(&p);
2147
f39878cc
PB		 2148 /*
2149 * Warn if something may race with us & replace the TLB entry
2150 * before we read it here. Everything with such races should
2151 * also have dedicated RiXi exception handlers, so this
2152 * shouldn't be hit.
2153 */
2154 WARN(cpu_has_tlbex_tlbp_race(), "Unhandled race in RiXi path");
2155
6dd9344c 2156 uasm_i_tlbr(&p);
73acc7df
RB		 2157
2158 switch (current_cpu_type()) {
2159 default:
77f3ee59 2160 if (cpu_has_mips_r2_exec_hazard) {
73acc7df
RB		 2161 uasm_i_ehb(&p);
2162
2163 case CPU_CAVIUM_OCTEON:
2164 case CPU_CAVIUM_OCTEON_PLUS:
2165 case CPU_CAVIUM_OCTEON2:
2166 break;
2167 }
2168 }
2169
6dd9344c 2170 /* Examine entrylo 0 or 1 based on ptr. */
cc33ae43 2171 if (use_bbit_insns()) {
bf28607f 2172 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
cc33ae43 2173 } else {
bf28607f
DD		 2174 uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t));
2175 uasm_i_beqz(&p, wr.r3, 8);
cc33ae43 2176 }
bf28607f
DD		 2177 /* load it in the delay slot*/
2178 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0);
2179 /* load it if ptr is odd */
2180 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1);
6dd9344c 2181 /*
bf28607f 2182 * If the entryLo (now in wr.r3) is valid (bit 1), RI or
6dd9344c
DD		 2183 * XI must have triggered it.
2184 */
cc33ae43 2185 if (use_bbit_insns()) {
bf28607f
DD		 2186 uasm_il_bbit1(&p, &r, wr.r3, 1, label_nopage_tlbl);
2187 uasm_i_nop(&p);
cc33ae43
DD		 2188 uasm_l_tlbl_goaround1(&l, p);
2189 } else {
bf28607f
DD		 2190 uasm_i_andi(&p, wr.r3, wr.r3, 2);
2191 uasm_il_bnez(&p, &r, wr.r3, label_nopage_tlbl);
2192 uasm_i_nop(&p);
cc33ae43 2193 }
bf28607f 2194 uasm_l_tlbl_goaround1(&l, p);
6dd9344c 2195 }
bbeeffec 2196 build_make_valid(&p, &r, wr.r1, wr.r2, wr.r3);
bf28607f 2197 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
1da177e4 2198
aa1762f4 2199#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
fd062c84
DD		 2200 /*
2201 * This is the entry point when build_r4000_tlbchange_handler_head
2202 * spots a huge page.
2203 */
2204 uasm_l_tlb_huge_update(&l, p);
bf28607f
DD		 2205 iPTE_LW(&p, wr.r1, wr.r2);
2206 build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl);
fd062c84 2207 build_tlb_probe_entry(&p);
6dd9344c 2208
5890f70f 2209 if (cpu_has_rixi && !cpu_has_rixiex) {
6dd9344c
DD		 2210 /*
2211 * If the page is not _PAGE_VALID, RI or XI could not
2212 * have triggered it. Skip the expensive test..
2213 */
cc33ae43 2214 if (use_bbit_insns()) {
bf28607f 2215 uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID),
cc33ae43
DD		 2216 label_tlbl_goaround2);
2217 } else {
bf28607f
DD		 2218 uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID);
2219 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2);
cc33ae43 2220 }
6dd9344c
DD		 2221 uasm_i_nop(&p);
2222
f39878cc
PB		 2223 /*
2224 * Warn if something may race with us & replace the TLB entry
2225 * before we read it here. Everything with such races should
2226 * also have dedicated RiXi exception handlers, so this
2227 * shouldn't be hit.
2228 */
2229 WARN(cpu_has_tlbex_tlbp_race(), "Unhandled race in RiXi path");
2230
6dd9344c 2231 uasm_i_tlbr(&p);
73acc7df
RB		 2232
2233 switch (current_cpu_type()) {
2234 default:
77f3ee59 2235 if (cpu_has_mips_r2_exec_hazard) {
73acc7df
RB		 2236 uasm_i_ehb(&p);
2237
2238 case CPU_CAVIUM_OCTEON:
2239 case CPU_CAVIUM_OCTEON_PLUS:
2240 case CPU_CAVIUM_OCTEON2:
2241 break;
2242 }
2243 }
2244
6dd9344c 2245 /* Examine entrylo 0 or 1 based on ptr. */
cc33ae43 2246 if (use_bbit_insns()) {
bf28607f 2247 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
cc33ae43 2248 } else {
bf28607f
DD		 2249 uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t));
2250 uasm_i_beqz(&p, wr.r3, 8);
cc33ae43 2251 }
bf28607f
DD		 2252 /* load it in the delay slot*/
2253 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0);
2254 /* load it if ptr is odd */
2255 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1);
6dd9344c 2256 /*
bf28607f 2257 * If the entryLo (now in wr.r3) is valid (bit 1), RI or
6dd9344c
DD		 2258 * XI must have triggered it.
2259 */
cc33ae43 2260 if (use_bbit_insns()) {
bf28607f 2261 uasm_il_bbit0(&p, &r, wr.r3, 1, label_tlbl_goaround2);
cc33ae43 2262 } else {
bf28607f
DD		 2263 uasm_i_andi(&p, wr.r3, wr.r3, 2);
2264 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2);
cc33ae43 2265 }
0f4ccbc8
DD		 2266 if (PM_DEFAULT_MASK == 0)
2267 uasm_i_nop(&p);
6dd9344c
DD		 2268 /*
2269 * We clobbered C0_PAGEMASK, restore it. On the other branch
2270 * it is restored in build_huge_tlb_write_entry.
2271 */
bf28607f 2272 build_restore_pagemask(&p, &r, wr.r3, label_nopage_tlbl, 0);
6dd9344c
DD		 2273
2274 uasm_l_tlbl_goaround2(&l, p);
2275 }
bf28607f 2276 uasm_i_ori(&p, wr.r1, wr.r1, (_PAGE_ACCESSED | _PAGE_VALID));
0115f6cb 2277 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 1);
fd062c84
DD		 2278#endif
2279
e30ec452 2280 uasm_l_nopage_tlbl(&l, p);
bf28607f 2281 build_restore_work_registers(&p);
2a0b24f5
SH		 2282#ifdef CONFIG_CPU_MICROMIPS
2283 if ((unsigned long)tlb_do_page_fault_0 & 1) {
2284 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_0));
2285 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_0));
2286 uasm_i_jr(&p, K0);
2287 } else
2288#endif
e30ec452
TS		 2289 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
2290 uasm_i_nop(&p);
1da177e4 2291
6ba045f9 2292 if (p >= handle_tlbl_end)
1da177e4
LT		 2293 panic("TLB load handler fastpath space exceeded");
2294
e30ec452
TS		 2295 uasm_resolve_relocs(relocs, labels);
2296 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n",
2297 (unsigned int)(p - handle_tlbl));
1da177e4 2298
6ba045f9 2299 dump_handler("r4000_tlb_load", handle_tlbl, handle_tlbl_size);
1da177e4
LT		 2300}
2301
078a55fc 2302static void build_r4000_tlb_store_handler(void)
1da177e4 2303{
2c0e57ea 2304 u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbs);
6ba045f9 2305 const int handle_tlbs_size = handle_tlbs_end - handle_tlbs;
e30ec452
TS		 2306 struct uasm_label *l = labels;
2307 struct uasm_reloc *r = relocs;
bf28607f 2308 struct work_registers wr;
1da177e4 2309
6ba045f9 2310 memset(handle_tlbs, 0, handle_tlbs_size * sizeof(handle_tlbs[0]));
1da177e4
LT		 2311 memset(labels, 0, sizeof(labels));
2312 memset(relocs, 0, sizeof(relocs));
2313
bf28607f
DD		 2314 wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
2315 build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs);
8df5beac
MR		 2316 if (m4kc_tlbp_war())
2317 build_tlb_probe_entry(&p);
bbeeffec 2318 build_make_write(&p, &r, wr.r1, wr.r2, wr.r3);
bf28607f 2319 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
1da177e4 2320
aa1762f4 2321#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
fd062c84
DD		 2322 /*
2323 * This is the entry point when
2324 * build_r4000_tlbchange_handler_head spots a huge page.
2325 */
2326 uasm_l_tlb_huge_update(&l, p);
bf28607f
DD		 2327 iPTE_LW(&p, wr.r1, wr.r2);
2328 build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs);
fd062c84 2329 build_tlb_probe_entry(&p);
bf28607f 2330 uasm_i_ori(&p, wr.r1, wr.r1,
fd062c84 2331 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY);
0115f6cb 2332 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 1);
fd062c84
DD		 2333#endif
2334
e30ec452 2335 uasm_l_nopage_tlbs(&l, p);
bf28607f 2336 build_restore_work_registers(&p);
2a0b24f5
SH		 2337#ifdef CONFIG_CPU_MICROMIPS
2338 if ((unsigned long)tlb_do_page_fault_1 & 1) {
2339 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1));
2340 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1));
2341 uasm_i_jr(&p, K0);
2342 } else
2343#endif
e30ec452
TS		 2344 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
2345 uasm_i_nop(&p);
1da177e4 2346
6ba045f9 2347 if (p >= handle_tlbs_end)
1da177e4
LT		 2348 panic("TLB store handler fastpath space exceeded");
2349
e30ec452
TS		 2350 uasm_resolve_relocs(relocs, labels);
2351 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n",
2352 (unsigned int)(p - handle_tlbs));
1da177e4 2353
6ba045f9 2354 dump_handler("r4000_tlb_store", handle_tlbs, handle_tlbs_size);
1da177e4
LT		 2355}
2356
078a55fc 2357static void build_r4000_tlb_modify_handler(void)
1da177e4 2358{
2c0e57ea 2359 u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbm);
6ba045f9 2360 const int handle_tlbm_size = handle_tlbm_end - handle_tlbm;
e30ec452
TS		 2361 struct uasm_label *l = labels;
2362 struct uasm_reloc *r = relocs;
bf28607f 2363 struct work_registers wr;
1da177e4 2364
6ba045f9 2365 memset(handle_tlbm, 0, handle_tlbm_size * sizeof(handle_tlbm[0]));
1da177e4
LT		 2366 memset(labels, 0, sizeof(labels));
2367 memset(relocs, 0, sizeof(relocs));
2368
bf28607f
DD		 2369 wr = build_r4000_tlbchange_handler_head(&p, &l, &r);
2370 build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm);
8df5beac
MR		 2371 if (m4kc_tlbp_war())
2372 build_tlb_probe_entry(&p);
1da177e4 2373 /* Present and writable bits set, set accessed and dirty bits. */
bbeeffec 2374 build_make_write(&p, &r, wr.r1, wr.r2, wr.r3);
bf28607f 2375 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2);
1da177e4 2376
aa1762f4 2377#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
fd062c84
DD		 2378 /*
2379 * This is the entry point when
2380 * build_r4000_tlbchange_handler_head spots a huge page.
2381 */
2382 uasm_l_tlb_huge_update(&l, p);
bf28607f
DD		 2383 iPTE_LW(&p, wr.r1, wr.r2);
2384 build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm);
fd062c84 2385 build_tlb_probe_entry(&p);
bf28607f 2386 uasm_i_ori(&p, wr.r1, wr.r1,
fd062c84 2387 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY);
0115f6cb 2388 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 0);
fd062c84
DD		 2389#endif
2390
e30ec452 2391 uasm_l_nopage_tlbm(&l, p);
bf28607f 2392 build_restore_work_registers(&p);
2a0b24f5
SH		 2393#ifdef CONFIG_CPU_MICROMIPS
2394 if ((unsigned long)tlb_do_page_fault_1 & 1) {
2395 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1));
2396 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1));
2397 uasm_i_jr(&p, K0);
2398 } else
2399#endif
e30ec452
TS		 2400 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
2401 uasm_i_nop(&p);
1da177e4 2402
6ba045f9 2403 if (p >= handle_tlbm_end)
1da177e4
LT		 2404 panic("TLB modify handler fastpath space exceeded");
2405
e30ec452
TS		 2406 uasm_resolve_relocs(relocs, labels);
2407 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n",
2408 (unsigned int)(p - handle_tlbm));
115f2a44 2409
6ba045f9 2410 dump_handler("r4000_tlb_modify", handle_tlbm, handle_tlbm_size);
1da177e4
LT		 2411}
2412
078a55fc 2413static void flush_tlb_handlers(void)
a3d9086b
JG		 2414{
2415 local_flush_icache_range((unsigned long)handle_tlbl,
6ac5310e 2416 (unsigned long)handle_tlbl_end);
a3d9086b 2417 local_flush_icache_range((unsigned long)handle_tlbs,
6ac5310e 2418 (unsigned long)handle_tlbs_end);
a3d9086b 2419 local_flush_icache_range((unsigned long)handle_tlbm,
6ac5310e 2420 (unsigned long)handle_tlbm_end);
6ac5310e
RB		 2421 local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd,
2422 (unsigned long)tlbmiss_handler_setup_pgd_end);
a3d9086b
JG		 2423}
2424
f1014d1b
MC		 2425static void print_htw_config(void)
2426{
2427 unsigned long config;
2428 unsigned int pwctl;
2429 const int field = 2 * sizeof(unsigned long);
2430
2431 config = read_c0_pwfield();
2432 pr_debug("PWField (0x%0*lx): GDI: 0x%02lx UDI: 0x%02lx MDI: 0x%02lx PTI: 0x%02lx PTEI: 0x%02lx\n",
2433 field, config,
2434 (config & MIPS_PWFIELD_GDI_MASK) >> MIPS_PWFIELD_GDI_SHIFT,
2435 (config & MIPS_PWFIELD_UDI_MASK) >> MIPS_PWFIELD_UDI_SHIFT,
2436 (config & MIPS_PWFIELD_MDI_MASK) >> MIPS_PWFIELD_MDI_SHIFT,
2437 (config & MIPS_PWFIELD_PTI_MASK) >> MIPS_PWFIELD_PTI_SHIFT,
2438 (config & MIPS_PWFIELD_PTEI_MASK) >> MIPS_PWFIELD_PTEI_SHIFT);
2439
2440 config = read_c0_pwsize();
6446e6cf 2441 pr_debug("PWSize (0x%0*lx): PS: 0x%lx GDW: 0x%02lx UDW: 0x%02lx MDW: 0x%02lx PTW: 0x%02lx PTEW: 0x%02lx\n",
f1014d1b 2442 field, config,
6446e6cf 2443 (config & MIPS_PWSIZE_PS_MASK) >> MIPS_PWSIZE_PS_SHIFT,
f1014d1b
MC		 2444 (config & MIPS_PWSIZE_GDW_MASK) >> MIPS_PWSIZE_GDW_SHIFT,
2445 (config & MIPS_PWSIZE_UDW_MASK) >> MIPS_PWSIZE_UDW_SHIFT,
2446 (config & MIPS_PWSIZE_MDW_MASK) >> MIPS_PWSIZE_MDW_SHIFT,
2447 (config & MIPS_PWSIZE_PTW_MASK) >> MIPS_PWSIZE_PTW_SHIFT,
2448 (config & MIPS_PWSIZE_PTEW_MASK) >> MIPS_PWSIZE_PTEW_SHIFT);
2449
2450 pwctl = read_c0_pwctl();
6446e6cf 2451 pr_debug("PWCtl (0x%x): PWEn: 0x%x XK: 0x%x XS: 0x%x XU: 0x%x DPH: 0x%x HugePg: 0x%x Psn: 0x%x\n",
f1014d1b
MC		 2452 pwctl,
2453 (pwctl & MIPS_PWCTL_PWEN_MASK) >> MIPS_PWCTL_PWEN_SHIFT,
6446e6cf
JH		 2454 (pwctl & MIPS_PWCTL_XK_MASK) >> MIPS_PWCTL_XK_SHIFT,
2455 (pwctl & MIPS_PWCTL_XS_MASK) >> MIPS_PWCTL_XS_SHIFT,
2456 (pwctl & MIPS_PWCTL_XU_MASK) >> MIPS_PWCTL_XU_SHIFT,
f1014d1b
MC		 2457 (pwctl & MIPS_PWCTL_DPH_MASK) >> MIPS_PWCTL_DPH_SHIFT,
2458 (pwctl & MIPS_PWCTL_HUGEPG_MASK) >> MIPS_PWCTL_HUGEPG_SHIFT,
2459 (pwctl & MIPS_PWCTL_PSN_MASK) >> MIPS_PWCTL_PSN_SHIFT);
2460}
2461
2462static void config_htw_params(void)
2463{
2464 unsigned long pwfield, pwsize, ptei;
2465 unsigned int config;
2466
2467 /*
2468 * We are using 2-level page tables, so we only need to
2469 * setup GDW and PTW appropriately. UDW and MDW will remain 0.
2470 * The default value of GDI/UDI/MDI/PTI is 0xc. It is illegal to
2471 * write values less than 0xc in these fields because the entire
2472 * write will be dropped. As a result of which, we must preserve
2473 * the original reset values and overwrite only what we really want.
2474 */
2475
2476 pwfield = read_c0_pwfield();
2477 /* re-initialize the GDI field */
2478 pwfield &= ~MIPS_PWFIELD_GDI_MASK;
2479 pwfield |= PGDIR_SHIFT << MIPS_PWFIELD_GDI_SHIFT;
2480 /* re-initialize the PTI field including the even/odd bit */
2481 pwfield &= ~MIPS_PWFIELD_PTI_MASK;
2482 pwfield |= PAGE_SHIFT << MIPS_PWFIELD_PTI_SHIFT;
cab25bc7
PB		 2483 if (CONFIG_PGTABLE_LEVELS >= 3) {
2484 pwfield &= ~MIPS_PWFIELD_MDI_MASK;
2485 pwfield |= PMD_SHIFT << MIPS_PWFIELD_MDI_SHIFT;
2486 }
f1014d1b
MC		 2487 /* Set the PTEI right shift */
2488 ptei = _PAGE_GLOBAL_SHIFT << MIPS_PWFIELD_PTEI_SHIFT;
2489 pwfield |= ptei;
2490 write_c0_pwfield(pwfield);
2491 /* Check whether the PTEI value is supported */
2492 back_to_back_c0_hazard();
2493 pwfield = read_c0_pwfield();
2494 if (((pwfield & MIPS_PWFIELD_PTEI_MASK) << MIPS_PWFIELD_PTEI_SHIFT)
2495 != ptei) {
2496 pr_warn("Unsupported PTEI field value: 0x%lx. HTW will not be enabled",
2497 ptei);
2498 /*
2499 * Drop option to avoid HTW being enabled via another path
2500 * (eg htw_reset())
2501 */
2502 current_cpu_data.options &= ~MIPS_CPU_HTW;
2503 return;
2504 }
2505
2506 pwsize = ilog2(PTRS_PER_PGD) << MIPS_PWSIZE_GDW_SHIFT;
2507 pwsize |= ilog2(PTRS_PER_PTE) << MIPS_PWSIZE_PTW_SHIFT;
cab25bc7
PB		 2508 if (CONFIG_PGTABLE_LEVELS >= 3)
2509 pwsize |= ilog2(PTRS_PER_PMD) << MIPS_PWSIZE_MDW_SHIFT;
c5b36783 2510
aa76042a 2511 /* Set pointer size to size of directory pointers */
97f2645f 2512 if (IS_ENABLED(CONFIG_64BIT))
aa76042a
JH		 2513 pwsize |= MIPS_PWSIZE_PS_MASK;
2514 /* PTEs may be multiple pointers long (e.g. with XPA) */
2515 pwsize |= ((PTE_T_LOG2 - PGD_T_LOG2) << MIPS_PWSIZE_PTEW_SHIFT)
2516 & MIPS_PWSIZE_PTEW_MASK;
c5b36783 2517
f1014d1b
MC		 2518 write_c0_pwsize(pwsize);
2519
2520 /* Make sure everything is set before we enable the HTW */
2521 back_to_back_c0_hazard();
2522
aa76042a
JH		 2523 /*
2524 * Enable HTW (and only for XUSeg on 64-bit), and disable the rest of
2525 * the pwctl fields.
2526 */
f1014d1b 2527 config = 1 << MIPS_PWCTL_PWEN_SHIFT;
97f2645f 2528 if (IS_ENABLED(CONFIG_64BIT))
aa76042a 2529 config |= MIPS_PWCTL_XU_MASK;
f1014d1b
MC		 2530 write_c0_pwctl(config);
2531 pr_info("Hardware Page Table Walker enabled\n");
2532
2533 print_htw_config();
2534}
2535
c5b36783
SH		 2536static void config_xpa_params(void)
2537{
2538#ifdef CONFIG_XPA
2539 unsigned int pagegrain;
2540
2541 if (mips_xpa_disabled) {
2542 pr_info("Extended Physical Addressing (XPA) disabled\n");
2543 return;
2544 }
2545
2546 pagegrain = read_c0_pagegrain();
2547 write_c0_pagegrain(pagegrain | PG_ELPA);
2548 back_to_back_c0_hazard();
2549 pagegrain = read_c0_pagegrain();
2550
2551 if (pagegrain & PG_ELPA)
2552 pr_info("Extended Physical Addressing (XPA) enabled\n");
2553 else
2554 panic("Extended Physical Addressing (XPA) disabled");
2555#endif
2556}
2557
00bf1c69
PB		 2558static void check_pabits(void)
2559{
2560 unsigned long entry;
2561 unsigned pabits, fillbits;
2562
2563 if (!cpu_has_rixi || !_PAGE_NO_EXEC) {
2564 /*
2565 * We'll only be making use of the fact that we can rotate bits
2566 * into the fill if the CPU supports RIXI, so don't bother
2567 * probing this for CPUs which don't.
2568 */
2569 return;
2570 }
2571
2572 write_c0_entrylo0(~0ul);
2573 back_to_back_c0_hazard();
2574 entry = read_c0_entrylo0();
2575
2576 /* clear all non-PFN bits */
2577 entry &= ~((1 << MIPS_ENTRYLO_PFN_SHIFT) - 1);
2578 entry &= ~(MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI);
2579
2580 /* find a lower bound on PABITS, and upper bound on fill bits */
2581 pabits = fls_long(entry) + 6;
2582 fillbits = max_t(int, (int)BITS_PER_LONG - pabits, 0);
2583
2584 /* minus the RI & XI bits */
2585 fillbits -= min_t(unsigned, fillbits, 2);
2586
2587 if (fillbits >= ilog2(_PAGE_NO_EXEC))
2588 fill_includes_sw_bits = true;
2589
2590 pr_debug("Entry* registers contain %u fill bits\n", fillbits);
2591}
2592
078a55fc 2593void build_tlb_refill_handler(void)
1da177e4
LT		 2594{
2595 /*
2596 * The refill handler is generated per-CPU, multi-node systems
2597 * may have local storage for it. The other handlers are only
2598 * needed once.
2599 */
2600 static int run_once = 0;
2601
97f2645f 2602 if (IS_ENABLED(CONFIG_XPA) && !cpu_has_rixi)
e56c7e18
PB		 2603 panic("Kernels supporting XPA currently require CPUs with RIXI");
2604
a2c763e0 2605 output_pgtable_bits_defines();
00bf1c69 2606 check_pabits();
a2c763e0 2607
1ec56329
DD		 2608#ifdef CONFIG_64BIT
2609 check_for_high_segbits = current_cpu_data.vmbits > (PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3);
2610#endif
2611
10cc3529 2612 switch (current_cpu_type()) {
1da177e4
LT		 2613 case CPU_R2000:
2614 case CPU_R3000:
2615 case CPU_R3000A:
2616 case CPU_R3081E:
2617 case CPU_TX3912:
2618 case CPU_TX3922:
2619 case CPU_TX3927:
82622284 2620#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
8759934e
HC		 2621 if (cpu_has_local_ebase)
2622 build_r3000_tlb_refill_handler();
1da177e4 2623 if (!run_once) {
8759934e
HC		 2624 if (!cpu_has_local_ebase)
2625 build_r3000_tlb_refill_handler();
f4ae17aa 2626 build_setup_pgd();
1da177e4
LT		 2627 build_r3000_tlb_load_handler();
2628 build_r3000_tlb_store_handler();
2629 build_r3000_tlb_modify_handler();
a3d9086b 2630 flush_tlb_handlers();
1da177e4
LT		 2631 run_once++;
2632 }
82622284
DD		 2633#else
2634 panic("No R3000 TLB refill handler");
2635#endif
1da177e4
LT		 2636 break;
2637
2638 case CPU_R6000:
2639 case CPU_R6000A:
2640 panic("No R6000 TLB refill handler yet");
2641 break;
2642
2643 case CPU_R8000:
2644 panic("No R8000 TLB refill handler yet");
2645 break;
2646
2647 default:
380cd582
HC		 2648 if (cpu_has_ldpte)
2649 setup_pw();
2650
1da177e4 2651 if (!run_once) {
bf28607f 2652 scratch_reg = allocate_kscratch();
f4ae17aa 2653 build_setup_pgd();
1da177e4
LT		 2654 build_r4000_tlb_load_handler();
2655 build_r4000_tlb_store_handler();
2656 build_r4000_tlb_modify_handler();
380cd582
HC		 2657 if (cpu_has_ldpte)
2658 build_loongson3_tlb_refill_handler();
2659 else if (!cpu_has_local_ebase)
8759934e 2660 build_r4000_tlb_refill_handler();
a3d9086b 2661 flush_tlb_handlers();
1da177e4
LT		 2662 run_once++;
2663 }
8759934e
HC		 2664 if (cpu_has_local_ebase)
2665 build_r4000_tlb_refill_handler();
c5b36783
SH		 2666 if (cpu_has_xpa)
2667 config_xpa_params();
f1014d1b
MC		 2668 if (cpu_has_htw)
2669 config_htw_params();
1da177e4
LT		 2670 }
2671}
Linux 6.x block layer and io_uring tree(s)