Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Synthesize TLB refill handlers at runtime. | |
7 | * | |
e30ec452 | 8 | * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer |
619b6e18 | 9 | * Copyright (C) 2005, 2007 Maciej W. Rozycki |
41c594ab RB |
10 | * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) |
11 | * | |
12 | * ... and the days got worse and worse and now you see | |
13 | * I've gone completly out of my mind. | |
14 | * | |
15 | * They're coming to take me a away haha | |
16 | * they're coming to take me a away hoho hihi haha | |
17 | * to the funny farm where code is beautiful all the time ... | |
18 | * | |
19 | * (Condolences to Napoleon XIV) | |
1da177e4 LT |
20 | */ |
21 | ||
1da177e4 LT |
22 | #include <linux/kernel.h> |
23 | #include <linux/types.h> | |
24 | #include <linux/string.h> | |
25 | #include <linux/init.h> | |
26 | ||
1da177e4 | 27 | #include <asm/mmu_context.h> |
1da177e4 LT |
28 | #include <asm/war.h> |
29 | ||
e30ec452 TS |
30 | #include "uasm.h" |
31 | ||
aeffdbba | 32 | static inline int r45k_bvahwbug(void) |
1da177e4 LT |
33 | { |
34 | /* XXX: We should probe for the presence of this bug, but we don't. */ | |
35 | return 0; | |
36 | } | |
37 | ||
aeffdbba | 38 | static inline int r4k_250MHZhwbug(void) |
1da177e4 LT |
39 | { |
40 | /* XXX: We should probe for the presence of this bug, but we don't. */ | |
41 | return 0; | |
42 | } | |
43 | ||
aeffdbba | 44 | static inline int __maybe_unused bcm1250_m3_war(void) |
1da177e4 LT |
45 | { |
46 | return BCM1250_M3_WAR; | |
47 | } | |
48 | ||
aeffdbba | 49 | static inline int __maybe_unused r10000_llsc_war(void) |
1da177e4 LT |
50 | { |
51 | return R10000_LLSC_WAR; | |
52 | } | |
53 | ||
8df5beac MR |
54 | /* |
55 | * Found by experiment: At least some revisions of the 4kc throw under | |
56 | * some circumstances a machine check exception, triggered by invalid | |
57 | * values in the index register. Delaying the tlbp instruction until | |
58 | * after the next branch, plus adding an additional nop in front of | |
59 | * tlbwi/tlbwr avoids the invalid index register values. Nobody knows | |
60 | * why; it's not an issue caused by the core RTL. | |
61 | * | |
62 | */ | |
234fcd14 | 63 | static int __cpuinit m4kc_tlbp_war(void) |
8df5beac MR |
64 | { |
65 | return (current_cpu_data.processor_id & 0xffff00) == | |
66 | (PRID_COMP_MIPS | PRID_IMP_4KC); | |
67 | } | |
68 | ||
e30ec452 | 69 | /* Handle labels (which must be positive integers). */ |
1da177e4 | 70 | enum label_id { |
e30ec452 | 71 | label_second_part = 1, |
1da177e4 | 72 | label_leave, |
656be92f AN |
73 | #ifdef MODULE_START |
74 | label_module_alloc, | |
75 | #endif | |
1da177e4 LT |
76 | label_vmalloc, |
77 | label_vmalloc_done, | |
78 | label_tlbw_hazard, | |
79 | label_split, | |
80 | label_nopage_tlbl, | |
81 | label_nopage_tlbs, | |
82 | label_nopage_tlbm, | |
83 | label_smp_pgtable_change, | |
84 | label_r3000_write_probe_fail, | |
1da177e4 LT |
85 | }; |
86 | ||
e30ec452 TS |
87 | UASM_L_LA(_second_part) |
88 | UASM_L_LA(_leave) | |
656be92f | 89 | #ifdef MODULE_START |
e30ec452 | 90 | UASM_L_LA(_module_alloc) |
619b6e18 | 91 | #endif |
e30ec452 TS |
92 | UASM_L_LA(_vmalloc) |
93 | UASM_L_LA(_vmalloc_done) | |
94 | UASM_L_LA(_tlbw_hazard) | |
95 | UASM_L_LA(_split) | |
96 | UASM_L_LA(_nopage_tlbl) | |
97 | UASM_L_LA(_nopage_tlbs) | |
98 | UASM_L_LA(_nopage_tlbm) | |
99 | UASM_L_LA(_smp_pgtable_change) | |
100 | UASM_L_LA(_r3000_write_probe_fail) | |
656be92f | 101 | |
92b1e6a6 FBH |
102 | /* |
103 | * For debug purposes. | |
104 | */ | |
105 | static inline void dump_handler(const u32 *handler, int count) | |
106 | { | |
107 | int i; | |
108 | ||
109 | pr_debug("\t.set push\n"); | |
110 | pr_debug("\t.set noreorder\n"); | |
111 | ||
112 | for (i = 0; i < count; i++) | |
113 | pr_debug("\t%p\t.word 0x%08x\n", &handler[i], handler[i]); | |
114 | ||
115 | pr_debug("\t.set pop\n"); | |
116 | } | |
117 | ||
1da177e4 LT |
118 | /* The only general purpose registers allowed in TLB handlers. */ |
119 | #define K0 26 | |
120 | #define K1 27 | |
121 | ||
122 | /* Some CP0 registers */ | |
41c594ab RB |
123 | #define C0_INDEX 0, 0 |
124 | #define C0_ENTRYLO0 2, 0 | |
125 | #define C0_TCBIND 2, 2 | |
126 | #define C0_ENTRYLO1 3, 0 | |
127 | #define C0_CONTEXT 4, 0 | |
128 | #define C0_BADVADDR 8, 0 | |
129 | #define C0_ENTRYHI 10, 0 | |
130 | #define C0_EPC 14, 0 | |
131 | #define C0_XCONTEXT 20, 0 | |
1da177e4 | 132 | |
875d43e7 | 133 | #ifdef CONFIG_64BIT |
e30ec452 | 134 | # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT) |
1da177e4 | 135 | #else |
e30ec452 | 136 | # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT) |
1da177e4 LT |
137 | #endif |
138 | ||
139 | /* The worst case length of the handler is around 18 instructions for | |
140 | * R3000-style TLBs and up to 63 instructions for R4000-style TLBs. | |
141 | * Maximum space available is 32 instructions for R3000 and 64 | |
142 | * instructions for R4000. | |
143 | * | |
144 | * We deliberately chose a buffer size of 128, so we won't scribble | |
145 | * over anything important on overflow before we panic. | |
146 | */ | |
234fcd14 | 147 | static u32 tlb_handler[128] __cpuinitdata; |
1da177e4 LT |
148 | |
149 | /* simply assume worst case size for labels and relocs */ | |
234fcd14 RB |
150 | static struct uasm_label labels[128] __cpuinitdata; |
151 | static struct uasm_reloc relocs[128] __cpuinitdata; | |
1da177e4 LT |
152 | |
153 | /* | |
154 | * The R3000 TLB handler is simple. | |
155 | */ | |
234fcd14 | 156 | static void __cpuinit build_r3000_tlb_refill_handler(void) |
1da177e4 LT |
157 | { |
158 | long pgdc = (long)pgd_current; | |
159 | u32 *p; | |
160 | ||
161 | memset(tlb_handler, 0, sizeof(tlb_handler)); | |
162 | p = tlb_handler; | |
163 | ||
e30ec452 TS |
164 | uasm_i_mfc0(&p, K0, C0_BADVADDR); |
165 | uasm_i_lui(&p, K1, uasm_rel_hi(pgdc)); /* cp0 delay */ | |
166 | uasm_i_lw(&p, K1, uasm_rel_lo(pgdc), K1); | |
167 | uasm_i_srl(&p, K0, K0, 22); /* load delay */ | |
168 | uasm_i_sll(&p, K0, K0, 2); | |
169 | uasm_i_addu(&p, K1, K1, K0); | |
170 | uasm_i_mfc0(&p, K0, C0_CONTEXT); | |
171 | uasm_i_lw(&p, K1, 0, K1); /* cp0 delay */ | |
172 | uasm_i_andi(&p, K0, K0, 0xffc); /* load delay */ | |
173 | uasm_i_addu(&p, K1, K1, K0); | |
174 | uasm_i_lw(&p, K0, 0, K1); | |
175 | uasm_i_nop(&p); /* load delay */ | |
176 | uasm_i_mtc0(&p, K0, C0_ENTRYLO0); | |
177 | uasm_i_mfc0(&p, K1, C0_EPC); /* cp0 delay */ | |
178 | uasm_i_tlbwr(&p); /* cp0 delay */ | |
179 | uasm_i_jr(&p, K1); | |
180 | uasm_i_rfe(&p); /* branch delay */ | |
1da177e4 LT |
181 | |
182 | if (p > tlb_handler + 32) | |
183 | panic("TLB refill handler space exceeded"); | |
184 | ||
e30ec452 TS |
185 | pr_debug("Wrote TLB refill handler (%u instructions).\n", |
186 | (unsigned int)(p - tlb_handler)); | |
1da177e4 | 187 | |
91b05e67 | 188 | memcpy((void *)ebase, tlb_handler, 0x80); |
92b1e6a6 FBH |
189 | |
190 | dump_handler((u32 *)ebase, 32); | |
1da177e4 LT |
191 | } |
192 | ||
193 | /* | |
194 | * The R4000 TLB handler is much more complicated. We have two | |
195 | * consecutive handler areas with 32 instructions space each. | |
196 | * Since they aren't used at the same time, we can overflow in the | |
197 | * other one.To keep things simple, we first assume linear space, | |
198 | * then we relocate it to the final handler layout as needed. | |
199 | */ | |
234fcd14 | 200 | static u32 final_handler[64] __cpuinitdata; |
1da177e4 LT |
201 | |
202 | /* | |
203 | * Hazards | |
204 | * | |
205 | * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0: | |
206 | * 2. A timing hazard exists for the TLBP instruction. | |
207 | * | |
208 | * stalling_instruction | |
209 | * TLBP | |
210 | * | |
211 | * The JTLB is being read for the TLBP throughout the stall generated by the | |
212 | * previous instruction. This is not really correct as the stalling instruction | |
213 | * can modify the address used to access the JTLB. The failure symptom is that | |
214 | * the TLBP instruction will use an address created for the stalling instruction | |
215 | * and not the address held in C0_ENHI and thus report the wrong results. | |
216 | * | |
217 | * The software work-around is to not allow the instruction preceding the TLBP | |
218 | * to stall - make it an NOP or some other instruction guaranteed not to stall. | |
219 | * | |
220 | * Errata 2 will not be fixed. This errata is also on the R5000. | |
221 | * | |
222 | * As if we MIPS hackers wouldn't know how to nop pipelines happy ... | |
223 | */ | |
234fcd14 | 224 | static void __cpuinit __maybe_unused build_tlb_probe_entry(u32 **p) |
1da177e4 | 225 | { |
10cc3529 | 226 | switch (current_cpu_type()) { |
326e2e1a | 227 | /* Found by experiment: R4600 v2.0/R4700 needs this, too. */ |
f5b4d956 | 228 | case CPU_R4600: |
326e2e1a | 229 | case CPU_R4700: |
1da177e4 LT |
230 | case CPU_R5000: |
231 | case CPU_R5000A: | |
232 | case CPU_NEVADA: | |
e30ec452 TS |
233 | uasm_i_nop(p); |
234 | uasm_i_tlbp(p); | |
1da177e4 LT |
235 | break; |
236 | ||
237 | default: | |
e30ec452 | 238 | uasm_i_tlbp(p); |
1da177e4 LT |
239 | break; |
240 | } | |
241 | } | |
242 | ||
243 | /* | |
244 | * Write random or indexed TLB entry, and care about the hazards from | |
245 | * the preceeding mtc0 and for the following eret. | |
246 | */ | |
247 | enum tlb_write_entry { tlb_random, tlb_indexed }; | |
248 | ||
234fcd14 | 249 | static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, |
e30ec452 | 250 | struct uasm_reloc **r, |
1da177e4 LT |
251 | enum tlb_write_entry wmode) |
252 | { | |
253 | void(*tlbw)(u32 **) = NULL; | |
254 | ||
255 | switch (wmode) { | |
e30ec452 TS |
256 | case tlb_random: tlbw = uasm_i_tlbwr; break; |
257 | case tlb_indexed: tlbw = uasm_i_tlbwi; break; | |
1da177e4 LT |
258 | } |
259 | ||
161548bf | 260 | if (cpu_has_mips_r2) { |
e30ec452 | 261 | uasm_i_ehb(p); |
161548bf RB |
262 | tlbw(p); |
263 | return; | |
264 | } | |
265 | ||
10cc3529 | 266 | switch (current_cpu_type()) { |
1da177e4 LT |
267 | case CPU_R4000PC: |
268 | case CPU_R4000SC: | |
269 | case CPU_R4000MC: | |
270 | case CPU_R4400PC: | |
271 | case CPU_R4400SC: | |
272 | case CPU_R4400MC: | |
273 | /* | |
274 | * This branch uses up a mtc0 hazard nop slot and saves | |
275 | * two nops after the tlbw instruction. | |
276 | */ | |
e30ec452 | 277 | uasm_il_bgezl(p, r, 0, label_tlbw_hazard); |
1da177e4 | 278 | tlbw(p); |
e30ec452 TS |
279 | uasm_l_tlbw_hazard(l, *p); |
280 | uasm_i_nop(p); | |
1da177e4 LT |
281 | break; |
282 | ||
283 | case CPU_R4600: | |
284 | case CPU_R4700: | |
285 | case CPU_R5000: | |
286 | case CPU_R5000A: | |
e30ec452 | 287 | uasm_i_nop(p); |
2c93e12c | 288 | tlbw(p); |
e30ec452 | 289 | uasm_i_nop(p); |
2c93e12c MR |
290 | break; |
291 | ||
292 | case CPU_R4300: | |
1da177e4 LT |
293 | case CPU_5KC: |
294 | case CPU_TX49XX: | |
295 | case CPU_AU1000: | |
296 | case CPU_AU1100: | |
297 | case CPU_AU1500: | |
298 | case CPU_AU1550: | |
e3ad1c23 | 299 | case CPU_AU1200: |
237cfee1 ML |
300 | case CPU_AU1210: |
301 | case CPU_AU1250: | |
bdf21b18 | 302 | case CPU_PR4450: |
e30ec452 | 303 | uasm_i_nop(p); |
1da177e4 LT |
304 | tlbw(p); |
305 | break; | |
306 | ||
307 | case CPU_R10000: | |
308 | case CPU_R12000: | |
44d921b2 | 309 | case CPU_R14000: |
1da177e4 | 310 | case CPU_4KC: |
b1ec4c8e | 311 | case CPU_4KEC: |
1da177e4 | 312 | case CPU_SB1: |
93ce2f52 | 313 | case CPU_SB1A: |
1da177e4 LT |
314 | case CPU_4KSC: |
315 | case CPU_20KC: | |
316 | case CPU_25KF: | |
1c0c13eb AJ |
317 | case CPU_BCM3302: |
318 | case CPU_BCM4710: | |
2a21c730 | 319 | case CPU_LOONGSON2: |
ec454d8c | 320 | case CPU_CAVIUM_OCTEON: |
8df5beac | 321 | if (m4kc_tlbp_war()) |
e30ec452 | 322 | uasm_i_nop(p); |
1da177e4 LT |
323 | tlbw(p); |
324 | break; | |
325 | ||
326 | case CPU_NEVADA: | |
e30ec452 | 327 | uasm_i_nop(p); /* QED specifies 2 nops hazard */ |
1da177e4 LT |
328 | /* |
329 | * This branch uses up a mtc0 hazard nop slot and saves | |
330 | * a nop after the tlbw instruction. | |
331 | */ | |
e30ec452 | 332 | uasm_il_bgezl(p, r, 0, label_tlbw_hazard); |
1da177e4 | 333 | tlbw(p); |
e30ec452 | 334 | uasm_l_tlbw_hazard(l, *p); |
1da177e4 LT |
335 | break; |
336 | ||
337 | case CPU_RM7000: | |
e30ec452 TS |
338 | uasm_i_nop(p); |
339 | uasm_i_nop(p); | |
340 | uasm_i_nop(p); | |
341 | uasm_i_nop(p); | |
1da177e4 LT |
342 | tlbw(p); |
343 | break; | |
344 | ||
1da177e4 LT |
345 | case CPU_RM9000: |
346 | /* | |
347 | * When the JTLB is updated by tlbwi or tlbwr, a subsequent | |
348 | * use of the JTLB for instructions should not occur for 4 | |
349 | * cpu cycles and use for data translations should not occur | |
350 | * for 3 cpu cycles. | |
351 | */ | |
e30ec452 TS |
352 | uasm_i_ssnop(p); |
353 | uasm_i_ssnop(p); | |
354 | uasm_i_ssnop(p); | |
355 | uasm_i_ssnop(p); | |
1da177e4 | 356 | tlbw(p); |
e30ec452 TS |
357 | uasm_i_ssnop(p); |
358 | uasm_i_ssnop(p); | |
359 | uasm_i_ssnop(p); | |
360 | uasm_i_ssnop(p); | |
1da177e4 LT |
361 | break; |
362 | ||
363 | case CPU_VR4111: | |
364 | case CPU_VR4121: | |
365 | case CPU_VR4122: | |
366 | case CPU_VR4181: | |
367 | case CPU_VR4181A: | |
e30ec452 TS |
368 | uasm_i_nop(p); |
369 | uasm_i_nop(p); | |
1da177e4 | 370 | tlbw(p); |
e30ec452 TS |
371 | uasm_i_nop(p); |
372 | uasm_i_nop(p); | |
1da177e4 LT |
373 | break; |
374 | ||
375 | case CPU_VR4131: | |
376 | case CPU_VR4133: | |
7623debf | 377 | case CPU_R5432: |
e30ec452 TS |
378 | uasm_i_nop(p); |
379 | uasm_i_nop(p); | |
1da177e4 LT |
380 | tlbw(p); |
381 | break; | |
382 | ||
383 | default: | |
384 | panic("No TLB refill handler yet (CPU type: %d)", | |
385 | current_cpu_data.cputype); | |
386 | break; | |
387 | } | |
388 | } | |
389 | ||
875d43e7 | 390 | #ifdef CONFIG_64BIT |
1da177e4 LT |
391 | /* |
392 | * TMP and PTR are scratch. | |
393 | * TMP will be clobbered, PTR will hold the pmd entry. | |
394 | */ | |
234fcd14 | 395 | static void __cpuinit |
e30ec452 | 396 | build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, |
1da177e4 LT |
397 | unsigned int tmp, unsigned int ptr) |
398 | { | |
399 | long pgdc = (long)pgd_current; | |
400 | ||
401 | /* | |
402 | * The vmalloc handling is not in the hotpath. | |
403 | */ | |
e30ec452 | 404 | uasm_i_dmfc0(p, tmp, C0_BADVADDR); |
656be92f | 405 | #ifdef MODULE_START |
e30ec452 | 406 | uasm_il_bltz(p, r, tmp, label_module_alloc); |
656be92f | 407 | #else |
e30ec452 | 408 | uasm_il_bltz(p, r, tmp, label_vmalloc); |
656be92f | 409 | #endif |
e30ec452 | 410 | /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */ |
1da177e4 LT |
411 | |
412 | #ifdef CONFIG_SMP | |
41c594ab RB |
413 | # ifdef CONFIG_MIPS_MT_SMTC |
414 | /* | |
415 | * SMTC uses TCBind value as "CPU" index | |
416 | */ | |
e30ec452 TS |
417 | uasm_i_mfc0(p, ptr, C0_TCBIND); |
418 | uasm_i_dsrl(p, ptr, ptr, 19); | |
41c594ab | 419 | # else |
1da177e4 | 420 | /* |
1b3a6e97 | 421 | * 64 bit SMP running in XKPHYS has smp_processor_id() << 3 |
1da177e4 LT |
422 | * stored in CONTEXT. |
423 | */ | |
e30ec452 TS |
424 | uasm_i_dmfc0(p, ptr, C0_CONTEXT); |
425 | uasm_i_dsrl(p, ptr, ptr, 23); | |
41c594ab | 426 | #endif |
e30ec452 TS |
427 | UASM_i_LA_mostly(p, tmp, pgdc); |
428 | uasm_i_daddu(p, ptr, ptr, tmp); | |
429 | uasm_i_dmfc0(p, tmp, C0_BADVADDR); | |
430 | uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); | |
1da177e4 | 431 | #else |
e30ec452 TS |
432 | UASM_i_LA_mostly(p, ptr, pgdc); |
433 | uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); | |
1da177e4 LT |
434 | #endif |
435 | ||
e30ec452 | 436 | uasm_l_vmalloc_done(l, *p); |
242954b5 RB |
437 | |
438 | if (PGDIR_SHIFT - 3 < 32) /* get pgd offset in bytes */ | |
e30ec452 | 439 | uasm_i_dsrl(p, tmp, tmp, PGDIR_SHIFT-3); |
242954b5 | 440 | else |
e30ec452 TS |
441 | uasm_i_dsrl32(p, tmp, tmp, PGDIR_SHIFT - 3 - 32); |
442 | ||
443 | uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3); | |
444 | uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */ | |
445 | uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */ | |
446 | uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */ | |
447 | uasm_i_dsrl(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */ | |
448 | uasm_i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3); | |
449 | uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */ | |
1da177e4 LT |
450 | } |
451 | ||
452 | /* | |
453 | * BVADDR is the faulting address, PTR is scratch. | |
454 | * PTR will hold the pgd for vmalloc. | |
455 | */ | |
234fcd14 | 456 | static void __cpuinit |
e30ec452 | 457 | build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, |
1da177e4 LT |
458 | unsigned int bvaddr, unsigned int ptr) |
459 | { | |
460 | long swpd = (long)swapper_pg_dir; | |
461 | ||
656be92f AN |
462 | #ifdef MODULE_START |
463 | long modd = (long)module_pg_dir; | |
464 | ||
e30ec452 | 465 | uasm_l_module_alloc(l, *p); |
656be92f AN |
466 | /* |
467 | * Assumption: | |
468 | * VMALLOC_START >= 0xc000000000000000UL | |
469 | * MODULE_START >= 0xe000000000000000UL | |
470 | */ | |
e30ec452 TS |
471 | UASM_i_SLL(p, ptr, bvaddr, 2); |
472 | uasm_il_bgez(p, r, ptr, label_vmalloc); | |
656be92f | 473 | |
e30ec452 TS |
474 | if (uasm_in_compat_space_p(MODULE_START) && |
475 | !uasm_rel_lo(MODULE_START)) { | |
476 | uasm_i_lui(p, ptr, uasm_rel_hi(MODULE_START)); /* delay slot */ | |
656be92f AN |
477 | } else { |
478 | /* unlikely configuration */ | |
e30ec452 TS |
479 | uasm_i_nop(p); /* delay slot */ |
480 | UASM_i_LA(p, ptr, MODULE_START); | |
656be92f | 481 | } |
e30ec452 | 482 | uasm_i_dsubu(p, bvaddr, bvaddr, ptr); |
656be92f | 483 | |
e30ec452 TS |
484 | if (uasm_in_compat_space_p(modd) && !uasm_rel_lo(modd)) { |
485 | uasm_il_b(p, r, label_vmalloc_done); | |
486 | uasm_i_lui(p, ptr, uasm_rel_hi(modd)); | |
656be92f | 487 | } else { |
e30ec452 TS |
488 | UASM_i_LA_mostly(p, ptr, modd); |
489 | uasm_il_b(p, r, label_vmalloc_done); | |
490 | if (uasm_in_compat_space_p(modd)) | |
491 | uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(modd)); | |
619b6e18 | 492 | else |
e30ec452 | 493 | uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(modd)); |
656be92f AN |
494 | } |
495 | ||
e30ec452 TS |
496 | uasm_l_vmalloc(l, *p); |
497 | if (uasm_in_compat_space_p(MODULE_START) && | |
498 | !uasm_rel_lo(MODULE_START) && | |
656be92f | 499 | MODULE_START << 32 == VMALLOC_START) |
e30ec452 | 500 | uasm_i_dsll32(p, ptr, ptr, 0); /* typical case */ |
656be92f | 501 | else |
e30ec452 | 502 | UASM_i_LA(p, ptr, VMALLOC_START); |
656be92f | 503 | #else |
e30ec452 TS |
504 | uasm_l_vmalloc(l, *p); |
505 | UASM_i_LA(p, ptr, VMALLOC_START); | |
656be92f | 506 | #endif |
e30ec452 | 507 | uasm_i_dsubu(p, bvaddr, bvaddr, ptr); |
1da177e4 | 508 | |
e30ec452 TS |
509 | if (uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd)) { |
510 | uasm_il_b(p, r, label_vmalloc_done); | |
511 | uasm_i_lui(p, ptr, uasm_rel_hi(swpd)); | |
1da177e4 | 512 | } else { |
e30ec452 TS |
513 | UASM_i_LA_mostly(p, ptr, swpd); |
514 | uasm_il_b(p, r, label_vmalloc_done); | |
515 | if (uasm_in_compat_space_p(swpd)) | |
516 | uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd)); | |
619b6e18 | 517 | else |
e30ec452 | 518 | uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd)); |
1da177e4 LT |
519 | } |
520 | } | |
521 | ||
875d43e7 | 522 | #else /* !CONFIG_64BIT */ |
1da177e4 LT |
523 | |
524 | /* | |
525 | * TMP and PTR are scratch. | |
526 | * TMP will be clobbered, PTR will hold the pgd entry. | |
527 | */ | |
234fcd14 | 528 | static void __cpuinit __maybe_unused |
1da177e4 LT |
529 | build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) |
530 | { | |
531 | long pgdc = (long)pgd_current; | |
532 | ||
533 | /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */ | |
534 | #ifdef CONFIG_SMP | |
41c594ab RB |
535 | #ifdef CONFIG_MIPS_MT_SMTC |
536 | /* | |
537 | * SMTC uses TCBind value as "CPU" index | |
538 | */ | |
e30ec452 TS |
539 | uasm_i_mfc0(p, ptr, C0_TCBIND); |
540 | UASM_i_LA_mostly(p, tmp, pgdc); | |
541 | uasm_i_srl(p, ptr, ptr, 19); | |
41c594ab RB |
542 | #else |
543 | /* | |
544 | * smp_processor_id() << 3 is stored in CONTEXT. | |
545 | */ | |
e30ec452 TS |
546 | uasm_i_mfc0(p, ptr, C0_CONTEXT); |
547 | UASM_i_LA_mostly(p, tmp, pgdc); | |
548 | uasm_i_srl(p, ptr, ptr, 23); | |
41c594ab | 549 | #endif |
e30ec452 | 550 | uasm_i_addu(p, ptr, tmp, ptr); |
1da177e4 | 551 | #else |
e30ec452 | 552 | UASM_i_LA_mostly(p, ptr, pgdc); |
1da177e4 | 553 | #endif |
e30ec452 TS |
554 | uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ |
555 | uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); | |
556 | uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */ | |
557 | uasm_i_sll(p, tmp, tmp, PGD_T_LOG2); | |
558 | uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ | |
1da177e4 LT |
559 | } |
560 | ||
875d43e7 | 561 | #endif /* !CONFIG_64BIT */ |
1da177e4 | 562 | |
234fcd14 | 563 | static void __cpuinit build_adjust_context(u32 **p, unsigned int ctx) |
1da177e4 | 564 | { |
242954b5 | 565 | unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12; |
1da177e4 LT |
566 | unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1); |
567 | ||
10cc3529 | 568 | switch (current_cpu_type()) { |
1da177e4 LT |
569 | case CPU_VR41XX: |
570 | case CPU_VR4111: | |
571 | case CPU_VR4121: | |
572 | case CPU_VR4122: | |
573 | case CPU_VR4131: | |
574 | case CPU_VR4181: | |
575 | case CPU_VR4181A: | |
576 | case CPU_VR4133: | |
577 | shift += 2; | |
578 | break; | |
579 | ||
580 | default: | |
581 | break; | |
582 | } | |
583 | ||
584 | if (shift) | |
e30ec452 TS |
585 | UASM_i_SRL(p, ctx, ctx, shift); |
586 | uasm_i_andi(p, ctx, ctx, mask); | |
1da177e4 LT |
587 | } |
588 | ||
234fcd14 | 589 | static void __cpuinit build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) |
1da177e4 LT |
590 | { |
591 | /* | |
592 | * Bug workaround for the Nevada. It seems as if under certain | |
593 | * circumstances the move from cp0_context might produce a | |
594 | * bogus result when the mfc0 instruction and its consumer are | |
595 | * in a different cacheline or a load instruction, probably any | |
596 | * memory reference, is between them. | |
597 | */ | |
10cc3529 | 598 | switch (current_cpu_type()) { |
1da177e4 | 599 | case CPU_NEVADA: |
e30ec452 | 600 | UASM_i_LW(p, ptr, 0, ptr); |
1da177e4 LT |
601 | GET_CONTEXT(p, tmp); /* get context reg */ |
602 | break; | |
603 | ||
604 | default: | |
605 | GET_CONTEXT(p, tmp); /* get context reg */ | |
e30ec452 | 606 | UASM_i_LW(p, ptr, 0, ptr); |
1da177e4 LT |
607 | break; |
608 | } | |
609 | ||
610 | build_adjust_context(p, tmp); | |
e30ec452 | 611 | UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */ |
1da177e4 LT |
612 | } |
613 | ||
234fcd14 | 614 | static void __cpuinit build_update_entries(u32 **p, unsigned int tmp, |
1da177e4 LT |
615 | unsigned int ptep) |
616 | { | |
617 | /* | |
618 | * 64bit address support (36bit on a 32bit CPU) in a 32bit | |
619 | * Kernel is a special case. Only a few CPUs use it. | |
620 | */ | |
621 | #ifdef CONFIG_64BIT_PHYS_ADDR | |
622 | if (cpu_has_64bits) { | |
e30ec452 TS |
623 | uasm_i_ld(p, tmp, 0, ptep); /* get even pte */ |
624 | uasm_i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ | |
625 | uasm_i_dsrl(p, tmp, tmp, 6); /* convert to entrylo0 */ | |
626 | uasm_i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */ | |
627 | uasm_i_dsrl(p, ptep, ptep, 6); /* convert to entrylo1 */ | |
628 | uasm_i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */ | |
1da177e4 LT |
629 | } else { |
630 | int pte_off_even = sizeof(pte_t) / 2; | |
631 | int pte_off_odd = pte_off_even + sizeof(pte_t); | |
632 | ||
633 | /* The pte entries are pre-shifted */ | |
e30ec452 TS |
634 | uasm_i_lw(p, tmp, pte_off_even, ptep); /* get even pte */ |
635 | uasm_i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */ | |
636 | uasm_i_lw(p, ptep, pte_off_odd, ptep); /* get odd pte */ | |
637 | uasm_i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */ | |
1da177e4 LT |
638 | } |
639 | #else | |
e30ec452 TS |
640 | UASM_i_LW(p, tmp, 0, ptep); /* get even pte */ |
641 | UASM_i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ | |
1da177e4 LT |
642 | if (r45k_bvahwbug()) |
643 | build_tlb_probe_entry(p); | |
e30ec452 | 644 | UASM_i_SRL(p, tmp, tmp, 6); /* convert to entrylo0 */ |
1da177e4 | 645 | if (r4k_250MHZhwbug()) |
e30ec452 TS |
646 | uasm_i_mtc0(p, 0, C0_ENTRYLO0); |
647 | uasm_i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */ | |
648 | UASM_i_SRL(p, ptep, ptep, 6); /* convert to entrylo1 */ | |
1da177e4 | 649 | if (r45k_bvahwbug()) |
e30ec452 | 650 | uasm_i_mfc0(p, tmp, C0_INDEX); |
1da177e4 | 651 | if (r4k_250MHZhwbug()) |
e30ec452 TS |
652 | uasm_i_mtc0(p, 0, C0_ENTRYLO1); |
653 | uasm_i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */ | |
1da177e4 LT |
654 | #endif |
655 | } | |
656 | ||
234fcd14 | 657 | static void __cpuinit build_r4000_tlb_refill_handler(void) |
1da177e4 LT |
658 | { |
659 | u32 *p = tlb_handler; | |
e30ec452 TS |
660 | struct uasm_label *l = labels; |
661 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
662 | u32 *f; |
663 | unsigned int final_len; | |
664 | ||
665 | memset(tlb_handler, 0, sizeof(tlb_handler)); | |
666 | memset(labels, 0, sizeof(labels)); | |
667 | memset(relocs, 0, sizeof(relocs)); | |
668 | memset(final_handler, 0, sizeof(final_handler)); | |
669 | ||
670 | /* | |
671 | * create the plain linear handler | |
672 | */ | |
673 | if (bcm1250_m3_war()) { | |
e30ec452 TS |
674 | UASM_i_MFC0(&p, K0, C0_BADVADDR); |
675 | UASM_i_MFC0(&p, K1, C0_ENTRYHI); | |
676 | uasm_i_xor(&p, K0, K0, K1); | |
677 | UASM_i_SRL(&p, K0, K0, PAGE_SHIFT + 1); | |
678 | uasm_il_bnez(&p, &r, K0, label_leave); | |
679 | /* No need for uasm_i_nop */ | |
1da177e4 LT |
680 | } |
681 | ||
875d43e7 | 682 | #ifdef CONFIG_64BIT |
1da177e4 LT |
683 | build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */ |
684 | #else | |
685 | build_get_pgde32(&p, K0, K1); /* get pgd in K1 */ | |
686 | #endif | |
687 | ||
688 | build_get_ptep(&p, K0, K1); | |
689 | build_update_entries(&p, K0, K1); | |
690 | build_tlb_write_entry(&p, &l, &r, tlb_random); | |
e30ec452 TS |
691 | uasm_l_leave(&l, p); |
692 | uasm_i_eret(&p); /* return from trap */ | |
1da177e4 | 693 | |
875d43e7 | 694 | #ifdef CONFIG_64BIT |
1da177e4 LT |
695 | build_get_pgd_vmalloc64(&p, &l, &r, K0, K1); |
696 | #endif | |
697 | ||
698 | /* | |
699 | * Overflow check: For the 64bit handler, we need at least one | |
700 | * free instruction slot for the wrap-around branch. In worst | |
701 | * case, if the intended insertion point is a delay slot, we | |
4b3f686d | 702 | * need three, with the second nop'ed and the third being |
1da177e4 LT |
703 | * unused. |
704 | */ | |
2a21c730 FZ |
705 | /* Loongson2 ebase is different than r4k, we have more space */ |
706 | #if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2) | |
1da177e4 LT |
707 | if ((p - tlb_handler) > 64) |
708 | panic("TLB refill handler space exceeded"); | |
709 | #else | |
710 | if (((p - tlb_handler) > 63) | |
711 | || (((p - tlb_handler) > 61) | |
e30ec452 | 712 | && uasm_insn_has_bdelay(relocs, tlb_handler + 29))) |
1da177e4 LT |
713 | panic("TLB refill handler space exceeded"); |
714 | #endif | |
715 | ||
716 | /* | |
717 | * Now fold the handler in the TLB refill handler space. | |
718 | */ | |
2a21c730 | 719 | #if defined(CONFIG_32BIT) || defined(CONFIG_CPU_LOONGSON2) |
1da177e4 LT |
720 | f = final_handler; |
721 | /* Simplest case, just copy the handler. */ | |
e30ec452 | 722 | uasm_copy_handler(relocs, labels, tlb_handler, p, f); |
1da177e4 | 723 | final_len = p - tlb_handler; |
875d43e7 | 724 | #else /* CONFIG_64BIT */ |
1da177e4 LT |
725 | f = final_handler + 32; |
726 | if ((p - tlb_handler) <= 32) { | |
727 | /* Just copy the handler. */ | |
e30ec452 | 728 | uasm_copy_handler(relocs, labels, tlb_handler, p, f); |
1da177e4 LT |
729 | final_len = p - tlb_handler; |
730 | } else { | |
731 | u32 *split = tlb_handler + 30; | |
732 | ||
733 | /* | |
734 | * Find the split point. | |
735 | */ | |
e30ec452 | 736 | if (uasm_insn_has_bdelay(relocs, split - 1)) |
1da177e4 LT |
737 | split--; |
738 | ||
739 | /* Copy first part of the handler. */ | |
e30ec452 | 740 | uasm_copy_handler(relocs, labels, tlb_handler, split, f); |
1da177e4 LT |
741 | f += split - tlb_handler; |
742 | ||
743 | /* Insert branch. */ | |
e30ec452 TS |
744 | uasm_l_split(&l, final_handler); |
745 | uasm_il_b(&f, &r, label_split); | |
746 | if (uasm_insn_has_bdelay(relocs, split)) | |
747 | uasm_i_nop(&f); | |
1da177e4 | 748 | else { |
e30ec452 TS |
749 | uasm_copy_handler(relocs, labels, split, split + 1, f); |
750 | uasm_move_labels(labels, f, f + 1, -1); | |
1da177e4 LT |
751 | f++; |
752 | split++; | |
753 | } | |
754 | ||
755 | /* Copy the rest of the handler. */ | |
e30ec452 | 756 | uasm_copy_handler(relocs, labels, split, p, final_handler); |
1da177e4 LT |
757 | final_len = (f - (final_handler + 32)) + (p - split); |
758 | } | |
875d43e7 | 759 | #endif /* CONFIG_64BIT */ |
1da177e4 | 760 | |
e30ec452 TS |
761 | uasm_resolve_relocs(relocs, labels); |
762 | pr_debug("Wrote TLB refill handler (%u instructions).\n", | |
763 | final_len); | |
1da177e4 | 764 | |
91b05e67 | 765 | memcpy((void *)ebase, final_handler, 0x100); |
92b1e6a6 FBH |
766 | |
767 | dump_handler((u32 *)ebase, 64); | |
1da177e4 LT |
768 | } |
769 | ||
770 | /* | |
771 | * TLB load/store/modify handlers. | |
772 | * | |
773 | * Only the fastpath gets synthesized at runtime, the slowpath for | |
774 | * do_page_fault remains normal asm. | |
775 | */ | |
776 | extern void tlb_do_page_fault_0(void); | |
777 | extern void tlb_do_page_fault_1(void); | |
778 | ||
1da177e4 LT |
779 | /* |
780 | * 128 instructions for the fastpath handler is generous and should | |
781 | * never be exceeded. | |
782 | */ | |
783 | #define FASTPATH_SIZE 128 | |
784 | ||
cbdbe07f FBH |
785 | u32 handle_tlbl[FASTPATH_SIZE] __cacheline_aligned; |
786 | u32 handle_tlbs[FASTPATH_SIZE] __cacheline_aligned; | |
787 | u32 handle_tlbm[FASTPATH_SIZE] __cacheline_aligned; | |
1da177e4 | 788 | |
234fcd14 | 789 | static void __cpuinit |
e30ec452 | 790 | iPTE_LW(u32 **p, struct uasm_label **l, unsigned int pte, unsigned int ptr) |
1da177e4 LT |
791 | { |
792 | #ifdef CONFIG_SMP | |
793 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
794 | if (cpu_has_64bits) | |
e30ec452 | 795 | uasm_i_lld(p, pte, 0, ptr); |
1da177e4 LT |
796 | else |
797 | # endif | |
e30ec452 | 798 | UASM_i_LL(p, pte, 0, ptr); |
1da177e4 LT |
799 | #else |
800 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
801 | if (cpu_has_64bits) | |
e30ec452 | 802 | uasm_i_ld(p, pte, 0, ptr); |
1da177e4 LT |
803 | else |
804 | # endif | |
e30ec452 | 805 | UASM_i_LW(p, pte, 0, ptr); |
1da177e4 LT |
806 | #endif |
807 | } | |
808 | ||
234fcd14 | 809 | static void __cpuinit |
e30ec452 | 810 | iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr, |
63b2d2f4 | 811 | unsigned int mode) |
1da177e4 | 812 | { |
63b2d2f4 TS |
813 | #ifdef CONFIG_64BIT_PHYS_ADDR |
814 | unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY); | |
815 | #endif | |
816 | ||
e30ec452 | 817 | uasm_i_ori(p, pte, pte, mode); |
1da177e4 LT |
818 | #ifdef CONFIG_SMP |
819 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
820 | if (cpu_has_64bits) | |
e30ec452 | 821 | uasm_i_scd(p, pte, 0, ptr); |
1da177e4 LT |
822 | else |
823 | # endif | |
e30ec452 | 824 | UASM_i_SC(p, pte, 0, ptr); |
1da177e4 LT |
825 | |
826 | if (r10000_llsc_war()) | |
e30ec452 | 827 | uasm_il_beqzl(p, r, pte, label_smp_pgtable_change); |
1da177e4 | 828 | else |
e30ec452 | 829 | uasm_il_beqz(p, r, pte, label_smp_pgtable_change); |
1da177e4 LT |
830 | |
831 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
832 | if (!cpu_has_64bits) { | |
e30ec452 TS |
833 | /* no uasm_i_nop needed */ |
834 | uasm_i_ll(p, pte, sizeof(pte_t) / 2, ptr); | |
835 | uasm_i_ori(p, pte, pte, hwmode); | |
836 | uasm_i_sc(p, pte, sizeof(pte_t) / 2, ptr); | |
837 | uasm_il_beqz(p, r, pte, label_smp_pgtable_change); | |
838 | /* no uasm_i_nop needed */ | |
839 | uasm_i_lw(p, pte, 0, ptr); | |
1da177e4 | 840 | } else |
e30ec452 | 841 | uasm_i_nop(p); |
1da177e4 | 842 | # else |
e30ec452 | 843 | uasm_i_nop(p); |
1da177e4 LT |
844 | # endif |
845 | #else | |
846 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
847 | if (cpu_has_64bits) | |
e30ec452 | 848 | uasm_i_sd(p, pte, 0, ptr); |
1da177e4 LT |
849 | else |
850 | # endif | |
e30ec452 | 851 | UASM_i_SW(p, pte, 0, ptr); |
1da177e4 LT |
852 | |
853 | # ifdef CONFIG_64BIT_PHYS_ADDR | |
854 | if (!cpu_has_64bits) { | |
e30ec452 TS |
855 | uasm_i_lw(p, pte, sizeof(pte_t) / 2, ptr); |
856 | uasm_i_ori(p, pte, pte, hwmode); | |
857 | uasm_i_sw(p, pte, sizeof(pte_t) / 2, ptr); | |
858 | uasm_i_lw(p, pte, 0, ptr); | |
1da177e4 LT |
859 | } |
860 | # endif | |
861 | #endif | |
862 | } | |
863 | ||
864 | /* | |
865 | * Check if PTE is present, if not then jump to LABEL. PTR points to | |
866 | * the page table where this PTE is located, PTE will be re-loaded | |
867 | * with it's original value. | |
868 | */ | |
234fcd14 | 869 | static void __cpuinit |
e30ec452 | 870 | build_pte_present(u32 **p, struct uasm_label **l, struct uasm_reloc **r, |
1da177e4 LT |
871 | unsigned int pte, unsigned int ptr, enum label_id lid) |
872 | { | |
e30ec452 TS |
873 | uasm_i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); |
874 | uasm_i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); | |
875 | uasm_il_bnez(p, r, pte, lid); | |
63b2d2f4 | 876 | iPTE_LW(p, l, pte, ptr); |
1da177e4 LT |
877 | } |
878 | ||
879 | /* Make PTE valid, store result in PTR. */ | |
234fcd14 | 880 | static void __cpuinit |
e30ec452 | 881 | build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte, |
1da177e4 LT |
882 | unsigned int ptr) |
883 | { | |
63b2d2f4 TS |
884 | unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED; |
885 | ||
886 | iPTE_SW(p, r, pte, ptr, mode); | |
1da177e4 LT |
887 | } |
888 | ||
889 | /* | |
890 | * Check if PTE can be written to, if not branch to LABEL. Regardless | |
891 | * restore PTE with value from PTR when done. | |
892 | */ | |
234fcd14 | 893 | static void __cpuinit |
e30ec452 | 894 | build_pte_writable(u32 **p, struct uasm_label **l, struct uasm_reloc **r, |
1da177e4 LT |
895 | unsigned int pte, unsigned int ptr, enum label_id lid) |
896 | { | |
e30ec452 TS |
897 | uasm_i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE); |
898 | uasm_i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE); | |
899 | uasm_il_bnez(p, r, pte, lid); | |
63b2d2f4 | 900 | iPTE_LW(p, l, pte, ptr); |
1da177e4 LT |
901 | } |
902 | ||
903 | /* Make PTE writable, update software status bits as well, then store | |
904 | * at PTR. | |
905 | */ | |
234fcd14 | 906 | static void __cpuinit |
e30ec452 | 907 | build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte, |
1da177e4 LT |
908 | unsigned int ptr) |
909 | { | |
63b2d2f4 TS |
910 | unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID |
911 | | _PAGE_DIRTY); | |
912 | ||
913 | iPTE_SW(p, r, pte, ptr, mode); | |
1da177e4 LT |
914 | } |
915 | ||
916 | /* | |
917 | * Check if PTE can be modified, if not branch to LABEL. Regardless | |
918 | * restore PTE with value from PTR when done. | |
919 | */ | |
234fcd14 | 920 | static void __cpuinit |
e30ec452 | 921 | build_pte_modifiable(u32 **p, struct uasm_label **l, struct uasm_reloc **r, |
1da177e4 LT |
922 | unsigned int pte, unsigned int ptr, enum label_id lid) |
923 | { | |
e30ec452 TS |
924 | uasm_i_andi(p, pte, pte, _PAGE_WRITE); |
925 | uasm_il_beqz(p, r, pte, lid); | |
63b2d2f4 | 926 | iPTE_LW(p, l, pte, ptr); |
1da177e4 LT |
927 | } |
928 | ||
929 | /* | |
930 | * R3000 style TLB load/store/modify handlers. | |
931 | */ | |
932 | ||
fded2e50 MR |
933 | /* |
934 | * This places the pte into ENTRYLO0 and writes it with tlbwi. | |
935 | * Then it returns. | |
936 | */ | |
234fcd14 | 937 | static void __cpuinit |
fded2e50 | 938 | build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp) |
1da177e4 | 939 | { |
e30ec452 TS |
940 | uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ |
941 | uasm_i_mfc0(p, tmp, C0_EPC); /* cp0 delay */ | |
942 | uasm_i_tlbwi(p); | |
943 | uasm_i_jr(p, tmp); | |
944 | uasm_i_rfe(p); /* branch delay */ | |
1da177e4 LT |
945 | } |
946 | ||
947 | /* | |
fded2e50 MR |
948 | * This places the pte into ENTRYLO0 and writes it with tlbwi |
949 | * or tlbwr as appropriate. This is because the index register | |
950 | * may have the probe fail bit set as a result of a trap on a | |
951 | * kseg2 access, i.e. without refill. Then it returns. | |
1da177e4 | 952 | */ |
234fcd14 | 953 | static void __cpuinit |
e30ec452 TS |
954 | build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l, |
955 | struct uasm_reloc **r, unsigned int pte, | |
956 | unsigned int tmp) | |
957 | { | |
958 | uasm_i_mfc0(p, tmp, C0_INDEX); | |
959 | uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ | |
960 | uasm_il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */ | |
961 | uasm_i_mfc0(p, tmp, C0_EPC); /* branch delay */ | |
962 | uasm_i_tlbwi(p); /* cp0 delay */ | |
963 | uasm_i_jr(p, tmp); | |
964 | uasm_i_rfe(p); /* branch delay */ | |
965 | uasm_l_r3000_write_probe_fail(l, *p); | |
966 | uasm_i_tlbwr(p); /* cp0 delay */ | |
967 | uasm_i_jr(p, tmp); | |
968 | uasm_i_rfe(p); /* branch delay */ | |
1da177e4 LT |
969 | } |
970 | ||
234fcd14 | 971 | static void __cpuinit |
1da177e4 LT |
972 | build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte, |
973 | unsigned int ptr) | |
974 | { | |
975 | long pgdc = (long)pgd_current; | |
976 | ||
e30ec452 TS |
977 | uasm_i_mfc0(p, pte, C0_BADVADDR); |
978 | uasm_i_lui(p, ptr, uasm_rel_hi(pgdc)); /* cp0 delay */ | |
979 | uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); | |
980 | uasm_i_srl(p, pte, pte, 22); /* load delay */ | |
981 | uasm_i_sll(p, pte, pte, 2); | |
982 | uasm_i_addu(p, ptr, ptr, pte); | |
983 | uasm_i_mfc0(p, pte, C0_CONTEXT); | |
984 | uasm_i_lw(p, ptr, 0, ptr); /* cp0 delay */ | |
985 | uasm_i_andi(p, pte, pte, 0xffc); /* load delay */ | |
986 | uasm_i_addu(p, ptr, ptr, pte); | |
987 | uasm_i_lw(p, pte, 0, ptr); | |
988 | uasm_i_tlbp(p); /* load delay */ | |
1da177e4 LT |
989 | } |
990 | ||
234fcd14 | 991 | static void __cpuinit build_r3000_tlb_load_handler(void) |
1da177e4 LT |
992 | { |
993 | u32 *p = handle_tlbl; | |
e30ec452 TS |
994 | struct uasm_label *l = labels; |
995 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
996 | |
997 | memset(handle_tlbl, 0, sizeof(handle_tlbl)); | |
998 | memset(labels, 0, sizeof(labels)); | |
999 | memset(relocs, 0, sizeof(relocs)); | |
1000 | ||
1001 | build_r3000_tlbchange_handler_head(&p, K0, K1); | |
1002 | build_pte_present(&p, &l, &r, K0, K1, label_nopage_tlbl); | |
e30ec452 | 1003 | uasm_i_nop(&p); /* load delay */ |
1da177e4 | 1004 | build_make_valid(&p, &r, K0, K1); |
fded2e50 | 1005 | build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); |
1da177e4 | 1006 | |
e30ec452 TS |
1007 | uasm_l_nopage_tlbl(&l, p); |
1008 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); | |
1009 | uasm_i_nop(&p); | |
1da177e4 LT |
1010 | |
1011 | if ((p - handle_tlbl) > FASTPATH_SIZE) | |
1012 | panic("TLB load handler fastpath space exceeded"); | |
1013 | ||
e30ec452 TS |
1014 | uasm_resolve_relocs(relocs, labels); |
1015 | pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", | |
1016 | (unsigned int)(p - handle_tlbl)); | |
1da177e4 | 1017 | |
92b1e6a6 | 1018 | dump_handler(handle_tlbl, ARRAY_SIZE(handle_tlbl)); |
1da177e4 LT |
1019 | } |
1020 | ||
234fcd14 | 1021 | static void __cpuinit build_r3000_tlb_store_handler(void) |
1da177e4 LT |
1022 | { |
1023 | u32 *p = handle_tlbs; | |
e30ec452 TS |
1024 | struct uasm_label *l = labels; |
1025 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
1026 | |
1027 | memset(handle_tlbs, 0, sizeof(handle_tlbs)); | |
1028 | memset(labels, 0, sizeof(labels)); | |
1029 | memset(relocs, 0, sizeof(relocs)); | |
1030 | ||
1031 | build_r3000_tlbchange_handler_head(&p, K0, K1); | |
1032 | build_pte_writable(&p, &l, &r, K0, K1, label_nopage_tlbs); | |
e30ec452 | 1033 | uasm_i_nop(&p); /* load delay */ |
1da177e4 | 1034 | build_make_write(&p, &r, K0, K1); |
fded2e50 | 1035 | build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); |
1da177e4 | 1036 | |
e30ec452 TS |
1037 | uasm_l_nopage_tlbs(&l, p); |
1038 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); | |
1039 | uasm_i_nop(&p); | |
1da177e4 LT |
1040 | |
1041 | if ((p - handle_tlbs) > FASTPATH_SIZE) | |
1042 | panic("TLB store handler fastpath space exceeded"); | |
1043 | ||
e30ec452 TS |
1044 | uasm_resolve_relocs(relocs, labels); |
1045 | pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", | |
1046 | (unsigned int)(p - handle_tlbs)); | |
1da177e4 | 1047 | |
92b1e6a6 | 1048 | dump_handler(handle_tlbs, ARRAY_SIZE(handle_tlbs)); |
1da177e4 LT |
1049 | } |
1050 | ||
234fcd14 | 1051 | static void __cpuinit build_r3000_tlb_modify_handler(void) |
1da177e4 LT |
1052 | { |
1053 | u32 *p = handle_tlbm; | |
e30ec452 TS |
1054 | struct uasm_label *l = labels; |
1055 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
1056 | |
1057 | memset(handle_tlbm, 0, sizeof(handle_tlbm)); | |
1058 | memset(labels, 0, sizeof(labels)); | |
1059 | memset(relocs, 0, sizeof(relocs)); | |
1060 | ||
1061 | build_r3000_tlbchange_handler_head(&p, K0, K1); | |
1062 | build_pte_modifiable(&p, &l, &r, K0, K1, label_nopage_tlbm); | |
e30ec452 | 1063 | uasm_i_nop(&p); /* load delay */ |
1da177e4 | 1064 | build_make_write(&p, &r, K0, K1); |
fded2e50 | 1065 | build_r3000_pte_reload_tlbwi(&p, K0, K1); |
1da177e4 | 1066 | |
e30ec452 TS |
1067 | uasm_l_nopage_tlbm(&l, p); |
1068 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); | |
1069 | uasm_i_nop(&p); | |
1da177e4 LT |
1070 | |
1071 | if ((p - handle_tlbm) > FASTPATH_SIZE) | |
1072 | panic("TLB modify handler fastpath space exceeded"); | |
1073 | ||
e30ec452 TS |
1074 | uasm_resolve_relocs(relocs, labels); |
1075 | pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", | |
1076 | (unsigned int)(p - handle_tlbm)); | |
1da177e4 | 1077 | |
92b1e6a6 | 1078 | dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm)); |
1da177e4 LT |
1079 | } |
1080 | ||
1081 | /* | |
1082 | * R4000 style TLB load/store/modify handlers. | |
1083 | */ | |
234fcd14 | 1084 | static void __cpuinit |
e30ec452 TS |
1085 | build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l, |
1086 | struct uasm_reloc **r, unsigned int pte, | |
1da177e4 LT |
1087 | unsigned int ptr) |
1088 | { | |
875d43e7 | 1089 | #ifdef CONFIG_64BIT |
1da177e4 LT |
1090 | build_get_pmde64(p, l, r, pte, ptr); /* get pmd in ptr */ |
1091 | #else | |
1092 | build_get_pgde32(p, pte, ptr); /* get pgd in ptr */ | |
1093 | #endif | |
1094 | ||
e30ec452 TS |
1095 | UASM_i_MFC0(p, pte, C0_BADVADDR); |
1096 | UASM_i_LW(p, ptr, 0, ptr); | |
1097 | UASM_i_SRL(p, pte, pte, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2); | |
1098 | uasm_i_andi(p, pte, pte, (PTRS_PER_PTE - 1) << PTE_T_LOG2); | |
1099 | UASM_i_ADDU(p, ptr, ptr, pte); | |
1da177e4 LT |
1100 | |
1101 | #ifdef CONFIG_SMP | |
e30ec452 TS |
1102 | uasm_l_smp_pgtable_change(l, *p); |
1103 | #endif | |
63b2d2f4 | 1104 | iPTE_LW(p, l, pte, ptr); /* get even pte */ |
8df5beac MR |
1105 | if (!m4kc_tlbp_war()) |
1106 | build_tlb_probe_entry(p); | |
1da177e4 LT |
1107 | } |
1108 | ||
234fcd14 | 1109 | static void __cpuinit |
e30ec452 TS |
1110 | build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l, |
1111 | struct uasm_reloc **r, unsigned int tmp, | |
1da177e4 LT |
1112 | unsigned int ptr) |
1113 | { | |
e30ec452 TS |
1114 | uasm_i_ori(p, ptr, ptr, sizeof(pte_t)); |
1115 | uasm_i_xori(p, ptr, ptr, sizeof(pte_t)); | |
1da177e4 LT |
1116 | build_update_entries(p, tmp, ptr); |
1117 | build_tlb_write_entry(p, l, r, tlb_indexed); | |
e30ec452 TS |
1118 | uasm_l_leave(l, *p); |
1119 | uasm_i_eret(p); /* return from trap */ | |
1da177e4 | 1120 | |
875d43e7 | 1121 | #ifdef CONFIG_64BIT |
1da177e4 LT |
1122 | build_get_pgd_vmalloc64(p, l, r, tmp, ptr); |
1123 | #endif | |
1124 | } | |
1125 | ||
234fcd14 | 1126 | static void __cpuinit build_r4000_tlb_load_handler(void) |
1da177e4 LT |
1127 | { |
1128 | u32 *p = handle_tlbl; | |
e30ec452 TS |
1129 | struct uasm_label *l = labels; |
1130 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
1131 | |
1132 | memset(handle_tlbl, 0, sizeof(handle_tlbl)); | |
1133 | memset(labels, 0, sizeof(labels)); | |
1134 | memset(relocs, 0, sizeof(relocs)); | |
1135 | ||
1136 | if (bcm1250_m3_war()) { | |
e30ec452 TS |
1137 | UASM_i_MFC0(&p, K0, C0_BADVADDR); |
1138 | UASM_i_MFC0(&p, K1, C0_ENTRYHI); | |
1139 | uasm_i_xor(&p, K0, K0, K1); | |
1140 | UASM_i_SRL(&p, K0, K0, PAGE_SHIFT + 1); | |
1141 | uasm_il_bnez(&p, &r, K0, label_leave); | |
1142 | /* No need for uasm_i_nop */ | |
1da177e4 LT |
1143 | } |
1144 | ||
1145 | build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); | |
1146 | build_pte_present(&p, &l, &r, K0, K1, label_nopage_tlbl); | |
8df5beac MR |
1147 | if (m4kc_tlbp_war()) |
1148 | build_tlb_probe_entry(&p); | |
1da177e4 LT |
1149 | build_make_valid(&p, &r, K0, K1); |
1150 | build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); | |
1151 | ||
e30ec452 TS |
1152 | uasm_l_nopage_tlbl(&l, p); |
1153 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); | |
1154 | uasm_i_nop(&p); | |
1da177e4 LT |
1155 | |
1156 | if ((p - handle_tlbl) > FASTPATH_SIZE) | |
1157 | panic("TLB load handler fastpath space exceeded"); | |
1158 | ||
e30ec452 TS |
1159 | uasm_resolve_relocs(relocs, labels); |
1160 | pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", | |
1161 | (unsigned int)(p - handle_tlbl)); | |
1da177e4 | 1162 | |
92b1e6a6 | 1163 | dump_handler(handle_tlbl, ARRAY_SIZE(handle_tlbl)); |
1da177e4 LT |
1164 | } |
1165 | ||
234fcd14 | 1166 | static void __cpuinit build_r4000_tlb_store_handler(void) |
1da177e4 LT |
1167 | { |
1168 | u32 *p = handle_tlbs; | |
e30ec452 TS |
1169 | struct uasm_label *l = labels; |
1170 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
1171 | |
1172 | memset(handle_tlbs, 0, sizeof(handle_tlbs)); | |
1173 | memset(labels, 0, sizeof(labels)); | |
1174 | memset(relocs, 0, sizeof(relocs)); | |
1175 | ||
1176 | build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); | |
1177 | build_pte_writable(&p, &l, &r, K0, K1, label_nopage_tlbs); | |
8df5beac MR |
1178 | if (m4kc_tlbp_war()) |
1179 | build_tlb_probe_entry(&p); | |
1da177e4 LT |
1180 | build_make_write(&p, &r, K0, K1); |
1181 | build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); | |
1182 | ||
e30ec452 TS |
1183 | uasm_l_nopage_tlbs(&l, p); |
1184 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); | |
1185 | uasm_i_nop(&p); | |
1da177e4 LT |
1186 | |
1187 | if ((p - handle_tlbs) > FASTPATH_SIZE) | |
1188 | panic("TLB store handler fastpath space exceeded"); | |
1189 | ||
e30ec452 TS |
1190 | uasm_resolve_relocs(relocs, labels); |
1191 | pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", | |
1192 | (unsigned int)(p - handle_tlbs)); | |
1da177e4 | 1193 | |
92b1e6a6 | 1194 | dump_handler(handle_tlbs, ARRAY_SIZE(handle_tlbs)); |
1da177e4 LT |
1195 | } |
1196 | ||
234fcd14 | 1197 | static void __cpuinit build_r4000_tlb_modify_handler(void) |
1da177e4 LT |
1198 | { |
1199 | u32 *p = handle_tlbm; | |
e30ec452 TS |
1200 | struct uasm_label *l = labels; |
1201 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
1202 | |
1203 | memset(handle_tlbm, 0, sizeof(handle_tlbm)); | |
1204 | memset(labels, 0, sizeof(labels)); | |
1205 | memset(relocs, 0, sizeof(relocs)); | |
1206 | ||
1207 | build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); | |
1208 | build_pte_modifiable(&p, &l, &r, K0, K1, label_nopage_tlbm); | |
8df5beac MR |
1209 | if (m4kc_tlbp_war()) |
1210 | build_tlb_probe_entry(&p); | |
1da177e4 LT |
1211 | /* Present and writable bits set, set accessed and dirty bits. */ |
1212 | build_make_write(&p, &r, K0, K1); | |
1213 | build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); | |
1214 | ||
e30ec452 TS |
1215 | uasm_l_nopage_tlbm(&l, p); |
1216 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); | |
1217 | uasm_i_nop(&p); | |
1da177e4 LT |
1218 | |
1219 | if ((p - handle_tlbm) > FASTPATH_SIZE) | |
1220 | panic("TLB modify handler fastpath space exceeded"); | |
1221 | ||
e30ec452 TS |
1222 | uasm_resolve_relocs(relocs, labels); |
1223 | pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", | |
1224 | (unsigned int)(p - handle_tlbm)); | |
115f2a44 | 1225 | |
92b1e6a6 | 1226 | dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm)); |
1da177e4 LT |
1227 | } |
1228 | ||
234fcd14 | 1229 | void __cpuinit build_tlb_refill_handler(void) |
1da177e4 LT |
1230 | { |
1231 | /* | |
1232 | * The refill handler is generated per-CPU, multi-node systems | |
1233 | * may have local storage for it. The other handlers are only | |
1234 | * needed once. | |
1235 | */ | |
1236 | static int run_once = 0; | |
1237 | ||
10cc3529 | 1238 | switch (current_cpu_type()) { |
1da177e4 LT |
1239 | case CPU_R2000: |
1240 | case CPU_R3000: | |
1241 | case CPU_R3000A: | |
1242 | case CPU_R3081E: | |
1243 | case CPU_TX3912: | |
1244 | case CPU_TX3922: | |
1245 | case CPU_TX3927: | |
1246 | build_r3000_tlb_refill_handler(); | |
1247 | if (!run_once) { | |
1248 | build_r3000_tlb_load_handler(); | |
1249 | build_r3000_tlb_store_handler(); | |
1250 | build_r3000_tlb_modify_handler(); | |
1251 | run_once++; | |
1252 | } | |
1253 | break; | |
1254 | ||
1255 | case CPU_R6000: | |
1256 | case CPU_R6000A: | |
1257 | panic("No R6000 TLB refill handler yet"); | |
1258 | break; | |
1259 | ||
1260 | case CPU_R8000: | |
1261 | panic("No R8000 TLB refill handler yet"); | |
1262 | break; | |
1263 | ||
1264 | default: | |
1265 | build_r4000_tlb_refill_handler(); | |
1266 | if (!run_once) { | |
1267 | build_r4000_tlb_load_handler(); | |
1268 | build_r4000_tlb_store_handler(); | |
1269 | build_r4000_tlb_modify_handler(); | |
1270 | run_once++; | |
1271 | } | |
1272 | } | |
1273 | } | |
1d40cfcd | 1274 | |
234fcd14 | 1275 | void __cpuinit flush_tlb_handlers(void) |
1d40cfcd | 1276 | { |
e0cee3ee | 1277 | local_flush_icache_range((unsigned long)handle_tlbl, |
1d40cfcd | 1278 | (unsigned long)handle_tlbl + sizeof(handle_tlbl)); |
e0cee3ee | 1279 | local_flush_icache_range((unsigned long)handle_tlbs, |
1d40cfcd | 1280 | (unsigned long)handle_tlbs + sizeof(handle_tlbs)); |
e0cee3ee | 1281 | local_flush_icache_range((unsigned long)handle_tlbm, |
1d40cfcd RB |
1282 | (unsigned long)handle_tlbm + sizeof(handle_tlbm)); |
1283 | } |