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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Synthesize TLB refill handlers at runtime. | |
7 | * | |
70342287 RB |
8 | * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer |
9 | * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki | |
41c594ab | 10 | * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) |
fd062c84 | 11 | * Copyright (C) 2008, 2009 Cavium Networks, Inc. |
113c62d9 | 12 | * Copyright (C) 2011 MIPS Technologies, Inc. |
41c594ab RB |
13 | * |
14 | * ... and the days got worse and worse and now you see | |
92a76f6d | 15 | * I've gone completely out of my mind. |
41c594ab RB |
16 | * |
17 | * They're coming to take me a away haha | |
18 | * they're coming to take me a away hoho hihi haha | |
19 | * to the funny farm where code is beautiful all the time ... | |
20 | * | |
21 | * (Condolences to Napoleon XIV) | |
1da177e4 LT |
22 | */ |
23 | ||
95affdda | 24 | #include <linux/bug.h> |
ccf01516 | 25 | #include <linux/export.h> |
1da177e4 LT |
26 | #include <linux/kernel.h> |
27 | #include <linux/types.h> | |
631330f5 | 28 | #include <linux/smp.h> |
1da177e4 | 29 | #include <linux/string.h> |
3d8bfdd0 | 30 | #include <linux/cache.h> |
65fddcfc | 31 | #include <linux/pgtable.h> |
1da177e4 | 32 | |
3d8bfdd0 | 33 | #include <asm/cacheflush.h> |
69f24d17 | 34 | #include <asm/cpu-type.h> |
a77dabc8 | 35 | #include <asm/mipsregs.h> |
4bcb4ad6 | 36 | #include <asm/mmu_context.h> |
8cc461b8 | 37 | #include <asm/regdef.h> |
3482d713 | 38 | #include <asm/uasm.h> |
b81947c6 | 39 | #include <asm/setup.h> |
722b4544 | 40 | #include <asm/tlbex.h> |
e30ec452 | 41 | |
a2d25e63 | 42 | static int mips_xpa_disabled; |
c5b36783 SH |
43 | |
44 | static int __init xpa_disable(char *s) | |
45 | { | |
46 | mips_xpa_disabled = 1; | |
47 | ||
48 | return 1; | |
49 | } | |
50 | ||
51 | __setup("noxpa", xpa_disable); | |
52 | ||
1ec56329 DD |
53 | /* |
54 | * TLB load/store/modify handlers. | |
55 | * | |
56 | * Only the fastpath gets synthesized at runtime, the slowpath for | |
57 | * do_page_fault remains normal asm. | |
58 | */ | |
59 | extern void tlb_do_page_fault_0(void); | |
60 | extern void tlb_do_page_fault_1(void); | |
61 | ||
bf28607f DD |
62 | struct work_registers { |
63 | int r1; | |
64 | int r2; | |
65 | int r3; | |
66 | }; | |
67 | ||
68 | struct tlb_reg_save { | |
69 | unsigned long a; | |
70 | unsigned long b; | |
71 | } ____cacheline_aligned_in_smp; | |
72 | ||
73 | static struct tlb_reg_save handler_reg_save[NR_CPUS]; | |
1ec56329 | 74 | |
aeffdbba | 75 | static inline int r45k_bvahwbug(void) |
1da177e4 LT |
76 | { |
77 | /* XXX: We should probe for the presence of this bug, but we don't. */ | |
78 | return 0; | |
79 | } | |
80 | ||
aeffdbba | 81 | static inline int r4k_250MHZhwbug(void) |
1da177e4 LT |
82 | { |
83 | /* XXX: We should probe for the presence of this bug, but we don't. */ | |
84 | return 0; | |
85 | } | |
86 | ||
ab574307 TB |
87 | extern int sb1250_m3_workaround_needed(void); |
88 | ||
aeffdbba | 89 | static inline int __maybe_unused bcm1250_m3_war(void) |
1da177e4 | 90 | { |
ab574307 TB |
91 | if (IS_ENABLED(CONFIG_SB1_PASS_2_WORKAROUNDS)) |
92 | return sb1250_m3_workaround_needed(); | |
93 | return 0; | |
1da177e4 LT |
94 | } |
95 | ||
aeffdbba | 96 | static inline int __maybe_unused r10000_llsc_war(void) |
1da177e4 | 97 | { |
256ec489 | 98 | return IS_ENABLED(CONFIG_WAR_R10000_LLSC); |
1da177e4 LT |
99 | } |
100 | ||
cc33ae43 DD |
101 | static int use_bbit_insns(void) |
102 | { | |
103 | switch (current_cpu_type()) { | |
104 | case CPU_CAVIUM_OCTEON: | |
105 | case CPU_CAVIUM_OCTEON_PLUS: | |
106 | case CPU_CAVIUM_OCTEON2: | |
4723b20a | 107 | case CPU_CAVIUM_OCTEON3: |
cc33ae43 DD |
108 | return 1; |
109 | default: | |
110 | return 0; | |
111 | } | |
112 | } | |
113 | ||
2c8c53e2 DD |
114 | static int use_lwx_insns(void) |
115 | { | |
116 | switch (current_cpu_type()) { | |
117 | case CPU_CAVIUM_OCTEON2: | |
4723b20a | 118 | case CPU_CAVIUM_OCTEON3: |
2c8c53e2 DD |
119 | return 1; |
120 | default: | |
121 | return 0; | |
122 | } | |
123 | } | |
124 | #if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \ | |
125 | CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 | |
126 | static bool scratchpad_available(void) | |
127 | { | |
128 | return true; | |
129 | } | |
130 | static int scratchpad_offset(int i) | |
131 | { | |
132 | /* | |
133 | * CVMSEG starts at address -32768 and extends for | |
134 | * CAVIUM_OCTEON_CVMSEG_SIZE 128 byte cache lines. | |
135 | */ | |
136 | i += 1; /* Kernel use starts at the top and works down. */ | |
137 | return CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128 - (8 * i) - 32768; | |
138 | } | |
139 | #else | |
140 | static bool scratchpad_available(void) | |
141 | { | |
142 | return false; | |
143 | } | |
144 | static int scratchpad_offset(int i) | |
145 | { | |
146 | BUG(); | |
e1c87d2a DD |
147 | /* Really unreachable, but evidently some GCC want this. */ |
148 | return 0; | |
2c8c53e2 DD |
149 | } |
150 | #endif | |
8df5beac MR |
151 | /* |
152 | * Found by experiment: At least some revisions of the 4kc throw under | |
153 | * some circumstances a machine check exception, triggered by invalid | |
154 | * values in the index register. Delaying the tlbp instruction until | |
155 | * after the next branch, plus adding an additional nop in front of | |
156 | * tlbwi/tlbwr avoids the invalid index register values. Nobody knows | |
157 | * why; it's not an issue caused by the core RTL. | |
158 | * | |
159 | */ | |
078a55fc | 160 | static int m4kc_tlbp_war(void) |
8df5beac | 161 | { |
5f930860 | 162 | return current_cpu_type() == CPU_4KC; |
8df5beac MR |
163 | } |
164 | ||
e30ec452 | 165 | /* Handle labels (which must be positive integers). */ |
1da177e4 | 166 | enum label_id { |
e30ec452 | 167 | label_second_part = 1, |
1da177e4 LT |
168 | label_leave, |
169 | label_vmalloc, | |
170 | label_vmalloc_done, | |
02a54177 RB |
171 | label_tlbw_hazard_0, |
172 | label_split = label_tlbw_hazard_0 + 8, | |
6dd9344c DD |
173 | label_tlbl_goaround1, |
174 | label_tlbl_goaround2, | |
1da177e4 LT |
175 | label_nopage_tlbl, |
176 | label_nopage_tlbs, | |
177 | label_nopage_tlbm, | |
178 | label_smp_pgtable_change, | |
179 | label_r3000_write_probe_fail, | |
1ec56329 | 180 | label_large_segbits_fault, |
aa1762f4 | 181 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 DD |
182 | label_tlb_huge_update, |
183 | #endif | |
1da177e4 LT |
184 | }; |
185 | ||
e30ec452 TS |
186 | UASM_L_LA(_second_part) |
187 | UASM_L_LA(_leave) | |
e30ec452 TS |
188 | UASM_L_LA(_vmalloc) |
189 | UASM_L_LA(_vmalloc_done) | |
02a54177 | 190 | /* _tlbw_hazard_x is handled differently. */ |
e30ec452 | 191 | UASM_L_LA(_split) |
6dd9344c DD |
192 | UASM_L_LA(_tlbl_goaround1) |
193 | UASM_L_LA(_tlbl_goaround2) | |
e30ec452 TS |
194 | UASM_L_LA(_nopage_tlbl) |
195 | UASM_L_LA(_nopage_tlbs) | |
196 | UASM_L_LA(_nopage_tlbm) | |
197 | UASM_L_LA(_smp_pgtable_change) | |
198 | UASM_L_LA(_r3000_write_probe_fail) | |
1ec56329 | 199 | UASM_L_LA(_large_segbits_fault) |
aa1762f4 | 200 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 DD |
201 | UASM_L_LA(_tlb_huge_update) |
202 | #endif | |
656be92f | 203 | |
078a55fc | 204 | static int hazard_instance; |
02a54177 | 205 | |
078a55fc | 206 | static void uasm_bgezl_hazard(u32 **p, struct uasm_reloc **r, int instance) |
02a54177 RB |
207 | { |
208 | switch (instance) { | |
209 | case 0 ... 7: | |
210 | uasm_il_bgezl(p, r, 0, label_tlbw_hazard_0 + instance); | |
211 | return; | |
212 | default: | |
213 | BUG(); | |
214 | } | |
215 | } | |
216 | ||
078a55fc | 217 | static void uasm_bgezl_label(struct uasm_label **l, u32 **p, int instance) |
02a54177 RB |
218 | { |
219 | switch (instance) { | |
220 | case 0 ... 7: | |
221 | uasm_build_label(l, *p, label_tlbw_hazard_0 + instance); | |
222 | break; | |
223 | default: | |
224 | BUG(); | |
225 | } | |
226 | } | |
227 | ||
92b1e6a6 | 228 | /* |
a2c763e0 RB |
229 | * pgtable bits are assigned dynamically depending on processor feature |
230 | * and statically based on kernel configuration. This spits out the actual | |
70342287 | 231 | * values the kernel is using. Required to make sense from disassembled |
a2c763e0 | 232 | * TLB exception handlers. |
92b1e6a6 | 233 | */ |
a2c763e0 RB |
234 | static void output_pgtable_bits_defines(void) |
235 | { | |
236 | #define pr_define(fmt, ...) \ | |
237 | pr_debug("#define " fmt, ##__VA_ARGS__) | |
238 | ||
239 | pr_debug("#include <asm/asm.h>\n"); | |
240 | pr_debug("#include <asm/regdef.h>\n"); | |
241 | pr_debug("\n"); | |
242 | ||
243 | pr_define("_PAGE_PRESENT_SHIFT %d\n", _PAGE_PRESENT_SHIFT); | |
780602d7 | 244 | pr_define("_PAGE_NO_READ_SHIFT %d\n", _PAGE_NO_READ_SHIFT); |
a2c763e0 RB |
245 | pr_define("_PAGE_WRITE_SHIFT %d\n", _PAGE_WRITE_SHIFT); |
246 | pr_define("_PAGE_ACCESSED_SHIFT %d\n", _PAGE_ACCESSED_SHIFT); | |
247 | pr_define("_PAGE_MODIFIED_SHIFT %d\n", _PAGE_MODIFIED_SHIFT); | |
970d032f | 248 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
a2c763e0 RB |
249 | pr_define("_PAGE_HUGE_SHIFT %d\n", _PAGE_HUGE_SHIFT); |
250 | #endif | |
a2c763e0 | 251 | #ifdef _PAGE_NO_EXEC_SHIFT |
780602d7 | 252 | if (cpu_has_rixi) |
a2c763e0 | 253 | pr_define("_PAGE_NO_EXEC_SHIFT %d\n", _PAGE_NO_EXEC_SHIFT); |
be0c37c9 | 254 | #endif |
a2c763e0 RB |
255 | pr_define("_PAGE_GLOBAL_SHIFT %d\n", _PAGE_GLOBAL_SHIFT); |
256 | pr_define("_PAGE_VALID_SHIFT %d\n", _PAGE_VALID_SHIFT); | |
257 | pr_define("_PAGE_DIRTY_SHIFT %d\n", _PAGE_DIRTY_SHIFT); | |
15fa3e8e | 258 | pr_define("PFN_PTE_SHIFT %d\n", PFN_PTE_SHIFT); |
a2c763e0 RB |
259 | pr_debug("\n"); |
260 | } | |
261 | ||
4bcb4ad6 | 262 | static inline void dump_handler(const char *symbol, const void *start, const void *end) |
92b1e6a6 | 263 | { |
4bcb4ad6 PB |
264 | unsigned int count = (end - start) / sizeof(u32); |
265 | const u32 *handler = start; | |
92b1e6a6 FBH |
266 | int i; |
267 | ||
a2c763e0 RB |
268 | pr_debug("LEAF(%s)\n", symbol); |
269 | ||
92b1e6a6 FBH |
270 | pr_debug("\t.set push\n"); |
271 | pr_debug("\t.set noreorder\n"); | |
272 | ||
273 | for (i = 0; i < count; i++) | |
a2c763e0 | 274 | pr_debug("\t.word\t0x%08x\t\t# %p\n", handler[i], &handler[i]); |
92b1e6a6 | 275 | |
a2c763e0 RB |
276 | pr_debug("\t.set\tpop\n"); |
277 | ||
278 | pr_debug("\tEND(%s)\n", symbol); | |
92b1e6a6 FBH |
279 | } |
280 | ||
875d43e7 | 281 | #ifdef CONFIG_64BIT |
e30ec452 | 282 | # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT) |
1da177e4 | 283 | #else |
e30ec452 | 284 | # define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT) |
1da177e4 LT |
285 | #endif |
286 | ||
287 | /* The worst case length of the handler is around 18 instructions for | |
288 | * R3000-style TLBs and up to 63 instructions for R4000-style TLBs. | |
289 | * Maximum space available is 32 instructions for R3000 and 64 | |
290 | * instructions for R4000. | |
291 | * | |
292 | * We deliberately chose a buffer size of 128, so we won't scribble | |
293 | * over anything important on overflow before we panic. | |
294 | */ | |
078a55fc | 295 | static u32 tlb_handler[128]; |
1da177e4 LT |
296 | |
297 | /* simply assume worst case size for labels and relocs */ | |
078a55fc PG |
298 | static struct uasm_label labels[128]; |
299 | static struct uasm_reloc relocs[128]; | |
1da177e4 | 300 | |
078a55fc | 301 | static int check_for_high_segbits; |
00bf1c69 | 302 | static bool fill_includes_sw_bits; |
3d8bfdd0 | 303 | |
078a55fc | 304 | static unsigned int kscratch_used_mask; |
3d8bfdd0 | 305 | |
7777b939 J |
306 | static inline int __maybe_unused c0_kscratch(void) |
307 | { | |
95b8a5e0 | 308 | return 31; |
7777b939 J |
309 | } |
310 | ||
078a55fc | 311 | static int allocate_kscratch(void) |
3d8bfdd0 DD |
312 | { |
313 | int r; | |
314 | unsigned int a = cpu_data[0].kscratch_mask & ~kscratch_used_mask; | |
315 | ||
316 | r = ffs(a); | |
317 | ||
318 | if (r == 0) | |
319 | return -1; | |
320 | ||
321 | r--; /* make it zero based */ | |
322 | ||
323 | kscratch_used_mask |= (1 << r); | |
324 | ||
325 | return r; | |
326 | } | |
327 | ||
078a55fc | 328 | static int scratch_reg; |
722b4544 JH |
329 | int pgd_reg; |
330 | EXPORT_SYMBOL_GPL(pgd_reg); | |
2c8c53e2 DD |
331 | enum vmalloc64_mode {not_refill, refill_scratch, refill_noscratch}; |
332 | ||
078a55fc | 333 | static struct work_registers build_get_work_registers(u32 **p) |
bf28607f DD |
334 | { |
335 | struct work_registers r; | |
336 | ||
0e6ecc1a | 337 | if (scratch_reg >= 0) { |
bf28607f | 338 | /* Save in CPU local C0_KScratch? */ |
7777b939 | 339 | UASM_i_MTC0(p, 1, c0_kscratch(), scratch_reg); |
8cc461b8 JY |
340 | r.r1 = GPR_K0; |
341 | r.r2 = GPR_K1; | |
342 | r.r3 = GPR_AT; | |
bf28607f DD |
343 | return r; |
344 | } | |
345 | ||
346 | if (num_possible_cpus() > 1) { | |
bf28607f | 347 | /* Get smp_processor_id */ |
8cc461b8 JY |
348 | UASM_i_CPUID_MFC0(p, GPR_K0, SMP_CPUID_REG); |
349 | UASM_i_SRL_SAFE(p, GPR_K0, GPR_K0, SMP_CPUID_REGSHIFT); | |
bf28607f | 350 | |
8cc461b8 JY |
351 | /* handler_reg_save index in GPR_K0 */ |
352 | UASM_i_SLL(p, GPR_K0, GPR_K0, ilog2(sizeof(struct tlb_reg_save))); | |
bf28607f | 353 | |
8cc461b8 JY |
354 | UASM_i_LA(p, GPR_K1, (long)&handler_reg_save); |
355 | UASM_i_ADDU(p, GPR_K0, GPR_K0, GPR_K1); | |
bf28607f | 356 | } else { |
8cc461b8 | 357 | UASM_i_LA(p, GPR_K0, (long)&handler_reg_save); |
bf28607f | 358 | } |
8cc461b8 JY |
359 | /* GPR_K0 now points to save area, save $1 and $2 */ |
360 | UASM_i_SW(p, 1, offsetof(struct tlb_reg_save, a), GPR_K0); | |
361 | UASM_i_SW(p, 2, offsetof(struct tlb_reg_save, b), GPR_K0); | |
bf28607f | 362 | |
8cc461b8 | 363 | r.r1 = GPR_K1; |
bf28607f DD |
364 | r.r2 = 1; |
365 | r.r3 = 2; | |
366 | return r; | |
367 | } | |
368 | ||
078a55fc | 369 | static void build_restore_work_registers(u32 **p) |
bf28607f | 370 | { |
0e6ecc1a | 371 | if (scratch_reg >= 0) { |
0b24cae4 | 372 | uasm_i_ehb(p); |
7777b939 | 373 | UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); |
bf28607f DD |
374 | return; |
375 | } | |
8cc461b8 JY |
376 | /* GPR_K0 already points to save area, restore $1 and $2 */ |
377 | UASM_i_LW(p, 1, offsetof(struct tlb_reg_save, a), GPR_K0); | |
378 | UASM_i_LW(p, 2, offsetof(struct tlb_reg_save, b), GPR_K0); | |
bf28607f DD |
379 | } |
380 | ||
2c8c53e2 | 381 | #ifndef CONFIG_MIPS_PGD_C0_CONTEXT |
3d8bfdd0 | 382 | |
82622284 DD |
383 | /* |
384 | * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current, | |
385 | * we cannot do r3000 under these circumstances. | |
3d8bfdd0 | 386 | * |
1da177e4 LT |
387 | * The R3000 TLB handler is simple. |
388 | */ | |
078a55fc | 389 | static void build_r3000_tlb_refill_handler(void) |
1da177e4 LT |
390 | { |
391 | long pgdc = (long)pgd_current; | |
392 | u32 *p; | |
393 | ||
394 | memset(tlb_handler, 0, sizeof(tlb_handler)); | |
395 | p = tlb_handler; | |
396 | ||
8cc461b8 JY |
397 | uasm_i_mfc0(&p, GPR_K0, C0_BADVADDR); |
398 | uasm_i_lui(&p, GPR_K1, uasm_rel_hi(pgdc)); /* cp0 delay */ | |
399 | uasm_i_lw(&p, GPR_K1, uasm_rel_lo(pgdc), GPR_K1); | |
400 | uasm_i_srl(&p, GPR_K0, GPR_K0, 22); /* load delay */ | |
401 | uasm_i_sll(&p, GPR_K0, GPR_K0, 2); | |
402 | uasm_i_addu(&p, GPR_K1, GPR_K1, GPR_K0); | |
403 | uasm_i_mfc0(&p, GPR_K0, C0_CONTEXT); | |
404 | uasm_i_lw(&p, GPR_K1, 0, GPR_K1); /* cp0 delay */ | |
405 | uasm_i_andi(&p, GPR_K0, GPR_K0, 0xffc); /* load delay */ | |
406 | uasm_i_addu(&p, GPR_K1, GPR_K1, GPR_K0); | |
407 | uasm_i_lw(&p, GPR_K0, 0, GPR_K1); | |
e30ec452 | 408 | uasm_i_nop(&p); /* load delay */ |
8cc461b8 JY |
409 | uasm_i_mtc0(&p, GPR_K0, C0_ENTRYLO0); |
410 | uasm_i_mfc0(&p, GPR_K1, C0_EPC); /* cp0 delay */ | |
e30ec452 | 411 | uasm_i_tlbwr(&p); /* cp0 delay */ |
8cc461b8 | 412 | uasm_i_jr(&p, GPR_K1); |
e30ec452 | 413 | uasm_i_rfe(&p); /* branch delay */ |
1da177e4 LT |
414 | |
415 | if (p > tlb_handler + 32) | |
416 | panic("TLB refill handler space exceeded"); | |
417 | ||
e30ec452 TS |
418 | pr_debug("Wrote TLB refill handler (%u instructions).\n", |
419 | (unsigned int)(p - tlb_handler)); | |
1da177e4 | 420 | |
91b05e67 | 421 | memcpy((void *)ebase, tlb_handler, 0x80); |
1062080a | 422 | local_flush_icache_range(ebase, ebase + 0x80); |
4bcb4ad6 | 423 | dump_handler("r3000_tlb_refill", (u32 *)ebase, (u32 *)(ebase + 0x80)); |
1da177e4 | 424 | } |
82622284 | 425 | #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ |
1da177e4 LT |
426 | |
427 | /* | |
428 | * The R4000 TLB handler is much more complicated. We have two | |
429 | * consecutive handler areas with 32 instructions space each. | |
430 | * Since they aren't used at the same time, we can overflow in the | |
431 | * other one.To keep things simple, we first assume linear space, | |
432 | * then we relocate it to the final handler layout as needed. | |
433 | */ | |
078a55fc | 434 | static u32 final_handler[64]; |
1da177e4 LT |
435 | |
436 | /* | |
437 | * Hazards | |
438 | * | |
439 | * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0: | |
440 | * 2. A timing hazard exists for the TLBP instruction. | |
441 | * | |
70342287 RB |
442 | * stalling_instruction |
443 | * TLBP | |
1da177e4 LT |
444 | * |
445 | * The JTLB is being read for the TLBP throughout the stall generated by the | |
446 | * previous instruction. This is not really correct as the stalling instruction | |
447 | * can modify the address used to access the JTLB. The failure symptom is that | |
448 | * the TLBP instruction will use an address created for the stalling instruction | |
449 | * and not the address held in C0_ENHI and thus report the wrong results. | |
450 | * | |
451 | * The software work-around is to not allow the instruction preceding the TLBP | |
452 | * to stall - make it an NOP or some other instruction guaranteed not to stall. | |
453 | * | |
70342287 | 454 | * Errata 2 will not be fixed. This errata is also on the R5000. |
1da177e4 LT |
455 | * |
456 | * As if we MIPS hackers wouldn't know how to nop pipelines happy ... | |
457 | */ | |
078a55fc | 458 | static void __maybe_unused build_tlb_probe_entry(u32 **p) |
1da177e4 | 459 | { |
10cc3529 | 460 | switch (current_cpu_type()) { |
326e2e1a | 461 | /* Found by experiment: R4600 v2.0/R4700 needs this, too. */ |
f5b4d956 | 462 | case CPU_R4600: |
326e2e1a | 463 | case CPU_R4700: |
1da177e4 | 464 | case CPU_R5000: |
1da177e4 | 465 | case CPU_NEVADA: |
e30ec452 TS |
466 | uasm_i_nop(p); |
467 | uasm_i_tlbp(p); | |
1da177e4 LT |
468 | break; |
469 | ||
470 | default: | |
e30ec452 | 471 | uasm_i_tlbp(p); |
1da177e4 LT |
472 | break; |
473 | } | |
474 | } | |
475 | ||
722b4544 JH |
476 | void build_tlb_write_entry(u32 **p, struct uasm_label **l, |
477 | struct uasm_reloc **r, | |
478 | enum tlb_write_entry wmode) | |
1da177e4 LT |
479 | { |
480 | void(*tlbw)(u32 **) = NULL; | |
481 | ||
482 | switch (wmode) { | |
e30ec452 TS |
483 | case tlb_random: tlbw = uasm_i_tlbwr; break; |
484 | case tlb_indexed: tlbw = uasm_i_tlbwi; break; | |
1da177e4 LT |
485 | } |
486 | ||
9eaffa84 RB |
487 | if (cpu_has_mips_r2_r6) { |
488 | if (cpu_has_mips_r2_exec_hazard) | |
41f0e4d0 | 489 | uasm_i_ehb(p); |
161548bf RB |
490 | tlbw(p); |
491 | return; | |
492 | } | |
493 | ||
10cc3529 | 494 | switch (current_cpu_type()) { |
1da177e4 LT |
495 | case CPU_R4000PC: |
496 | case CPU_R4000SC: | |
497 | case CPU_R4000MC: | |
498 | case CPU_R4400PC: | |
499 | case CPU_R4400SC: | |
500 | case CPU_R4400MC: | |
501 | /* | |
502 | * This branch uses up a mtc0 hazard nop slot and saves | |
503 | * two nops after the tlbw instruction. | |
504 | */ | |
02a54177 | 505 | uasm_bgezl_hazard(p, r, hazard_instance); |
1da177e4 | 506 | tlbw(p); |
02a54177 RB |
507 | uasm_bgezl_label(l, p, hazard_instance); |
508 | hazard_instance++; | |
e30ec452 | 509 | uasm_i_nop(p); |
1da177e4 LT |
510 | break; |
511 | ||
512 | case CPU_R4600: | |
513 | case CPU_R4700: | |
e30ec452 | 514 | uasm_i_nop(p); |
2c93e12c | 515 | tlbw(p); |
e30ec452 | 516 | uasm_i_nop(p); |
2c93e12c MR |
517 | break; |
518 | ||
359187d6 | 519 | case CPU_R5000: |
359187d6 RB |
520 | case CPU_NEVADA: |
521 | uasm_i_nop(p); /* QED specifies 2 nops hazard */ | |
522 | uasm_i_nop(p); /* QED specifies 2 nops hazard */ | |
523 | tlbw(p); | |
524 | break; | |
525 | ||
65ce6197 | 526 | case CPU_R4300: |
1da177e4 LT |
527 | case CPU_5KC: |
528 | case CPU_TX49XX: | |
bdf21b18 | 529 | case CPU_PR4450: |
e30ec452 | 530 | uasm_i_nop(p); |
1da177e4 LT |
531 | tlbw(p); |
532 | break; | |
533 | ||
534 | case CPU_R10000: | |
535 | case CPU_R12000: | |
44d921b2 | 536 | case CPU_R14000: |
30577391 | 537 | case CPU_R16000: |
1da177e4 | 538 | case CPU_4KC: |
b1ec4c8e | 539 | case CPU_4KEC: |
113c62d9 | 540 | case CPU_M14KC: |
f8fa4811 | 541 | case CPU_M14KEC: |
1da177e4 | 542 | case CPU_SB1: |
93ce2f52 | 543 | case CPU_SB1A: |
1da177e4 LT |
544 | case CPU_4KSC: |
545 | case CPU_20KC: | |
546 | case CPU_25KF: | |
602977b0 KC |
547 | case CPU_BMIPS32: |
548 | case CPU_BMIPS3300: | |
549 | case CPU_BMIPS4350: | |
550 | case CPU_BMIPS4380: | |
551 | case CPU_BMIPS5000: | |
268a2d60 JY |
552 | case CPU_LOONGSON2EF: |
553 | case CPU_LOONGSON64: | |
a644b277 | 554 | case CPU_R5500: |
8df5beac | 555 | if (m4kc_tlbp_war()) |
e30ec452 | 556 | uasm_i_nop(p); |
c9b02990 | 557 | fallthrough; |
2f794d09 | 558 | case CPU_ALCHEMY: |
1da177e4 LT |
559 | tlbw(p); |
560 | break; | |
561 | ||
1da177e4 | 562 | case CPU_RM7000: |
e30ec452 TS |
563 | uasm_i_nop(p); |
564 | uasm_i_nop(p); | |
565 | uasm_i_nop(p); | |
566 | uasm_i_nop(p); | |
1da177e4 LT |
567 | tlbw(p); |
568 | break; | |
569 | ||
3b25b763 | 570 | case CPU_XBURST: |
83ccf69d LPC |
571 | tlbw(p); |
572 | uasm_i_nop(p); | |
573 | break; | |
574 | ||
1da177e4 LT |
575 | default: |
576 | panic("No TLB refill handler yet (CPU type: %d)", | |
d7b12056 | 577 | current_cpu_type()); |
1da177e4 LT |
578 | break; |
579 | } | |
580 | } | |
722b4544 | 581 | EXPORT_SYMBOL_GPL(build_tlb_write_entry); |
1da177e4 | 582 | |
078a55fc PG |
583 | static __maybe_unused void build_convert_pte_to_entrylo(u32 **p, |
584 | unsigned int reg) | |
fd062c84 | 585 | { |
2caa89b4 PB |
586 | if (_PAGE_GLOBAL_SHIFT == 0) { |
587 | /* pte_t is already in EntryLo format */ | |
588 | return; | |
589 | } | |
590 | ||
74de14fe | 591 | if (cpu_has_rixi && _PAGE_NO_EXEC != 0) { |
00bf1c69 PB |
592 | if (fill_includes_sw_bits) { |
593 | UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL)); | |
594 | } else { | |
595 | UASM_i_SRL(p, reg, reg, ilog2(_PAGE_NO_EXEC)); | |
596 | UASM_i_ROTR(p, reg, reg, | |
597 | ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); | |
598 | } | |
6dd9344c | 599 | } else { |
34adb28d | 600 | #ifdef CONFIG_PHYS_ADDR_T_64BIT |
3be6022c | 601 | uasm_i_dsrl_safe(p, reg, reg, ilog2(_PAGE_GLOBAL)); |
6dd9344c DD |
602 | #else |
603 | UASM_i_SRL(p, reg, reg, ilog2(_PAGE_GLOBAL)); | |
604 | #endif | |
605 | } | |
606 | } | |
fd062c84 | 607 | |
aa1762f4 | 608 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 | 609 | |
078a55fc PG |
610 | static void build_restore_pagemask(u32 **p, struct uasm_reloc **r, |
611 | unsigned int tmp, enum label_id lid, | |
612 | int restore_scratch) | |
6dd9344c | 613 | { |
2c8c53e2 | 614 | if (restore_scratch) { |
b42aa3fd PB |
615 | /* |
616 | * Ensure the MFC0 below observes the value written to the | |
617 | * KScratch register by the prior MTC0. | |
618 | */ | |
619 | if (scratch_reg >= 0) | |
620 | uasm_i_ehb(p); | |
621 | ||
2c8c53e2 DD |
622 | /* Reset default page size */ |
623 | if (PM_DEFAULT_MASK >> 16) { | |
624 | uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16); | |
625 | uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff); | |
626 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); | |
627 | uasm_il_b(p, r, lid); | |
628 | } else if (PM_DEFAULT_MASK) { | |
629 | uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK); | |
630 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); | |
631 | uasm_il_b(p, r, lid); | |
632 | } else { | |
633 | uasm_i_mtc0(p, 0, C0_PAGEMASK); | |
634 | uasm_il_b(p, r, lid); | |
635 | } | |
b42aa3fd | 636 | if (scratch_reg >= 0) |
7777b939 | 637 | UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); |
b42aa3fd | 638 | else |
2c8c53e2 | 639 | UASM_i_LW(p, 1, scratchpad_offset(0), 0); |
fd062c84 | 640 | } else { |
2c8c53e2 DD |
641 | /* Reset default page size */ |
642 | if (PM_DEFAULT_MASK >> 16) { | |
643 | uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16); | |
644 | uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff); | |
645 | uasm_il_b(p, r, lid); | |
646 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); | |
647 | } else if (PM_DEFAULT_MASK) { | |
648 | uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK); | |
649 | uasm_il_b(p, r, lid); | |
650 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); | |
651 | } else { | |
652 | uasm_il_b(p, r, lid); | |
653 | uasm_i_mtc0(p, 0, C0_PAGEMASK); | |
654 | } | |
fd062c84 DD |
655 | } |
656 | } | |
657 | ||
078a55fc PG |
658 | static void build_huge_tlb_write_entry(u32 **p, struct uasm_label **l, |
659 | struct uasm_reloc **r, | |
660 | unsigned int tmp, | |
661 | enum tlb_write_entry wmode, | |
662 | int restore_scratch) | |
6dd9344c DD |
663 | { |
664 | /* Set huge page tlb entry size */ | |
665 | uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16); | |
666 | uasm_i_ori(p, tmp, tmp, PM_HUGE_MASK & 0xffff); | |
667 | uasm_i_mtc0(p, tmp, C0_PAGEMASK); | |
668 | ||
669 | build_tlb_write_entry(p, l, r, wmode); | |
670 | ||
2c8c53e2 | 671 | build_restore_pagemask(p, r, tmp, label_leave, restore_scratch); |
6dd9344c DD |
672 | } |
673 | ||
fd062c84 DD |
674 | /* |
675 | * Check if Huge PTE is present, if so then jump to LABEL. | |
676 | */ | |
078a55fc | 677 | static void |
fd062c84 | 678 | build_is_huge_pte(u32 **p, struct uasm_reloc **r, unsigned int tmp, |
078a55fc | 679 | unsigned int pmd, int lid) |
fd062c84 DD |
680 | { |
681 | UASM_i_LW(p, tmp, 0, pmd); | |
cc33ae43 DD |
682 | if (use_bbit_insns()) { |
683 | uasm_il_bbit1(p, r, tmp, ilog2(_PAGE_HUGE), lid); | |
684 | } else { | |
685 | uasm_i_andi(p, tmp, tmp, _PAGE_HUGE); | |
686 | uasm_il_bnez(p, r, tmp, lid); | |
687 | } | |
fd062c84 DD |
688 | } |
689 | ||
078a55fc PG |
690 | static void build_huge_update_entries(u32 **p, unsigned int pte, |
691 | unsigned int tmp) | |
fd062c84 DD |
692 | { |
693 | int small_sequence; | |
694 | ||
695 | /* | |
696 | * A huge PTE describes an area the size of the | |
697 | * configured huge page size. This is twice the | |
698 | * of the large TLB entry size we intend to use. | |
699 | * A TLB entry half the size of the configured | |
700 | * huge page size is configured into entrylo0 | |
701 | * and entrylo1 to cover the contiguous huge PTE | |
702 | * address space. | |
703 | */ | |
704 | small_sequence = (HPAGE_SIZE >> 7) < 0x10000; | |
705 | ||
70342287 | 706 | /* We can clobber tmp. It isn't used after this.*/ |
fd062c84 DD |
707 | if (!small_sequence) |
708 | uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16)); | |
709 | ||
6dd9344c | 710 | build_convert_pte_to_entrylo(p, pte); |
9b8c3891 | 711 | UASM_i_MTC0(p, pte, C0_ENTRYLO0); /* load it */ |
fd062c84 DD |
712 | /* convert to entrylo1 */ |
713 | if (small_sequence) | |
714 | UASM_i_ADDIU(p, pte, pte, HPAGE_SIZE >> 7); | |
715 | else | |
716 | UASM_i_ADDU(p, pte, pte, tmp); | |
717 | ||
9b8c3891 | 718 | UASM_i_MTC0(p, pte, C0_ENTRYLO1); /* load it */ |
fd062c84 DD |
719 | } |
720 | ||
078a55fc PG |
721 | static void build_huge_handler_tail(u32 **p, struct uasm_reloc **r, |
722 | struct uasm_label **l, | |
723 | unsigned int pte, | |
0115f6cb HC |
724 | unsigned int ptr, |
725 | unsigned int flush) | |
fd062c84 DD |
726 | { |
727 | #ifdef CONFIG_SMP | |
728 | UASM_i_SC(p, pte, 0, ptr); | |
729 | uasm_il_beqz(p, r, pte, label_tlb_huge_update); | |
730 | UASM_i_LW(p, pte, 0, ptr); /* Needed because SC killed our PTE */ | |
731 | #else | |
732 | UASM_i_SW(p, pte, 0, ptr); | |
733 | #endif | |
0115f6cb HC |
734 | if (cpu_has_ftlb && flush) { |
735 | BUG_ON(!cpu_has_tlbinv); | |
736 | ||
737 | UASM_i_MFC0(p, ptr, C0_ENTRYHI); | |
738 | uasm_i_ori(p, ptr, ptr, MIPS_ENTRYHI_EHINV); | |
739 | UASM_i_MTC0(p, ptr, C0_ENTRYHI); | |
740 | build_tlb_write_entry(p, l, r, tlb_indexed); | |
741 | ||
742 | uasm_i_xori(p, ptr, ptr, MIPS_ENTRYHI_EHINV); | |
743 | UASM_i_MTC0(p, ptr, C0_ENTRYHI); | |
744 | build_huge_update_entries(p, pte, ptr); | |
745 | build_huge_tlb_write_entry(p, l, r, pte, tlb_random, 0); | |
746 | ||
747 | return; | |
748 | } | |
749 | ||
fd062c84 | 750 | build_huge_update_entries(p, pte, ptr); |
2c8c53e2 | 751 | build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed, 0); |
fd062c84 | 752 | } |
aa1762f4 | 753 | #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */ |
fd062c84 | 754 | |
875d43e7 | 755 | #ifdef CONFIG_64BIT |
1da177e4 LT |
756 | /* |
757 | * TMP and PTR are scratch. | |
758 | * TMP will be clobbered, PTR will hold the pmd entry. | |
759 | */ | |
722b4544 JH |
760 | void build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, |
761 | unsigned int tmp, unsigned int ptr) | |
1da177e4 | 762 | { |
82622284 | 763 | #ifndef CONFIG_MIPS_PGD_C0_CONTEXT |
1da177e4 | 764 | long pgdc = (long)pgd_current; |
82622284 | 765 | #endif |
1da177e4 LT |
766 | /* |
767 | * The vmalloc handling is not in the hotpath. | |
768 | */ | |
e30ec452 | 769 | uasm_i_dmfc0(p, tmp, C0_BADVADDR); |
1ec56329 DD |
770 | |
771 | if (check_for_high_segbits) { | |
772 | /* | |
2f9060b1 | 773 | * The kernel currently implicitly assumes that the |
1ec56329 DD |
774 | * MIPS SEGBITS parameter for the processor is |
775 | * (PGDIR_SHIFT+PGDIR_BITS) or less, and will never | |
776 | * allocate virtual addresses outside the maximum | |
777 | * range for SEGBITS = (PGDIR_SHIFT+PGDIR_BITS). But | |
778 | * that doesn't prevent user code from accessing the | |
779 | * higher xuseg addresses. Here, we make sure that | |
780 | * everything but the lower xuseg addresses goes down | |
781 | * the module_alloc/vmalloc path. | |
782 | */ | |
bb5af4f6 | 783 | uasm_i_dsrl_safe(p, ptr, tmp, PGDIR_SHIFT + PGD_TABLE_ORDER + PAGE_SHIFT - 3); |
1ec56329 DD |
784 | uasm_il_bnez(p, r, ptr, label_vmalloc); |
785 | } else { | |
786 | uasm_il_bltz(p, r, tmp, label_vmalloc); | |
787 | } | |
e30ec452 | 788 | /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */ |
1da177e4 | 789 | |
3d8bfdd0 DD |
790 | if (pgd_reg != -1) { |
791 | /* pgd is in pgd_reg */ | |
380cd582 HC |
792 | if (cpu_has_ldpte) |
793 | UASM_i_MFC0(p, ptr, C0_PWBASE); | |
794 | else | |
795 | UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); | |
3d8bfdd0 | 796 | } else { |
f4ae17aa | 797 | #if defined(CONFIG_MIPS_PGD_C0_CONTEXT) |
3d8bfdd0 DD |
798 | /* |
799 | * &pgd << 11 stored in CONTEXT [23..63]. | |
800 | */ | |
801 | UASM_i_MFC0(p, ptr, C0_CONTEXT); | |
802 | ||
803 | /* Clear lower 23 bits of context. */ | |
804 | uasm_i_dins(p, ptr, 0, 0, 23); | |
805 | ||
c6972fb9 HP |
806 | /* insert bit[63:59] of CAC_BASE into bit[11:6] of ptr */ |
807 | uasm_i_ori(p, ptr, ptr, ((u64)(CAC_BASE) >> 53)); | |
3d8bfdd0 | 808 | uasm_i_drotr(p, ptr, ptr, 11); |
82622284 | 809 | #elif defined(CONFIG_SMP) |
f4ae17aa J |
810 | UASM_i_CPUID_MFC0(p, ptr, SMP_CPUID_REG); |
811 | uasm_i_dsrl_safe(p, ptr, ptr, SMP_CPUID_PTRSHIFT); | |
812 | UASM_i_LA_mostly(p, tmp, pgdc); | |
813 | uasm_i_daddu(p, ptr, ptr, tmp); | |
814 | uasm_i_dmfc0(p, tmp, C0_BADVADDR); | |
815 | uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); | |
1da177e4 | 816 | #else |
f4ae17aa J |
817 | UASM_i_LA_mostly(p, ptr, pgdc); |
818 | uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); | |
1da177e4 | 819 | #endif |
f4ae17aa | 820 | } |
1da177e4 | 821 | |
e30ec452 | 822 | uasm_l_vmalloc_done(l, *p); |
242954b5 | 823 | |
3be6022c DD |
824 | /* get pgd offset in bytes */ |
825 | uasm_i_dsrl_safe(p, tmp, tmp, PGDIR_SHIFT - 3); | |
e30ec452 TS |
826 | |
827 | uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3); | |
828 | uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */ | |
3377e227 AB |
829 | #ifndef __PAGETABLE_PUD_FOLDED |
830 | uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */ | |
831 | uasm_i_ld(p, ptr, 0, ptr); /* get pud pointer */ | |
832 | uasm_i_dsrl_safe(p, tmp, tmp, PUD_SHIFT - 3); /* get pud offset in bytes */ | |
833 | uasm_i_andi(p, tmp, tmp, (PTRS_PER_PUD - 1) << 3); | |
834 | uasm_i_daddu(p, ptr, ptr, tmp); /* add in pud offset */ | |
835 | #endif | |
325f8a0a | 836 | #ifndef __PAGETABLE_PMD_FOLDED |
e30ec452 TS |
837 | uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */ |
838 | uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */ | |
3be6022c | 839 | uasm_i_dsrl_safe(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */ |
e30ec452 TS |
840 | uasm_i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3); |
841 | uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */ | |
325f8a0a | 842 | #endif |
1da177e4 | 843 | } |
722b4544 | 844 | EXPORT_SYMBOL_GPL(build_get_pmde64); |
1da177e4 LT |
845 | |
846 | /* | |
847 | * BVADDR is the faulting address, PTR is scratch. | |
848 | * PTR will hold the pgd for vmalloc. | |
849 | */ | |
078a55fc | 850 | static void |
e30ec452 | 851 | build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, |
1ec56329 DD |
852 | unsigned int bvaddr, unsigned int ptr, |
853 | enum vmalloc64_mode mode) | |
1da177e4 LT |
854 | { |
855 | long swpd = (long)swapper_pg_dir; | |
1ec56329 DD |
856 | int single_insn_swpd; |
857 | int did_vmalloc_branch = 0; | |
858 | ||
859 | single_insn_swpd = uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd); | |
1da177e4 | 860 | |
e30ec452 | 861 | uasm_l_vmalloc(l, *p); |
1da177e4 | 862 | |
2c8c53e2 | 863 | if (mode != not_refill && check_for_high_segbits) { |
1ec56329 DD |
864 | if (single_insn_swpd) { |
865 | uasm_il_bltz(p, r, bvaddr, label_vmalloc_done); | |
866 | uasm_i_lui(p, ptr, uasm_rel_hi(swpd)); | |
867 | did_vmalloc_branch = 1; | |
868 | /* fall through */ | |
869 | } else { | |
870 | uasm_il_bgez(p, r, bvaddr, label_large_segbits_fault); | |
871 | } | |
872 | } | |
873 | if (!did_vmalloc_branch) { | |
2f8f8c04 | 874 | if (single_insn_swpd) { |
1ec56329 DD |
875 | uasm_il_b(p, r, label_vmalloc_done); |
876 | uasm_i_lui(p, ptr, uasm_rel_hi(swpd)); | |
877 | } else { | |
878 | UASM_i_LA_mostly(p, ptr, swpd); | |
879 | uasm_il_b(p, r, label_vmalloc_done); | |
880 | if (uasm_in_compat_space_p(swpd)) | |
881 | uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd)); | |
882 | else | |
883 | uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd)); | |
884 | } | |
885 | } | |
2c8c53e2 | 886 | if (mode != not_refill && check_for_high_segbits) { |
1ec56329 | 887 | uasm_l_large_segbits_fault(l, *p); |
b42aa3fd PB |
888 | |
889 | if (mode == refill_scratch && scratch_reg >= 0) | |
890 | uasm_i_ehb(p); | |
891 | ||
1ec56329 DD |
892 | /* |
893 | * We get here if we are an xsseg address, or if we are | |
894 | * an xuseg address above (PGDIR_SHIFT+PGDIR_BITS) boundary. | |
895 | * | |
896 | * Ignoring xsseg (assume disabled so would generate | |
897 | * (address errors?), the only remaining possibility | |
898 | * is the upper xuseg addresses. On processors with | |
899 | * TLB_SEGBITS <= PGDIR_SHIFT+PGDIR_BITS, these | |
900 | * addresses would have taken an address error. We try | |
901 | * to mimic that here by taking a load/istream page | |
902 | * fault. | |
903 | */ | |
e02e07e3 HC |
904 | if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS)) |
905 | uasm_i_sync(p, 0); | |
1ec56329 DD |
906 | UASM_i_LA(p, ptr, (unsigned long)tlb_do_page_fault_0); |
907 | uasm_i_jr(p, ptr); | |
2c8c53e2 DD |
908 | |
909 | if (mode == refill_scratch) { | |
b42aa3fd | 910 | if (scratch_reg >= 0) |
7777b939 | 911 | UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); |
b42aa3fd | 912 | else |
2c8c53e2 DD |
913 | UASM_i_LW(p, 1, scratchpad_offset(0), 0); |
914 | } else { | |
915 | uasm_i_nop(p); | |
916 | } | |
1da177e4 LT |
917 | } |
918 | } | |
919 | ||
875d43e7 | 920 | #else /* !CONFIG_64BIT */ |
1da177e4 LT |
921 | |
922 | /* | |
923 | * TMP and PTR are scratch. | |
924 | * TMP will be clobbered, PTR will hold the pgd entry. | |
925 | */ | |
722b4544 | 926 | void build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) |
1da177e4 | 927 | { |
f4ae17aa J |
928 | if (pgd_reg != -1) { |
929 | /* pgd is in pgd_reg */ | |
930 | uasm_i_mfc0(p, ptr, c0_kscratch(), pgd_reg); | |
931 | uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ | |
932 | } else { | |
933 | long pgdc = (long)pgd_current; | |
1da177e4 | 934 | |
f4ae17aa | 935 | /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */ |
1da177e4 | 936 | #ifdef CONFIG_SMP |
f4ae17aa J |
937 | uasm_i_mfc0(p, ptr, SMP_CPUID_REG); |
938 | UASM_i_LA_mostly(p, tmp, pgdc); | |
939 | uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT); | |
940 | uasm_i_addu(p, ptr, tmp, ptr); | |
1da177e4 | 941 | #else |
f4ae17aa | 942 | UASM_i_LA_mostly(p, ptr, pgdc); |
1da177e4 | 943 | #endif |
f4ae17aa J |
944 | uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ |
945 | uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); | |
946 | } | |
e30ec452 TS |
947 | uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */ |
948 | uasm_i_sll(p, tmp, tmp, PGD_T_LOG2); | |
949 | uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ | |
1da177e4 | 950 | } |
722b4544 | 951 | EXPORT_SYMBOL_GPL(build_get_pgde32); |
1da177e4 | 952 | |
875d43e7 | 953 | #endif /* !CONFIG_64BIT */ |
1da177e4 | 954 | |
078a55fc | 955 | static void build_adjust_context(u32 **p, unsigned int ctx) |
1da177e4 | 956 | { |
242954b5 | 957 | unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12; |
1da177e4 LT |
958 | unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1); |
959 | ||
1da177e4 | 960 | if (shift) |
e30ec452 TS |
961 | UASM_i_SRL(p, ctx, ctx, shift); |
962 | uasm_i_andi(p, ctx, ctx, mask); | |
1da177e4 LT |
963 | } |
964 | ||
722b4544 | 965 | void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) |
1da177e4 LT |
966 | { |
967 | /* | |
968 | * Bug workaround for the Nevada. It seems as if under certain | |
969 | * circumstances the move from cp0_context might produce a | |
970 | * bogus result when the mfc0 instruction and its consumer are | |
971 | * in a different cacheline or a load instruction, probably any | |
972 | * memory reference, is between them. | |
973 | */ | |
10cc3529 | 974 | switch (current_cpu_type()) { |
1da177e4 | 975 | case CPU_NEVADA: |
e30ec452 | 976 | UASM_i_LW(p, ptr, 0, ptr); |
1da177e4 LT |
977 | GET_CONTEXT(p, tmp); /* get context reg */ |
978 | break; | |
979 | ||
980 | default: | |
981 | GET_CONTEXT(p, tmp); /* get context reg */ | |
e30ec452 | 982 | UASM_i_LW(p, ptr, 0, ptr); |
1da177e4 LT |
983 | break; |
984 | } | |
985 | ||
986 | build_adjust_context(p, tmp); | |
e30ec452 | 987 | UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */ |
1da177e4 | 988 | } |
722b4544 | 989 | EXPORT_SYMBOL_GPL(build_get_ptep); |
1da177e4 | 990 | |
722b4544 | 991 | void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep) |
1da177e4 | 992 | { |
2caa89b4 PB |
993 | int pte_off_even = 0; |
994 | int pte_off_odd = sizeof(pte_t); | |
7b2cb64f | 995 | |
2caa89b4 PB |
996 | #if defined(CONFIG_CPU_MIPS32) && defined(CONFIG_PHYS_ADDR_T_64BIT) |
997 | /* The low 32 bits of EntryLo is stored in pte_high */ | |
998 | pte_off_even += offsetof(pte_t, pte_high); | |
999 | pte_off_odd += offsetof(pte_t, pte_high); | |
1000 | #endif | |
1001 | ||
97f2645f | 1002 | if (IS_ENABLED(CONFIG_XPA)) { |
c5b36783 | 1003 | uasm_i_lw(p, tmp, pte_off_even, ptep); /* even pte */ |
c5b36783 | 1004 | UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); |
c5b36783 | 1005 | UASM_i_MTC0(p, tmp, C0_ENTRYLO0); |
7b2cb64f | 1006 | |
4b6f99d3 JH |
1007 | if (cpu_has_xpa && !mips_xpa_disabled) { |
1008 | uasm_i_lw(p, tmp, 0, ptep); | |
1009 | uasm_i_ext(p, tmp, tmp, 0, 24); | |
1010 | uasm_i_mthc0(p, tmp, C0_ENTRYLO0); | |
1011 | } | |
f3832196 JH |
1012 | |
1013 | uasm_i_lw(p, tmp, pte_off_odd, ptep); /* odd pte */ | |
1014 | UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); | |
1015 | UASM_i_MTC0(p, tmp, C0_ENTRYLO1); | |
1016 | ||
4b6f99d3 JH |
1017 | if (cpu_has_xpa && !mips_xpa_disabled) { |
1018 | uasm_i_lw(p, tmp, sizeof(pte_t), ptep); | |
1019 | uasm_i_ext(p, tmp, tmp, 0, 24); | |
1020 | uasm_i_mthc0(p, tmp, C0_ENTRYLO1); | |
1021 | } | |
7b2cb64f PB |
1022 | return; |
1023 | } | |
1024 | ||
2caa89b4 PB |
1025 | UASM_i_LW(p, tmp, pte_off_even, ptep); /* get even pte */ |
1026 | UASM_i_LW(p, ptep, pte_off_odd, ptep); /* get odd pte */ | |
1da177e4 LT |
1027 | if (r45k_bvahwbug()) |
1028 | build_tlb_probe_entry(p); | |
974a0b6a PB |
1029 | build_convert_pte_to_entrylo(p, tmp); |
1030 | if (r4k_250MHZhwbug()) | |
1031 | UASM_i_MTC0(p, 0, C0_ENTRYLO0); | |
1032 | UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ | |
1033 | build_convert_pte_to_entrylo(p, ptep); | |
1034 | if (r45k_bvahwbug()) | |
1035 | uasm_i_mfc0(p, tmp, C0_INDEX); | |
1da177e4 | 1036 | if (r4k_250MHZhwbug()) |
9b8c3891 DD |
1037 | UASM_i_MTC0(p, 0, C0_ENTRYLO1); |
1038 | UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ | |
1da177e4 | 1039 | } |
722b4544 | 1040 | EXPORT_SYMBOL_GPL(build_update_entries); |
1da177e4 | 1041 | |
2c8c53e2 DD |
1042 | struct mips_huge_tlb_info { |
1043 | int huge_pte; | |
1044 | int restore_scratch; | |
9e0f162a | 1045 | bool need_reload_pte; |
2c8c53e2 DD |
1046 | }; |
1047 | ||
078a55fc | 1048 | static struct mips_huge_tlb_info |
2c8c53e2 DD |
1049 | build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l, |
1050 | struct uasm_reloc **r, unsigned int tmp, | |
7777b939 | 1051 | unsigned int ptr, int c0_scratch_reg) |
2c8c53e2 DD |
1052 | { |
1053 | struct mips_huge_tlb_info rv; | |
1054 | unsigned int even, odd; | |
1055 | int vmalloc_branch_delay_filled = 0; | |
1056 | const int scratch = 1; /* Our extra working register */ | |
1057 | ||
1058 | rv.huge_pte = scratch; | |
1059 | rv.restore_scratch = 0; | |
9e0f162a | 1060 | rv.need_reload_pte = false; |
2c8c53e2 DD |
1061 | |
1062 | if (check_for_high_segbits) { | |
1063 | UASM_i_MFC0(p, tmp, C0_BADVADDR); | |
1064 | ||
1065 | if (pgd_reg != -1) | |
7777b939 | 1066 | UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); |
2c8c53e2 DD |
1067 | else |
1068 | UASM_i_MFC0(p, ptr, C0_CONTEXT); | |
1069 | ||
7777b939 J |
1070 | if (c0_scratch_reg >= 0) |
1071 | UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg); | |
2c8c53e2 DD |
1072 | else |
1073 | UASM_i_SW(p, scratch, scratchpad_offset(0), 0); | |
1074 | ||
1075 | uasm_i_dsrl_safe(p, scratch, tmp, | |
bb5af4f6 | 1076 | PGDIR_SHIFT + PGD_TABLE_ORDER + PAGE_SHIFT - 3); |
2c8c53e2 DD |
1077 | uasm_il_bnez(p, r, scratch, label_vmalloc); |
1078 | ||
1079 | if (pgd_reg == -1) { | |
1080 | vmalloc_branch_delay_filled = 1; | |
1081 | /* Clear lower 23 bits of context. */ | |
1082 | uasm_i_dins(p, ptr, 0, 0, 23); | |
1083 | } | |
1084 | } else { | |
1085 | if (pgd_reg != -1) | |
7777b939 | 1086 | UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); |
2c8c53e2 DD |
1087 | else |
1088 | UASM_i_MFC0(p, ptr, C0_CONTEXT); | |
1089 | ||
1090 | UASM_i_MFC0(p, tmp, C0_BADVADDR); | |
1091 | ||
7777b939 J |
1092 | if (c0_scratch_reg >= 0) |
1093 | UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg); | |
2c8c53e2 DD |
1094 | else |
1095 | UASM_i_SW(p, scratch, scratchpad_offset(0), 0); | |
1096 | ||
1097 | if (pgd_reg == -1) | |
1098 | /* Clear lower 23 bits of context. */ | |
1099 | uasm_i_dins(p, ptr, 0, 0, 23); | |
1100 | ||
1101 | uasm_il_bltz(p, r, tmp, label_vmalloc); | |
1102 | } | |
1103 | ||
1104 | if (pgd_reg == -1) { | |
1105 | vmalloc_branch_delay_filled = 1; | |
c6972fb9 HP |
1106 | /* insert bit[63:59] of CAC_BASE into bit[11:6] of ptr */ |
1107 | uasm_i_ori(p, ptr, ptr, ((u64)(CAC_BASE) >> 53)); | |
1108 | ||
2c8c53e2 DD |
1109 | uasm_i_drotr(p, ptr, ptr, 11); |
1110 | } | |
1111 | ||
1112 | #ifdef __PAGETABLE_PMD_FOLDED | |
1113 | #define LOC_PTEP scratch | |
1114 | #else | |
1115 | #define LOC_PTEP ptr | |
1116 | #endif | |
1117 | ||
1118 | if (!vmalloc_branch_delay_filled) | |
1119 | /* get pgd offset in bytes */ | |
1120 | uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3); | |
1121 | ||
1122 | uasm_l_vmalloc_done(l, *p); | |
1123 | ||
1124 | /* | |
70342287 RB |
1125 | * tmp ptr |
1126 | * fall-through case = badvaddr *pgd_current | |
1127 | * vmalloc case = badvaddr swapper_pg_dir | |
2c8c53e2 DD |
1128 | */ |
1129 | ||
1130 | if (vmalloc_branch_delay_filled) | |
1131 | /* get pgd offset in bytes */ | |
1132 | uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3); | |
1133 | ||
1134 | #ifdef __PAGETABLE_PMD_FOLDED | |
1135 | GET_CONTEXT(p, tmp); /* get context reg */ | |
1136 | #endif | |
1137 | uasm_i_andi(p, scratch, scratch, (PTRS_PER_PGD - 1) << 3); | |
1138 | ||
1139 | if (use_lwx_insns()) { | |
1140 | UASM_i_LWX(p, LOC_PTEP, scratch, ptr); | |
1141 | } else { | |
1142 | uasm_i_daddu(p, ptr, ptr, scratch); /* add in pgd offset */ | |
1143 | uasm_i_ld(p, LOC_PTEP, 0, ptr); /* get pmd pointer */ | |
1144 | } | |
1145 | ||
3377e227 AB |
1146 | #ifndef __PAGETABLE_PUD_FOLDED |
1147 | /* get pud offset in bytes */ | |
1148 | uasm_i_dsrl_safe(p, scratch, tmp, PUD_SHIFT - 3); | |
1149 | uasm_i_andi(p, scratch, scratch, (PTRS_PER_PUD - 1) << 3); | |
1150 | ||
1151 | if (use_lwx_insns()) { | |
1152 | UASM_i_LWX(p, ptr, scratch, ptr); | |
1153 | } else { | |
1154 | uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */ | |
1155 | UASM_i_LW(p, ptr, 0, ptr); | |
1156 | } | |
1157 | /* ptr contains a pointer to PMD entry */ | |
1158 | /* tmp contains the address */ | |
1159 | #endif | |
1160 | ||
2c8c53e2 DD |
1161 | #ifndef __PAGETABLE_PMD_FOLDED |
1162 | /* get pmd offset in bytes */ | |
1163 | uasm_i_dsrl_safe(p, scratch, tmp, PMD_SHIFT - 3); | |
1164 | uasm_i_andi(p, scratch, scratch, (PTRS_PER_PMD - 1) << 3); | |
1165 | GET_CONTEXT(p, tmp); /* get context reg */ | |
1166 | ||
1167 | if (use_lwx_insns()) { | |
1168 | UASM_i_LWX(p, scratch, scratch, ptr); | |
1169 | } else { | |
1170 | uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */ | |
1171 | UASM_i_LW(p, scratch, 0, ptr); | |
1172 | } | |
1173 | #endif | |
1174 | /* Adjust the context during the load latency. */ | |
1175 | build_adjust_context(p, tmp); | |
1176 | ||
aa1762f4 | 1177 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
2c8c53e2 DD |
1178 | uasm_il_bbit1(p, r, scratch, ilog2(_PAGE_HUGE), label_tlb_huge_update); |
1179 | /* | |
1180 | * The in the LWX case we don't want to do the load in the | |
70342287 | 1181 | * delay slot. It cannot issue in the same cycle and may be |
2c8c53e2 DD |
1182 | * speculative and unneeded. |
1183 | */ | |
1184 | if (use_lwx_insns()) | |
1185 | uasm_i_nop(p); | |
aa1762f4 | 1186 | #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */ |
2c8c53e2 DD |
1187 | |
1188 | ||
1189 | /* build_update_entries */ | |
1190 | if (use_lwx_insns()) { | |
1191 | even = ptr; | |
1192 | odd = tmp; | |
1193 | UASM_i_LWX(p, even, scratch, tmp); | |
1194 | UASM_i_ADDIU(p, tmp, tmp, sizeof(pte_t)); | |
1195 | UASM_i_LWX(p, odd, scratch, tmp); | |
1196 | } else { | |
1197 | UASM_i_ADDU(p, ptr, scratch, tmp); /* add in offset */ | |
1198 | even = tmp; | |
1199 | odd = ptr; | |
1200 | UASM_i_LW(p, even, 0, ptr); /* get even pte */ | |
1201 | UASM_i_LW(p, odd, sizeof(pte_t), ptr); /* get odd pte */ | |
1202 | } | |
05857c64 | 1203 | if (cpu_has_rixi) { |
748e787e | 1204 | uasm_i_drotr(p, even, even, ilog2(_PAGE_GLOBAL)); |
2c8c53e2 | 1205 | UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */ |
748e787e | 1206 | uasm_i_drotr(p, odd, odd, ilog2(_PAGE_GLOBAL)); |
2c8c53e2 DD |
1207 | } else { |
1208 | uasm_i_dsrl_safe(p, even, even, ilog2(_PAGE_GLOBAL)); | |
1209 | UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */ | |
1210 | uasm_i_dsrl_safe(p, odd, odd, ilog2(_PAGE_GLOBAL)); | |
1211 | } | |
1212 | UASM_i_MTC0(p, odd, C0_ENTRYLO1); /* load it */ | |
1213 | ||
7777b939 | 1214 | if (c0_scratch_reg >= 0) { |
0b24cae4 | 1215 | uasm_i_ehb(p); |
7777b939 | 1216 | UASM_i_MFC0(p, scratch, c0_kscratch(), c0_scratch_reg); |
2c8c53e2 DD |
1217 | build_tlb_write_entry(p, l, r, tlb_random); |
1218 | uasm_l_leave(l, *p); | |
1219 | rv.restore_scratch = 1; | |
1220 | } else if (PAGE_SHIFT == 14 || PAGE_SHIFT == 13) { | |
1221 | build_tlb_write_entry(p, l, r, tlb_random); | |
1222 | uasm_l_leave(l, *p); | |
1223 | UASM_i_LW(p, scratch, scratchpad_offset(0), 0); | |
1224 | } else { | |
1225 | UASM_i_LW(p, scratch, scratchpad_offset(0), 0); | |
1226 | build_tlb_write_entry(p, l, r, tlb_random); | |
1227 | uasm_l_leave(l, *p); | |
1228 | rv.restore_scratch = 1; | |
1229 | } | |
1230 | ||
1231 | uasm_i_eret(p); /* return from trap */ | |
1232 | ||
1233 | return rv; | |
1234 | } | |
1235 | ||
e6f72d3a DD |
1236 | /* |
1237 | * For a 64-bit kernel, we are using the 64-bit XTLB refill exception | |
1238 | * because EXL == 0. If we wrap, we can also use the 32 instruction | |
1239 | * slots before the XTLB refill exception handler which belong to the | |
1240 | * unused TLB refill exception. | |
1241 | */ | |
1242 | #define MIPS64_REFILL_INSNS 32 | |
1243 | ||
078a55fc | 1244 | static void build_r4000_tlb_refill_handler(void) |
1da177e4 LT |
1245 | { |
1246 | u32 *p = tlb_handler; | |
e30ec452 TS |
1247 | struct uasm_label *l = labels; |
1248 | struct uasm_reloc *r = relocs; | |
1da177e4 LT |
1249 | u32 *f; |
1250 | unsigned int final_len; | |
4a9040f4 RB |
1251 | struct mips_huge_tlb_info htlb_info __maybe_unused; |
1252 | enum vmalloc64_mode vmalloc_mode __maybe_unused; | |
18280eda | 1253 | |
1da177e4 LT |
1254 | memset(tlb_handler, 0, sizeof(tlb_handler)); |
1255 | memset(labels, 0, sizeof(labels)); | |
1256 | memset(relocs, 0, sizeof(relocs)); | |
1257 | memset(final_handler, 0, sizeof(final_handler)); | |
1258 | ||
18280eda | 1259 | if (IS_ENABLED(CONFIG_64BIT) && (scratch_reg >= 0 || scratchpad_available()) && use_bbit_insns()) { |
8cc461b8 | 1260 | htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, GPR_K0, GPR_K1, |
2c8c53e2 DD |
1261 | scratch_reg); |
1262 | vmalloc_mode = refill_scratch; | |
1263 | } else { | |
8cc461b8 | 1264 | htlb_info.huge_pte = GPR_K0; |
2c8c53e2 | 1265 | htlb_info.restore_scratch = 0; |
9e0f162a | 1266 | htlb_info.need_reload_pte = true; |
2c8c53e2 DD |
1267 | vmalloc_mode = refill_noscratch; |
1268 | /* | |
1269 | * create the plain linear handler | |
1270 | */ | |
1271 | if (bcm1250_m3_war()) { | |
1272 | unsigned int segbits = 44; | |
1273 | ||
8cc461b8 JY |
1274 | uasm_i_dmfc0(&p, GPR_K0, C0_BADVADDR); |
1275 | uasm_i_dmfc0(&p, GPR_K1, C0_ENTRYHI); | |
1276 | uasm_i_xor(&p, GPR_K0, GPR_K0, GPR_K1); | |
1277 | uasm_i_dsrl_safe(&p, GPR_K1, GPR_K0, 62); | |
1278 | uasm_i_dsrl_safe(&p, GPR_K0, GPR_K0, 12 + 1); | |
1279 | uasm_i_dsll_safe(&p, GPR_K0, GPR_K0, 64 + 12 + 1 - segbits); | |
1280 | uasm_i_or(&p, GPR_K0, GPR_K0, GPR_K1); | |
1281 | uasm_il_bnez(&p, &r, GPR_K0, label_leave); | |
2c8c53e2 DD |
1282 | /* No need for uasm_i_nop */ |
1283 | } | |
1da177e4 | 1284 | |
875d43e7 | 1285 | #ifdef CONFIG_64BIT |
8cc461b8 | 1286 | build_get_pmde64(&p, &l, &r, GPR_K0, GPR_K1); /* get pmd in GPR_K1 */ |
1da177e4 | 1287 | #else |
8cc461b8 | 1288 | build_get_pgde32(&p, GPR_K0, GPR_K1); /* get pgd in GPR_K1 */ |
1da177e4 LT |
1289 | #endif |
1290 | ||
aa1762f4 | 1291 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
8cc461b8 | 1292 | build_is_huge_pte(&p, &r, GPR_K0, GPR_K1, label_tlb_huge_update); |
fd062c84 DD |
1293 | #endif |
1294 | ||
8cc461b8 JY |
1295 | build_get_ptep(&p, GPR_K0, GPR_K1); |
1296 | build_update_entries(&p, GPR_K0, GPR_K1); | |
2c8c53e2 DD |
1297 | build_tlb_write_entry(&p, &l, &r, tlb_random); |
1298 | uasm_l_leave(&l, p); | |
1299 | uasm_i_eret(&p); /* return from trap */ | |
1300 | } | |
aa1762f4 | 1301 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 | 1302 | uasm_l_tlb_huge_update(&l, p); |
9e0f162a | 1303 | if (htlb_info.need_reload_pte) |
8cc461b8 JY |
1304 | UASM_i_LW(&p, htlb_info.huge_pte, 0, GPR_K1); |
1305 | build_huge_update_entries(&p, htlb_info.huge_pte, GPR_K1); | |
1306 | build_huge_tlb_write_entry(&p, &l, &r, GPR_K0, tlb_random, | |
2c8c53e2 | 1307 | htlb_info.restore_scratch); |
fd062c84 DD |
1308 | #endif |
1309 | ||
875d43e7 | 1310 | #ifdef CONFIG_64BIT |
8cc461b8 | 1311 | build_get_pgd_vmalloc64(&p, &l, &r, GPR_K0, GPR_K1, vmalloc_mode); |
1da177e4 LT |
1312 | #endif |
1313 | ||
1314 | /* | |
1315 | * Overflow check: For the 64bit handler, we need at least one | |
1316 | * free instruction slot for the wrap-around branch. In worst | |
1317 | * case, if the intended insertion point is a delay slot, we | |
4b3f686d | 1318 | * need three, with the second nop'ed and the third being |
1da177e4 LT |
1319 | * unused. |
1320 | */ | |
14bd8c08 RB |
1321 | switch (boot_cpu_type()) { |
1322 | default: | |
1323 | if (sizeof(long) == 4) { | |
bc431d21 | 1324 | fallthrough; |
268a2d60 | 1325 | case CPU_LOONGSON2EF: |
14bd8c08 RB |
1326 | /* Loongson2 ebase is different than r4k, we have more space */ |
1327 | if ((p - tlb_handler) > 64) | |
1328 | panic("TLB refill handler space exceeded"); | |
95affdda | 1329 | /* |
14bd8c08 | 1330 | * Now fold the handler in the TLB refill handler space. |
95affdda | 1331 | */ |
14bd8c08 RB |
1332 | f = final_handler; |
1333 | /* Simplest case, just copy the handler. */ | |
1334 | uasm_copy_handler(relocs, labels, tlb_handler, p, f); | |
1335 | final_len = p - tlb_handler; | |
1336 | break; | |
1337 | } else { | |
1338 | if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1) | |
1339 | || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3) | |
1340 | && uasm_insn_has_bdelay(relocs, | |
1341 | tlb_handler + MIPS64_REFILL_INSNS - 3))) | |
1342 | panic("TLB refill handler space exceeded"); | |
95affdda | 1343 | /* |
14bd8c08 | 1344 | * Now fold the handler in the TLB refill handler space. |
95affdda | 1345 | */ |
14bd8c08 RB |
1346 | f = final_handler + MIPS64_REFILL_INSNS; |
1347 | if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) { | |
1348 | /* Just copy the handler. */ | |
1349 | uasm_copy_handler(relocs, labels, tlb_handler, p, f); | |
1350 | final_len = p - tlb_handler; | |
1351 | } else { | |
1352 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT | |
1353 | const enum label_id ls = label_tlb_huge_update; | |
1354 | #else | |
1355 | const enum label_id ls = label_vmalloc; | |
1356 | #endif | |
1357 | u32 *split; | |
1358 | int ov = 0; | |
1359 | int i; | |
1360 | ||
1361 | for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++) | |
1362 | ; | |
1363 | BUG_ON(i == ARRAY_SIZE(labels)); | |
1364 | split = labels[i].addr; | |
1365 | ||
1366 | /* | |
1367 | * See if we have overflown one way or the other. | |
1368 | */ | |
1369 | if (split > tlb_handler + MIPS64_REFILL_INSNS || | |
1370 | split < p - MIPS64_REFILL_INSNS) | |
1371 | ov = 1; | |
1372 | ||
1373 | if (ov) { | |
1374 | /* | |
1375 | * Split two instructions before the end. One | |
1376 | * for the branch and one for the instruction | |
1377 | * in the delay slot. | |
1378 | */ | |
1379 | split = tlb_handler + MIPS64_REFILL_INSNS - 2; | |
1380 | ||
1381 | /* | |
1382 | * If the branch would fall in a delay slot, | |
1383 | * we must back up an additional instruction | |
1384 | * so that it is no longer in a delay slot. | |
1385 | */ | |
1386 | if (uasm_insn_has_bdelay(relocs, split - 1)) | |
1387 | split--; | |
1388 | } | |
1389 | /* Copy first part of the handler. */ | |
1390 | uasm_copy_handler(relocs, labels, tlb_handler, split, f); | |
1391 | f += split - tlb_handler; | |
1392 | ||
1393 | if (ov) { | |
1394 | /* Insert branch. */ | |
1395 | uasm_l_split(&l, final_handler); | |
1396 | uasm_il_b(&f, &r, label_split); | |
1397 | if (uasm_insn_has_bdelay(relocs, split)) | |
1398 | uasm_i_nop(&f); | |
1399 | else { | |
1400 | uasm_copy_handler(relocs, labels, | |
1401 | split, split + 1, f); | |
1402 | uasm_move_labels(labels, f, f + 1, -1); | |
1403 | f++; | |
1404 | split++; | |
1405 | } | |
1406 | } | |
1407 | ||
1408 | /* Copy the rest of the handler. */ | |
1409 | uasm_copy_handler(relocs, labels, split, p, final_handler); | |
1410 | final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) + | |
1411 | (p - split); | |
95affdda | 1412 | } |
1da177e4 | 1413 | } |
14bd8c08 | 1414 | break; |
1da177e4 | 1415 | } |
1da177e4 | 1416 | |
e30ec452 TS |
1417 | uasm_resolve_relocs(relocs, labels); |
1418 | pr_debug("Wrote TLB refill handler (%u instructions).\n", | |
1419 | final_len); | |
1da177e4 | 1420 | |
91b05e67 | 1421 | memcpy((void *)ebase, final_handler, 0x100); |
1062080a | 1422 | local_flush_icache_range(ebase, ebase + 0x100); |
4bcb4ad6 | 1423 | dump_handler("r4000_tlb_refill", (u32 *)ebase, (u32 *)(ebase + 0x100)); |
1da177e4 LT |
1424 | } |
1425 | ||
380cd582 HC |
1426 | static void setup_pw(void) |
1427 | { | |
d191aaff | 1428 | unsigned int pwctl; |
380cd582 HC |
1429 | unsigned long pgd_i, pgd_w; |
1430 | #ifndef __PAGETABLE_PMD_FOLDED | |
1431 | unsigned long pmd_i, pmd_w; | |
1432 | #endif | |
1433 | unsigned long pt_i, pt_w; | |
1434 | unsigned long pte_i, pte_w; | |
1435 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT | |
1436 | unsigned long psn; | |
1437 | ||
1438 | psn = ilog2(_PAGE_HUGE); /* bit used to indicate huge page */ | |
1439 | #endif | |
1440 | pgd_i = PGDIR_SHIFT; /* 1st level PGD */ | |
1441 | #ifndef __PAGETABLE_PMD_FOLDED | |
bb5af4f6 | 1442 | pgd_w = PGDIR_SHIFT - PMD_SHIFT + PGD_TABLE_ORDER; |
380cd582 HC |
1443 | |
1444 | pmd_i = PMD_SHIFT; /* 2nd level PMD */ | |
1445 | pmd_w = PMD_SHIFT - PAGE_SHIFT; | |
1446 | #else | |
bb5af4f6 | 1447 | pgd_w = PGDIR_SHIFT - PAGE_SHIFT + PGD_TABLE_ORDER; |
380cd582 HC |
1448 | #endif |
1449 | ||
1450 | pt_i = PAGE_SHIFT; /* 3rd level PTE */ | |
1451 | pt_w = PAGE_SHIFT - 3; | |
1452 | ||
1453 | pte_i = ilog2(_PAGE_GLOBAL); | |
1454 | pte_w = 0; | |
d191aaff | 1455 | pwctl = 1 << 30; /* Set PWDirExt */ |
380cd582 HC |
1456 | |
1457 | #ifndef __PAGETABLE_PMD_FOLDED | |
1458 | write_c0_pwfield(pgd_i << 24 | pmd_i << 12 | pt_i << 6 | pte_i); | |
1459 | write_c0_pwsize(1 << 30 | pgd_w << 24 | pmd_w << 12 | pt_w << 6 | pte_w); | |
1460 | #else | |
1461 | write_c0_pwfield(pgd_i << 24 | pt_i << 6 | pte_i); | |
1462 | write_c0_pwsize(1 << 30 | pgd_w << 24 | pt_w << 6 | pte_w); | |
1463 | #endif | |
1464 | ||
1465 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT | |
d191aaff | 1466 | pwctl |= (1 << 6 | psn); |
380cd582 | 1467 | #endif |
d191aaff | 1468 | write_c0_pwctl(pwctl); |
b023a939 | 1469 | write_c0_kpgd((long)swapper_pg_dir); |
380cd582 HC |
1470 | kscratch_used_mask |= (1 << 7); /* KScratch6 is used for KPGD */ |
1471 | } | |
1472 | ||
1473 | static void build_loongson3_tlb_refill_handler(void) | |
1474 | { | |
1475 | u32 *p = tlb_handler; | |
1476 | struct uasm_label *l = labels; | |
1477 | struct uasm_reloc *r = relocs; | |
1478 | ||
1479 | memset(labels, 0, sizeof(labels)); | |
1480 | memset(relocs, 0, sizeof(relocs)); | |
1481 | memset(tlb_handler, 0, sizeof(tlb_handler)); | |
1482 | ||
1483 | if (check_for_high_segbits) { | |
8cc461b8 JY |
1484 | uasm_i_dmfc0(&p, GPR_K0, C0_BADVADDR); |
1485 | uasm_i_dsrl_safe(&p, GPR_K1, GPR_K0, | |
1486 | PGDIR_SHIFT + PGD_TABLE_ORDER + PAGE_SHIFT - 3); | |
1487 | uasm_il_beqz(&p, &r, GPR_K1, label_vmalloc); | |
380cd582 HC |
1488 | uasm_i_nop(&p); |
1489 | ||
8cc461b8 | 1490 | uasm_il_bgez(&p, &r, GPR_K0, label_large_segbits_fault); |
380cd582 HC |
1491 | uasm_i_nop(&p); |
1492 | uasm_l_vmalloc(&l, p); | |
1493 | } | |
1494 | ||
8cc461b8 | 1495 | uasm_i_dmfc0(&p, GPR_K1, C0_PGD); |
380cd582 | 1496 | |
8cc461b8 | 1497 | uasm_i_lddir(&p, GPR_K0, GPR_K1, 3); /* global page dir */ |
380cd582 | 1498 | #ifndef __PAGETABLE_PMD_FOLDED |
8cc461b8 | 1499 | uasm_i_lddir(&p, GPR_K1, GPR_K0, 1); /* middle page dir */ |
380cd582 | 1500 | #endif |
8cc461b8 JY |
1501 | uasm_i_ldpte(&p, GPR_K1, 0); /* even */ |
1502 | uasm_i_ldpte(&p, GPR_K1, 1); /* odd */ | |
380cd582 HC |
1503 | uasm_i_tlbwr(&p); |
1504 | ||
1505 | /* restore page mask */ | |
1506 | if (PM_DEFAULT_MASK >> 16) { | |
8cc461b8 JY |
1507 | uasm_i_lui(&p, GPR_K0, PM_DEFAULT_MASK >> 16); |
1508 | uasm_i_ori(&p, GPR_K0, GPR_K0, PM_DEFAULT_MASK & 0xffff); | |
1509 | uasm_i_mtc0(&p, GPR_K0, C0_PAGEMASK); | |
380cd582 | 1510 | } else if (PM_DEFAULT_MASK) { |
8cc461b8 JY |
1511 | uasm_i_ori(&p, GPR_K0, 0, PM_DEFAULT_MASK); |
1512 | uasm_i_mtc0(&p, GPR_K0, C0_PAGEMASK); | |
380cd582 HC |
1513 | } else { |
1514 | uasm_i_mtc0(&p, 0, C0_PAGEMASK); | |
1515 | } | |
1516 | ||
1517 | uasm_i_eret(&p); | |
1518 | ||
1519 | if (check_for_high_segbits) { | |
1520 | uasm_l_large_segbits_fault(&l, p); | |
8cc461b8 JY |
1521 | UASM_i_LA(&p, GPR_K1, (unsigned long)tlb_do_page_fault_0); |
1522 | uasm_i_jr(&p, GPR_K1); | |
380cd582 HC |
1523 | uasm_i_nop(&p); |
1524 | } | |
1525 | ||
1526 | uasm_resolve_relocs(relocs, labels); | |
1527 | memcpy((void *)(ebase + 0x80), tlb_handler, 0x80); | |
1528 | local_flush_icache_range(ebase + 0x80, ebase + 0x100); | |
4bcb4ad6 PB |
1529 | dump_handler("loongson3_tlb_refill", |
1530 | (u32 *)(ebase + 0x80), (u32 *)(ebase + 0x100)); | |
380cd582 HC |
1531 | } |
1532 | ||
f4ae17aa | 1533 | static void build_setup_pgd(void) |
3d8bfdd0 DD |
1534 | { |
1535 | const int a0 = 4; | |
f4ae17aa J |
1536 | const int __maybe_unused a1 = 5; |
1537 | const int __maybe_unused a2 = 6; | |
4bcb4ad6 | 1538 | u32 *p = (u32 *)msk_isa16_mode((ulong)tlbmiss_handler_setup_pgd); |
f4ae17aa J |
1539 | #ifndef CONFIG_MIPS_PGD_C0_CONTEXT |
1540 | long pgdc = (long)pgd_current; | |
1541 | #endif | |
3d8bfdd0 | 1542 | |
4bcb4ad6 | 1543 | memset(p, 0, tlbmiss_handler_setup_pgd_end - (char *)p); |
3d8bfdd0 DD |
1544 | memset(labels, 0, sizeof(labels)); |
1545 | memset(relocs, 0, sizeof(relocs)); | |
3d8bfdd0 | 1546 | pgd_reg = allocate_kscratch(); |
f4ae17aa | 1547 | #ifdef CONFIG_MIPS_PGD_C0_CONTEXT |
3d8bfdd0 | 1548 | if (pgd_reg == -1) { |
f4ae17aa J |
1549 | struct uasm_label *l = labels; |
1550 | struct uasm_reloc *r = relocs; | |
1551 | ||
3d8bfdd0 DD |
1552 | /* PGD << 11 in c0_Context */ |
1553 | /* | |
1554 | * If it is a ckseg0 address, convert to a physical | |
1555 | * address. Shifting right by 29 and adding 4 will | |
1556 | * result in zero for these addresses. | |
1557 | * | |
1558 | */ | |
1559 | UASM_i_SRA(&p, a1, a0, 29); | |
1560 | UASM_i_ADDIU(&p, a1, a1, 4); | |
1561 | uasm_il_bnez(&p, &r, a1, label_tlbl_goaround1); | |
1562 | uasm_i_nop(&p); | |
1563 | uasm_i_dinsm(&p, a0, 0, 29, 64 - 29); | |
1564 | uasm_l_tlbl_goaround1(&l, p); | |
1565 | UASM_i_SLL(&p, a0, a0, 11); | |
3d8bfdd0 | 1566 | UASM_i_MTC0(&p, a0, C0_CONTEXT); |
0b24cae4 DK |
1567 | uasm_i_jr(&p, 31); |
1568 | uasm_i_ehb(&p); | |
3d8bfdd0 DD |
1569 | } else { |
1570 | /* PGD in c0_KScratch */ | |
380cd582 HC |
1571 | if (cpu_has_ldpte) |
1572 | UASM_i_MTC0(&p, a0, C0_PWBASE); | |
1573 | else | |
1574 | UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg); | |
0b24cae4 DK |
1575 | uasm_i_jr(&p, 31); |
1576 | uasm_i_ehb(&p); | |
3d8bfdd0 | 1577 | } |
f4ae17aa J |
1578 | #else |
1579 | #ifdef CONFIG_SMP | |
1580 | /* Save PGD to pgd_current[smp_processor_id()] */ | |
1581 | UASM_i_CPUID_MFC0(&p, a1, SMP_CPUID_REG); | |
1582 | UASM_i_SRL_SAFE(&p, a1, a1, SMP_CPUID_PTRSHIFT); | |
1583 | UASM_i_LA_mostly(&p, a2, pgdc); | |
1584 | UASM_i_ADDU(&p, a2, a2, a1); | |
1585 | UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2); | |
1586 | #else | |
1587 | UASM_i_LA_mostly(&p, a2, pgdc); | |
1588 | UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2); | |
1589 | #endif /* SMP */ | |
f4ae17aa J |
1590 | |
1591 | /* if pgd_reg is allocated, save PGD also to scratch register */ | |
0b24cae4 | 1592 | if (pgd_reg != -1) { |
f4ae17aa | 1593 | UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg); |
0b24cae4 DK |
1594 | uasm_i_jr(&p, 31); |
1595 | uasm_i_ehb(&p); | |
1596 | } else { | |
1597 | uasm_i_jr(&p, 31); | |
f4ae17aa | 1598 | uasm_i_nop(&p); |
0b24cae4 | 1599 | } |
f4ae17aa | 1600 | #endif |
4bcb4ad6 | 1601 | if (p >= (u32 *)tlbmiss_handler_setup_pgd_end) |
6ba045f9 J |
1602 | panic("tlbmiss_handler_setup_pgd space exceeded"); |
1603 | ||
3d8bfdd0 | 1604 | uasm_resolve_relocs(relocs, labels); |
6ba045f9 | 1605 | pr_debug("Wrote tlbmiss_handler_setup_pgd (%u instructions).\n", |
4bcb4ad6 | 1606 | (unsigned int)(p - (u32 *)tlbmiss_handler_setup_pgd)); |
3d8bfdd0 | 1607 | |
6ba045f9 | 1608 | dump_handler("tlbmiss_handler", tlbmiss_handler_setup_pgd, |
4bcb4ad6 | 1609 | tlbmiss_handler_setup_pgd_end); |
3d8bfdd0 | 1610 | } |
1da177e4 | 1611 | |
078a55fc | 1612 | static void |
bd1437e4 | 1613 | iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr) |
1da177e4 LT |
1614 | { |
1615 | #ifdef CONFIG_SMP | |
e02e07e3 HC |
1616 | if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS)) |
1617 | uasm_i_sync(p, 0); | |
34adb28d | 1618 | # ifdef CONFIG_PHYS_ADDR_T_64BIT |
1da177e4 | 1619 | if (cpu_has_64bits) |
e30ec452 | 1620 | uasm_i_lld(p, pte, 0, ptr); |
1da177e4 LT |
1621 | else |
1622 | # endif | |
e30ec452 | 1623 | UASM_i_LL(p, pte, 0, ptr); |
1da177e4 | 1624 | #else |
34adb28d | 1625 | # ifdef CONFIG_PHYS_ADDR_T_64BIT |
1da177e4 | 1626 | if (cpu_has_64bits) |
e30ec452 | 1627 | uasm_i_ld(p, pte, 0, ptr); |
1da177e4 LT |
1628 | else |
1629 | # endif | |
e30ec452 | 1630 | UASM_i_LW(p, pte, 0, ptr); |
1da177e4 LT |
1631 | #endif |
1632 | } | |
1633 | ||
078a55fc | 1634 | static void |
e30ec452 | 1635 | iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr, |
bbeeffec | 1636 | unsigned int mode, unsigned int scratch) |
1da177e4 | 1637 | { |
63b2d2f4 | 1638 | unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY); |
b4ebbb87 | 1639 | unsigned int swmode = mode & ~hwmode; |
63b2d2f4 | 1640 | |
97f2645f | 1641 | if (IS_ENABLED(CONFIG_XPA) && !cpu_has_64bits) { |
b4ebbb87 | 1642 | uasm_i_lui(p, scratch, swmode >> 16); |
c5b36783 | 1643 | uasm_i_or(p, pte, pte, scratch); |
b4ebbb87 PB |
1644 | BUG_ON(swmode & 0xffff); |
1645 | } else { | |
1646 | uasm_i_ori(p, pte, pte, mode); | |
1647 | } | |
1648 | ||
1da177e4 | 1649 | #ifdef CONFIG_SMP |
34adb28d | 1650 | # ifdef CONFIG_PHYS_ADDR_T_64BIT |
1da177e4 | 1651 | if (cpu_has_64bits) |
e30ec452 | 1652 | uasm_i_scd(p, pte, 0, ptr); |
1da177e4 LT |
1653 | else |
1654 | # endif | |
e30ec452 | 1655 | UASM_i_SC(p, pte, 0, ptr); |
1da177e4 LT |
1656 | |
1657 | if (r10000_llsc_war()) | |
e30ec452 | 1658 | uasm_il_beqzl(p, r, pte, label_smp_pgtable_change); |
1da177e4 | 1659 | else |
e30ec452 | 1660 | uasm_il_beqz(p, r, pte, label_smp_pgtable_change); |
1da177e4 | 1661 | |
34adb28d | 1662 | # ifdef CONFIG_PHYS_ADDR_T_64BIT |
1da177e4 | 1663 | if (!cpu_has_64bits) { |
e30ec452 TS |
1664 | /* no uasm_i_nop needed */ |
1665 | uasm_i_ll(p, pte, sizeof(pte_t) / 2, ptr); | |
1666 | uasm_i_ori(p, pte, pte, hwmode); | |
b4ebbb87 | 1667 | BUG_ON(hwmode & ~0xffff); |
e30ec452 TS |
1668 | uasm_i_sc(p, pte, sizeof(pte_t) / 2, ptr); |
1669 | uasm_il_beqz(p, r, pte, label_smp_pgtable_change); | |
1670 | /* no uasm_i_nop needed */ | |
1671 | uasm_i_lw(p, pte, 0, ptr); | |
1da177e4 | 1672 | } else |
e30ec452 | 1673 | uasm_i_nop(p); |
1da177e4 | 1674 | # else |
e30ec452 | 1675 | uasm_i_nop(p); |
1da177e4 LT |
1676 | # endif |
1677 | #else | |
34adb28d | 1678 | # ifdef CONFIG_PHYS_ADDR_T_64BIT |
1da177e4 | 1679 | if (cpu_has_64bits) |
e30ec452 | 1680 | uasm_i_sd(p, pte, 0, ptr); |
1da177e4 LT |
1681 | else |
1682 | # endif | |
e30ec452 | 1683 | UASM_i_SW(p, pte, 0, ptr); |
1da177e4 | 1684 | |
34adb28d | 1685 | # ifdef CONFIG_PHYS_ADDR_T_64BIT |
1da177e4 | 1686 | if (!cpu_has_64bits) { |
e30ec452 TS |
1687 | uasm_i_lw(p, pte, sizeof(pte_t) / 2, ptr); |
1688 | uasm_i_ori(p, pte, pte, hwmode); | |
b4ebbb87 | 1689 | BUG_ON(hwmode & ~0xffff); |
e30ec452 TS |
1690 | uasm_i_sw(p, pte, sizeof(pte_t) / 2, ptr); |
1691 | uasm_i_lw(p, pte, 0, ptr); | |
1da177e4 LT |
1692 | } |
1693 | # endif | |
1694 | #endif | |
1695 | } | |
1696 | ||
1697 | /* | |
1698 | * Check if PTE is present, if not then jump to LABEL. PTR points to | |
1699 | * the page table where this PTE is located, PTE will be re-loaded | |
2f9060b1 | 1700 | * with its original value. |
1da177e4 | 1701 | */ |
078a55fc | 1702 | static void |
bd1437e4 | 1703 | build_pte_present(u32 **p, struct uasm_reloc **r, |
bf28607f | 1704 | int pte, int ptr, int scratch, enum label_id lid) |
1da177e4 | 1705 | { |
bf28607f | 1706 | int t = scratch >= 0 ? scratch : pte; |
8fe4908b | 1707 | int cur = pte; |
bf28607f | 1708 | |
05857c64 | 1709 | if (cpu_has_rixi) { |
cc33ae43 DD |
1710 | if (use_bbit_insns()) { |
1711 | uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid); | |
1712 | uasm_i_nop(p); | |
1713 | } else { | |
8fe4908b JH |
1714 | if (_PAGE_PRESENT_SHIFT) { |
1715 | uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT); | |
1716 | cur = t; | |
1717 | } | |
1718 | uasm_i_andi(p, t, cur, 1); | |
bf28607f DD |
1719 | uasm_il_beqz(p, r, t, lid); |
1720 | if (pte == t) | |
1721 | /* You lose the SMP race :-(*/ | |
1722 | iPTE_LW(p, pte, ptr); | |
cc33ae43 | 1723 | } |
6dd9344c | 1724 | } else { |
8fe4908b JH |
1725 | if (_PAGE_PRESENT_SHIFT) { |
1726 | uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT); | |
1727 | cur = t; | |
1728 | } | |
1729 | uasm_i_andi(p, t, cur, | |
780602d7 PB |
1730 | (_PAGE_PRESENT | _PAGE_NO_READ) >> _PAGE_PRESENT_SHIFT); |
1731 | uasm_i_xori(p, t, t, _PAGE_PRESENT >> _PAGE_PRESENT_SHIFT); | |
bf28607f DD |
1732 | uasm_il_bnez(p, r, t, lid); |
1733 | if (pte == t) | |
1734 | /* You lose the SMP race :-(*/ | |
1735 | iPTE_LW(p, pte, ptr); | |
6dd9344c | 1736 | } |
1da177e4 LT |
1737 | } |
1738 | ||
1739 | /* Make PTE valid, store result in PTR. */ | |
078a55fc | 1740 | static void |
e30ec452 | 1741 | build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte, |
bbeeffec | 1742 | unsigned int ptr, unsigned int scratch) |
1da177e4 | 1743 | { |
63b2d2f4 TS |
1744 | unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED; |
1745 | ||
bbeeffec | 1746 | iPTE_SW(p, r, pte, ptr, mode, scratch); |
1da177e4 LT |
1747 | } |
1748 | ||
1749 | /* | |
1750 | * Check if PTE can be written to, if not branch to LABEL. Regardless | |
1751 | * restore PTE with value from PTR when done. | |
1752 | */ | |
078a55fc | 1753 | static void |
bd1437e4 | 1754 | build_pte_writable(u32 **p, struct uasm_reloc **r, |
bf28607f DD |
1755 | unsigned int pte, unsigned int ptr, int scratch, |
1756 | enum label_id lid) | |
1da177e4 | 1757 | { |
bf28607f | 1758 | int t = scratch >= 0 ? scratch : pte; |
8fe4908b | 1759 | int cur = pte; |
bf28607f | 1760 | |
8fe4908b JH |
1761 | if (_PAGE_PRESENT_SHIFT) { |
1762 | uasm_i_srl(p, t, cur, _PAGE_PRESENT_SHIFT); | |
1763 | cur = t; | |
1764 | } | |
1765 | uasm_i_andi(p, t, cur, | |
a3ae565a JH |
1766 | (_PAGE_PRESENT | _PAGE_WRITE) >> _PAGE_PRESENT_SHIFT); |
1767 | uasm_i_xori(p, t, t, | |
1768 | (_PAGE_PRESENT | _PAGE_WRITE) >> _PAGE_PRESENT_SHIFT); | |
bf28607f DD |
1769 | uasm_il_bnez(p, r, t, lid); |
1770 | if (pte == t) | |
1771 | /* You lose the SMP race :-(*/ | |
cc33ae43 | 1772 | iPTE_LW(p, pte, ptr); |
bf28607f DD |
1773 | else |
1774 | uasm_i_nop(p); | |
1da177e4 LT |
1775 | } |
1776 | ||
1777 | /* Make PTE writable, update software status bits as well, then store | |
1778 | * at PTR. | |
1779 | */ | |
078a55fc | 1780 | static void |
e30ec452 | 1781 | build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte, |
bbeeffec | 1782 | unsigned int ptr, unsigned int scratch) |
1da177e4 | 1783 | { |
63b2d2f4 TS |
1784 | unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID |
1785 | | _PAGE_DIRTY); | |
1786 | ||
bbeeffec | 1787 | iPTE_SW(p, r, pte, ptr, mode, scratch); |
1da177e4 LT |
1788 | } |
1789 | ||
1790 | /* | |
1791 | * Check if PTE can be modified, if not branch to LABEL. Regardless | |
1792 | * restore PTE with value from PTR when done. | |
1793 | */ | |
078a55fc | 1794 | static void |
bd1437e4 | 1795 | build_pte_modifiable(u32 **p, struct uasm_reloc **r, |
bf28607f DD |
1796 | unsigned int pte, unsigned int ptr, int scratch, |
1797 | enum label_id lid) | |
1da177e4 | 1798 | { |
cc33ae43 DD |
1799 | if (use_bbit_insns()) { |
1800 | uasm_il_bbit0(p, r, pte, ilog2(_PAGE_WRITE), lid); | |
1801 | uasm_i_nop(p); | |
1802 | } else { | |
bf28607f | 1803 | int t = scratch >= 0 ? scratch : pte; |
c5b36783 SH |
1804 | uasm_i_srl(p, t, pte, _PAGE_WRITE_SHIFT); |
1805 | uasm_i_andi(p, t, t, 1); | |
bf28607f DD |
1806 | uasm_il_beqz(p, r, t, lid); |
1807 | if (pte == t) | |
1808 | /* You lose the SMP race :-(*/ | |
1809 | iPTE_LW(p, pte, ptr); | |
cc33ae43 | 1810 | } |
1da177e4 LT |
1811 | } |
1812 | ||
82622284 | 1813 | #ifndef CONFIG_MIPS_PGD_C0_CONTEXT |
3d8bfdd0 DD |
1814 | |
1815 | ||
1da177e4 LT |
1816 | /* |
1817 | * R3000 style TLB load/store/modify handlers. | |
1818 | */ | |
1819 | ||
fded2e50 MR |
1820 | /* |
1821 | * This places the pte into ENTRYLO0 and writes it with tlbwi. | |
1822 | * Then it returns. | |
1823 | */ | |
078a55fc | 1824 | static void |
fded2e50 | 1825 | build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp) |
1da177e4 | 1826 | { |
e30ec452 TS |
1827 | uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ |
1828 | uasm_i_mfc0(p, tmp, C0_EPC); /* cp0 delay */ | |
1829 | uasm_i_tlbwi(p); | |
1830 | uasm_i_jr(p, tmp); | |
1831 | uasm_i_rfe(p); /* branch delay */ | |
1da177e4 LT |
1832 | } |
1833 | ||
1834 | /* | |
fded2e50 MR |
1835 | * This places the pte into ENTRYLO0 and writes it with tlbwi |
1836 | * or tlbwr as appropriate. This is because the index register | |
1837 | * may have the probe fail bit set as a result of a trap on a | |
1838 | * kseg2 access, i.e. without refill. Then it returns. | |
1da177e4 | 1839 | */ |
078a55fc | 1840 | static void |
e30ec452 TS |
1841 | build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l, |
1842 | struct uasm_reloc **r, unsigned int pte, | |
1843 | unsigned int tmp) | |
1844 | { | |
1845 | uasm_i_mfc0(p, tmp, C0_INDEX); | |
1846 | uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ | |
1847 | uasm_il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */ | |
1848 | uasm_i_mfc0(p, tmp, C0_EPC); /* branch delay */ | |
1849 | uasm_i_tlbwi(p); /* cp0 delay */ | |
1850 | uasm_i_jr(p, tmp); | |
1851 | uasm_i_rfe(p); /* branch delay */ | |
1852 | uasm_l_r3000_write_probe_fail(l, *p); | |
1853 | uasm_i_tlbwr(p); /* cp0 delay */ | |
1854 | uasm_i_jr(p, tmp); | |
1855 | uasm_i_rfe(p); /* branch delay */ | |
1da177e4 LT |
1856 | } |
1857 | ||
078a55fc | 1858 | static void |
1da177e4 LT |
1859 | build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte, |
1860 | unsigned int ptr) | |
1861 | { | |
1862 | long pgdc = (long)pgd_current; | |
1863 | ||
e30ec452 TS |
1864 | uasm_i_mfc0(p, pte, C0_BADVADDR); |
1865 | uasm_i_lui(p, ptr, uasm_rel_hi(pgdc)); /* cp0 delay */ | |
1866 | uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); | |
1867 | uasm_i_srl(p, pte, pte, 22); /* load delay */ | |
1868 | uasm_i_sll(p, pte, pte, 2); | |
1869 | uasm_i_addu(p, ptr, ptr, pte); | |
1870 | uasm_i_mfc0(p, pte, C0_CONTEXT); | |
1871 | uasm_i_lw(p, ptr, 0, ptr); /* cp0 delay */ | |
1872 | uasm_i_andi(p, pte, pte, 0xffc); /* load delay */ | |
1873 | uasm_i_addu(p, ptr, ptr, pte); | |
1874 | uasm_i_lw(p, pte, 0, ptr); | |
1875 | uasm_i_tlbp(p); /* load delay */ | |
1da177e4 LT |
1876 | } |
1877 | ||
078a55fc | 1878 | static void build_r3000_tlb_load_handler(void) |
1da177e4 | 1879 | { |
4bcb4ad6 | 1880 | u32 *p = (u32 *)handle_tlbl; |
e30ec452 TS |
1881 | struct uasm_label *l = labels; |
1882 | struct uasm_reloc *r = relocs; | |
1da177e4 | 1883 | |
4bcb4ad6 | 1884 | memset(p, 0, handle_tlbl_end - (char *)p); |
1da177e4 LT |
1885 | memset(labels, 0, sizeof(labels)); |
1886 | memset(relocs, 0, sizeof(relocs)); | |
1887 | ||
8cc461b8 JY |
1888 | build_r3000_tlbchange_handler_head(&p, GPR_K0, GPR_K1); |
1889 | build_pte_present(&p, &r, GPR_K0, GPR_K1, -1, label_nopage_tlbl); | |
e30ec452 | 1890 | uasm_i_nop(&p); /* load delay */ |
8cc461b8 JY |
1891 | build_make_valid(&p, &r, GPR_K0, GPR_K1, -1); |
1892 | build_r3000_tlb_reload_write(&p, &l, &r, GPR_K0, GPR_K1); | |
1da177e4 | 1893 | |
e30ec452 TS |
1894 | uasm_l_nopage_tlbl(&l, p); |
1895 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); | |
1896 | uasm_i_nop(&p); | |
1da177e4 | 1897 | |
4bcb4ad6 | 1898 | if (p >= (u32 *)handle_tlbl_end) |
1da177e4 LT |
1899 | panic("TLB load handler fastpath space exceeded"); |
1900 | ||
e30ec452 TS |
1901 | uasm_resolve_relocs(relocs, labels); |
1902 | pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", | |
4bcb4ad6 | 1903 | (unsigned int)(p - (u32 *)handle_tlbl)); |
1da177e4 | 1904 | |
4bcb4ad6 | 1905 | dump_handler("r3000_tlb_load", handle_tlbl, handle_tlbl_end); |
1da177e4 LT |
1906 | } |
1907 | ||
078a55fc | 1908 | static void build_r3000_tlb_store_handler(void) |
1da177e4 | 1909 | { |
4bcb4ad6 | 1910 | u32 *p = (u32 *)handle_tlbs; |
e30ec452 TS |
1911 | struct uasm_label *l = labels; |
1912 | struct uasm_reloc *r = relocs; | |
1da177e4 | 1913 | |
4bcb4ad6 | 1914 | memset(p, 0, handle_tlbs_end - (char *)p); |
1da177e4 LT |
1915 | memset(labels, 0, sizeof(labels)); |
1916 | memset(relocs, 0, sizeof(relocs)); | |
1917 | ||
8cc461b8 JY |
1918 | build_r3000_tlbchange_handler_head(&p, GPR_K0, GPR_K1); |
1919 | build_pte_writable(&p, &r, GPR_K0, GPR_K1, -1, label_nopage_tlbs); | |
e30ec452 | 1920 | uasm_i_nop(&p); /* load delay */ |
8cc461b8 JY |
1921 | build_make_write(&p, &r, GPR_K0, GPR_K1, -1); |
1922 | build_r3000_tlb_reload_write(&p, &l, &r, GPR_K0, GPR_K1); | |
1da177e4 | 1923 | |
e30ec452 TS |
1924 | uasm_l_nopage_tlbs(&l, p); |
1925 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); | |
1926 | uasm_i_nop(&p); | |
1da177e4 | 1927 | |
4bcb4ad6 | 1928 | if (p >= (u32 *)handle_tlbs_end) |
1da177e4 LT |
1929 | panic("TLB store handler fastpath space exceeded"); |
1930 | ||
e30ec452 TS |
1931 | uasm_resolve_relocs(relocs, labels); |
1932 | pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", | |
4bcb4ad6 | 1933 | (unsigned int)(p - (u32 *)handle_tlbs)); |
1da177e4 | 1934 | |
4bcb4ad6 | 1935 | dump_handler("r3000_tlb_store", handle_tlbs, handle_tlbs_end); |
1da177e4 LT |
1936 | } |
1937 | ||
078a55fc | 1938 | static void build_r3000_tlb_modify_handler(void) |
1da177e4 | 1939 | { |
4bcb4ad6 | 1940 | u32 *p = (u32 *)handle_tlbm; |
e30ec452 TS |
1941 | struct uasm_label *l = labels; |
1942 | struct uasm_reloc *r = relocs; | |
1da177e4 | 1943 | |
4bcb4ad6 | 1944 | memset(p, 0, handle_tlbm_end - (char *)p); |
1da177e4 LT |
1945 | memset(labels, 0, sizeof(labels)); |
1946 | memset(relocs, 0, sizeof(relocs)); | |
1947 | ||
8cc461b8 JY |
1948 | build_r3000_tlbchange_handler_head(&p, GPR_K0, GPR_K1); |
1949 | build_pte_modifiable(&p, &r, GPR_K0, GPR_K1, -1, label_nopage_tlbm); | |
e30ec452 | 1950 | uasm_i_nop(&p); /* load delay */ |
8cc461b8 JY |
1951 | build_make_write(&p, &r, GPR_K0, GPR_K1, -1); |
1952 | build_r3000_pte_reload_tlbwi(&p, GPR_K0, GPR_K1); | |
1da177e4 | 1953 | |
e30ec452 TS |
1954 | uasm_l_nopage_tlbm(&l, p); |
1955 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); | |
1956 | uasm_i_nop(&p); | |
1da177e4 | 1957 | |
4bcb4ad6 | 1958 | if (p >= (u32 *)handle_tlbm_end) |
1da177e4 LT |
1959 | panic("TLB modify handler fastpath space exceeded"); |
1960 | ||
e30ec452 TS |
1961 | uasm_resolve_relocs(relocs, labels); |
1962 | pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", | |
4bcb4ad6 | 1963 | (unsigned int)(p - (u32 *)handle_tlbm)); |
1da177e4 | 1964 | |
4bcb4ad6 | 1965 | dump_handler("r3000_tlb_modify", handle_tlbm, handle_tlbm_end); |
1da177e4 | 1966 | } |
82622284 | 1967 | #endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ |
1da177e4 | 1968 | |
f39878cc PB |
1969 | static bool cpu_has_tlbex_tlbp_race(void) |
1970 | { | |
1971 | /* | |
1972 | * When a Hardware Table Walker is running it can replace TLB entries | |
1973 | * at any time, leading to a race between it & the CPU. | |
1974 | */ | |
1975 | if (cpu_has_htw) | |
1976 | return true; | |
1977 | ||
1978 | /* | |
1979 | * If the CPU shares FTLB RAM with its siblings then our entry may be | |
1980 | * replaced at any time by a sibling performing a write to the FTLB. | |
1981 | */ | |
1982 | if (cpu_has_shared_ftlb_ram) | |
1983 | return true; | |
1984 | ||
1985 | /* In all other cases there ought to be no race condition to handle */ | |
1986 | return false; | |
1987 | } | |
1988 | ||
1da177e4 LT |
1989 | /* |
1990 | * R4000 style TLB load/store/modify handlers. | |
1991 | */ | |
078a55fc | 1992 | static struct work_registers |
e30ec452 | 1993 | build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l, |
bf28607f | 1994 | struct uasm_reloc **r) |
1da177e4 | 1995 | { |
bf28607f DD |
1996 | struct work_registers wr = build_get_work_registers(p); |
1997 | ||
875d43e7 | 1998 | #ifdef CONFIG_64BIT |
bf28607f | 1999 | build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */ |
1da177e4 | 2000 | #else |
bf28607f | 2001 | build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */ |
1da177e4 LT |
2002 | #endif |
2003 | ||
aa1762f4 | 2004 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 DD |
2005 | /* |
2006 | * For huge tlb entries, pmd doesn't contain an address but | |
2007 | * instead contains the tlb pte. Check the PAGE_HUGE bit and | |
2008 | * see if we need to jump to huge tlb processing. | |
2009 | */ | |
bf28607f | 2010 | build_is_huge_pte(p, r, wr.r1, wr.r2, label_tlb_huge_update); |
fd062c84 DD |
2011 | #endif |
2012 | ||
bf28607f DD |
2013 | UASM_i_MFC0(p, wr.r1, C0_BADVADDR); |
2014 | UASM_i_LW(p, wr.r2, 0, wr.r2); | |
6963c72d | 2015 | UASM_i_SRL(p, wr.r1, wr.r1, PAGE_SHIFT - PTE_T_LOG2); |
bf28607f DD |
2016 | uasm_i_andi(p, wr.r1, wr.r1, (PTRS_PER_PTE - 1) << PTE_T_LOG2); |
2017 | UASM_i_ADDU(p, wr.r2, wr.r2, wr.r1); | |
1da177e4 LT |
2018 | |
2019 | #ifdef CONFIG_SMP | |
e30ec452 TS |
2020 | uasm_l_smp_pgtable_change(l, *p); |
2021 | #endif | |
bf28607f | 2022 | iPTE_LW(p, wr.r1, wr.r2); /* get even pte */ |
070e76cb | 2023 | if (!m4kc_tlbp_war()) { |
8df5beac | 2024 | build_tlb_probe_entry(p); |
f39878cc | 2025 | if (cpu_has_tlbex_tlbp_race()) { |
070e76cb LY |
2026 | /* race condition happens, leaving */ |
2027 | uasm_i_ehb(p); | |
2028 | uasm_i_mfc0(p, wr.r3, C0_INDEX); | |
2029 | uasm_il_bltz(p, r, wr.r3, label_leave); | |
2030 | uasm_i_nop(p); | |
2031 | } | |
2032 | } | |
bf28607f | 2033 | return wr; |
1da177e4 LT |
2034 | } |
2035 | ||
078a55fc | 2036 | static void |
e30ec452 TS |
2037 | build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l, |
2038 | struct uasm_reloc **r, unsigned int tmp, | |
1da177e4 LT |
2039 | unsigned int ptr) |
2040 | { | |
e30ec452 TS |
2041 | uasm_i_ori(p, ptr, ptr, sizeof(pte_t)); |
2042 | uasm_i_xori(p, ptr, ptr, sizeof(pte_t)); | |
1da177e4 LT |
2043 | build_update_entries(p, tmp, ptr); |
2044 | build_tlb_write_entry(p, l, r, tlb_indexed); | |
e30ec452 | 2045 | uasm_l_leave(l, *p); |
bf28607f | 2046 | build_restore_work_registers(p); |
e30ec452 | 2047 | uasm_i_eret(p); /* return from trap */ |
1da177e4 | 2048 | |
875d43e7 | 2049 | #ifdef CONFIG_64BIT |
1ec56329 | 2050 | build_get_pgd_vmalloc64(p, l, r, tmp, ptr, not_refill); |
1da177e4 LT |
2051 | #endif |
2052 | } | |
2053 | ||
078a55fc | 2054 | static void build_r4000_tlb_load_handler(void) |
1da177e4 | 2055 | { |
2c0e57ea | 2056 | u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbl); |
e30ec452 TS |
2057 | struct uasm_label *l = labels; |
2058 | struct uasm_reloc *r = relocs; | |
bf28607f | 2059 | struct work_registers wr; |
1da177e4 | 2060 | |
4bcb4ad6 | 2061 | memset(p, 0, handle_tlbl_end - (char *)p); |
1da177e4 LT |
2062 | memset(labels, 0, sizeof(labels)); |
2063 | memset(relocs, 0, sizeof(relocs)); | |
2064 | ||
2065 | if (bcm1250_m3_war()) { | |
3d45285d RB |
2066 | unsigned int segbits = 44; |
2067 | ||
8cc461b8 JY |
2068 | uasm_i_dmfc0(&p, GPR_K0, C0_BADVADDR); |
2069 | uasm_i_dmfc0(&p, GPR_K1, C0_ENTRYHI); | |
2070 | uasm_i_xor(&p, GPR_K0, GPR_K0, GPR_K1); | |
2071 | uasm_i_dsrl_safe(&p, GPR_K1, GPR_K0, 62); | |
2072 | uasm_i_dsrl_safe(&p, GPR_K0, GPR_K0, 12 + 1); | |
2073 | uasm_i_dsll_safe(&p, GPR_K0, GPR_K0, 64 + 12 + 1 - segbits); | |
2074 | uasm_i_or(&p, GPR_K0, GPR_K0, GPR_K1); | |
2075 | uasm_il_bnez(&p, &r, GPR_K0, label_leave); | |
e30ec452 | 2076 | /* No need for uasm_i_nop */ |
1da177e4 LT |
2077 | } |
2078 | ||
bf28607f DD |
2079 | wr = build_r4000_tlbchange_handler_head(&p, &l, &r); |
2080 | build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl); | |
8df5beac MR |
2081 | if (m4kc_tlbp_war()) |
2082 | build_tlb_probe_entry(&p); | |
6dd9344c | 2083 | |
5890f70f | 2084 | if (cpu_has_rixi && !cpu_has_rixiex) { |
6dd9344c DD |
2085 | /* |
2086 | * If the page is not _PAGE_VALID, RI or XI could not | |
2087 | * have triggered it. Skip the expensive test.. | |
2088 | */ | |
cc33ae43 | 2089 | if (use_bbit_insns()) { |
bf28607f | 2090 | uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID), |
cc33ae43 DD |
2091 | label_tlbl_goaround1); |
2092 | } else { | |
bf28607f DD |
2093 | uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID); |
2094 | uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround1); | |
cc33ae43 | 2095 | } |
6dd9344c DD |
2096 | uasm_i_nop(&p); |
2097 | ||
f39878cc PB |
2098 | /* |
2099 | * Warn if something may race with us & replace the TLB entry | |
2100 | * before we read it here. Everything with such races should | |
2101 | * also have dedicated RiXi exception handlers, so this | |
2102 | * shouldn't be hit. | |
2103 | */ | |
2104 | WARN(cpu_has_tlbex_tlbp_race(), "Unhandled race in RiXi path"); | |
2105 | ||
6dd9344c | 2106 | uasm_i_tlbr(&p); |
73acc7df | 2107 | |
13e6b812 TB |
2108 | if (cpu_has_mips_r2_exec_hazard) |
2109 | uasm_i_ehb(&p); | |
73acc7df | 2110 | |
6dd9344c | 2111 | /* Examine entrylo 0 or 1 based on ptr. */ |
cc33ae43 | 2112 | if (use_bbit_insns()) { |
bf28607f | 2113 | uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8); |
cc33ae43 | 2114 | } else { |
bf28607f DD |
2115 | uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t)); |
2116 | uasm_i_beqz(&p, wr.r3, 8); | |
cc33ae43 | 2117 | } |
bf28607f DD |
2118 | /* load it in the delay slot*/ |
2119 | UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0); | |
2120 | /* load it if ptr is odd */ | |
2121 | UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1); | |
6dd9344c | 2122 | /* |
bf28607f | 2123 | * If the entryLo (now in wr.r3) is valid (bit 1), RI or |
6dd9344c DD |
2124 | * XI must have triggered it. |
2125 | */ | |
cc33ae43 | 2126 | if (use_bbit_insns()) { |
bf28607f DD |
2127 | uasm_il_bbit1(&p, &r, wr.r3, 1, label_nopage_tlbl); |
2128 | uasm_i_nop(&p); | |
cc33ae43 DD |
2129 | uasm_l_tlbl_goaround1(&l, p); |
2130 | } else { | |
bf28607f DD |
2131 | uasm_i_andi(&p, wr.r3, wr.r3, 2); |
2132 | uasm_il_bnez(&p, &r, wr.r3, label_nopage_tlbl); | |
2133 | uasm_i_nop(&p); | |
cc33ae43 | 2134 | } |
bf28607f | 2135 | uasm_l_tlbl_goaround1(&l, p); |
6dd9344c | 2136 | } |
bbeeffec | 2137 | build_make_valid(&p, &r, wr.r1, wr.r2, wr.r3); |
bf28607f | 2138 | build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); |
1da177e4 | 2139 | |
aa1762f4 | 2140 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 DD |
2141 | /* |
2142 | * This is the entry point when build_r4000_tlbchange_handler_head | |
2143 | * spots a huge page. | |
2144 | */ | |
2145 | uasm_l_tlb_huge_update(&l, p); | |
bf28607f DD |
2146 | iPTE_LW(&p, wr.r1, wr.r2); |
2147 | build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl); | |
fd062c84 | 2148 | build_tlb_probe_entry(&p); |
6dd9344c | 2149 | |
5890f70f | 2150 | if (cpu_has_rixi && !cpu_has_rixiex) { |
6dd9344c DD |
2151 | /* |
2152 | * If the page is not _PAGE_VALID, RI or XI could not | |
2153 | * have triggered it. Skip the expensive test.. | |
2154 | */ | |
cc33ae43 | 2155 | if (use_bbit_insns()) { |
bf28607f | 2156 | uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID), |
cc33ae43 DD |
2157 | label_tlbl_goaround2); |
2158 | } else { | |
bf28607f DD |
2159 | uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID); |
2160 | uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2); | |
cc33ae43 | 2161 | } |
6dd9344c DD |
2162 | uasm_i_nop(&p); |
2163 | ||
f39878cc PB |
2164 | /* |
2165 | * Warn if something may race with us & replace the TLB entry | |
2166 | * before we read it here. Everything with such races should | |
2167 | * also have dedicated RiXi exception handlers, so this | |
2168 | * shouldn't be hit. | |
2169 | */ | |
2170 | WARN(cpu_has_tlbex_tlbp_race(), "Unhandled race in RiXi path"); | |
2171 | ||
6dd9344c | 2172 | uasm_i_tlbr(&p); |
73acc7df | 2173 | |
13e6b812 TB |
2174 | if (cpu_has_mips_r2_exec_hazard) |
2175 | uasm_i_ehb(&p); | |
73acc7df | 2176 | |
6dd9344c | 2177 | /* Examine entrylo 0 or 1 based on ptr. */ |
cc33ae43 | 2178 | if (use_bbit_insns()) { |
bf28607f | 2179 | uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8); |
cc33ae43 | 2180 | } else { |
bf28607f DD |
2181 | uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t)); |
2182 | uasm_i_beqz(&p, wr.r3, 8); | |
cc33ae43 | 2183 | } |
bf28607f DD |
2184 | /* load it in the delay slot*/ |
2185 | UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0); | |
2186 | /* load it if ptr is odd */ | |
2187 | UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1); | |
6dd9344c | 2188 | /* |
bf28607f | 2189 | * If the entryLo (now in wr.r3) is valid (bit 1), RI or |
6dd9344c DD |
2190 | * XI must have triggered it. |
2191 | */ | |
cc33ae43 | 2192 | if (use_bbit_insns()) { |
bf28607f | 2193 | uasm_il_bbit0(&p, &r, wr.r3, 1, label_tlbl_goaround2); |
cc33ae43 | 2194 | } else { |
bf28607f DD |
2195 | uasm_i_andi(&p, wr.r3, wr.r3, 2); |
2196 | uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2); | |
cc33ae43 | 2197 | } |
0f4ccbc8 DD |
2198 | if (PM_DEFAULT_MASK == 0) |
2199 | uasm_i_nop(&p); | |
6dd9344c DD |
2200 | /* |
2201 | * We clobbered C0_PAGEMASK, restore it. On the other branch | |
2202 | * it is restored in build_huge_tlb_write_entry. | |
2203 | */ | |
bf28607f | 2204 | build_restore_pagemask(&p, &r, wr.r3, label_nopage_tlbl, 0); |
6dd9344c DD |
2205 | |
2206 | uasm_l_tlbl_goaround2(&l, p); | |
2207 | } | |
bf28607f | 2208 | uasm_i_ori(&p, wr.r1, wr.r1, (_PAGE_ACCESSED | _PAGE_VALID)); |
0115f6cb | 2209 | build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 1); |
fd062c84 DD |
2210 | #endif |
2211 | ||
e30ec452 | 2212 | uasm_l_nopage_tlbl(&l, p); |
e02e07e3 HC |
2213 | if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS)) |
2214 | uasm_i_sync(&p, 0); | |
bf28607f | 2215 | build_restore_work_registers(&p); |
2a0b24f5 SH |
2216 | #ifdef CONFIG_CPU_MICROMIPS |
2217 | if ((unsigned long)tlb_do_page_fault_0 & 1) { | |
8cc461b8 JY |
2218 | uasm_i_lui(&p, GPR_K0, uasm_rel_hi((long)tlb_do_page_fault_0)); |
2219 | uasm_i_addiu(&p, GPR_K0, GPR_K0, uasm_rel_lo((long)tlb_do_page_fault_0)); | |
2220 | uasm_i_jr(&p, GPR_K0); | |
2a0b24f5 SH |
2221 | } else |
2222 | #endif | |
e30ec452 TS |
2223 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); |
2224 | uasm_i_nop(&p); | |
1da177e4 | 2225 | |
4bcb4ad6 | 2226 | if (p >= (u32 *)handle_tlbl_end) |
1da177e4 LT |
2227 | panic("TLB load handler fastpath space exceeded"); |
2228 | ||
e30ec452 TS |
2229 | uasm_resolve_relocs(relocs, labels); |
2230 | pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", | |
4bcb4ad6 | 2231 | (unsigned int)(p - (u32 *)handle_tlbl)); |
1da177e4 | 2232 | |
4bcb4ad6 | 2233 | dump_handler("r4000_tlb_load", handle_tlbl, handle_tlbl_end); |
1da177e4 LT |
2234 | } |
2235 | ||
078a55fc | 2236 | static void build_r4000_tlb_store_handler(void) |
1da177e4 | 2237 | { |
2c0e57ea | 2238 | u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbs); |
e30ec452 TS |
2239 | struct uasm_label *l = labels; |
2240 | struct uasm_reloc *r = relocs; | |
bf28607f | 2241 | struct work_registers wr; |
1da177e4 | 2242 | |
4bcb4ad6 | 2243 | memset(p, 0, handle_tlbs_end - (char *)p); |
1da177e4 LT |
2244 | memset(labels, 0, sizeof(labels)); |
2245 | memset(relocs, 0, sizeof(relocs)); | |
2246 | ||
bf28607f DD |
2247 | wr = build_r4000_tlbchange_handler_head(&p, &l, &r); |
2248 | build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs); | |
8df5beac MR |
2249 | if (m4kc_tlbp_war()) |
2250 | build_tlb_probe_entry(&p); | |
bbeeffec | 2251 | build_make_write(&p, &r, wr.r1, wr.r2, wr.r3); |
bf28607f | 2252 | build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); |
1da177e4 | 2253 | |
aa1762f4 | 2254 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 DD |
2255 | /* |
2256 | * This is the entry point when | |
2257 | * build_r4000_tlbchange_handler_head spots a huge page. | |
2258 | */ | |
2259 | uasm_l_tlb_huge_update(&l, p); | |
bf28607f DD |
2260 | iPTE_LW(&p, wr.r1, wr.r2); |
2261 | build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs); | |
fd062c84 | 2262 | build_tlb_probe_entry(&p); |
bf28607f | 2263 | uasm_i_ori(&p, wr.r1, wr.r1, |
fd062c84 | 2264 | _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); |
0115f6cb | 2265 | build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 1); |
fd062c84 DD |
2266 | #endif |
2267 | ||
e30ec452 | 2268 | uasm_l_nopage_tlbs(&l, p); |
e02e07e3 HC |
2269 | if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS)) |
2270 | uasm_i_sync(&p, 0); | |
bf28607f | 2271 | build_restore_work_registers(&p); |
2a0b24f5 SH |
2272 | #ifdef CONFIG_CPU_MICROMIPS |
2273 | if ((unsigned long)tlb_do_page_fault_1 & 1) { | |
8cc461b8 JY |
2274 | uasm_i_lui(&p, GPR_K0, uasm_rel_hi((long)tlb_do_page_fault_1)); |
2275 | uasm_i_addiu(&p, GPR_K0, GPR_K0, uasm_rel_lo((long)tlb_do_page_fault_1)); | |
2276 | uasm_i_jr(&p, GPR_K0); | |
2a0b24f5 SH |
2277 | } else |
2278 | #endif | |
e30ec452 TS |
2279 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); |
2280 | uasm_i_nop(&p); | |
1da177e4 | 2281 | |
4bcb4ad6 | 2282 | if (p >= (u32 *)handle_tlbs_end) |
1da177e4 LT |
2283 | panic("TLB store handler fastpath space exceeded"); |
2284 | ||
e30ec452 TS |
2285 | uasm_resolve_relocs(relocs, labels); |
2286 | pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", | |
4bcb4ad6 | 2287 | (unsigned int)(p - (u32 *)handle_tlbs)); |
1da177e4 | 2288 | |
4bcb4ad6 | 2289 | dump_handler("r4000_tlb_store", handle_tlbs, handle_tlbs_end); |
1da177e4 LT |
2290 | } |
2291 | ||
078a55fc | 2292 | static void build_r4000_tlb_modify_handler(void) |
1da177e4 | 2293 | { |
2c0e57ea | 2294 | u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbm); |
e30ec452 TS |
2295 | struct uasm_label *l = labels; |
2296 | struct uasm_reloc *r = relocs; | |
bf28607f | 2297 | struct work_registers wr; |
1da177e4 | 2298 | |
4bcb4ad6 | 2299 | memset(p, 0, handle_tlbm_end - (char *)p); |
1da177e4 LT |
2300 | memset(labels, 0, sizeof(labels)); |
2301 | memset(relocs, 0, sizeof(relocs)); | |
2302 | ||
bf28607f DD |
2303 | wr = build_r4000_tlbchange_handler_head(&p, &l, &r); |
2304 | build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm); | |
8df5beac MR |
2305 | if (m4kc_tlbp_war()) |
2306 | build_tlb_probe_entry(&p); | |
1da177e4 | 2307 | /* Present and writable bits set, set accessed and dirty bits. */ |
bbeeffec | 2308 | build_make_write(&p, &r, wr.r1, wr.r2, wr.r3); |
bf28607f | 2309 | build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); |
1da177e4 | 2310 | |
aa1762f4 | 2311 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
fd062c84 DD |
2312 | /* |
2313 | * This is the entry point when | |
2314 | * build_r4000_tlbchange_handler_head spots a huge page. | |
2315 | */ | |
2316 | uasm_l_tlb_huge_update(&l, p); | |
bf28607f DD |
2317 | iPTE_LW(&p, wr.r1, wr.r2); |
2318 | build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm); | |
fd062c84 | 2319 | build_tlb_probe_entry(&p); |
bf28607f | 2320 | uasm_i_ori(&p, wr.r1, wr.r1, |
fd062c84 | 2321 | _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); |
0115f6cb | 2322 | build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2, 0); |
fd062c84 DD |
2323 | #endif |
2324 | ||
e30ec452 | 2325 | uasm_l_nopage_tlbm(&l, p); |
e02e07e3 HC |
2326 | if (IS_ENABLED(CONFIG_CPU_LOONGSON3_WORKAROUNDS)) |
2327 | uasm_i_sync(&p, 0); | |
bf28607f | 2328 | build_restore_work_registers(&p); |
2a0b24f5 SH |
2329 | #ifdef CONFIG_CPU_MICROMIPS |
2330 | if ((unsigned long)tlb_do_page_fault_1 & 1) { | |
8cc461b8 JY |
2331 | uasm_i_lui(&p, GPR_K0, uasm_rel_hi((long)tlb_do_page_fault_1)); |
2332 | uasm_i_addiu(&p, GPR_K0, GPR_K0, uasm_rel_lo((long)tlb_do_page_fault_1)); | |
2333 | uasm_i_jr(&p, GPR_K0); | |
2a0b24f5 SH |
2334 | } else |
2335 | #endif | |
e30ec452 TS |
2336 | uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); |
2337 | uasm_i_nop(&p); | |
1da177e4 | 2338 | |
4bcb4ad6 | 2339 | if (p >= (u32 *)handle_tlbm_end) |
1da177e4 LT |
2340 | panic("TLB modify handler fastpath space exceeded"); |
2341 | ||
e30ec452 TS |
2342 | uasm_resolve_relocs(relocs, labels); |
2343 | pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", | |
4bcb4ad6 | 2344 | (unsigned int)(p - (u32 *)handle_tlbm)); |
115f2a44 | 2345 | |
4bcb4ad6 | 2346 | dump_handler("r4000_tlb_modify", handle_tlbm, handle_tlbm_end); |
1da177e4 LT |
2347 | } |
2348 | ||
078a55fc | 2349 | static void flush_tlb_handlers(void) |
a3d9086b JG |
2350 | { |
2351 | local_flush_icache_range((unsigned long)handle_tlbl, | |
6ac5310e | 2352 | (unsigned long)handle_tlbl_end); |
a3d9086b | 2353 | local_flush_icache_range((unsigned long)handle_tlbs, |
6ac5310e | 2354 | (unsigned long)handle_tlbs_end); |
a3d9086b | 2355 | local_flush_icache_range((unsigned long)handle_tlbm, |
6ac5310e | 2356 | (unsigned long)handle_tlbm_end); |
6ac5310e RB |
2357 | local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd, |
2358 | (unsigned long)tlbmiss_handler_setup_pgd_end); | |
a3d9086b JG |
2359 | } |
2360 | ||
f1014d1b MC |
2361 | static void print_htw_config(void) |
2362 | { | |
2363 | unsigned long config; | |
2364 | unsigned int pwctl; | |
2365 | const int field = 2 * sizeof(unsigned long); | |
2366 | ||
2367 | config = read_c0_pwfield(); | |
2368 | pr_debug("PWField (0x%0*lx): GDI: 0x%02lx UDI: 0x%02lx MDI: 0x%02lx PTI: 0x%02lx PTEI: 0x%02lx\n", | |
2369 | field, config, | |
2370 | (config & MIPS_PWFIELD_GDI_MASK) >> MIPS_PWFIELD_GDI_SHIFT, | |
2371 | (config & MIPS_PWFIELD_UDI_MASK) >> MIPS_PWFIELD_UDI_SHIFT, | |
2372 | (config & MIPS_PWFIELD_MDI_MASK) >> MIPS_PWFIELD_MDI_SHIFT, | |
2373 | (config & MIPS_PWFIELD_PTI_MASK) >> MIPS_PWFIELD_PTI_SHIFT, | |
2374 | (config & MIPS_PWFIELD_PTEI_MASK) >> MIPS_PWFIELD_PTEI_SHIFT); | |
2375 | ||
2376 | config = read_c0_pwsize(); | |
6446e6cf | 2377 | pr_debug("PWSize (0x%0*lx): PS: 0x%lx GDW: 0x%02lx UDW: 0x%02lx MDW: 0x%02lx PTW: 0x%02lx PTEW: 0x%02lx\n", |
f1014d1b | 2378 | field, config, |
6446e6cf | 2379 | (config & MIPS_PWSIZE_PS_MASK) >> MIPS_PWSIZE_PS_SHIFT, |
f1014d1b MC |
2380 | (config & MIPS_PWSIZE_GDW_MASK) >> MIPS_PWSIZE_GDW_SHIFT, |
2381 | (config & MIPS_PWSIZE_UDW_MASK) >> MIPS_PWSIZE_UDW_SHIFT, | |
2382 | (config & MIPS_PWSIZE_MDW_MASK) >> MIPS_PWSIZE_MDW_SHIFT, | |
2383 | (config & MIPS_PWSIZE_PTW_MASK) >> MIPS_PWSIZE_PTW_SHIFT, | |
2384 | (config & MIPS_PWSIZE_PTEW_MASK) >> MIPS_PWSIZE_PTEW_SHIFT); | |
2385 | ||
2386 | pwctl = read_c0_pwctl(); | |
6446e6cf | 2387 | pr_debug("PWCtl (0x%x): PWEn: 0x%x XK: 0x%x XS: 0x%x XU: 0x%x DPH: 0x%x HugePg: 0x%x Psn: 0x%x\n", |
f1014d1b MC |
2388 | pwctl, |
2389 | (pwctl & MIPS_PWCTL_PWEN_MASK) >> MIPS_PWCTL_PWEN_SHIFT, | |
6446e6cf JH |
2390 | (pwctl & MIPS_PWCTL_XK_MASK) >> MIPS_PWCTL_XK_SHIFT, |
2391 | (pwctl & MIPS_PWCTL_XS_MASK) >> MIPS_PWCTL_XS_SHIFT, | |
2392 | (pwctl & MIPS_PWCTL_XU_MASK) >> MIPS_PWCTL_XU_SHIFT, | |
f1014d1b MC |
2393 | (pwctl & MIPS_PWCTL_DPH_MASK) >> MIPS_PWCTL_DPH_SHIFT, |
2394 | (pwctl & MIPS_PWCTL_HUGEPG_MASK) >> MIPS_PWCTL_HUGEPG_SHIFT, | |
2395 | (pwctl & MIPS_PWCTL_PSN_MASK) >> MIPS_PWCTL_PSN_SHIFT); | |
2396 | } | |
2397 | ||
2398 | static void config_htw_params(void) | |
2399 | { | |
2400 | unsigned long pwfield, pwsize, ptei; | |
2401 | unsigned int config; | |
2402 | ||
2403 | /* | |
2404 | * We are using 2-level page tables, so we only need to | |
2405 | * setup GDW and PTW appropriately. UDW and MDW will remain 0. | |
2406 | * The default value of GDI/UDI/MDI/PTI is 0xc. It is illegal to | |
2407 | * write values less than 0xc in these fields because the entire | |
2408 | * write will be dropped. As a result of which, we must preserve | |
2409 | * the original reset values and overwrite only what we really want. | |
2410 | */ | |
2411 | ||
2412 | pwfield = read_c0_pwfield(); | |
2413 | /* re-initialize the GDI field */ | |
2414 | pwfield &= ~MIPS_PWFIELD_GDI_MASK; | |
2415 | pwfield |= PGDIR_SHIFT << MIPS_PWFIELD_GDI_SHIFT; | |
2416 | /* re-initialize the PTI field including the even/odd bit */ | |
2417 | pwfield &= ~MIPS_PWFIELD_PTI_MASK; | |
2418 | pwfield |= PAGE_SHIFT << MIPS_PWFIELD_PTI_SHIFT; | |
cab25bc7 PB |
2419 | if (CONFIG_PGTABLE_LEVELS >= 3) { |
2420 | pwfield &= ~MIPS_PWFIELD_MDI_MASK; | |
2421 | pwfield |= PMD_SHIFT << MIPS_PWFIELD_MDI_SHIFT; | |
2422 | } | |
f1014d1b MC |
2423 | /* Set the PTEI right shift */ |
2424 | ptei = _PAGE_GLOBAL_SHIFT << MIPS_PWFIELD_PTEI_SHIFT; | |
2425 | pwfield |= ptei; | |
2426 | write_c0_pwfield(pwfield); | |
2427 | /* Check whether the PTEI value is supported */ | |
2428 | back_to_back_c0_hazard(); | |
2429 | pwfield = read_c0_pwfield(); | |
2430 | if (((pwfield & MIPS_PWFIELD_PTEI_MASK) << MIPS_PWFIELD_PTEI_SHIFT) | |
2431 | != ptei) { | |
2432 | pr_warn("Unsupported PTEI field value: 0x%lx. HTW will not be enabled", | |
2433 | ptei); | |
2434 | /* | |
2435 | * Drop option to avoid HTW being enabled via another path | |
2436 | * (eg htw_reset()) | |
2437 | */ | |
2438 | current_cpu_data.options &= ~MIPS_CPU_HTW; | |
2439 | return; | |
2440 | } | |
2441 | ||
2442 | pwsize = ilog2(PTRS_PER_PGD) << MIPS_PWSIZE_GDW_SHIFT; | |
2443 | pwsize |= ilog2(PTRS_PER_PTE) << MIPS_PWSIZE_PTW_SHIFT; | |
cab25bc7 PB |
2444 | if (CONFIG_PGTABLE_LEVELS >= 3) |
2445 | pwsize |= ilog2(PTRS_PER_PMD) << MIPS_PWSIZE_MDW_SHIFT; | |
c5b36783 | 2446 | |
aa76042a | 2447 | /* Set pointer size to size of directory pointers */ |
97f2645f | 2448 | if (IS_ENABLED(CONFIG_64BIT)) |
aa76042a JH |
2449 | pwsize |= MIPS_PWSIZE_PS_MASK; |
2450 | /* PTEs may be multiple pointers long (e.g. with XPA) */ | |
2451 | pwsize |= ((PTE_T_LOG2 - PGD_T_LOG2) << MIPS_PWSIZE_PTEW_SHIFT) | |
2452 | & MIPS_PWSIZE_PTEW_MASK; | |
c5b36783 | 2453 | |
f1014d1b MC |
2454 | write_c0_pwsize(pwsize); |
2455 | ||
2456 | /* Make sure everything is set before we enable the HTW */ | |
2457 | back_to_back_c0_hazard(); | |
2458 | ||
aa76042a JH |
2459 | /* |
2460 | * Enable HTW (and only for XUSeg on 64-bit), and disable the rest of | |
2461 | * the pwctl fields. | |
2462 | */ | |
f1014d1b | 2463 | config = 1 << MIPS_PWCTL_PWEN_SHIFT; |
97f2645f | 2464 | if (IS_ENABLED(CONFIG_64BIT)) |
aa76042a | 2465 | config |= MIPS_PWCTL_XU_MASK; |
f1014d1b MC |
2466 | write_c0_pwctl(config); |
2467 | pr_info("Hardware Page Table Walker enabled\n"); | |
2468 | ||
2469 | print_htw_config(); | |
2470 | } | |
2471 | ||
c5b36783 SH |
2472 | static void config_xpa_params(void) |
2473 | { | |
2474 | #ifdef CONFIG_XPA | |
2475 | unsigned int pagegrain; | |
2476 | ||
2477 | if (mips_xpa_disabled) { | |
2478 | pr_info("Extended Physical Addressing (XPA) disabled\n"); | |
2479 | return; | |
2480 | } | |
2481 | ||
2482 | pagegrain = read_c0_pagegrain(); | |
2483 | write_c0_pagegrain(pagegrain | PG_ELPA); | |
2484 | back_to_back_c0_hazard(); | |
2485 | pagegrain = read_c0_pagegrain(); | |
2486 | ||
2487 | if (pagegrain & PG_ELPA) | |
2488 | pr_info("Extended Physical Addressing (XPA) enabled\n"); | |
2489 | else | |
2490 | panic("Extended Physical Addressing (XPA) disabled"); | |
2491 | #endif | |
2492 | } | |
2493 | ||
00bf1c69 PB |
2494 | static void check_pabits(void) |
2495 | { | |
2496 | unsigned long entry; | |
2497 | unsigned pabits, fillbits; | |
2498 | ||
74de14fe | 2499 | if (!cpu_has_rixi || _PAGE_NO_EXEC == 0) { |
00bf1c69 PB |
2500 | /* |
2501 | * We'll only be making use of the fact that we can rotate bits | |
2502 | * into the fill if the CPU supports RIXI, so don't bother | |
2503 | * probing this for CPUs which don't. | |
2504 | */ | |
2505 | return; | |
2506 | } | |
2507 | ||
2508 | write_c0_entrylo0(~0ul); | |
2509 | back_to_back_c0_hazard(); | |
2510 | entry = read_c0_entrylo0(); | |
2511 | ||
2512 | /* clear all non-PFN bits */ | |
2513 | entry &= ~((1 << MIPS_ENTRYLO_PFN_SHIFT) - 1); | |
2514 | entry &= ~(MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI); | |
2515 | ||
2516 | /* find a lower bound on PABITS, and upper bound on fill bits */ | |
2517 | pabits = fls_long(entry) + 6; | |
2518 | fillbits = max_t(int, (int)BITS_PER_LONG - pabits, 0); | |
2519 | ||
2520 | /* minus the RI & XI bits */ | |
2521 | fillbits -= min_t(unsigned, fillbits, 2); | |
2522 | ||
2523 | if (fillbits >= ilog2(_PAGE_NO_EXEC)) | |
2524 | fill_includes_sw_bits = true; | |
2525 | ||
2526 | pr_debug("Entry* registers contain %u fill bits\n", fillbits); | |
2527 | } | |
2528 | ||
078a55fc | 2529 | void build_tlb_refill_handler(void) |
1da177e4 LT |
2530 | { |
2531 | /* | |
2532 | * The refill handler is generated per-CPU, multi-node systems | |
2533 | * may have local storage for it. The other handlers are only | |
2534 | * needed once. | |
2535 | */ | |
2536 | static int run_once = 0; | |
2537 | ||
97f2645f | 2538 | if (IS_ENABLED(CONFIG_XPA) && !cpu_has_rixi) |
e56c7e18 PB |
2539 | panic("Kernels supporting XPA currently require CPUs with RIXI"); |
2540 | ||
a2c763e0 | 2541 | output_pgtable_bits_defines(); |
00bf1c69 | 2542 | check_pabits(); |
a2c763e0 | 2543 | |
1ec56329 | 2544 | #ifdef CONFIG_64BIT |
bb5af4f6 | 2545 | check_for_high_segbits = current_cpu_data.vmbits > (PGDIR_SHIFT + PGD_TABLE_ORDER + PAGE_SHIFT - 3); |
1ec56329 DD |
2546 | #endif |
2547 | ||
54e8d9f0 | 2548 | if (cpu_has_3kex) { |
82622284 | 2549 | #ifndef CONFIG_MIPS_PGD_C0_CONTEXT |
1da177e4 | 2550 | if (!run_once) { |
f4ae17aa | 2551 | build_setup_pgd(); |
775b089a | 2552 | build_r3000_tlb_refill_handler(); |
1da177e4 LT |
2553 | build_r3000_tlb_load_handler(); |
2554 | build_r3000_tlb_store_handler(); | |
2555 | build_r3000_tlb_modify_handler(); | |
a3d9086b | 2556 | flush_tlb_handlers(); |
1da177e4 LT |
2557 | run_once++; |
2558 | } | |
82622284 DD |
2559 | #else |
2560 | panic("No R3000 TLB refill handler"); | |
2561 | #endif | |
54e8d9f0 PB |
2562 | return; |
2563 | } | |
1da177e4 | 2564 | |
54e8d9f0 PB |
2565 | if (cpu_has_ldpte) |
2566 | setup_pw(); | |
380cd582 | 2567 | |
54e8d9f0 PB |
2568 | if (!run_once) { |
2569 | scratch_reg = allocate_kscratch(); | |
2570 | build_setup_pgd(); | |
2571 | build_r4000_tlb_load_handler(); | |
2572 | build_r4000_tlb_store_handler(); | |
2573 | build_r4000_tlb_modify_handler(); | |
2574 | if (cpu_has_ldpte) | |
2575 | build_loongson3_tlb_refill_handler(); | |
775b089a | 2576 | else |
8759934e | 2577 | build_r4000_tlb_refill_handler(); |
54e8d9f0 PB |
2578 | flush_tlb_handlers(); |
2579 | run_once++; | |
1da177e4 | 2580 | } |
54e8d9f0 PB |
2581 | if (cpu_has_xpa) |
2582 | config_xpa_params(); | |
2583 | if (cpu_has_htw) | |
2584 | config_htw_params(); | |
1da177e4 | 2585 | } |