[linux-2.6-block.git] / arch / mips / mm / tlb-r4k.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
 * Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle ralf@gnu.org
 * Carsten Langgaard, carstenl@mips.com
 * Copyright (C) 2002 MIPS Technologies, Inc.  All rights reserved.
 */
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/smp.h>
#include <linux/mm.h>
#include <linux/hugetlb.h>
#include <linux/module.h>

#include <asm/cpu.h>
#include <asm/cpu-type.h>
#include <asm/bootinfo.h>
#include <asm/mmu_context.h>
#include <asm/pgtable.h>
#include <asm/tlb.h>
#include <asm/tlbmisc.h>

extern void build_tlb_refill_handler(void);

/* Atomicity and interruptability */
#ifdef CONFIG_MIPS_MT_SMTC

#include <asm/smtc.h>
#include <asm/mipsmtregs.h>

#define ENTER_CRITICAL(flags) \
	{ \
	unsigned int mvpflags; \
	local_irq_save(flags);\
	mvpflags = dvpe()
#define EXIT_CRITICAL(flags) \
	evpe(mvpflags); \
	local_irq_restore(flags); \
	}
#else

#define ENTER_CRITICAL(flags) local_irq_save(flags)
#define EXIT_CRITICAL(flags) local_irq_restore(flags)

#endif /* CONFIG_MIPS_MT_SMTC */

/*
 * LOONGSON2 has a 4 entry itlb which is a subset of dtlb,
 * unfortrunately, itlb is not totally transparent to software.
 */
static inline void flush_itlb(void)
{
	switch (current_cpu_type()) {
	case CPU_LOONGSON2:
		write_c0_diag(4);
		break;
	default:
		break;
	}
}

static inline void flush_itlb_vm(struct vm_area_struct *vma)
{
	if (vma->vm_flags & VM_EXEC)
		flush_itlb();
}

void local_flush_tlb_all(void)
{
	unsigned long flags;
	unsigned long old_ctx;
	int entry, ftlbhighset;

	ENTER_CRITICAL(flags);
	/* Save old context and create impossible VPN2 value */
	old_ctx = read_c0_entryhi();
	write_c0_entrylo0(0);
	write_c0_entrylo1(0);

	entry = read_c0_wired();

	/* Blast 'em all away. */
	if (cpu_has_tlbinv) {
		if (current_cpu_data.tlbsizevtlb) {
			write_c0_index(0);
			mtc0_tlbw_hazard();
			tlbinvf();  /* invalidate VTLB */
		}
		ftlbhighset = current_cpu_data.tlbsizevtlb +
			current_cpu_data.tlbsizeftlbsets;
		for (entry = current_cpu_data.tlbsizevtlb;
		     entry < ftlbhighset;
		     entry++) {
			write_c0_index(entry);
			mtc0_tlbw_hazard();
			tlbinvf();  /* invalidate one FTLB set */
		}
	} else {
		while (entry < current_cpu_data.tlbsize) {
			/* Make sure all entries differ. */
			write_c0_entryhi(UNIQUE_ENTRYHI(entry));
			write_c0_index(entry);
			mtc0_tlbw_hazard();
			tlb_write_indexed();
			entry++;
		}
	}
	tlbw_use_hazard();
	write_c0_entryhi(old_ctx);
	flush_itlb();
	EXIT_CRITICAL(flags);
}
EXPORT_SYMBOL(local_flush_tlb_all);

/* All entries common to a mm share an asid.  To effectively flush
   these entries, we just bump the asid. */
void local_flush_tlb_mm(struct mm_struct *mm)
{
	int cpu;

	preempt_disable();

	cpu = smp_processor_id();

	if (cpu_context(cpu, mm) != 0) {
		drop_mmu_context(mm, cpu);
	}

	preempt_enable();
}

void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
	unsigned long end)
{
	struct mm_struct *mm = vma->vm_mm;
	int cpu = smp_processor_id();

	if (cpu_context(cpu, mm) != 0) {
		unsigned long size, flags;

		ENTER_CRITICAL(flags);
		start = round_down(start, PAGE_SIZE << 1);
		end = round_up(end, PAGE_SIZE << 1);
		size = (end - start) >> (PAGE_SHIFT + 1);
		if (size <= (current_cpu_data.tlbsizeftlbsets ?
			     current_cpu_data.tlbsize / 8 :
			     current_cpu_data.tlbsize / 2)) {
			int oldpid = read_c0_entryhi();
			int newpid = cpu_asid(cpu, mm);

			while (start < end) {
				int idx;

				write_c0_entryhi(start | newpid);
				start += (PAGE_SIZE << 1);
				mtc0_tlbw_hazard();
				tlb_probe();
				tlb_probe_hazard();
				idx = read_c0_index();
				write_c0_entrylo0(0);
				write_c0_entrylo1(0);
				if (idx < 0)
					continue;
				/* Make sure all entries differ. */
				write_c0_entryhi(UNIQUE_ENTRYHI(idx));
				mtc0_tlbw_hazard();
				tlb_write_indexed();
			}
			tlbw_use_hazard();
			write_c0_entryhi(oldpid);
		} else {
			drop_mmu_context(mm, cpu);
		}
		flush_itlb();
		EXIT_CRITICAL(flags);
	}
}

void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
{
	unsigned long size, flags;

	ENTER_CRITICAL(flags);
	size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
	size = (size + 1) >> 1;
	if (size <= (current_cpu_data.tlbsizeftlbsets ?
		     current_cpu_data.tlbsize / 8 :
		     current_cpu_data.tlbsize / 2)) {
		int pid = read_c0_entryhi();

		start &= (PAGE_MASK << 1);
		end += ((PAGE_SIZE << 1) - 1);
		end &= (PAGE_MASK << 1);

		while (start < end) {
			int idx;

			write_c0_entryhi(start);
			start += (PAGE_SIZE << 1);
			mtc0_tlbw_hazard();
			tlb_probe();
			tlb_probe_hazard();
			idx = read_c0_index();
			write_c0_entrylo0(0);
			write_c0_entrylo1(0);
			if (idx < 0)
				continue;
			/* Make sure all entries differ. */
			write_c0_entryhi(UNIQUE_ENTRYHI(idx));
			mtc0_tlbw_hazard();
			tlb_write_indexed();
		}
		tlbw_use_hazard();
		write_c0_entryhi(pid);
	} else {
		local_flush_tlb_all();
	}
	flush_itlb();
	EXIT_CRITICAL(flags);
}

void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
{
	int cpu = smp_processor_id();

	if (cpu_context(cpu, vma->vm_mm) != 0) {
		unsigned long flags;
		int oldpid, newpid, idx;

		newpid = cpu_asid(cpu, vma->vm_mm);
		page &= (PAGE_MASK << 1);
		ENTER_CRITICAL(flags);
		oldpid = read_c0_entryhi();
		write_c0_entryhi(page | newpid);
		mtc0_tlbw_hazard();
		tlb_probe();
		tlb_probe_hazard();
		idx = read_c0_index();
		write_c0_entrylo0(0);
		write_c0_entrylo1(0);
		if (idx < 0)
			goto finish;
		/* Make sure all entries differ. */
		write_c0_entryhi(UNIQUE_ENTRYHI(idx));
		mtc0_tlbw_hazard();
		tlb_write_indexed();
		tlbw_use_hazard();

	finish:
		write_c0_entryhi(oldpid);
		flush_itlb_vm(vma);
		EXIT_CRITICAL(flags);
	}
}

/*
 * This one is only used for pages with the global bit set so we don't care
 * much about the ASID.
 */
void local_flush_tlb_one(unsigned long page)
{
	unsigned long flags;
	int oldpid, idx;

	ENTER_CRITICAL(flags);
	oldpid = read_c0_entryhi();
	page &= (PAGE_MASK << 1);
	write_c0_entryhi(page);
	mtc0_tlbw_hazard();
	tlb_probe();
	tlb_probe_hazard();
	idx = read_c0_index();
	write_c0_entrylo0(0);
	write_c0_entrylo1(0);
	if (idx >= 0) {
		/* Make sure all entries differ. */
		write_c0_entryhi(UNIQUE_ENTRYHI(idx));
		mtc0_tlbw_hazard();
		tlb_write_indexed();
		tlbw_use_hazard();
	}
	write_c0_entryhi(oldpid);
	flush_itlb();
	EXIT_CRITICAL(flags);
}

/*
 * We will need multiple versions of update_mmu_cache(), one that just
 * updates the TLB with the new pte(s), and another which also checks
 * for the R4k "end of page" hardware bug and does the needy.
 */
void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
{
	unsigned long flags;
	pgd_t *pgdp;
	pud_t *pudp;
	pmd_t *pmdp;
	pte_t *ptep;
	int idx, pid;

	/*
	 * Handle debugger faulting in for debugee.
	 */
	if (current->active_mm != vma->vm_mm)
		return;

	ENTER_CRITICAL(flags);

	pid = read_c0_entryhi() & ASID_MASK;
	address &= (PAGE_MASK << 1);
	write_c0_entryhi(address | pid);
	pgdp = pgd_offset(vma->vm_mm, address);
	mtc0_tlbw_hazard();
	tlb_probe();
	tlb_probe_hazard();
	pudp = pud_offset(pgdp, address);
	pmdp = pmd_offset(pudp, address);
	idx = read_c0_index();
#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
	/* this could be a huge page  */
	if (pmd_huge(*pmdp)) {
		unsigned long lo;
		write_c0_pagemask(PM_HUGE_MASK);
		ptep = (pte_t *)pmdp;
		lo = pte_to_entrylo(pte_val(*ptep));
		write_c0_entrylo0(lo);
		write_c0_entrylo1(lo + (HPAGE_SIZE >> 7));

		mtc0_tlbw_hazard();
		if (idx < 0)
			tlb_write_random();
		else
			tlb_write_indexed();
		tlbw_use_hazard();
		write_c0_pagemask(PM_DEFAULT_MASK);
	} else
#endif
	{
		ptep = pte_offset_map(pmdp, address);

#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
		write_c0_entrylo0(ptep->pte_high);
		ptep++;
		write_c0_entrylo1(ptep->pte_high);
#else
		write_c0_entrylo0(pte_to_entrylo(pte_val(*ptep++)));
		write_c0_entrylo1(pte_to_entrylo(pte_val(*ptep)));
#endif
		mtc0_tlbw_hazard();
		if (idx < 0)
			tlb_write_random();
		else
			tlb_write_indexed();
	}
	tlbw_use_hazard();
	flush_itlb_vm(vma);
	EXIT_CRITICAL(flags);
}

void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
		     unsigned long entryhi, unsigned long pagemask)
{
	unsigned long flags;
	unsigned long wired;
	unsigned long old_pagemask;
	unsigned long old_ctx;

	ENTER_CRITICAL(flags);
	/* Save old context and create impossible VPN2 value */
	old_ctx = read_c0_entryhi();
	old_pagemask = read_c0_pagemask();
	wired = read_c0_wired();
	write_c0_wired(wired + 1);
	write_c0_index(wired);
	tlbw_use_hazard();	/* What is the hazard here? */
	write_c0_pagemask(pagemask);
	write_c0_entryhi(entryhi);
	write_c0_entrylo0(entrylo0);
	write_c0_entrylo1(entrylo1);
	mtc0_tlbw_hazard();
	tlb_write_indexed();
	tlbw_use_hazard();

	write_c0_entryhi(old_ctx);
	tlbw_use_hazard();	/* What is the hazard here? */
	write_c0_pagemask(old_pagemask);
	local_flush_tlb_all();
	EXIT_CRITICAL(flags);
}

#ifdef CONFIG_TRANSPARENT_HUGEPAGE

int __init has_transparent_hugepage(void)
{
	unsigned int mask;
	unsigned long flags;

	ENTER_CRITICAL(flags);
	write_c0_pagemask(PM_HUGE_MASK);
	back_to_back_c0_hazard();
	mask = read_c0_pagemask();
	write_c0_pagemask(PM_DEFAULT_MASK);

	EXIT_CRITICAL(flags);

	return mask == PM_HUGE_MASK;
}

#endif /* CONFIG_TRANSPARENT_HUGEPAGE  */

static int ntlb;
static int __init set_ntlb(char *str)
{
	get_option(&str, &ntlb);
	return 1;
}

__setup("ntlb=", set_ntlb);

void tlb_init(void)
{
	/*
	 * You should never change this register:
	 *   - On R4600 1.7 the tlbp never hits for pages smaller than
	 *     the value in the c0_pagemask register.
	 *   - The entire mm handling assumes the c0_pagemask register to
	 *     be set to fixed-size pages.
	 */
	write_c0_pagemask(PM_DEFAULT_MASK);
	write_c0_wired(0);
	if (current_cpu_type() == CPU_R10000 ||
	    current_cpu_type() == CPU_R12000 ||
	    current_cpu_type() == CPU_R14000)
		write_c0_framemask(0);

	if (cpu_has_rixi) {
		/*
		 * Enable the no read, no exec bits, and enable large virtual
		 * address.
		 */
		u32 pg = PG_RIE | PG_XIE;
#ifdef CONFIG_64BIT
		pg |= PG_ELPA;
#endif
		write_c0_pagegrain(pg);
	}

	/* From this point on the ARC firmware is dead.	 */
	local_flush_tlb_all();

	/* Did I tell you that ARC SUCKS?  */

	if (ntlb) {
		if (ntlb > 1 && ntlb <= current_cpu_data.tlbsize) {
			int wired = current_cpu_data.tlbsize - ntlb;
			write_c0_wired(wired);
			write_c0_index(wired-1);
			printk("Restricting TLB to %d entries\n", ntlb);
		} else
			printk("Ignoring invalid argument ntlb=%d\n", ntlb);
	}

	build_tlb_refill_handler();
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
79add627	6	* Copyright (C) 1996 David S. Miller (davem@davemloft.net)
1da177e4 LT	7	* Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle ralf@gnu.org
	8	* Carsten Langgaard, carstenl@mips.com
	9	* Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved.
	10	*/
1da177e4 LT	11	#include <linux/init.h>
1da177e4 LT	12	#include <linux/sched.h>
631330f5	13	#include <linux/smp.h>
1da177e4	14	#include <linux/mm.h>
fd062c84	15	#include <linux/hugetlb.h>
f2e3656d	16	#include <linux/module.h>
1da177e4 LT	17
1da177e4 LT	18	#include <asm/cpu.h>
69f24d17	19	#include <asm/cpu-type.h>
1da177e4 LT	20	#include <asm/bootinfo.h>
	21	#include <asm/mmu_context.h>
	22	#include <asm/pgtable.h>
c01905ee	23	#include <asm/tlb.h>
3d18c983	24	#include <asm/tlbmisc.h>
1da177e4 LT	25
	26	extern void build_tlb_refill_handler(void);
	27
41c594ab RB	28	/* Atomicity and interruptability */
	29	#ifdef CONFIG_MIPS_MT_SMTC
	30
	31	#include <asm/smtc.h>
	32	#include <asm/mipsmtregs.h>
	33
	34	#define ENTER_CRITICAL(flags) \
	35	{ \
	36	unsigned int mvpflags; \
	37	local_irq_save(flags);\
	38	mvpflags = dvpe()
	39	#define EXIT_CRITICAL(flags) \
	40	evpe(mvpflags); \
	41	local_irq_restore(flags); \
	42	}
	43	#else
	44
	45	#define ENTER_CRITICAL(flags) local_irq_save(flags)
	46	#define EXIT_CRITICAL(flags) local_irq_restore(flags)
	47
	48	#endif /* CONFIG_MIPS_MT_SMTC */
	49
2a21c730 FZ	50	/*
	51	* LOONGSON2 has a 4 entry itlb which is a subset of dtlb,
	52	* unfortrunately, itlb is not totally transparent to software.
	53	*/
14bd8c08 RB	54	static inline void flush_itlb(void)
	55	{
	56	switch (current_cpu_type()) {
	57	case CPU_LOONGSON2:
	58	write_c0_diag(4);
	59	break;
	60	default:
	61	break;
	62	}
	63	}
2a21c730	64
14bd8c08 RB	65	static inline void flush_itlb_vm(struct vm_area_struct *vma)
	66	{
	67	if (vma->vm_flags & VM_EXEC)
	68	flush_itlb();
	69	}
2a21c730	70
1da177e4 LT	71	void local_flush_tlb_all(void)
	72	{
	73	unsigned long flags;
	74	unsigned long old_ctx;
75b5b5e0	75	int entry, ftlbhighset;
1da177e4	76
41c594ab	77	ENTER_CRITICAL(flags);
1da177e4 LT	78	/* Save old context and create impossible VPN2 value */
	79	old_ctx = read_c0_entryhi();
	80	write_c0_entrylo0(0);
	81	write_c0_entrylo1(0);
	82
	83	entry = read_c0_wired();
	84
	85	/* Blast 'em all away. */
75b5b5e0 LY	86	if (cpu_has_tlbinv) {
	87	if (current_cpu_data.tlbsizevtlb) {
	88	write_c0_index(0);
	89	mtc0_tlbw_hazard();
	90	tlbinvf(); /* invalidate VTLB */
	91	}
	92	ftlbhighset = current_cpu_data.tlbsizevtlb +
	93	current_cpu_data.tlbsizeftlbsets;
	94	for (entry = current_cpu_data.tlbsizevtlb;
	95	entry < ftlbhighset;
	96	entry++) {
	97	write_c0_index(entry);
	98	mtc0_tlbw_hazard();
	99	tlbinvf(); /* invalidate one FTLB set */
	100	}
601cfa7b LY	101	} else {
	102	while (entry < current_cpu_data.tlbsize) {
	103	/* Make sure all entries differ. */
	104	write_c0_entryhi(UNIQUE_ENTRYHI(entry));
	105	write_c0_index(entry);
	106	mtc0_tlbw_hazard();
	107	tlb_write_indexed();
	108	entry++;
	109	}
1da177e4 LT	110	}
	111	tlbw_use_hazard();
	112	write_c0_entryhi(old_ctx);
14bd8c08	113	flush_itlb();
41c594ab	114	EXIT_CRITICAL(flags);
1da177e4	115	}
f2e3656d	116	EXPORT_SYMBOL(local_flush_tlb_all);
1da177e4	117
172546bf TS	118	/* All entries common to a mm share an asid. To effectively flush
172546bf TS	119	these entries, we just bump the asid. */
1da177e4 LT	120	void local_flush_tlb_mm(struct mm_struct *mm)
1da177e4 LT	121	{
172546bf TS	122	int cpu;
	123
	124	preempt_disable();
1da177e4	125
172546bf TS	126	cpu = smp_processor_id();
	127
	128	if (cpu_context(cpu, mm) != 0) {
	129	drop_mmu_context(mm, cpu);
	130	}
	131
	132	preempt_enable();
1da177e4 LT	133	}
	134
	135	void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
	136	unsigned long end)
	137	{
	138	struct mm_struct *mm = vma->vm_mm;
	139	int cpu = smp_processor_id();
	140
	141	if (cpu_context(cpu, mm) != 0) {
a5e696e5	142	unsigned long size, flags;
1da177e4	143
41c594ab	144	ENTER_CRITICAL(flags);
ac53c4fc DD	145	start = round_down(start, PAGE_SIZE << 1);
	146	end = round_up(end, PAGE_SIZE << 1);
	147	size = (end - start) >> (PAGE_SHIFT + 1);
75b5b5e0 LY	148	if (size <= (current_cpu_data.tlbsizeftlbsets ?
	149	current_cpu_data.tlbsize / 8 :
	150	current_cpu_data.tlbsize / 2)) {
1da177e4 LT	151	int oldpid = read_c0_entryhi();
	152	int newpid = cpu_asid(cpu, mm);
	153
1da177e4 LT	154	while (start < end) {
	155	int idx;
	156
	157	write_c0_entryhi(start \| newpid);
ac53c4fc	158	start += (PAGE_SIZE << 1);
1da177e4 LT	159	mtc0_tlbw_hazard();
1da177e4 LT	160	tlb_probe();
432bef2a	161	tlb_probe_hazard();
1da177e4 LT	162	idx = read_c0_index();
	163	write_c0_entrylo0(0);
	164	write_c0_entrylo1(0);
	165	if (idx < 0)
	166	continue;
	167	/* Make sure all entries differ. */
172546bf	168	write_c0_entryhi(UNIQUE_ENTRYHI(idx));
1da177e4 LT	169	mtc0_tlbw_hazard();
	170	tlb_write_indexed();
	171	}
	172	tlbw_use_hazard();
	173	write_c0_entryhi(oldpid);
	174	} else {
	175	drop_mmu_context(mm, cpu);
	176	}
14bd8c08	177	flush_itlb();
41c594ab	178	EXIT_CRITICAL(flags);
1da177e4 LT	179	}
	180	}
	181
	182	void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
	183	{
a5e696e5	184	unsigned long size, flags;
1da177e4	185
41c594ab	186	ENTER_CRITICAL(flags);
1da177e4 LT	187	size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
1da177e4 LT	188	size = (size + 1) >> 1;
75b5b5e0 LY	189	if (size <= (current_cpu_data.tlbsizeftlbsets ?
	190	current_cpu_data.tlbsize / 8 :
	191	current_cpu_data.tlbsize / 2)) {
1da177e4 LT	192	int pid = read_c0_entryhi();
	193
	194	start &= (PAGE_MASK << 1);
	195	end += ((PAGE_SIZE << 1) - 1);
	196	end &= (PAGE_MASK << 1);
	197
	198	while (start < end) {
	199	int idx;
	200
	201	write_c0_entryhi(start);
	202	start += (PAGE_SIZE << 1);
	203	mtc0_tlbw_hazard();
	204	tlb_probe();
432bef2a	205	tlb_probe_hazard();
1da177e4 LT	206	idx = read_c0_index();
	207	write_c0_entrylo0(0);
	208	write_c0_entrylo1(0);
	209	if (idx < 0)
	210	continue;
	211	/* Make sure all entries differ. */
172546bf	212	write_c0_entryhi(UNIQUE_ENTRYHI(idx));
1da177e4 LT	213	mtc0_tlbw_hazard();
	214	tlb_write_indexed();
	215	}
	216	tlbw_use_hazard();
	217	write_c0_entryhi(pid);
	218	} else {
	219	local_flush_tlb_all();
	220	}
14bd8c08	221	flush_itlb();
41c594ab	222	EXIT_CRITICAL(flags);
1da177e4 LT	223	}
	224
	225	void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
	226	{
	227	int cpu = smp_processor_id();
	228
	229	if (cpu_context(cpu, vma->vm_mm) != 0) {
	230	unsigned long flags;
	231	int oldpid, newpid, idx;
	232
	233	newpid = cpu_asid(cpu, vma->vm_mm);
	234	page &= (PAGE_MASK << 1);
41c594ab	235	ENTER_CRITICAL(flags);
1da177e4 LT	236	oldpid = read_c0_entryhi();
	237	write_c0_entryhi(page \| newpid);
	238	mtc0_tlbw_hazard();
	239	tlb_probe();
432bef2a	240	tlb_probe_hazard();
1da177e4 LT	241	idx = read_c0_index();
	242	write_c0_entrylo0(0);
	243	write_c0_entrylo1(0);
	244	if (idx < 0)
	245	goto finish;
	246	/* Make sure all entries differ. */
172546bf	247	write_c0_entryhi(UNIQUE_ENTRYHI(idx));
1da177e4 LT	248	mtc0_tlbw_hazard();
	249	tlb_write_indexed();
	250	tlbw_use_hazard();
	251
	252	finish:
	253	write_c0_entryhi(oldpid);
14bd8c08	254	flush_itlb_vm(vma);
41c594ab	255	EXIT_CRITICAL(flags);
1da177e4 LT	256	}
	257	}
	258
	259	/*
	260	* This one is only used for pages with the global bit set so we don't care
	261	* much about the ASID.
	262	*/
	263	void local_flush_tlb_one(unsigned long page)
	264	{
	265	unsigned long flags;
	266	int oldpid, idx;
	267
41c594ab	268	ENTER_CRITICAL(flags);
1da177e4	269	oldpid = read_c0_entryhi();
172546bf	270	page &= (PAGE_MASK << 1);
1da177e4 LT	271	write_c0_entryhi(page);
	272	mtc0_tlbw_hazard();
	273	tlb_probe();
432bef2a	274	tlb_probe_hazard();
1da177e4 LT	275	idx = read_c0_index();
	276	write_c0_entrylo0(0);
	277	write_c0_entrylo1(0);
	278	if (idx >= 0) {
	279	/* Make sure all entries differ. */
172546bf	280	write_c0_entryhi(UNIQUE_ENTRYHI(idx));
1da177e4 LT	281	mtc0_tlbw_hazard();
	282	tlb_write_indexed();
	283	tlbw_use_hazard();
	284	}
	285	write_c0_entryhi(oldpid);
14bd8c08	286	flush_itlb();
41c594ab	287	EXIT_CRITICAL(flags);
1da177e4 LT	288	}
	289
	290	/*
	291	* We will need multiple versions of update_mmu_cache(), one that just
	292	* updates the TLB with the new pte(s), and another which also checks
	293	* for the R4k "end of page" hardware bug and does the needy.
	294	*/
	295	void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
	296	{
	297	unsigned long flags;
	298	pgd_t *pgdp;
c6e8b587	299	pud_t *pudp;
1da177e4 LT	300	pmd_t *pmdp;
	301	pte_t *ptep;
	302	int idx, pid;
	303
	304	/*
	305	* Handle debugger faulting in for debugee.
	306	*/
	307	if (current->active_mm != vma->vm_mm)
	308	return;
	309
41c594ab	310	ENTER_CRITICAL(flags);
172546bf	311
48c4ac97	312	pid = read_c0_entryhi() & ASID_MASK;
1da177e4 LT	313	address &= (PAGE_MASK << 1);
	314	write_c0_entryhi(address \| pid);
	315	pgdp = pgd_offset(vma->vm_mm, address);
	316	mtc0_tlbw_hazard();
	317	tlb_probe();
432bef2a	318	tlb_probe_hazard();
c6e8b587 RB	319	pudp = pud_offset(pgdp, address);
c6e8b587 RB	320	pmdp = pmd_offset(pudp, address);
1da177e4	321	idx = read_c0_index();
aa1762f4	322	#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
fd062c84 DD	323	/* this could be a huge page */
	324	if (pmd_huge(*pmdp)) {
	325	unsigned long lo;
	326	write_c0_pagemask(PM_HUGE_MASK);
	327	ptep = (pte_t *)pmdp;
6dd9344c	328	lo = pte_to_entrylo(pte_val(*ptep));
fd062c84 DD	329	write_c0_entrylo0(lo);
	330	write_c0_entrylo1(lo + (HPAGE_SIZE >> 7));
	331
	332	mtc0_tlbw_hazard();
	333	if (idx < 0)
	334	tlb_write_random();
	335	else
	336	tlb_write_indexed();
fb944c9b	337	tlbw_use_hazard();
fd062c84 DD	338	write_c0_pagemask(PM_DEFAULT_MASK);
	339	} else
	340	#endif
	341	{
	342	ptep = pte_offset_map(pmdp, address);
1da177e4	343
962f480e	344	#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
fd062c84 DD	345	write_c0_entrylo0(ptep->pte_high);
	346	ptep++;
	347	write_c0_entrylo1(ptep->pte_high);
1da177e4	348	#else
6dd9344c DD	349	write_c0_entrylo0(pte_to_entrylo(pte_val(*ptep++)));
6dd9344c DD	350	write_c0_entrylo1(pte_to_entrylo(pte_val(*ptep)));
1da177e4	351	#endif
fd062c84 DD	352	mtc0_tlbw_hazard();
	353	if (idx < 0)
	354	tlb_write_random();
	355	else
	356	tlb_write_indexed();
	357	}
1da177e4	358	tlbw_use_hazard();
14bd8c08	359	flush_itlb_vm(vma);
41c594ab	360	EXIT_CRITICAL(flags);
1da177e4 LT	361	}
1da177e4 LT	362
694b8c35 ML	363	void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
694b8c35 ML	364	unsigned long entryhi, unsigned long pagemask)
1da177e4 LT	365	{
	366	unsigned long flags;
	367	unsigned long wired;
	368	unsigned long old_pagemask;
	369	unsigned long old_ctx;
	370
41c594ab	371	ENTER_CRITICAL(flags);
1da177e4 LT	372	/* Save old context and create impossible VPN2 value */
	373	old_ctx = read_c0_entryhi();
	374	old_pagemask = read_c0_pagemask();
	375	wired = read_c0_wired();
	376	write_c0_wired(wired + 1);
	377	write_c0_index(wired);
432bef2a	378	tlbw_use_hazard(); /* What is the hazard here? */
1da177e4 LT	379	write_c0_pagemask(pagemask);
	380	write_c0_entryhi(entryhi);
	381	write_c0_entrylo0(entrylo0);
	382	write_c0_entrylo1(entrylo1);
	383	mtc0_tlbw_hazard();
	384	tlb_write_indexed();
	385	tlbw_use_hazard();
	386
	387	write_c0_entryhi(old_ctx);
432bef2a	388	tlbw_use_hazard(); /* What is the hazard here? */
1da177e4 LT	389	write_c0_pagemask(old_pagemask);
1da177e4 LT	390	local_flush_tlb_all();
41c594ab	391	EXIT_CRITICAL(flags);
1da177e4 LT	392	}
1da177e4 LT	393
970d032f RB	394	#ifdef CONFIG_TRANSPARENT_HUGEPAGE
	395
	396	int __init has_transparent_hugepage(void)
	397	{
	398	unsigned int mask;
	399	unsigned long flags;
	400
	401	ENTER_CRITICAL(flags);
	402	write_c0_pagemask(PM_HUGE_MASK);
	403	back_to_back_c0_hazard();
	404	mask = read_c0_pagemask();
	405	write_c0_pagemask(PM_DEFAULT_MASK);
	406
	407	EXIT_CRITICAL(flags);
	408
	409	return mask == PM_HUGE_MASK;
	410	}
	411
	412	#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
	413
078a55fc	414	static int ntlb;
41c594ab RB	415	static int __init set_ntlb(char *str)
	416	{
	417	get_option(&str, &ntlb);
	418	return 1;
	419	}
	420
	421	__setup("ntlb=", set_ntlb);
	422
078a55fc	423	void tlb_init(void)
1da177e4	424	{
1da177e4 LT	425	/*
	426	* You should never change this register:
	427	* - On R4600 1.7 the tlbp never hits for pages smaller than
	428	* the value in the c0_pagemask register.
	429	* - The entire mm handling assumes the c0_pagemask register to
a7c2996e	430	* be set to fixed-size pages.
1da177e4	431	*/
1da177e4 LT	432	write_c0_pagemask(PM_DEFAULT_MASK);
1da177e4 LT	433	write_c0_wired(0);
cde15b59 RB	434	if (current_cpu_type() == CPU_R10000 \|\|
	435	current_cpu_type() == CPU_R12000 \|\|
	436	current_cpu_type() == CPU_R14000)
	437	write_c0_framemask(0);
6dd9344c	438
05857c64	439	if (cpu_has_rixi) {
6dd9344c DD	440	/*
	441	* Enable the no read, no exec bits, and enable large virtual
	442	* address.
	443	*/
	444	u32 pg = PG_RIE \| PG_XIE;
	445	#ifdef CONFIG_64BIT
	446	pg \|= PG_ELPA;
	447	#endif
	448	write_c0_pagegrain(pg);
	449	}
	450
70342287	451	/* From this point on the ARC firmware is dead. */
1da177e4 LT	452	local_flush_tlb_all();
1da177e4 LT	453
c6281edb TS	454	/* Did I tell you that ARC SUCKS? */
c6281edb TS	455
41c594ab RB	456	if (ntlb) {
	457	if (ntlb > 1 && ntlb <= current_cpu_data.tlbsize) {
	458	int wired = current_cpu_data.tlbsize - ntlb;
	459	write_c0_wired(wired);
	460	write_c0_index(wired-1);
49a89efb	461	printk("Restricting TLB to %d entries\n", ntlb);
41c594ab RB	462	} else
	463	printk("Ignoring invalid argument ntlb=%d\n", ntlb);
	464	}
	465
1da177e4 LT	466	build_tlb_refill_handler();
1da177e4 LT	467	}