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9318c51a CD |
1 | /* |
2 | * Copyright (C) 2006 Chris Dearman (chris@mips.com), | |
3 | */ | |
4 | #include <linux/init.h> | |
5 | #include <linux/kernel.h> | |
6 | #include <linux/sched.h> | |
7 | #include <linux/mm.h> | |
8 | ||
9 | #include <asm/mipsregs.h> | |
10 | #include <asm/bcache.h> | |
11 | #include <asm/cacheops.h> | |
12 | #include <asm/page.h> | |
13 | #include <asm/pgtable.h> | |
14 | #include <asm/system.h> | |
15 | #include <asm/mmu_context.h> | |
16 | #include <asm/r4kcache.h> | |
17 | ||
18 | /* | |
19 | * MIPS32/MIPS64 L2 cache handling | |
20 | */ | |
21 | ||
22 | /* | |
23 | * Writeback and invalidate the secondary cache before DMA. | |
24 | */ | |
25 | static void mips_sc_wback_inv(unsigned long addr, unsigned long size) | |
26 | { | |
a2c2bc4b | 27 | blast_scache_range(addr, addr + size); |
9318c51a CD |
28 | } |
29 | ||
30 | /* | |
31 | * Invalidate the secondary cache before DMA. | |
32 | */ | |
33 | static void mips_sc_inv(unsigned long addr, unsigned long size) | |
34 | { | |
a2c2bc4b | 35 | blast_inv_scache_range(addr, addr + size); |
9318c51a CD |
36 | } |
37 | ||
38 | static void mips_sc_enable(void) | |
39 | { | |
40 | /* L2 cache is permanently enabled */ | |
41 | } | |
42 | ||
43 | static void mips_sc_disable(void) | |
44 | { | |
45 | /* L2 cache is permanently enabled */ | |
46 | } | |
47 | ||
48 | static struct bcache_ops mips_sc_ops = { | |
49 | .bc_enable = mips_sc_enable, | |
50 | .bc_disable = mips_sc_disable, | |
51 | .bc_wback_inv = mips_sc_wback_inv, | |
52 | .bc_inv = mips_sc_inv | |
53 | }; | |
54 | ||
55 | static inline int __init mips_sc_probe(void) | |
56 | { | |
57 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
58 | unsigned int config1, config2; | |
59 | unsigned int tmp; | |
60 | ||
61 | /* Mark as not present until probe completed */ | |
62 | c->scache.flags |= MIPS_CACHE_NOT_PRESENT; | |
63 | ||
64 | /* Ignore anything but MIPSxx processors */ | |
65 | if (c->isa_level != MIPS_CPU_ISA_M32R1 && | |
66 | c->isa_level != MIPS_CPU_ISA_M32R2 && | |
67 | c->isa_level != MIPS_CPU_ISA_M64R1 && | |
68 | c->isa_level != MIPS_CPU_ISA_M64R2) | |
69 | return 0; | |
70 | ||
71 | /* Does this MIPS32/MIPS64 CPU have a config2 register? */ | |
72 | config1 = read_c0_config1(); | |
73 | if (!(config1 & MIPS_CONF_M)) | |
74 | return 0; | |
75 | ||
76 | config2 = read_c0_config2(); | |
77 | tmp = (config2 >> 4) & 0x0f; | |
78 | if (0 < tmp && tmp <= 7) | |
79 | c->scache.linesz = 2 << tmp; | |
80 | else | |
81 | return 0; | |
82 | ||
83 | tmp = (config2 >> 8) & 0x0f; | |
84 | if (0 <= tmp && tmp <= 7) | |
85 | c->scache.sets = 64 << tmp; | |
86 | else | |
87 | return 0; | |
88 | ||
89 | tmp = (config2 >> 0) & 0x0f; | |
90 | if (0 <= tmp && tmp <= 7) | |
91 | c->scache.ways = tmp + 1; | |
92 | else | |
93 | return 0; | |
94 | ||
95 | c->scache.waysize = c->scache.sets * c->scache.linesz; | |
a2c2bc4b | 96 | c->scache.waybit = __ffs(c->scache.waysize); |
9318c51a CD |
97 | |
98 | c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; | |
99 | ||
100 | return 1; | |
101 | } | |
102 | ||
103 | int __init mips_sc_init(void) | |
104 | { | |
105 | int found = mips_sc_probe (); | |
106 | if (found) { | |
107 | mips_sc_enable(); | |
108 | bcops = &mips_sc_ops; | |
109 | } | |
110 | return found; | |
111 | } | |
112 |