[linux-2.6-block.git] / arch / mips / mm / init.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1994 - 2000 Ralf Baechle
 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
 * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
 */
#include <linux/bug.h>
#include <linux/init.h>
#include <linux/export.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/smp.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/types.h>
#include <linux/pagemap.h>
#include <linux/ptrace.h>
#include <linux/mman.h>
#include <linux/mm.h>
#include <linux/memblock.h>
#include <linux/highmem.h>
#include <linux/swap.h>
#include <linux/proc_fs.h>
#include <linux/pfn.h>
#include <linux/hardirq.h>
#include <linux/gfp.h>
#include <linux/kcore.h>
#include <linux/initrd.h>
#include <linux/execmem.h>

#include <asm/bootinfo.h>
#include <asm/cachectl.h>
#include <asm/cpu.h>
#include <asm/dma.h>
#include <asm/maar.h>
#include <asm/mmu_context.h>
#include <asm/mmzone.h>
#include <asm/sections.h>
#include <asm/pgalloc.h>
#include <asm/tlb.h>
#include <asm/fixmap.h>

/*
 * We have up to 8 empty zeroed pages so we can map one of the right colour
 * when needed.	 This is necessary only on R4000 / R4400 SC and MC versions
 * where we have to avoid VCED / VECI exceptions for good performance at
 * any price.  Since page is never written to after the initialization we
 * don't have to care about aliases on other CPUs.
 */
unsigned long empty_zero_page, zero_page_mask;
EXPORT_SYMBOL_GPL(empty_zero_page);
EXPORT_SYMBOL(zero_page_mask);

/*
 * Not static inline because used by IP27 special magic initialization code
 */
static void __init setup_zero_pages(void)
{
	unsigned int order;

	if (cpu_has_vce)
		order = 3;
	else
		order = 0;

	empty_zero_page = (unsigned long)memblock_alloc_or_panic(PAGE_SIZE << order, PAGE_SIZE);

	zero_page_mask = ((PAGE_SIZE << order) - 1) & PAGE_MASK;
}

static void *__kmap_pgprot(struct page *page, unsigned long addr, pgprot_t prot)
{
	enum fixed_addresses idx;
	unsigned int old_mmid;
	unsigned long vaddr, flags, entrylo;
	unsigned long old_ctx;
	pte_t pte;
	int tlbidx;

	BUG_ON(folio_test_dcache_dirty(page_folio(page)));

	preempt_disable();
	pagefault_disable();
	idx = (addr >> PAGE_SHIFT) & (FIX_N_COLOURS - 1);
	idx += in_interrupt() ? FIX_N_COLOURS : 0;
	vaddr = __fix_to_virt(FIX_CMAP_END - idx);
	pte = mk_pte(page, prot);
#if defined(CONFIG_XPA)
	entrylo = pte_to_entrylo(pte.pte_high);
#elif defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
	entrylo = pte.pte_high;
#else
	entrylo = pte_to_entrylo(pte_val(pte));
#endif

	local_irq_save(flags);
	old_ctx = read_c0_entryhi();
	write_c0_entryhi(vaddr & (PAGE_MASK << 1));
	write_c0_entrylo0(entrylo);
	write_c0_entrylo1(entrylo);
	if (cpu_has_mmid) {
		old_mmid = read_c0_memorymapid();
		write_c0_memorymapid(MMID_KERNEL_WIRED);
	}
#ifdef CONFIG_XPA
	if (cpu_has_xpa) {
		entrylo = (pte.pte_low & _PFNX_MASK);
		writex_c0_entrylo0(entrylo);
		writex_c0_entrylo1(entrylo);
	}
#endif
	tlbidx = num_wired_entries();
	write_c0_wired(tlbidx + 1);
	write_c0_index(tlbidx);
	mtc0_tlbw_hazard();
	tlb_write_indexed();
	tlbw_use_hazard();
	write_c0_entryhi(old_ctx);
	if (cpu_has_mmid)
		write_c0_memorymapid(old_mmid);
	local_irq_restore(flags);

	return (void*) vaddr;
}

void *kmap_coherent(struct page *page, unsigned long addr)
{
	return __kmap_pgprot(page, addr, PAGE_KERNEL);
}

void *kmap_noncoherent(struct page *page, unsigned long addr)
{
	return __kmap_pgprot(page, addr, PAGE_KERNEL_NC);
}

void kunmap_coherent(void)
{
	unsigned int wired;
	unsigned long flags, old_ctx;

	local_irq_save(flags);
	old_ctx = read_c0_entryhi();
	wired = num_wired_entries() - 1;
	write_c0_wired(wired);
	write_c0_index(wired);
	write_c0_entryhi(UNIQUE_ENTRYHI(wired));
	write_c0_entrylo0(0);
	write_c0_entrylo1(0);
	mtc0_tlbw_hazard();
	tlb_write_indexed();
	tlbw_use_hazard();
	write_c0_entryhi(old_ctx);
	local_irq_restore(flags);
	pagefault_enable();
	preempt_enable();
}

void copy_user_highpage(struct page *to, struct page *from,
	unsigned long vaddr, struct vm_area_struct *vma)
{
	struct folio *src = page_folio(from);
	void *vfrom, *vto;

	vto = kmap_atomic(to);
	if (cpu_has_dc_aliases &&
	    folio_mapped(src) && !folio_test_dcache_dirty(src)) {
		vfrom = kmap_coherent(from, vaddr);
		copy_page(vto, vfrom);
		kunmap_coherent();
	} else {
		vfrom = kmap_atomic(from);
		copy_page(vto, vfrom);
		kunmap_atomic(vfrom);
	}
	if ((!cpu_has_ic_fills_f_dc) ||
	    pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
		flush_data_cache_page((unsigned long)vto);
	kunmap_atomic(vto);
	/* Make sure this page is cleared on other CPU's too before using it */
	smp_wmb();
}

void copy_to_user_page(struct vm_area_struct *vma,
	struct page *page, unsigned long vaddr, void *dst, const void *src,
	unsigned long len)
{
	struct folio *folio = page_folio(page);

	if (cpu_has_dc_aliases &&
	    folio_mapped(folio) && !folio_test_dcache_dirty(folio)) {
		void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
		memcpy(vto, src, len);
		kunmap_coherent();
	} else {
		memcpy(dst, src, len);
		if (cpu_has_dc_aliases)
			folio_set_dcache_dirty(folio);
	}
	if (vma->vm_flags & VM_EXEC)
		flush_cache_page(vma, vaddr, page_to_pfn(page));
}

void copy_from_user_page(struct vm_area_struct *vma,
	struct page *page, unsigned long vaddr, void *dst, const void *src,
	unsigned long len)
{
	struct folio *folio = page_folio(page);

	if (cpu_has_dc_aliases &&
	    folio_mapped(folio) && !folio_test_dcache_dirty(folio)) {
		void *vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
		memcpy(dst, vfrom, len);
		kunmap_coherent();
	} else {
		memcpy(dst, src, len);
		if (cpu_has_dc_aliases)
			folio_set_dcache_dirty(folio);
	}
}
EXPORT_SYMBOL_GPL(copy_from_user_page);

void __init fixrange_init(unsigned long start, unsigned long end,
	pgd_t *pgd_base)
{
#ifdef CONFIG_HIGHMEM
	pgd_t *pgd;
	pud_t *pud;
	pmd_t *pmd;
	pte_t *pte;
	int i, j, k;
	unsigned long vaddr;

	vaddr = start;
	i = pgd_index(vaddr);
	j = pud_index(vaddr);
	k = pmd_index(vaddr);
	pgd = pgd_base + i;

	for ( ; (i < PTRS_PER_PGD) && (vaddr < end); pgd++, i++) {
		pud = (pud_t *)pgd;
		for ( ; (j < PTRS_PER_PUD) && (vaddr < end); pud++, j++) {
			pmd = (pmd_t *)pud;
			for (; (k < PTRS_PER_PMD) && (vaddr < end); pmd++, k++) {
				if (pmd_none(*pmd)) {
					pte = (pte_t *) memblock_alloc_low(PAGE_SIZE,
									   PAGE_SIZE);
					if (!pte)
						panic("%s: Failed to allocate %lu bytes align=%lx\n",
						      __func__, PAGE_SIZE,
						      PAGE_SIZE);

					set_pmd(pmd, __pmd((unsigned long)pte));
					BUG_ON(pte != pte_offset_kernel(pmd, 0));
				}
				vaddr += PMD_SIZE;
			}
			k = 0;
		}
		j = 0;
	}
#endif
}

struct maar_walk_info {
	struct maar_config cfg[16];
	unsigned int num_cfg;
};

static int maar_res_walk(unsigned long start_pfn, unsigned long nr_pages,
			 void *data)
{
	struct maar_walk_info *wi = data;
	struct maar_config *cfg = &wi->cfg[wi->num_cfg];
	unsigned int maar_align;

	/* MAAR registers hold physical addresses right shifted by 4 bits */
	maar_align = BIT(MIPS_MAAR_ADDR_SHIFT + 4);

	/* Fill in the MAAR config entry */
	cfg->lower = ALIGN(PFN_PHYS(start_pfn), maar_align);
	cfg->upper = ALIGN_DOWN(PFN_PHYS(start_pfn + nr_pages), maar_align) - 1;
	cfg->attrs = MIPS_MAAR_S;

	/* Ensure we don't overflow the cfg array */
	if (!WARN_ON(wi->num_cfg >= ARRAY_SIZE(wi->cfg)))
		wi->num_cfg++;

	return 0;
}


unsigned __weak platform_maar_init(unsigned num_pairs)
{
	unsigned int num_configured;
	struct maar_walk_info wi;

	wi.num_cfg = 0;
	walk_system_ram_range(0, max_pfn, &wi, maar_res_walk);

	num_configured = maar_config(wi.cfg, wi.num_cfg, num_pairs);
	if (num_configured < wi.num_cfg)
		pr_warn("Not enough MAAR pairs (%u) for all memory regions (%u)\n",
			num_pairs, wi.num_cfg);

	return num_configured;
}

void maar_init(void)
{
	unsigned num_maars, used, i;
	phys_addr_t lower, upper, attr;
	static struct {
		struct maar_config cfgs[3];
		unsigned used;
	} recorded = { { { 0 } }, 0 };

	if (!cpu_has_maar)
		return;

	/* Detect the number of MAARs */
	write_c0_maari(~0);
	back_to_back_c0_hazard();
	num_maars = read_c0_maari() + 1;

	/* MAARs should be in pairs */
	WARN_ON(num_maars % 2);

	/* Set MAARs using values we recorded already */
	if (recorded.used) {
		used = maar_config(recorded.cfgs, recorded.used, num_maars / 2);
		BUG_ON(used != recorded.used);
	} else {
		/* Configure the required MAARs */
		used = platform_maar_init(num_maars / 2);
	}

	/* Disable any further MAARs */
	for (i = (used * 2); i < num_maars; i++) {
		write_c0_maari(i);
		back_to_back_c0_hazard();
		write_c0_maar(0);
		back_to_back_c0_hazard();
	}

	if (recorded.used)
		return;

	pr_info("MAAR configuration:\n");
	for (i = 0; i < num_maars; i += 2) {
		write_c0_maari(i);
		back_to_back_c0_hazard();
		upper = read_c0_maar();
#ifdef CONFIG_XPA
		upper |= (phys_addr_t)readx_c0_maar() << MIPS_MAARX_ADDR_SHIFT;
#endif

		write_c0_maari(i + 1);
		back_to_back_c0_hazard();
		lower = read_c0_maar();
#ifdef CONFIG_XPA
		lower |= (phys_addr_t)readx_c0_maar() << MIPS_MAARX_ADDR_SHIFT;
#endif

		attr = lower & upper;
		lower = (lower & MIPS_MAAR_ADDR) << 4;
		upper = ((upper & MIPS_MAAR_ADDR) << 4) | 0xffff;

		pr_info("  [%d]: ", i / 2);
		if ((attr & MIPS_MAAR_V) != MIPS_MAAR_V) {
			pr_cont("disabled\n");
			continue;
		}

		pr_cont("%pa-%pa", &lower, &upper);

		if (attr & MIPS_MAAR_S)
			pr_cont(" speculate");

		pr_cont("\n");

		/* Record the setup for use on secondary CPUs */
		if (used <= ARRAY_SIZE(recorded.cfgs)) {
			recorded.cfgs[recorded.used].lower = lower;
			recorded.cfgs[recorded.used].upper = upper;
			recorded.cfgs[recorded.used].attrs = attr;
			recorded.used++;
		}
	}
}

#ifndef CONFIG_NUMA
void __init paging_init(void)
{
	unsigned long max_zone_pfns[MAX_NR_ZONES];

	pagetable_init();

#ifdef CONFIG_ZONE_DMA
	max_zone_pfns[ZONE_DMA] = MAX_DMA_PFN;
#endif
#ifdef CONFIG_ZONE_DMA32
	max_zone_pfns[ZONE_DMA32] = MAX_DMA32_PFN;
#endif
	max_zone_pfns[ZONE_NORMAL] = max_low_pfn;
#ifdef CONFIG_HIGHMEM
	max_zone_pfns[ZONE_HIGHMEM] = highend_pfn;

	if (cpu_has_dc_aliases && max_low_pfn != highend_pfn) {
		printk(KERN_WARNING "This processor doesn't support highmem."
		       " %ldk highmem ignored\n",
		       (highend_pfn - max_low_pfn) << (PAGE_SHIFT - 10));
		max_zone_pfns[ZONE_HIGHMEM] = max_low_pfn;
	}
#endif

	free_area_init(max_zone_pfns);
}

#ifdef CONFIG_64BIT
static struct kcore_list kcore_kseg0;
#endif

void __init arch_mm_preinit(void)
{
	/*
	 * When PFN_PTE_SHIFT is greater than PAGE_SHIFT we won't have enough PTE
	 * bits to hold a full 32b physical address on MIPS32 systems.
	 */
	BUILD_BUG_ON(IS_ENABLED(CONFIG_32BIT) && (PFN_PTE_SHIFT > PAGE_SHIFT));

	maar_init();
	setup_zero_pages();	/* Setup zeroed pages.  */

#ifdef CONFIG_64BIT
	if ((unsigned long) &_text > (unsigned long) CKSEG0)
		/* The -4 is a hack so that user tools don't have to handle
		   the overflow.  */
		kclist_add(&kcore_kseg0, (void *) CKSEG0,
				0x80000000 - 4, KCORE_TEXT);
#endif
}
#else  /* CONFIG_NUMA */
void __init arch_mm_preinit(void)
{
	setup_zero_pages();	/* This comes from node 0 */
}
#endif /* !CONFIG_NUMA */

void free_init_pages(const char *what, unsigned long begin, unsigned long end)
{
	unsigned long pfn;

	for (pfn = PFN_UP(begin); pfn < PFN_DOWN(end); pfn++) {
		struct page *page = pfn_to_page(pfn);
		void *addr = phys_to_virt(PFN_PHYS(pfn));

		memset(addr, POISON_FREE_INITMEM, PAGE_SIZE);
		free_reserved_page(page);
	}
	printk(KERN_INFO "Freeing %s: %ldk freed\n", what, (end - begin) >> 10);
}

void (*free_init_pages_eva)(void *begin, void *end) = NULL;

void __weak __init prom_free_prom_memory(void)
{
	/* nothing to do */
}

void __ref free_initmem(void)
{
	prom_free_prom_memory();
	/*
	 * Let the platform define a specific function to free the
	 * init section since EVA may have used any possible mapping
	 * between virtual and physical addresses.
	 */
	if (free_init_pages_eva)
		free_init_pages_eva((void *)&__init_begin, (void *)&__init_end);
	else
		free_initmem_default(POISON_FREE_INITMEM);
}

#ifdef CONFIG_HAVE_SETUP_PER_CPU_AREA
unsigned long __per_cpu_offset[NR_CPUS] __read_mostly;
EXPORT_SYMBOL(__per_cpu_offset);

static int __init pcpu_cpu_distance(unsigned int from, unsigned int to)
{
	return node_distance(cpu_to_node(from), cpu_to_node(to));
}

static int __init pcpu_cpu_to_node(int cpu)
{
	return cpu_to_node(cpu);
}

void __init setup_per_cpu_areas(void)
{
	unsigned long delta;
	unsigned int cpu;
	int rc;

	/*
	 * Always reserve area for module percpu variables.  That's
	 * what the legacy allocator did.
	 */
	rc = pcpu_embed_first_chunk(PERCPU_MODULE_RESERVE,
				    PERCPU_DYNAMIC_RESERVE, PAGE_SIZE,
				    pcpu_cpu_distance,
				    pcpu_cpu_to_node);
	if (rc < 0)
		panic("Failed to initialize percpu areas.");

	delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
	for_each_possible_cpu(cpu)
		__per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu];
}
#endif

#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
unsigned long pgd_current[NR_CPUS];
#endif

/*
 * Align swapper_pg_dir in to 64K, allows its address to be loaded
 * with a single LUI instruction in the TLB handlers.  If we used
 * __aligned(64K), its size would get rounded up to the alignment
 * size, and waste space.  So we place it in its own section and align
 * it in the linker script.
 */
pgd_t swapper_pg_dir[PTRS_PER_PGD] __section(".bss..swapper_pg_dir");
#ifndef __PAGETABLE_PUD_FOLDED
pud_t invalid_pud_table[PTRS_PER_PUD] __page_aligned_bss;
#endif
#ifndef __PAGETABLE_PMD_FOLDED
pmd_t invalid_pmd_table[PTRS_PER_PMD] __page_aligned_bss;
EXPORT_SYMBOL_GPL(invalid_pmd_table);
#endif
pte_t invalid_pte_table[PTRS_PER_PTE] __page_aligned_bss;
EXPORT_SYMBOL(invalid_pte_table);

#ifdef CONFIG_EXECMEM
#ifdef MODULES_VADDR
static struct execmem_info execmem_info __ro_after_init;

struct execmem_info __init *execmem_arch_setup(void)
{
	execmem_info = (struct execmem_info){
		.ranges = {
			[EXECMEM_DEFAULT] = {
				.start	= MODULES_VADDR,
				.end	= MODULES_END,
				.pgprot	= PAGE_KERNEL,
				.alignment = 1,
			},
		},
	};

	return &execmem_info;
}
#endif
#endif /* CONFIG_EXECMEM */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 1994 - 2000 Ralf Baechle
	7	* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
	8	* Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
	9	* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
	10	*/
b868868a	11	#include <linux/bug.h>
1da177e4	12	#include <linux/init.h>
d9ba5778	13	#include <linux/export.h>
1da177e4 LT	14	#include <linux/signal.h>
1da177e4 LT	15	#include <linux/sched.h>
631330f5	16	#include <linux/smp.h>
1da177e4 LT	17	#include <linux/kernel.h>
	18	#include <linux/errno.h>
	19	#include <linux/string.h>
	20	#include <linux/types.h>
	21	#include <linux/pagemap.h>
	22	#include <linux/ptrace.h>
	23	#include <linux/mman.h>
	24	#include <linux/mm.h>
57c8a661	25	#include <linux/memblock.h>
1da177e4 LT	26	#include <linux/highmem.h>
1da177e4 LT	27	#include <linux/swap.h>
3d503753	28	#include <linux/proc_fs.h>
22a9835c	29	#include <linux/pfn.h>
0f334a3e	30	#include <linux/hardirq.h>
5a0e3ad6	31	#include <linux/gfp.h>
2f96b8c1	32	#include <linux/kcore.h>
2aa7687c	33	#include <linux/initrd.h>
0cc2dc49	34	#include <linux/execmem.h>
1da177e4 LT	35
	36	#include <asm/bootinfo.h>
	37	#include <asm/cachectl.h>
	38	#include <asm/cpu.h>
	39	#include <asm/dma.h>
cbd95a89	40	#include <asm/maar.h>
1da177e4	41	#include <asm/mmu_context.h>
e021227a	42	#include <asm/mmzone.h>
1da177e4	43	#include <asm/sections.h>
1da177e4 LT	44	#include <asm/pgalloc.h>
1da177e4 LT	45	#include <asm/tlb.h>
f8829cae RB	46	#include <asm/fixmap.h>
f8829cae RB	47
1da177e4 LT	48	/*
1da177e4 LT	49	* We have up to 8 empty zeroed pages so we can map one of the right colour
70342287	50	* when needed. This is necessary only on R4000 / R4400 SC and MC versions
1da177e4 LT	51	* where we have to avoid VCED / VECI exceptions for good performance at
	52	* any price. Since page is never written to after the initialization we
	53	* don't have to care about aliases on other CPUs.
	54	*/
	55	unsigned long empty_zero_page, zero_page_mask;
497d2adc	56	EXPORT_SYMBOL_GPL(empty_zero_page);
0b70068e	57	EXPORT_SYMBOL(zero_page_mask);
1da177e4 LT	58
	59	/*
	60	* Not static inline because used by IP27 special magic initialization code
	61	*/
e74e2b8e	62	static void __init setup_zero_pages(void)
1da177e4	63	{
e74e2b8e	64	unsigned int order;
1da177e4 LT	65
	66	if (cpu_has_vce)
	67	order = 3;
	68	else
	69	order = 0;
	70
e74e2b8e	71	empty_zero_page = (unsigned long)memblock_alloc_or_panic(PAGE_SIZE << order, PAGE_SIZE);
1da177e4	72
31605922	73	zero_page_mask = ((PAGE_SIZE << order) - 1) & PAGE_MASK;
1da177e4 LT	74	}
1da177e4 LT	75
e2a9e5ad	76	static void __kmap_pgprot(struct page page, unsigned long addr, pgprot_t prot)
f8829cae RB	77	{
f8829cae RB	78	enum fixed_addresses idx;
3f649ab7	79	unsigned int old_mmid;
f8829cae RB	80	unsigned long vaddr, flags, entrylo;
	81	unsigned long old_ctx;
	82	pte_t pte;
	83	int tlbidx;
	84
15fa3e8e	85	BUG_ON(folio_test_dcache_dirty(page_folio(page)));
b868868a	86
ce01948e	87	preempt_disable();
bdb43806	88	pagefault_disable();
f8829cae	89	idx = (addr >> PAGE_SHIFT) & (FIX_N_COLOURS - 1);
0f334a3e	90	idx += in_interrupt() ? FIX_N_COLOURS : 0;
f8829cae	91	vaddr = __fix_to_virt(FIX_CMAP_END - idx);
e2a9e5ad	92	pte = mk_pte(page, prot);
7b2cb64f	93	#if defined(CONFIG_XPA)
c5b36783	94	entrylo = pte_to_entrylo(pte.pte_high);
7b2cb64f PB	95	#elif defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
7b2cb64f PB	96	entrylo = pte.pte_high;
f8829cae	97	#else
6dd9344c	98	entrylo = pte_to_entrylo(pte_val(pte));
f8829cae RB	99	#endif
f8829cae RB	100
b633648c	101	local_irq_save(flags);
f8829cae RB	102	old_ctx = read_c0_entryhi();
	103	write_c0_entryhi(vaddr & (PAGE_MASK << 1));
	104	write_c0_entrylo0(entrylo);
	105	write_c0_entrylo1(entrylo);
c8790d65 PB	106	if (cpu_has_mmid) {
	107	old_mmid = read_c0_memorymapid();
	108	write_c0_memorymapid(MMID_KERNEL_WIRED);
	109	}
c5b36783	110	#ifdef CONFIG_XPA
4b6f99d3 JH	111	if (cpu_has_xpa) {
	112	entrylo = (pte.pte_low & _PFNX_MASK);
	113	writex_c0_entrylo0(entrylo);
	114	writex_c0_entrylo1(entrylo);
	115	}
c5b36783	116	#endif
10313980	117	tlbidx = num_wired_entries();
f8829cae RB	118	write_c0_wired(tlbidx + 1);
	119	write_c0_index(tlbidx);
	120	mtc0_tlbw_hazard();
	121	tlb_write_indexed();
f8829cae RB	122	tlbw_use_hazard();
f8829cae RB	123	write_c0_entryhi(old_ctx);
c8790d65 PB	124	if (cpu_has_mmid)
c8790d65 PB	125	write_c0_memorymapid(old_mmid);
b633648c	126	local_irq_restore(flags);
f8829cae RB	127
	128	return (void*) vaddr;
	129	}
	130
e2a9e5ad PB	131	void kmap_coherent(struct page page, unsigned long addr)
	132	{
	133	return __kmap_pgprot(page, addr, PAGE_KERNEL);
	134	}
	135
	136	void kmap_noncoherent(struct page page, unsigned long addr)
	137	{
	138	return __kmap_pgprot(page, addr, PAGE_KERNEL_NC);
	139	}
	140
eacb9d61	141	void kunmap_coherent(void)
f8829cae	142	{
f8829cae RB	143	unsigned int wired;
	144	unsigned long flags, old_ctx;
	145
b633648c	146	local_irq_save(flags);
f8829cae	147	old_ctx = read_c0_entryhi();
10313980	148	wired = num_wired_entries() - 1;
f8829cae RB	149	write_c0_wired(wired);
	150	write_c0_index(wired);
	151	write_c0_entryhi(UNIQUE_ENTRYHI(wired));
	152	write_c0_entrylo0(0);
	153	write_c0_entrylo1(0);
	154	mtc0_tlbw_hazard();
	155	tlb_write_indexed();
	156	tlbw_use_hazard();
	157	write_c0_entryhi(old_ctx);
b633648c	158	local_irq_restore(flags);
bdb43806	159	pagefault_enable();
ce01948e	160	preempt_enable();
f8829cae RB	161	}
f8829cae RB	162
bcd02280 AN	163	void copy_user_highpage(struct page to, struct page from,
	164	unsigned long vaddr, struct vm_area_struct *vma)
	165	{
15fa3e8e	166	struct folio *src = page_folio(from);
bcd02280 AN	167	void vfrom, vto;
bcd02280 AN	168
9c02048f	169	vto = kmap_atomic(to);
9a74b3eb	170	if (cpu_has_dc_aliases &&
15fa3e8e	171	folio_mapped(src) && !folio_test_dcache_dirty(src)) {
bcd02280 AN	172	vfrom = kmap_coherent(from, vaddr);
bcd02280 AN	173	copy_page(vto, vfrom);
eacb9d61	174	kunmap_coherent();
bcd02280	175	} else {
9c02048f	176	vfrom = kmap_atomic(from);
bcd02280	177	copy_page(vto, vfrom);
9c02048f	178	kunmap_atomic(vfrom);
bcd02280	179	}
39b8d525	180	if ((!cpu_has_ic_fills_f_dc) \|\|
bcd02280 AN	181	pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
bcd02280 AN	182	flush_data_cache_page((unsigned long)vto);
9c02048f	183	kunmap_atomic(vto);
bcd02280 AN	184	/* Make sure this page is cleared on other CPU's too before using it */
	185	smp_wmb();
	186	}
	187
f8829cae RB	188	void copy_to_user_page(struct vm_area_struct *vma,
	189	struct page page, unsigned long vaddr, void dst, const void *src,
	190	unsigned long len)
	191	{
15fa3e8e MWO	192	struct folio *folio = page_folio(page);
15fa3e8e MWO	193
9a74b3eb	194	if (cpu_has_dc_aliases &&
15fa3e8e	195	folio_mapped(folio) && !folio_test_dcache_dirty(folio)) {
f8829cae RB	196	void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
f8829cae RB	197	memcpy(vto, src, len);
eacb9d61	198	kunmap_coherent();
985c30ef	199	} else {
f8829cae	200	memcpy(dst, src, len);
985c30ef	201	if (cpu_has_dc_aliases)
15fa3e8e	202	folio_set_dcache_dirty(folio);
985c30ef	203	}
b2a3c5be	204	if (vma->vm_flags & VM_EXEC)
f8829cae RB	205	flush_cache_page(vma, vaddr, page_to_pfn(page));
	206	}
	207
f8829cae RB	208	void copy_from_user_page(struct vm_area_struct *vma,
	209	struct page page, unsigned long vaddr, void dst, const void *src,
	210	unsigned long len)
	211	{
15fa3e8e MWO	212	struct folio *folio = page_folio(page);
15fa3e8e MWO	213
9a74b3eb	214	if (cpu_has_dc_aliases &&
15fa3e8e	215	folio_mapped(folio) && !folio_test_dcache_dirty(folio)) {
985c30ef	216	void *vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
f8829cae	217	memcpy(dst, vfrom, len);
eacb9d61	218	kunmap_coherent();
985c30ef	219	} else {
f8829cae	220	memcpy(dst, src, len);
985c30ef	221	if (cpu_has_dc_aliases)
15fa3e8e	222	folio_set_dcache_dirty(folio);
985c30ef	223	}
f8829cae	224	}
bf9621aa	225	EXPORT_SYMBOL_GPL(copy_from_user_page);
f8829cae	226
84fd089a	227	void __init fixrange_init(unsigned long start, unsigned long end,
1da177e4 LT	228	pgd_t *pgd_base)
1da177e4 LT	229	{
b633648c	230	#ifdef CONFIG_HIGHMEM
1da177e4	231	pgd_t *pgd;
c6e8b587	232	pud_t *pud;
1da177e4 LT	233	pmd_t *pmd;
1da177e4 LT	234	pte_t *pte;
c6e8b587	235	int i, j, k;
1da177e4 LT	236	unsigned long vaddr;
	237
	238	vaddr = start;
31168f03 MR	239	i = pgd_index(vaddr);
	240	j = pud_index(vaddr);
	241	k = pmd_index(vaddr);
1da177e4 LT	242	pgd = pgd_base + i;
1da177e4 LT	243
464fd83e	244	for ( ; (i < PTRS_PER_PGD) && (vaddr < end); pgd++, i++) {
c6e8b587	245	pud = (pud_t *)pgd;
464fd83e	246	for ( ; (j < PTRS_PER_PUD) && (vaddr < end); pud++, j++) {
c6e8b587	247	pmd = (pmd_t *)pud;
464fd83e	248	for (; (k < PTRS_PER_PMD) && (vaddr < end); pmd++, k++) {
c6e8b587	249	if (pmd_none(*pmd)) {
e8625dce MR	250	pte = (pte_t *) memblock_alloc_low(PAGE_SIZE,
e8625dce MR	251	PAGE_SIZE);
8a7f97b9 MR	252	if (!pte)
	253	panic("%s: Failed to allocate %lu bytes align=%lx\n",
	254	__func__, PAGE_SIZE,
	255	PAGE_SIZE);
	256
f8829cae	257	set_pmd(pmd, __pmd((unsigned long)pte));
b72b7092	258	BUG_ON(pte != pte_offset_kernel(pmd, 0));
c6e8b587 RB	259	}
c6e8b587 RB	260	vaddr += PMD_SIZE;
1da177e4	261	}
c6e8b587	262	k = 0;
1da177e4 LT	263	}
	264	j = 0;
	265	}
f8829cae	266	#endif
1da177e4	267	}
1da177e4	268
a5718fe8 JY	269	struct maar_walk_info {
	270	struct maar_config cfg[16];
	271	unsigned int num_cfg;
	272	};
	273
	274	static int maar_res_walk(unsigned long start_pfn, unsigned long nr_pages,
	275	void *data)
def3ab5d	276	{
a5718fe8 JY	277	struct maar_walk_info *wi = data;
	278	struct maar_config *cfg = &wi->cfg[wi->num_cfg];
	279	unsigned int maar_align;
def3ab5d	280
a5718fe8 JY	281	/* MAAR registers hold physical addresses right shifted by 4 bits */
a5718fe8 JY	282	maar_align = BIT(MIPS_MAAR_ADDR_SHIFT + 4);
def3ab5d	283
a5718fe8 JY	284	/* Fill in the MAAR config entry */
	285	cfg->lower = ALIGN(PFN_PHYS(start_pfn), maar_align);
	286	cfg->upper = ALIGN_DOWN(PFN_PHYS(start_pfn + nr_pages), maar_align) - 1;
	287	cfg->attrs = MIPS_MAAR_S;
def3ab5d	288
a5718fe8 JY	289	/* Ensure we don't overflow the cfg array */
	290	if (!WARN_ON(wi->num_cfg >= ARRAY_SIZE(wi->cfg)))
	291	wi->num_cfg++;
	292
	293	return 0;
	294	}
	295
	296
	297	unsigned __weak platform_maar_init(unsigned num_pairs)
	298	{
	299	unsigned int num_configured;
	300	struct maar_walk_info wi;
	301
	302	wi.num_cfg = 0;
	303	walk_system_ram_range(0, max_pfn, &wi, maar_res_walk);
def3ab5d	304
a5718fe8 JY	305	num_configured = maar_config(wi.cfg, wi.num_cfg, num_pairs);
	306	if (num_configured < wi.num_cfg)
	307	pr_warn("Not enough MAAR pairs (%u) for all memory regions (%u)\n",
	308	num_pairs, wi.num_cfg);
def3ab5d PB	309
	310	return num_configured;
	311	}
	312
e060f6ed	313	void maar_init(void)
def3ab5d PB	314	{
def3ab5d PB	315	unsigned num_maars, used, i;
651ca7f4	316	phys_addr_t lower, upper, attr;
e060f6ed PB	317	static struct {
	318	struct maar_config cfgs[3];
	319	unsigned used;
	320	} recorded = { { { 0 } }, 0 };
def3ab5d PB	321
	322	if (!cpu_has_maar)
	323	return;
	324
	325	/* Detect the number of MAARs */
	326	write_c0_maari(~0);
	327	back_to_back_c0_hazard();
	328	num_maars = read_c0_maari() + 1;
	329
	330	/* MAARs should be in pairs */
	331	WARN_ON(num_maars % 2);
	332
e060f6ed PB	333	/* Set MAARs using values we recorded already */
	334	if (recorded.used) {
	335	used = maar_config(recorded.cfgs, recorded.used, num_maars / 2);
	336	BUG_ON(used != recorded.used);
	337	} else {
	338	/* Configure the required MAARs */
	339	used = platform_maar_init(num_maars / 2);
	340	}
def3ab5d PB	341
	342	/* Disable any further MAARs */
	343	for (i = (used * 2); i < num_maars; i++) {
	344	write_c0_maari(i);
	345	back_to_back_c0_hazard();
	346	write_c0_maar(0);
	347	back_to_back_c0_hazard();
	348	}
651ca7f4	349
e060f6ed PB	350	if (recorded.used)
	351	return;
	352
651ca7f4 PB	353	pr_info("MAAR configuration:\n");
	354	for (i = 0; i < num_maars; i += 2) {
	355	write_c0_maari(i);
	356	back_to_back_c0_hazard();
	357	upper = read_c0_maar();
9ee195fd SS	358	#ifdef CONFIG_XPA
	359	upper \|= (phys_addr_t)readx_c0_maar() << MIPS_MAARX_ADDR_SHIFT;
	360	#endif
651ca7f4 PB	361
	362	write_c0_maari(i + 1);
	363	back_to_back_c0_hazard();
	364	lower = read_c0_maar();
9ee195fd SS	365	#ifdef CONFIG_XPA
	366	lower \|= (phys_addr_t)readx_c0_maar() << MIPS_MAARX_ADDR_SHIFT;
	367	#endif
651ca7f4 PB	368
	369	attr = lower & upper;
	370	lower = (lower & MIPS_MAAR_ADDR) << 4;
	371	upper = ((upper & MIPS_MAAR_ADDR) << 4) \| 0xffff;
	372
	373	pr_info(" [%d]: ", i / 2);
9ee195fd	374	if ((attr & MIPS_MAAR_V) != MIPS_MAAR_V) {
651ca7f4 PB	375	pr_cont("disabled\n");
	376	continue;
	377	}
	378
	379	pr_cont("%pa-%pa", &lower, &upper);
	380
	381	if (attr & MIPS_MAAR_S)
	382	pr_cont(" speculate");
	383
	384	pr_cont("\n");
e060f6ed PB	385
	386	/* Record the setup for use on secondary CPUs */
	387	if (used <= ARRAY_SIZE(recorded.cfgs)) {
	388	recorded.cfgs[recorded.used].lower = lower;
	389	recorded.cfgs[recorded.used].upper = upper;
	390	recorded.cfgs[recorded.used].attrs = attr;
	391	recorded.used++;
	392	}
651ca7f4	393	}
def3ab5d PB	394	}
def3ab5d PB	395
a9ee6cf5	396	#ifndef CONFIG_NUMA
1da177e4 LT	397	void __init paging_init(void)
1da177e4 LT	398	{
cce335ae	399	unsigned long max_zone_pfns[MAX_NR_ZONES];
1da177e4 LT	400
	401	pagetable_init();
	402
05502339	403	#ifdef CONFIG_ZONE_DMA
cce335ae	404	max_zone_pfns[ZONE_DMA] = MAX_DMA_PFN;
1da177e4	405	#endif
cce335ae RB	406	#ifdef CONFIG_ZONE_DMA32
	407	max_zone_pfns[ZONE_DMA32] = MAX_DMA32_PFN;
	408	#endif
	409	max_zone_pfns[ZONE_NORMAL] = max_low_pfn;
1da177e4	410	#ifdef CONFIG_HIGHMEM
cce335ae	411	max_zone_pfns[ZONE_HIGHMEM] = highend_pfn;
cbb8fc07	412
cce335ae	413	if (cpu_has_dc_aliases && max_low_pfn != highend_pfn) {
cbb8fc07	414	printk(KERN_WARNING "This processor doesn't support highmem."
cce335ae RB	415	" %ldk highmem ignored\n",
	416	(highend_pfn - max_low_pfn) << (PAGE_SHIFT - 10));
	417	max_zone_pfns[ZONE_HIGHMEM] = max_low_pfn;
cbb8fc07	418	}
1da177e4 LT	419	#endif
1da177e4 LT	420
9691a071	421	free_area_init(max_zone_pfns);
1da177e4 LT	422	}
1da177e4 LT	423
3d503753 DJ	424	#ifdef CONFIG_64BIT
	425	static struct kcore_list kcore_kseg0;
	426	#endif
	427
0d98484e	428	void __init arch_mm_preinit(void)
1132137e	429	{
05d013a0	430	/*
15fa3e8e	431	* When PFN_PTE_SHIFT is greater than PAGE_SHIFT we won't have enough PTE
05d013a0 PB	432	* bits to hold a full 32b physical address on MIPS32 systems.
05d013a0 PB	433	*/
15fa3e8e	434	BUILD_BUG_ON(IS_ENABLED(CONFIG_32BIT) && (PFN_PTE_SHIFT > PAGE_SHIFT));
05d013a0	435
ab9988a3	436	maar_init();
31605922	437	setup_zero_pages(); /* Setup zeroed pages. */
1da177e4	438
3d503753 DJ	439	#ifdef CONFIG_64BIT
	440	if ((unsigned long) &_text > (unsigned long) CKSEG0)
	441	/* The -4 is a hack so that user tools don't have to handle
	442	the overflow. */
c30bb2a2 KH	443	kclist_add(&kcore_kseg0, (void *) CKSEG0,
c30bb2a2 KH	444	0x80000000 - 4, KCORE_TEXT);
3d503753	445	#endif
1da177e4	446	}
67e7a600	447	#else /* CONFIG_NUMA */
0d98484e	448	void __init arch_mm_preinit(void)
67e7a600	449	{
67e7a600 MRM	450	setup_zero_pages(); /* This comes from node 0 */
67e7a600 MRM	451	}
a9ee6cf5	452	#endif /* !CONFIG_NUMA */
1da177e4	453
c44e8d5e	454	void free_init_pages(const char *what, unsigned long begin, unsigned long end)
6fd11a21	455	{
acd86b86	456	unsigned long pfn;
6fd11a21	457
acd86b86 FBH	458	for (pfn = PFN_UP(begin); pfn < PFN_DOWN(end); pfn++) {
	459	struct page *page = pfn_to_page(pfn);
	460	void *addr = phys_to_virt(PFN_PHYS(pfn));
	461
acd86b86	462	memset(addr, POISON_FREE_INITMEM, PAGE_SIZE);
31605922	463	free_reserved_page(page);
6fd11a21 RB	464	}
	465	printk(KERN_INFO "Freeing %s: %ldk freed\n", what, (end - begin) >> 10);
	466	}
	467
0893d3fb MC	468	void (free_init_pages_eva)(void begin, void *end) = NULL;
0893d3fb MC	469
a6e83ace TB	470	void __weak __init prom_free_prom_memory(void)
	471	{
	472	/* nothing to do */
	473	}
	474
bd721ea7	475	void __ref free_initmem(void)
1da177e4	476	{
c44e8d5e	477	prom_free_prom_memory();
0893d3fb MC	478	/*
	479	* Let the platform define a specific function to free the
	480	* init section since EVA may have used any possible mapping
	481	* between virtual and physical addresses.
	482	*/
	483	if (free_init_pages_eva)
	484	free_init_pages_eva((void )&__init_begin, (void )&__init_end);
	485	else
	486	free_initmem_default(POISON_FREE_INITMEM);
1da177e4	487	}
69a6c312	488
f3c560a6 TB	489	#ifdef CONFIG_HAVE_SETUP_PER_CPU_AREA
	490	unsigned long __per_cpu_offset[NR_CPUS] __read_mostly;
	491	EXPORT_SYMBOL(__per_cpu_offset);
	492
	493	static int __init pcpu_cpu_distance(unsigned int from, unsigned int to)
	494	{
	495	return node_distance(cpu_to_node(from), cpu_to_node(to));
	496	}
	497
1ca3fb3a KW	498	static int __init pcpu_cpu_to_node(int cpu)
	499	{
	500	return cpu_to_node(cpu);
	501	}
	502
f3c560a6 TB	503	void __init setup_per_cpu_areas(void)
	504	{
	505	unsigned long delta;
	506	unsigned int cpu;
	507	int rc;
	508
	509	/*
	510	* Always reserve area for module percpu variables. That's
	511	* what the legacy allocator did.
	512	*/
	513	rc = pcpu_embed_first_chunk(PERCPU_MODULE_RESERVE,
	514	PERCPU_DYNAMIC_RESERVE, PAGE_SIZE,
	515	pcpu_cpu_distance,
23f91716	516	pcpu_cpu_to_node);
f3c560a6 TB	517	if (rc < 0)
	518	panic("Failed to initialize percpu areas.");
	519
	520	delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
	521	for_each_possible_cpu(cpu)
	522	__per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu];
	523	}
	524	#endif
	525
82622284	526	#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
69a6c312	527	unsigned long pgd_current[NR_CPUS];
82622284	528	#endif
9975e77d RB	529
9975e77d RB	530	/*
485172b3 DD	531	* Align swapper_pg_dir in to 64K, allows its address to be loaded
	532	* with a single LUI instruction in the TLB handlers. If we used
	533	* __aligned(64K), its size would get rounded up to the alignment
	534	* size, and waste space. So we place it in its own section and align
	535	* it in the linker script.
9975e77d	536	*/
33def849	537	pgd_t swapper_pg_dir[PTRS_PER_PGD] __section(".bss..swapper_pg_dir");
3377e227 AB	538	#ifndef __PAGETABLE_PUD_FOLDED
	539	pud_t invalid_pud_table[PTRS_PER_PUD] __page_aligned_bss;
	540	#endif
325f8a0a	541	#ifndef __PAGETABLE_PMD_FOLDED
485172b3	542	pmd_t invalid_pmd_table[PTRS_PER_PMD] __page_aligned_bss;
ccf01516	543	EXPORT_SYMBOL_GPL(invalid_pmd_table);
69a6c312	544	#endif
485172b3	545	pte_t invalid_pte_table[PTRS_PER_PTE] __page_aligned_bss;
aa4089e6	546	EXPORT_SYMBOL(invalid_pte_table);
0cc2dc49 MRI	547
	548	#ifdef CONFIG_EXECMEM
	549	#ifdef MODULES_VADDR
	550	static struct execmem_info execmem_info __ro_after_init;
	551
	552	struct execmem_info __init *execmem_arch_setup(void)
	553	{
	554	execmem_info = (struct execmem_info){
	555	.ranges = {
	556	[EXECMEM_DEFAULT] = {
	557	.start = MODULES_VADDR,
	558	.end = MODULES_END,
	559	.pgprot = PAGE_KERNEL,
	560	.alignment = 1,
	561	},
	562	},
	563	};
	564
	565	return &execmem_info;
	566	}
	567	#endif
	568	#endif /* CONFIG_EXECMEM */