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1da177e4 | 1 | /* |
aa0980b8 MR |
2 | * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc. |
3 | * All rights reserved. | |
4 | * Authors: Carsten Langgaard <carstenl@mips.com> | |
5 | * Maciej W. Rozycki <macro@mips.com> | |
1da177e4 LT |
6 | * |
7 | * This program is free software; you can distribute it and/or modify it | |
8 | * under the terms of the GNU General Public License (Version 2) as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
14 | * for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along | |
17 | * with this program; if not, write to the Free Software Foundation, Inc., | |
18 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. | |
19 | * | |
20 | * PROM library initialisation code. | |
21 | */ | |
22 | #include <linux/config.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/string.h> | |
25 | #include <linux/kernel.h> | |
26 | ||
1da177e4 | 27 | #include <asm/bootinfo.h> |
aa0980b8 MR |
28 | #include <asm/gt64120.h> |
29 | #include <asm/io.h> | |
30 | #include <asm/system.h> | |
e01402b1 RB |
31 | #include <asm/cacheflush.h> |
32 | #include <asm/traps.h> | |
aa0980b8 | 33 | |
1da177e4 LT |
34 | #include <asm/mips-boards/prom.h> |
35 | #include <asm/mips-boards/generic.h> | |
1da177e4 | 36 | #include <asm/mips-boards/bonito64.h> |
aa0980b8 MR |
37 | #include <asm/mips-boards/msc01_pci.h> |
38 | ||
1da177e4 | 39 | #include <asm/mips-boards/malta.h> |
1da177e4 LT |
40 | |
41 | #ifdef CONFIG_KGDB | |
42 | extern int rs_kgdb_hook(int, int); | |
43 | extern int rs_putDebugChar(char); | |
44 | extern char rs_getDebugChar(void); | |
45 | extern int saa9730_kgdb_hook(int); | |
46 | extern int saa9730_putDebugChar(char); | |
47 | extern char saa9730_getDebugChar(void); | |
48 | #endif | |
49 | ||
50 | int prom_argc; | |
51 | int *_prom_argv, *_prom_envp; | |
52 | ||
53 | /* | |
54 | * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer. | |
55 | * This macro take care of sign extension, if running in 64-bit mode. | |
56 | */ | |
57 | #define prom_envp(index) ((char *)(long)_prom_envp[(index)]) | |
58 | ||
59 | int init_debug = 0; | |
60 | ||
61 | unsigned int mips_revision_corid; | |
62 | ||
63 | /* Bonito64 system controller register base. */ | |
64 | unsigned long _pcictrl_bonito; | |
65 | unsigned long _pcictrl_bonito_pcicfg; | |
66 | ||
67 | /* GT64120 system controller register base */ | |
68 | unsigned long _pcictrl_gt64120; | |
69 | ||
70 | /* MIPS System controller register base */ | |
71 | unsigned long _pcictrl_msc; | |
72 | ||
73 | char *prom_getenv(char *envname) | |
74 | { | |
75 | /* | |
76 | * Return a pointer to the given environment variable. | |
77 | * In 64-bit mode: we're using 64-bit pointers, but all pointers | |
78 | * in the PROM structures are only 32-bit, so we need some | |
79 | * workarounds, if we are running in 64-bit mode. | |
80 | */ | |
81 | int i, index=0; | |
82 | ||
83 | i = strlen(envname); | |
84 | ||
85 | while (prom_envp(index)) { | |
86 | if(strncmp(envname, prom_envp(index), i) == 0) { | |
87 | return(prom_envp(index+1)); | |
88 | } | |
89 | index += 2; | |
90 | } | |
91 | ||
92 | return NULL; | |
93 | } | |
94 | ||
95 | static inline unsigned char str2hexnum(unsigned char c) | |
96 | { | |
97 | if (c >= '0' && c <= '9') | |
98 | return c - '0'; | |
99 | if (c >= 'a' && c <= 'f') | |
100 | return c - 'a' + 10; | |
101 | return 0; /* foo */ | |
102 | } | |
103 | ||
104 | static inline void str2eaddr(unsigned char *ea, unsigned char *str) | |
105 | { | |
106 | int i; | |
107 | ||
108 | for (i = 0; i < 6; i++) { | |
109 | unsigned char num; | |
110 | ||
111 | if((*str == '.') || (*str == ':')) | |
112 | str++; | |
113 | num = str2hexnum(*str++) << 4; | |
114 | num |= (str2hexnum(*str++)); | |
115 | ea[i] = num; | |
116 | } | |
117 | } | |
118 | ||
119 | int get_ethernet_addr(char *ethernet_addr) | |
120 | { | |
121 | char *ethaddr_str; | |
122 | ||
123 | ethaddr_str = prom_getenv("ethaddr"); | |
124 | if (!ethaddr_str) { | |
125 | printk("ethaddr not set in boot prom\n"); | |
126 | return -1; | |
127 | } | |
128 | str2eaddr(ethernet_addr, ethaddr_str); | |
129 | ||
130 | if (init_debug > 1) { | |
131 | int i; | |
132 | printk("get_ethernet_addr: "); | |
133 | for (i=0; i<5; i++) | |
134 | printk("%02x:", (unsigned char)*(ethernet_addr+i)); | |
135 | printk("%02x\n", *(ethernet_addr+i)); | |
136 | } | |
137 | ||
138 | return 0; | |
139 | } | |
140 | ||
141 | #ifdef CONFIG_SERIAL_8250_CONSOLE | |
142 | static void __init console_config(void) | |
143 | { | |
144 | char console_string[40]; | |
145 | int baud = 0; | |
146 | char parity = '\0', bits = '\0', flow = '\0'; | |
147 | char *s; | |
148 | ||
149 | if ((strstr(prom_getcmdline(), "console=ttyS")) == NULL) { | |
150 | s = prom_getenv("modetty0"); | |
151 | if (s) { | |
152 | while (*s >= '0' && *s <= '9') | |
153 | baud = baud*10 + *s++ - '0'; | |
154 | if (*s == ',') s++; | |
155 | if (*s) parity = *s++; | |
156 | if (*s == ',') s++; | |
157 | if (*s) bits = *s++; | |
158 | if (*s == ',') s++; | |
159 | if (*s == 'h') flow = 'r'; | |
160 | } | |
161 | if (baud == 0) | |
162 | baud = 38400; | |
163 | if (parity != 'n' && parity != 'o' && parity != 'e') | |
164 | parity = 'n'; | |
165 | if (bits != '7' && bits != '8') | |
166 | bits = '8'; | |
167 | if (flow == '\0') | |
168 | flow = 'r'; | |
169 | sprintf (console_string, " console=ttyS0,%d%c%c%c", baud, parity, bits, flow); | |
170 | strcat (prom_getcmdline(), console_string); | |
171 | prom_printf("Config serial console:%s\n", console_string); | |
172 | } | |
173 | } | |
174 | #endif | |
175 | ||
176 | #ifdef CONFIG_KGDB | |
177 | void __init kgdb_config (void) | |
178 | { | |
179 | extern int (*generic_putDebugChar)(char); | |
180 | extern char (*generic_getDebugChar)(void); | |
181 | char *argptr; | |
182 | int line, speed; | |
183 | ||
184 | argptr = prom_getcmdline(); | |
185 | if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) { | |
186 | argptr += strlen("kgdb=ttyS"); | |
187 | if (*argptr != '0' && *argptr != '1') | |
188 | printk("KGDB: Unknown serial line /dev/ttyS%c, " | |
189 | "falling back to /dev/ttyS1\n", *argptr); | |
190 | line = *argptr == '0' ? 0 : 1; | |
191 | printk("KGDB: Using serial line /dev/ttyS%d for session\n", line); | |
192 | ||
193 | speed = 0; | |
194 | if (*++argptr == ',') | |
195 | { | |
196 | int c; | |
197 | while ((c = *++argptr) && ('0' <= c && c <= '9')) | |
198 | speed = speed * 10 + c - '0'; | |
199 | } | |
200 | #ifdef CONFIG_MIPS_ATLAS | |
201 | if (line == 1) { | |
202 | speed = saa9730_kgdb_hook(speed); | |
203 | generic_putDebugChar = saa9730_putDebugChar; | |
204 | generic_getDebugChar = saa9730_getDebugChar; | |
205 | } | |
42a3b4f2 | 206 | else |
1da177e4 LT |
207 | #endif |
208 | { | |
209 | speed = rs_kgdb_hook(line, speed); | |
210 | generic_putDebugChar = rs_putDebugChar; | |
211 | generic_getDebugChar = rs_getDebugChar; | |
212 | } | |
213 | ||
214 | prom_printf("KGDB: Using serial line /dev/ttyS%d at %d for session, " | |
215 | "please connect your debugger\n", line ? 1 : 0, speed); | |
216 | ||
217 | { | |
218 | char *s; | |
219 | for (s = "Please connect GDB to this port\r\n"; *s; ) | |
220 | generic_putDebugChar (*s++); | |
221 | } | |
222 | ||
223 | kgdb_enabled = 1; | |
224 | /* Breakpoint is invoked after interrupts are initialised */ | |
225 | } | |
226 | } | |
227 | #endif | |
228 | ||
e01402b1 RB |
229 | void __init mips_nmi_setup (void) |
230 | { | |
231 | void *base; | |
232 | extern char except_vec_nmi; | |
233 | ||
234 | base = cpu_has_veic ? | |
235 | (void *)(CAC_BASE + 0xa80) : | |
236 | (void *)(CAC_BASE + 0x380); | |
237 | memcpy(base, &except_vec_nmi, 0x80); | |
238 | flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); | |
239 | } | |
240 | ||
241 | void __init mips_ejtag_setup (void) | |
242 | { | |
243 | void *base; | |
244 | extern char except_vec_ejtag_debug; | |
245 | ||
246 | base = cpu_has_veic ? | |
247 | (void *)(CAC_BASE + 0xa00) : | |
248 | (void *)(CAC_BASE + 0x300); | |
249 | memcpy(base, &except_vec_ejtag_debug, 0x80); | |
250 | flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); | |
251 | } | |
252 | ||
1da177e4 LT |
253 | void __init prom_init(void) |
254 | { | |
aa0980b8 MR |
255 | u32 start, map, mask, data; |
256 | ||
1da177e4 LT |
257 | prom_argc = fw_arg0; |
258 | _prom_argv = (int *) fw_arg1; | |
259 | _prom_envp = (int *) fw_arg2; | |
260 | ||
261 | mips_display_message("LINUX"); | |
262 | ||
263 | #ifdef CONFIG_MIPS_SEAD | |
264 | set_io_port_base(KSEG1); | |
265 | #else | |
266 | /* | |
267 | * early setup of _pcictrl_bonito so that we can determine | |
268 | * the system controller on a CORE_EMUL board | |
269 | */ | |
270 | _pcictrl_bonito = (unsigned long)ioremap(BONITO_REG_BASE, BONITO_REG_SIZE); | |
271 | ||
272 | mips_revision_corid = MIPS_REVISION_CORID; | |
273 | ||
274 | if (mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL) { | |
42a3b4f2 | 275 | if (BONITO_PCIDID == 0x0001df53 || |
1da177e4 LT |
276 | BONITO_PCIDID == 0x0003df53) |
277 | mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_BON; | |
278 | else | |
279 | mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_MSC; | |
280 | } | |
281 | switch(mips_revision_corid) { | |
282 | case MIPS_REVISION_CORID_QED_RM5261: | |
283 | case MIPS_REVISION_CORID_CORE_LV: | |
284 | case MIPS_REVISION_CORID_CORE_FPGA: | |
285 | case MIPS_REVISION_CORID_CORE_FPGAR2: | |
286 | /* | |
287 | * Setup the North bridge to do Master byte-lane swapping | |
288 | * when running in bigendian. | |
289 | */ | |
290 | _pcictrl_gt64120 = (unsigned long)ioremap(MIPS_GT_BASE, 0x2000); | |
291 | ||
292 | #ifdef CONFIG_CPU_LITTLE_ENDIAN | |
293 | GT_WRITE(GT_PCI0_CMD_OFS, GT_PCI0_CMD_MBYTESWAP_BIT | | |
294 | GT_PCI0_CMD_SBYTESWAP_BIT); | |
295 | #else | |
296 | GT_WRITE(GT_PCI0_CMD_OFS, 0); | |
297 | #endif | |
aa0980b8 MR |
298 | /* Fix up PCI I/O mapping if necessary (for Atlas). */ |
299 | start = GT_READ(GT_PCI0IOLD_OFS); | |
300 | map = GT_READ(GT_PCI0IOREMAP_OFS); | |
301 | if ((start & map) != 0) { | |
302 | map &= ~start; | |
303 | GT_WRITE(GT_PCI0IOREMAP_OFS, map); | |
304 | } | |
1da177e4 | 305 | |
1da177e4 | 306 | set_io_port_base(MALTA_GT_PORT_BASE); |
1da177e4 LT |
307 | break; |
308 | ||
309 | case MIPS_REVISION_CORID_CORE_EMUL_BON: | |
310 | case MIPS_REVISION_CORID_BONITO64: | |
311 | case MIPS_REVISION_CORID_CORE_20K: | |
312 | _pcictrl_bonito_pcicfg = (unsigned long)ioremap(BONITO_PCICFG_BASE, BONITO_PCICFG_SIZE); | |
313 | ||
314 | /* | |
315 | * Disable Bonito IOBC. | |
316 | */ | |
317 | BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & | |
318 | ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | | |
319 | BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); | |
320 | ||
321 | /* | |
322 | * Setup the North bridge to do Master byte-lane swapping | |
323 | * when running in bigendian. | |
324 | */ | |
325 | #ifdef CONFIG_CPU_LITTLE_ENDIAN | |
326 | BONITO_BONGENCFG = BONITO_BONGENCFG & | |
327 | ~(BONITO_BONGENCFG_MSTRBYTESWAP | | |
328 | BONITO_BONGENCFG_BYTESWAP); | |
329 | #else | |
330 | BONITO_BONGENCFG = BONITO_BONGENCFG | | |
331 | BONITO_BONGENCFG_MSTRBYTESWAP | | |
332 | BONITO_BONGENCFG_BYTESWAP; | |
333 | #endif | |
334 | ||
1da177e4 | 335 | set_io_port_base(MALTA_BONITO_PORT_BASE); |
1da177e4 LT |
336 | break; |
337 | ||
338 | case MIPS_REVISION_CORID_CORE_MSC: | |
339 | case MIPS_REVISION_CORID_CORE_FPGA2: | |
340 | case MIPS_REVISION_CORID_CORE_EMUL_MSC: | |
42a3b4f2 | 341 | _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000); |
1da177e4 | 342 | |
aa0980b8 MR |
343 | mb(); |
344 | MSC_READ(MSC01_PCI_CFG, data); | |
345 | MSC_WRITE(MSC01_PCI_CFG, data & ~MSC01_PCI_CFG_EN_BIT); | |
346 | wmb(); | |
347 | ||
348 | /* Fix up lane swapping. */ | |
1da177e4 LT |
349 | #ifdef CONFIG_CPU_LITTLE_ENDIAN |
350 | MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP); | |
351 | #else | |
352 | MSC_WRITE(MSC01_PCI_SWAP, | |
353 | MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_IO_SHF | | |
354 | MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF | | |
355 | MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF); | |
356 | #endif | |
aa0980b8 MR |
357 | /* Fix up target memory mapping. */ |
358 | MSC_READ(MSC01_PCI_BAR0, mask); | |
359 | MSC_WRITE(MSC01_PCI_P2SCMSKL, mask & MSC01_PCI_BAR0_SIZE_MSK); | |
360 | ||
361 | /* Don't handle target retries indefinitely. */ | |
362 | if ((data & MSC01_PCI_CFG_MAXRTRY_MSK) == | |
363 | MSC01_PCI_CFG_MAXRTRY_MSK) | |
364 | data = (data & ~(MSC01_PCI_CFG_MAXRTRY_MSK << | |
365 | MSC01_PCI_CFG_MAXRTRY_SHF)) | | |
366 | ((MSC01_PCI_CFG_MAXRTRY_MSK - 1) << | |
367 | MSC01_PCI_CFG_MAXRTRY_SHF); | |
368 | ||
369 | wmb(); | |
370 | MSC_WRITE(MSC01_PCI_CFG, data); | |
371 | mb(); | |
1da177e4 | 372 | |
1da177e4 | 373 | set_io_port_base(MALTA_MSC_PORT_BASE); |
1da177e4 LT |
374 | break; |
375 | ||
376 | default: | |
377 | /* Unknown Core card */ | |
378 | mips_display_message("CC Error"); | |
379 | while(1); /* We die here... */ | |
380 | } | |
381 | #endif | |
e01402b1 RB |
382 | board_nmi_handler_setup = mips_nmi_setup; |
383 | board_ejtag_handler_setup = mips_ejtag_setup; | |
384 | ||
1da177e4 LT |
385 | prom_printf("\nLINUX started...\n"); |
386 | prom_init_cmdline(); | |
387 | prom_meminit(); | |
388 | #ifdef CONFIG_SERIAL_8250_CONSOLE | |
389 | console_config(); | |
390 | #endif | |
391 | } |