[linux-block.git] / arch / mips / mips-boards / generic / init.c

/*
 * Copyright (C) 1999, 2000, 2004, 2005  MIPS Technologies, Inc.
 *	All rights reserved.
 *	Authors: Carsten Langgaard <carstenl@mips.com>
 *		 Maciej W. Rozycki <macro@mips.com>
 *
 *  This program is free software; you can distribute it and/or modify it
 *  under the terms of the GNU General Public License (Version 2) as
 *  published by the Free Software Foundation.
 *
 *  This program is distributed in the hope it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 *  for more details.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 *
 * PROM library initialisation code.
 */
#include <linux/init.h>
#include <linux/string.h>
#include <linux/kernel.h>

#include <asm/bootinfo.h>
#include <asm/gt64120.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/cacheflush.h>
#include <asm/traps.h>

#include <asm/mips-boards/prom.h>
#include <asm/mips-boards/generic.h>
#include <asm/mips-boards/bonito64.h>
#include <asm/mips-boards/msc01_pci.h>

#include <asm/mips-boards/malta.h>

#ifdef CONFIG_KGDB
extern int rs_kgdb_hook(int, int);
extern int rs_putDebugChar(char);
extern char rs_getDebugChar(void);
extern int saa9730_kgdb_hook(int);
extern int saa9730_putDebugChar(char);
extern char saa9730_getDebugChar(void);
#endif

int prom_argc;
int *_prom_argv, *_prom_envp;

/*
 * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer.
 * This macro take care of sign extension, if running in 64-bit mode.
 */
#define prom_envp(index) ((char *)(long)_prom_envp[(index)])

int init_debug = 0;

unsigned int mips_revision_corid;

/* Bonito64 system controller register base. */
unsigned long _pcictrl_bonito;
unsigned long _pcictrl_bonito_pcicfg;

/* GT64120 system controller register base */
unsigned long _pcictrl_gt64120;

/* MIPS System controller register base */
unsigned long _pcictrl_msc;

char *prom_getenv(char *envname)
{
	/*
	 * Return a pointer to the given environment variable.
	 * In 64-bit mode: we're using 64-bit pointers, but all pointers
	 * in the PROM structures are only 32-bit, so we need some
	 * workarounds, if we are running in 64-bit mode.
	 */
	int i, index=0;

	i = strlen(envname);

	while (prom_envp(index)) {
		if(strncmp(envname, prom_envp(index), i) == 0) {
			return(prom_envp(index+1));
		}
		index += 2;
	}

	return NULL;
}

static inline unsigned char str2hexnum(unsigned char c)
{
	if (c >= '0' && c <= '9')
		return c - '0';
	if (c >= 'a' && c <= 'f')
		return c - 'a' + 10;
	return 0; /* foo */
}

static inline void str2eaddr(unsigned char *ea, unsigned char *str)
{
	int i;

	for (i = 0; i < 6; i++) {
		unsigned char num;

		if((*str == '.') || (*str == ':'))
			str++;
		num = str2hexnum(*str++) << 4;
		num |= (str2hexnum(*str++));
		ea[i] = num;
	}
}

int get_ethernet_addr(char *ethernet_addr)
{
        char *ethaddr_str;

        ethaddr_str = prom_getenv("ethaddr");
	if (!ethaddr_str) {
	        printk("ethaddr not set in boot prom\n");
		return -1;
	}
	str2eaddr(ethernet_addr, ethaddr_str);

	if (init_debug > 1) {
	        int i;
		printk("get_ethernet_addr: ");
	        for (i=0; i<5; i++)
		        printk("%02x:", (unsigned char)*(ethernet_addr+i));
		printk("%02x\n", *(ethernet_addr+i));
	}

	return 0;
}

#ifdef CONFIG_SERIAL_8250_CONSOLE
static void __init console_config(void)
{
	char console_string[40];
	int baud = 0;
	char parity = '\0', bits = '\0', flow = '\0';
	char *s;

	if ((strstr(prom_getcmdline(), "console=ttyS")) == NULL) {
		s = prom_getenv("modetty0");
		if (s) {
			while (*s >= '0' && *s <= '9')
				baud = baud*10 + *s++ - '0';
			if (*s == ',') s++;
			if (*s) parity = *s++;
			if (*s == ',') s++;
			if (*s) bits = *s++;
			if (*s == ',') s++;
			if (*s == 'h') flow = 'r';
		}
		if (baud == 0)
			baud = 38400;
		if (parity != 'n' && parity != 'o' && parity != 'e')
			parity = 'n';
		if (bits != '7' && bits != '8')
			bits = '8';
		if (flow == '\0')
			flow = 'r';
		sprintf (console_string, " console=ttyS0,%d%c%c%c", baud, parity, bits, flow);
		strcat (prom_getcmdline(), console_string);
		prom_printf("Config serial console:%s\n", console_string);
	}
}
#endif

#ifdef CONFIG_KGDB
void __init kgdb_config (void)
{
	extern int (*generic_putDebugChar)(char);
	extern char (*generic_getDebugChar)(void);
	char *argptr;
	int line, speed;

	argptr = prom_getcmdline();
	if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) {
		argptr += strlen("kgdb=ttyS");
		if (*argptr != '0' && *argptr != '1')
			printk("KGDB: Unknown serial line /dev/ttyS%c, "
			       "falling back to /dev/ttyS1\n", *argptr);
		line = *argptr == '0' ? 0 : 1;
		printk("KGDB: Using serial line /dev/ttyS%d for session\n", line);

		speed = 0;
		if (*++argptr == ',')
		{
			int c;
			while ((c = *++argptr) && ('0' <= c && c <= '9'))
				speed = speed * 10 + c - '0';
		}
#ifdef CONFIG_MIPS_ATLAS
		if (line == 1) {
			speed = saa9730_kgdb_hook(speed);
			generic_putDebugChar = saa9730_putDebugChar;
			generic_getDebugChar = saa9730_getDebugChar;
		}
		else
#endif
		{
			speed = rs_kgdb_hook(line, speed);
			generic_putDebugChar = rs_putDebugChar;
			generic_getDebugChar = rs_getDebugChar;
		}

		prom_printf("KGDB: Using serial line /dev/ttyS%d at %d for session, "
			    "please connect your debugger\n", line ? 1 : 0, speed);

		{
			char *s;
			for (s = "Please connect GDB to this port\r\n"; *s; )
				generic_putDebugChar (*s++);
		}

		/* Breakpoint is invoked after interrupts are initialised */
	}
}
#endif

void __init mips_nmi_setup (void)
{
	void *base;
	extern char except_vec_nmi;

	base = cpu_has_veic ?
		(void *)(CAC_BASE + 0xa80) :
		(void *)(CAC_BASE + 0x380);
	memcpy(base, &except_vec_nmi, 0x80);
	flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
}

void __init mips_ejtag_setup (void)
{
	void *base;
	extern char except_vec_ejtag_debug;

	base = cpu_has_veic ?
		(void *)(CAC_BASE + 0xa00) :
		(void *)(CAC_BASE + 0x300);
	memcpy(base, &except_vec_ejtag_debug, 0x80);
	flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
}

void __init prom_init(void)
{
	u32 start, map, mask, data;

	prom_argc = fw_arg0;
	_prom_argv = (int *) fw_arg1;
	_prom_envp = (int *) fw_arg2;

	mips_display_message("LINUX");

#ifdef CONFIG_MIPS_SEAD
	set_io_port_base(KSEG1);
#else
	/*
	 * early setup of _pcictrl_bonito so that we can determine
	 * the system controller on a CORE_EMUL board
	 */
	_pcictrl_bonito = (unsigned long)ioremap(BONITO_REG_BASE, BONITO_REG_SIZE);

	mips_revision_corid = MIPS_REVISION_CORID;

	if (mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL) {
		if (BONITO_PCIDID == 0x0001df53 ||
		    BONITO_PCIDID == 0x0003df53)
			mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_BON;
		else
			mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_MSC;
	}
	switch(mips_revision_corid) {
	case MIPS_REVISION_CORID_QED_RM5261:
	case MIPS_REVISION_CORID_CORE_LV:
	case MIPS_REVISION_CORID_CORE_FPGA:
	case MIPS_REVISION_CORID_CORE_FPGAR2:
		/*
		 * Setup the North bridge to do Master byte-lane swapping
		 * when running in bigendian.
		 */
		_pcictrl_gt64120 = (unsigned long)ioremap(MIPS_GT_BASE, 0x2000);

#ifdef CONFIG_CPU_LITTLE_ENDIAN
		GT_WRITE(GT_PCI0_CMD_OFS, GT_PCI0_CMD_MBYTESWAP_BIT |
			 GT_PCI0_CMD_SBYTESWAP_BIT);
#else
		GT_WRITE(GT_PCI0_CMD_OFS, 0);
#endif
		/* Fix up PCI I/O mapping if necessary (for Atlas).  */
		start = GT_READ(GT_PCI0IOLD_OFS);
		map = GT_READ(GT_PCI0IOREMAP_OFS);
		if ((start & map) != 0) {
			map &= ~start;
			GT_WRITE(GT_PCI0IOREMAP_OFS, map);
		}

		set_io_port_base(MALTA_GT_PORT_BASE);
		break;

	case MIPS_REVISION_CORID_CORE_EMUL_BON:
	case MIPS_REVISION_CORID_BONITO64:
	case MIPS_REVISION_CORID_CORE_20K:
		_pcictrl_bonito_pcicfg = (unsigned long)ioremap(BONITO_PCICFG_BASE, BONITO_PCICFG_SIZE);

		/*
		 * Disable Bonito IOBC.
		 */
		BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
			~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
			  BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);

		/*
		 * Setup the North bridge to do Master byte-lane swapping
		 * when running in bigendian.
		 */
#ifdef CONFIG_CPU_LITTLE_ENDIAN
		BONITO_BONGENCFG = BONITO_BONGENCFG &
			~(BONITO_BONGENCFG_MSTRBYTESWAP |
			  BONITO_BONGENCFG_BYTESWAP);
#else
		BONITO_BONGENCFG = BONITO_BONGENCFG |
			BONITO_BONGENCFG_MSTRBYTESWAP |
			BONITO_BONGENCFG_BYTESWAP;
#endif

		set_io_port_base(MALTA_BONITO_PORT_BASE);
		break;

	case MIPS_REVISION_CORID_CORE_MSC:
	case MIPS_REVISION_CORID_CORE_FPGA2:
	case MIPS_REVISION_CORID_CORE_FPGA3:
	case MIPS_REVISION_CORID_CORE_24K:
	case MIPS_REVISION_CORID_CORE_EMUL_MSC:
		_pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000);

		mb();
		MSC_READ(MSC01_PCI_CFG, data);
		MSC_WRITE(MSC01_PCI_CFG, data & ~MSC01_PCI_CFG_EN_BIT);
		wmb();

		/* Fix up lane swapping.  */
#ifdef CONFIG_CPU_LITTLE_ENDIAN
		MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP);
#else
		MSC_WRITE(MSC01_PCI_SWAP,
			  MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_IO_SHF |
			  MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF |
			  MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF);
#endif
		/* Fix up target memory mapping.  */
		MSC_READ(MSC01_PCI_BAR0, mask);
		MSC_WRITE(MSC01_PCI_P2SCMSKL, mask & MSC01_PCI_BAR0_SIZE_MSK);

		/* Don't handle target retries indefinitely.  */
		if ((data & MSC01_PCI_CFG_MAXRTRY_MSK) ==
		    MSC01_PCI_CFG_MAXRTRY_MSK)
			data = (data & ~(MSC01_PCI_CFG_MAXRTRY_MSK <<
					 MSC01_PCI_CFG_MAXRTRY_SHF)) |
			       ((MSC01_PCI_CFG_MAXRTRY_MSK - 1) <<
				MSC01_PCI_CFG_MAXRTRY_SHF);

		wmb();
		MSC_WRITE(MSC01_PCI_CFG, data);
		mb();

		set_io_port_base(MALTA_MSC_PORT_BASE);
		break;

	default:
		/* Unknown Core card */
		mips_display_message("CC Error");
		while(1);   /* We die here... */
	}
#endif
	board_nmi_handler_setup = mips_nmi_setup;
	board_ejtag_handler_setup = mips_ejtag_setup;

	prom_printf("\nLINUX started...\n");
	prom_init_cmdline();
	prom_meminit();
#ifdef CONFIG_SERIAL_8250_CONSOLE
	console_config();
#endif
}
Commit	Line	Data
1da177e4	1	/*
aa0980b8 MR	2	* Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc.
	3	* All rights reserved.
	4	* Authors: Carsten Langgaard <carstenl@mips.com>
	5	* Maciej W. Rozycki <macro@mips.com>
1da177e4 LT	6	*
	7	* This program is free software; you can distribute it and/or modify it
	8	* under the terms of the GNU General Public License (Version 2) as
	9	* published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope it will be useful, but WITHOUT
	12	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	13	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	14	* for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License along
	17	* with this program; if not, write to the Free Software Foundation, Inc.,
	18	* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
	19	*
	20	* PROM library initialisation code.
	21	*/
1da177e4 LT	22	#include <linux/init.h>
	23	#include <linux/string.h>
	24	#include <linux/kernel.h>
	25
1da177e4	26	#include <asm/bootinfo.h>
aa0980b8 MR	27	#include <asm/gt64120.h>
	28	#include <asm/io.h>
	29	#include <asm/system.h>
e01402b1 RB	30	#include <asm/cacheflush.h>
e01402b1 RB	31	#include <asm/traps.h>
aa0980b8	32
1da177e4 LT	33	#include <asm/mips-boards/prom.h>
1da177e4 LT	34	#include <asm/mips-boards/generic.h>
1da177e4	35	#include <asm/mips-boards/bonito64.h>
aa0980b8 MR	36	#include <asm/mips-boards/msc01_pci.h>
aa0980b8 MR	37
1da177e4	38	#include <asm/mips-boards/malta.h>
1da177e4 LT	39
	40	#ifdef CONFIG_KGDB
	41	extern int rs_kgdb_hook(int, int);
	42	extern int rs_putDebugChar(char);
	43	extern char rs_getDebugChar(void);
	44	extern int saa9730_kgdb_hook(int);
	45	extern int saa9730_putDebugChar(char);
	46	extern char saa9730_getDebugChar(void);
	47	#endif
	48
	49	int prom_argc;
	50	int _prom_argv, _prom_envp;
	51
	52	/*
	53	* YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer.
	54	* This macro take care of sign extension, if running in 64-bit mode.
	55	*/
	56	#define prom_envp(index) ((char *)(long)_prom_envp[(index)])
	57
	58	int init_debug = 0;
	59
	60	unsigned int mips_revision_corid;
	61
	62	/* Bonito64 system controller register base. */
	63	unsigned long _pcictrl_bonito;
	64	unsigned long _pcictrl_bonito_pcicfg;
	65
	66	/* GT64120 system controller register base */
	67	unsigned long _pcictrl_gt64120;
	68
	69	/* MIPS System controller register base */
	70	unsigned long _pcictrl_msc;
	71
	72	char prom_getenv(char envname)
	73	{
	74	/*
	75	* Return a pointer to the given environment variable.
	76	* In 64-bit mode: we're using 64-bit pointers, but all pointers
	77	* in the PROM structures are only 32-bit, so we need some
	78	* workarounds, if we are running in 64-bit mode.
	79	*/
	80	int i, index=0;
	81
	82	i = strlen(envname);
	83
	84	while (prom_envp(index)) {
	85	if(strncmp(envname, prom_envp(index), i) == 0) {
	86	return(prom_envp(index+1));
	87	}
	88	index += 2;
	89	}
	90
	91	return NULL;
	92	}
	93
	94	static inline unsigned char str2hexnum(unsigned char c)
	95	{
	96	if (c >= '0' && c <= '9')
	97	return c - '0';
	98	if (c >= 'a' && c <= 'f')
	99	return c - 'a' + 10;
	100	return 0; /* foo */
	101	}
	102
103	static inline void str2eaddr(unsigned char ea, unsigned char str)
104	{
105	int i;
106
107	for (i = 0; i < 6; i++) {
108	unsigned char num;
109
110	if((str == '.') \|\| (str == ':'))
111	str++;
112	num = str2hexnum(*str++) << 4;
113	num \|= (str2hexnum(*str++));
114	ea[i] = num;
115	}
116	}
117
118	int get_ethernet_addr(char *ethernet_addr)
119	{
120	char *ethaddr_str;
121
122	ethaddr_str = prom_getenv("ethaddr");
123	if (!ethaddr_str) {
124	printk("ethaddr not set in boot prom\n");
125	return -1;
126	}
127	str2eaddr(ethernet_addr, ethaddr_str);
128
129	if (init_debug > 1) {
130	int i;
131	printk("get_ethernet_addr: ");
132	for (i=0; i<5; i++)
133	printk("%02x:", (unsigned char)*(ethernet_addr+i));
134	printk("%02x\n", *(ethernet_addr+i));
135	}
136
137	return 0;
138	}
139
140	#ifdef CONFIG_SERIAL_8250_CONSOLE
141	static void __init console_config(void)
142	{
143	char console_string[40];
144	int baud = 0;
145	char parity = '\0', bits = '\0', flow = '\0';
146	char *s;
147
148	if ((strstr(prom_getcmdline(), "console=ttyS")) == NULL) {
149	s = prom_getenv("modetty0");
150	if (s) {
151	while (s >= '0' && s <= '9')
152	baud = baud10 + s++ - '0';
153	if (*s == ',') s++;
154	if (s) parity = s++;
155	if (*s == ',') s++;
156	if (s) bits = s++;
157	if (*s == ',') s++;
158	if (*s == 'h') flow = 'r';
159	}
160	if (baud == 0)
161	baud = 38400;
162	if (parity != 'n' && parity != 'o' && parity != 'e')
163	parity = 'n';
164	if (bits != '7' && bits != '8')
165	bits = '8';
166	if (flow == '\0')
167	flow = 'r';
168	sprintf (console_string, " console=ttyS0,%d%c%c%c", baud, parity, bits, flow);
169	strcat (prom_getcmdline(), console_string);
170	prom_printf("Config serial console:%s\n", console_string);
171	}
172	}
173	#endif
174
175	#ifdef CONFIG_KGDB
176	void __init kgdb_config (void)
177	{
178	extern int (*generic_putDebugChar)(char);
179	extern char (*generic_getDebugChar)(void);
180	char *argptr;
181	int line, speed;
182
183	argptr = prom_getcmdline();
184	if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) {
185	argptr += strlen("kgdb=ttyS");
186	if (argptr != '0' && argptr != '1')
187	printk("KGDB: Unknown serial line /dev/ttyS%c, "
188	"falling back to /dev/ttyS1\n", *argptr);
189	line = *argptr == '0' ? 0 : 1;
190	printk("KGDB: Using serial line /dev/ttyS%d for session\n", line);
191
192	speed = 0;
193	if (*++argptr == ',')
194	{
195	int c;
196	while ((c = *++argptr) && ('0' <= c && c <= '9'))
197	speed = speed * 10 + c - '0';
198	}
199	#ifdef CONFIG_MIPS_ATLAS
200	if (line == 1) {
201	speed = saa9730_kgdb_hook(speed);
202	generic_putDebugChar = saa9730_putDebugChar;
203	generic_getDebugChar = saa9730_getDebugChar;
204	}
42a3b4f2	205	else
1da177e4 LT	206	#endif
	207	{
	208	speed = rs_kgdb_hook(line, speed);
	209	generic_putDebugChar = rs_putDebugChar;
	210	generic_getDebugChar = rs_getDebugChar;
	211	}
	212
	213	prom_printf("KGDB: Using serial line /dev/ttyS%d at %d for session, "
	214	"please connect your debugger\n", line ? 1 : 0, speed);
	215
	216	{
	217	char *s;
	218	for (s = "Please connect GDB to this port\r\n"; *s; )
	219	generic_putDebugChar (*s++);
	220	}
	221
1da177e4 LT	222	/* Breakpoint is invoked after interrupts are initialised */
	223	}
	224	}
	225	#endif
	226
e01402b1 RB	227	void __init mips_nmi_setup (void)
	228	{
	229	void *base;
	230	extern char except_vec_nmi;
	231
	232	base = cpu_has_veic ?
	233	(void *)(CAC_BASE + 0xa80) :
	234	(void *)(CAC_BASE + 0x380);
	235	memcpy(base, &except_vec_nmi, 0x80);
	236	flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
	237	}
	238
	239	void __init mips_ejtag_setup (void)
	240	{
	241	void *base;
	242	extern char except_vec_ejtag_debug;
	243
	244	base = cpu_has_veic ?
	245	(void *)(CAC_BASE + 0xa00) :
	246	(void *)(CAC_BASE + 0x300);
	247	memcpy(base, &except_vec_ejtag_debug, 0x80);
	248	flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
	249	}
	250
1da177e4 LT	251	void __init prom_init(void)
1da177e4 LT	252	{
aa0980b8 MR	253	u32 start, map, mask, data;
aa0980b8 MR	254
1da177e4 LT	255	prom_argc = fw_arg0;
	256	_prom_argv = (int *) fw_arg1;
	257	_prom_envp = (int *) fw_arg2;
	258
	259	mips_display_message("LINUX");
	260
	261	#ifdef CONFIG_MIPS_SEAD
	262	set_io_port_base(KSEG1);
	263	#else
	264	/*
	265	* early setup of _pcictrl_bonito so that we can determine
	266	* the system controller on a CORE_EMUL board
	267	*/
	268	_pcictrl_bonito = (unsigned long)ioremap(BONITO_REG_BASE, BONITO_REG_SIZE);
	269
	270	mips_revision_corid = MIPS_REVISION_CORID;
	271
	272	if (mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL) {
42a3b4f2	273	if (BONITO_PCIDID == 0x0001df53 \|\|
1da177e4 LT	274	BONITO_PCIDID == 0x0003df53)
	275	mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_BON;
	276	else
	277	mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_MSC;
	278	}
	279	switch(mips_revision_corid) {
	280	case MIPS_REVISION_CORID_QED_RM5261:
	281	case MIPS_REVISION_CORID_CORE_LV:
	282	case MIPS_REVISION_CORID_CORE_FPGA:
	283	case MIPS_REVISION_CORID_CORE_FPGAR2:
	284	/*
	285	* Setup the North bridge to do Master byte-lane swapping
	286	* when running in bigendian.
	287	*/
	288	_pcictrl_gt64120 = (unsigned long)ioremap(MIPS_GT_BASE, 0x2000);
	289
	290	#ifdef CONFIG_CPU_LITTLE_ENDIAN
	291	GT_WRITE(GT_PCI0_CMD_OFS, GT_PCI0_CMD_MBYTESWAP_BIT \|
	292	GT_PCI0_CMD_SBYTESWAP_BIT);
	293	#else
	294	GT_WRITE(GT_PCI0_CMD_OFS, 0);
	295	#endif
aa0980b8 MR	296	/* Fix up PCI I/O mapping if necessary (for Atlas). */
	297	start = GT_READ(GT_PCI0IOLD_OFS);
	298	map = GT_READ(GT_PCI0IOREMAP_OFS);
	299	if ((start & map) != 0) {
	300	map &= ~start;
	301	GT_WRITE(GT_PCI0IOREMAP_OFS, map);
	302	}
1da177e4	303
1da177e4	304	set_io_port_base(MALTA_GT_PORT_BASE);
1da177e4 LT	305	break;
	306
	307	case MIPS_REVISION_CORID_CORE_EMUL_BON:
	308	case MIPS_REVISION_CORID_BONITO64:
	309	case MIPS_REVISION_CORID_CORE_20K:
	310	_pcictrl_bonito_pcicfg = (unsigned long)ioremap(BONITO_PCICFG_BASE, BONITO_PCICFG_SIZE);
	311
	312	/*
	313	* Disable Bonito IOBC.
	314	*/
	315	BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
	316	~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED \|
	317	BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
	318
	319	/*
	320	* Setup the North bridge to do Master byte-lane swapping
	321	* when running in bigendian.
	322	*/
	323	#ifdef CONFIG_CPU_LITTLE_ENDIAN
	324	BONITO_BONGENCFG = BONITO_BONGENCFG &
	325	~(BONITO_BONGENCFG_MSTRBYTESWAP \|
	326	BONITO_BONGENCFG_BYTESWAP);
	327	#else
	328	BONITO_BONGENCFG = BONITO_BONGENCFG \|
	329	BONITO_BONGENCFG_MSTRBYTESWAP \|
	330	BONITO_BONGENCFG_BYTESWAP;
	331	#endif
	332
1da177e4	333	set_io_port_base(MALTA_BONITO_PORT_BASE);
1da177e4 LT	334	break;
	335
	336	case MIPS_REVISION_CORID_CORE_MSC:
	337	case MIPS_REVISION_CORID_CORE_FPGA2:
479a0e3e	338	case MIPS_REVISION_CORID_CORE_FPGA3:
7a834196	339	case MIPS_REVISION_CORID_CORE_24K:
1da177e4	340	case MIPS_REVISION_CORID_CORE_EMUL_MSC:
42a3b4f2	341	_pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000);
1da177e4	342
aa0980b8 MR	343	mb();
	344	MSC_READ(MSC01_PCI_CFG, data);
	345	MSC_WRITE(MSC01_PCI_CFG, data & ~MSC01_PCI_CFG_EN_BIT);
	346	wmb();
	347
	348	/* Fix up lane swapping. */
1da177e4 LT	349	#ifdef CONFIG_CPU_LITTLE_ENDIAN
	350	MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP);
	351	#else
	352	MSC_WRITE(MSC01_PCI_SWAP,
	353	MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_IO_SHF \|
	354	MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF \|
	355	MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF);
	356	#endif
aa0980b8 MR	357	/* Fix up target memory mapping. */
	358	MSC_READ(MSC01_PCI_BAR0, mask);
	359	MSC_WRITE(MSC01_PCI_P2SCMSKL, mask & MSC01_PCI_BAR0_SIZE_MSK);
	360
	361	/* Don't handle target retries indefinitely. */
	362	if ((data & MSC01_PCI_CFG_MAXRTRY_MSK) ==
	363	MSC01_PCI_CFG_MAXRTRY_MSK)
	364	data = (data & ~(MSC01_PCI_CFG_MAXRTRY_MSK <<
	365	MSC01_PCI_CFG_MAXRTRY_SHF)) \|
	366	((MSC01_PCI_CFG_MAXRTRY_MSK - 1) <<
	367	MSC01_PCI_CFG_MAXRTRY_SHF);
	368
	369	wmb();
	370	MSC_WRITE(MSC01_PCI_CFG, data);
	371	mb();
1da177e4	372
1da177e4	373	set_io_port_base(MALTA_MSC_PORT_BASE);
1da177e4 LT	374	break;
	375
	376	default:
	377	/* Unknown Core card */
	378	mips_display_message("CC Error");
	379	while(1); /* We die here... */
	380	}
	381	#endif
e01402b1 RB	382	board_nmi_handler_setup = mips_nmi_setup;
	383	board_ejtag_handler_setup = mips_ejtag_setup;
	384
1da177e4 LT	385	prom_printf("\nLINUX started...\n");
	386	prom_init_cmdline();
	387	prom_meminit();
	388	#ifdef CONFIG_SERIAL_8250_CONSOLE
	389	console_config();
	390	#endif
	391	}