Commit | Line | Data |
---|---|---|
9d5a6349 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
1da177e4 LT |
2 | /* IEEE754 floating point arithmetic |
3 | * single precision | |
4 | */ | |
5 | /* | |
6 | * MIPS floating point support | |
7 | * Copyright (C) 1994-2000 Algorithmics Ltd. | |
1da177e4 LT |
8 | */ |
9 | ||
cae55066 | 10 | #include <linux/compiler.h> |
1da177e4 LT |
11 | |
12 | #include "ieee754sp.h" | |
13 | ||
2209bcb1 | 14 | int ieee754sp_class(union ieee754sp x) |
1da177e4 LT |
15 | { |
16 | COMPXSP; | |
17 | EXPLODEXSP; | |
18 | return xc; | |
19 | } | |
20 | ||
e06b530b | 21 | static inline int ieee754sp_isnan(union ieee754sp x) |
1da177e4 | 22 | { |
c9a10845 | 23 | return ieee754_class_nan(ieee754sp_class(x)); |
1da177e4 LT |
24 | } |
25 | ||
f71baa11 | 26 | static inline int ieee754sp_issnan(union ieee754sp x) |
1da177e4 | 27 | { |
90d53a91 MR |
28 | int qbit; |
29 | ||
1da177e4 | 30 | assert(ieee754sp_isnan(x)); |
90d53a91 MR |
31 | qbit = (SPMANT(x) & SP_MBIT(SP_FBITS - 1)) == SP_MBIT(SP_FBITS - 1); |
32 | return ieee754_csr.nan2008 ^ qbit; | |
1da177e4 LT |
33 | } |
34 | ||
35 | ||
d5afa7e9 MR |
36 | /* |
37 | * Raise the Invalid Operation IEEE 754 exception | |
38 | * and convert the signaling NaN supplied to a quiet NaN. | |
39 | */ | |
90efba36 | 40 | union ieee754sp __cold ieee754sp_nanxcpt(union ieee754sp r) |
1da177e4 | 41 | { |
d5afa7e9 | 42 | assert(ieee754sp_issnan(r)); |
1da177e4 | 43 | |
d5afa7e9 | 44 | ieee754_setcx(IEEE754_INVALID_OPERATION); |
acd9e20c | 45 | if (ieee754_csr.nan2008) { |
90d53a91 | 46 | SPMANT(r) |= SP_MBIT(SP_FBITS - 1); |
acd9e20c MR |
47 | } else { |
48 | SPMANT(r) &= ~SP_MBIT(SP_FBITS - 1); | |
49 | if (!ieee754sp_isnan(r)) | |
50 | SPMANT(r) |= SP_MBIT(SP_FBITS - 2); | |
51 | } | |
90d53a91 MR |
52 | |
53 | return r; | |
1da177e4 LT |
54 | } |
55 | ||
a58f85b5 | 56 | static unsigned int ieee754sp_get_rounding(int sn, unsigned int xm) |
1da177e4 LT |
57 | { |
58 | /* inexact must round of 3 bits | |
59 | */ | |
60 | if (xm & (SP_MBIT(3) - 1)) { | |
61 | switch (ieee754_csr.rm) { | |
56a64733 | 62 | case FPU_CSR_RZ: |
1da177e4 | 63 | break; |
56a64733 | 64 | case FPU_CSR_RN: |
1da177e4 LT |
65 | xm += 0x3 + ((xm >> 3) & 1); |
66 | /* xm += (xm&0x8)?0x4:0x3 */ | |
67 | break; | |
56a64733 | 68 | case FPU_CSR_RU: /* toward +Infinity */ |
1da177e4 LT |
69 | if (!sn) /* ?? */ |
70 | xm += 0x8; | |
71 | break; | |
56a64733 | 72 | case FPU_CSR_RD: /* toward -Infinity */ |
70342287 | 73 | if (sn) /* ?? */ |
1da177e4 LT |
74 | xm += 0x8; |
75 | break; | |
76 | } | |
77 | } | |
78 | return xm; | |
79 | } | |
80 | ||
81 | ||
82 | /* generate a normal/denormal number with over,under handling | |
83 | * sn is sign | |
84 | * xe is an unbiased exponent | |
85 | * xm is 3bit extended precision value. | |
86 | */ | |
a58f85b5 | 87 | union ieee754sp ieee754sp_format(int sn, int xe, unsigned int xm) |
1da177e4 LT |
88 | { |
89 | assert(xm); /* we don't gen exact zeros (probably should) */ | |
90 | ||
92a76f6d | 91 | assert((xm >> (SP_FBITS + 1 + 3)) == 0); /* no excess */ |
1da177e4 LT |
92 | assert(xm & (SP_HIDDEN_BIT << 3)); |
93 | ||
94 | if (xe < SP_EMIN) { | |
95 | /* strip lower bits */ | |
96 | int es = SP_EMIN - xe; | |
97 | ||
98 | if (ieee754_csr.nod) { | |
9e8bad1f RB |
99 | ieee754_setcx(IEEE754_UNDERFLOW); |
100 | ieee754_setcx(IEEE754_INEXACT); | |
1da177e4 LT |
101 | |
102 | switch(ieee754_csr.rm) { | |
56a64733 RB |
103 | case FPU_CSR_RN: |
104 | case FPU_CSR_RZ: | |
1da177e4 | 105 | return ieee754sp_zero(sn); |
56a64733 | 106 | case FPU_CSR_RU: /* toward +Infinity */ |
47fa0c02 | 107 | if (sn == 0) |
1da177e4 LT |
108 | return ieee754sp_min(0); |
109 | else | |
110 | return ieee754sp_zero(1); | |
56a64733 | 111 | case FPU_CSR_RD: /* toward -Infinity */ |
47fa0c02 | 112 | if (sn == 0) |
1da177e4 LT |
113 | return ieee754sp_zero(0); |
114 | else | |
115 | return ieee754sp_min(1); | |
116 | } | |
117 | } | |
118 | ||
de2fc342 RB |
119 | if (xe == SP_EMIN - 1 && |
120 | ieee754sp_get_rounding(sn, xm) >> (SP_FBITS + 1 + 3)) | |
1da177e4 LT |
121 | { |
122 | /* Not tiny after rounding */ | |
9e8bad1f | 123 | ieee754_setcx(IEEE754_INEXACT); |
de2fc342 | 124 | xm = ieee754sp_get_rounding(sn, xm); |
1da177e4 LT |
125 | xm >>= 1; |
126 | /* Clear grs bits */ | |
127 | xm &= ~(SP_MBIT(3) - 1); | |
128 | xe++; | |
47fa0c02 | 129 | } else { |
1da177e4 LT |
130 | /* sticky right shift es bits |
131 | */ | |
db57f29d PB |
132 | xm = XSPSRS(xm, es); |
133 | xe += es; | |
1da177e4 LT |
134 | assert((xm & (SP_HIDDEN_BIT << 3)) == 0); |
135 | assert(xe == SP_EMIN); | |
136 | } | |
137 | } | |
138 | if (xm & (SP_MBIT(3) - 1)) { | |
9e8bad1f | 139 | ieee754_setcx(IEEE754_INEXACT); |
1da177e4 | 140 | if ((xm & (SP_HIDDEN_BIT << 3)) == 0) { |
9e8bad1f | 141 | ieee754_setcx(IEEE754_UNDERFLOW); |
1da177e4 LT |
142 | } |
143 | ||
144 | /* inexact must round of 3 bits | |
145 | */ | |
de2fc342 | 146 | xm = ieee754sp_get_rounding(sn, xm); |
1da177e4 LT |
147 | /* adjust exponent for rounding add overflowing |
148 | */ | |
ad8fb553 | 149 | if (xm >> (SP_FBITS + 1 + 3)) { |
1da177e4 LT |
150 | /* add causes mantissa overflow */ |
151 | xm >>= 1; | |
152 | xe++; | |
153 | } | |
154 | } | |
155 | /* strip grs bits */ | |
156 | xm >>= 3; | |
157 | ||
92a76f6d | 158 | assert((xm >> (SP_FBITS + 1)) == 0); /* no excess */ |
1da177e4 LT |
159 | assert(xe >= SP_EMIN); |
160 | ||
161 | if (xe > SP_EMAX) { | |
9e8bad1f RB |
162 | ieee754_setcx(IEEE754_OVERFLOW); |
163 | ieee754_setcx(IEEE754_INEXACT); | |
1da177e4 LT |
164 | /* -O can be table indexed by (rm,sn) */ |
165 | switch (ieee754_csr.rm) { | |
56a64733 | 166 | case FPU_CSR_RN: |
1da177e4 | 167 | return ieee754sp_inf(sn); |
56a64733 | 168 | case FPU_CSR_RZ: |
1da177e4 | 169 | return ieee754sp_max(sn); |
56a64733 | 170 | case FPU_CSR_RU: /* toward +Infinity */ |
1da177e4 LT |
171 | if (sn == 0) |
172 | return ieee754sp_inf(0); | |
173 | else | |
174 | return ieee754sp_max(1); | |
56a64733 | 175 | case FPU_CSR_RD: /* toward -Infinity */ |
1da177e4 LT |
176 | if (sn == 0) |
177 | return ieee754sp_max(0); | |
178 | else | |
179 | return ieee754sp_inf(1); | |
180 | } | |
181 | } | |
182 | /* gen norm/denorm/zero */ | |
183 | ||
184 | if ((xm & SP_HIDDEN_BIT) == 0) { | |
185 | /* we underflow (tiny/zero) */ | |
186 | assert(xe == SP_EMIN); | |
187 | if (ieee754_csr.mx & IEEE754_UNDERFLOW) | |
9e8bad1f | 188 | ieee754_setcx(IEEE754_UNDERFLOW); |
1da177e4 LT |
189 | return buildsp(sn, SP_EMIN - 1 + SP_EBIAS, xm); |
190 | } else { | |
92a76f6d | 191 | assert((xm >> (SP_FBITS + 1)) == 0); /* no excess */ |
1da177e4 LT |
192 | assert(xm & SP_HIDDEN_BIT); |
193 | ||
194 | return buildsp(sn, xe + SP_EBIAS, xm & ~SP_HIDDEN_BIT); | |
195 | } | |
196 | } |