Commit | Line | Data |
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1da177e4 LT |
1 | /* IEEE754 floating point arithmetic |
2 | * double precision: common utilities | |
3 | */ | |
4 | /* | |
5 | * MIPS floating point support | |
6 | * Copyright (C) 1994-2000 Algorithmics Ltd. | |
1da177e4 | 7 | * |
1da177e4 LT |
8 | * This program is free software; you can distribute it and/or modify it |
9 | * under the terms of the GNU General Public License (Version 2) as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | * for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along | |
18 | * with this program; if not, write to the Free Software Foundation, Inc., | |
3f7cac41 | 19 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
1da177e4 LT |
20 | */ |
21 | ||
cae55066 | 22 | #include <linux/compiler.h> |
1da177e4 LT |
23 | |
24 | #include "ieee754dp.h" | |
25 | ||
2209bcb1 | 26 | int ieee754dp_class(union ieee754dp x) |
1da177e4 LT |
27 | { |
28 | COMPXDP; | |
29 | EXPLODEXDP; | |
30 | return xc; | |
31 | } | |
32 | ||
e06b530b | 33 | static inline int ieee754dp_isnan(union ieee754dp x) |
1da177e4 | 34 | { |
c9a10845 | 35 | return ieee754_class_nan(ieee754dp_class(x)); |
1da177e4 LT |
36 | } |
37 | ||
f71baa11 | 38 | static inline int ieee754dp_issnan(union ieee754dp x) |
1da177e4 | 39 | { |
90d53a91 MR |
40 | int qbit; |
41 | ||
1da177e4 | 42 | assert(ieee754dp_isnan(x)); |
90d53a91 MR |
43 | qbit = (DPMANT(x) & DP_MBIT(DP_FBITS - 1)) == DP_MBIT(DP_FBITS - 1); |
44 | return ieee754_csr.nan2008 ^ qbit; | |
1da177e4 LT |
45 | } |
46 | ||
47 | ||
d5afa7e9 MR |
48 | /* |
49 | * Raise the Invalid Operation IEEE 754 exception | |
50 | * and convert the signaling NaN supplied to a quiet NaN. | |
51 | */ | |
90efba36 | 52 | union ieee754dp __cold ieee754dp_nanxcpt(union ieee754dp r) |
1da177e4 | 53 | { |
d5afa7e9 | 54 | assert(ieee754dp_issnan(r)); |
1da177e4 | 55 | |
d5afa7e9 | 56 | ieee754_setcx(IEEE754_INVALID_OPERATION); |
90d53a91 MR |
57 | if (ieee754_csr.nan2008) |
58 | DPMANT(r) |= DP_MBIT(DP_FBITS - 1); | |
59 | else | |
60 | r = ieee754dp_indef(); | |
61 | ||
62 | return r; | |
1da177e4 LT |
63 | } |
64 | ||
de2fc342 | 65 | static u64 ieee754dp_get_rounding(int sn, u64 xm) |
1da177e4 LT |
66 | { |
67 | /* inexact must round of 3 bits | |
68 | */ | |
69 | if (xm & (DP_MBIT(3) - 1)) { | |
70 | switch (ieee754_csr.rm) { | |
56a64733 | 71 | case FPU_CSR_RZ: |
1da177e4 | 72 | break; |
56a64733 | 73 | case FPU_CSR_RN: |
1da177e4 LT |
74 | xm += 0x3 + ((xm >> 3) & 1); |
75 | /* xm += (xm&0x8)?0x4:0x3 */ | |
76 | break; | |
56a64733 | 77 | case FPU_CSR_RU: /* toward +Infinity */ |
1da177e4 LT |
78 | if (!sn) /* ?? */ |
79 | xm += 0x8; | |
80 | break; | |
56a64733 | 81 | case FPU_CSR_RD: /* toward -Infinity */ |
70342287 | 82 | if (sn) /* ?? */ |
1da177e4 LT |
83 | xm += 0x8; |
84 | break; | |
85 | } | |
86 | } | |
87 | return xm; | |
88 | } | |
89 | ||
90 | ||
91 | /* generate a normal/denormal number with over,under handling | |
92 | * sn is sign | |
93 | * xe is an unbiased exponent | |
94 | * xm is 3bit extended precision value. | |
95 | */ | |
2209bcb1 | 96 | union ieee754dp ieee754dp_format(int sn, int xe, u64 xm) |
1da177e4 LT |
97 | { |
98 | assert(xm); /* we don't gen exact zeros (probably should) */ | |
99 | ||
92a76f6d | 100 | assert((xm >> (DP_FBITS + 1 + 3)) == 0); /* no excess */ |
1da177e4 LT |
101 | assert(xm & (DP_HIDDEN_BIT << 3)); |
102 | ||
103 | if (xe < DP_EMIN) { | |
104 | /* strip lower bits */ | |
105 | int es = DP_EMIN - xe; | |
106 | ||
107 | if (ieee754_csr.nod) { | |
9e8bad1f RB |
108 | ieee754_setcx(IEEE754_UNDERFLOW); |
109 | ieee754_setcx(IEEE754_INEXACT); | |
1da177e4 LT |
110 | |
111 | switch(ieee754_csr.rm) { | |
56a64733 RB |
112 | case FPU_CSR_RN: |
113 | case FPU_CSR_RZ: | |
1da177e4 | 114 | return ieee754dp_zero(sn); |
56a64733 | 115 | case FPU_CSR_RU: /* toward +Infinity */ |
47fa0c02 | 116 | if (sn == 0) |
1da177e4 LT |
117 | return ieee754dp_min(0); |
118 | else | |
119 | return ieee754dp_zero(1); | |
56a64733 | 120 | case FPU_CSR_RD: /* toward -Infinity */ |
47fa0c02 | 121 | if (sn == 0) |
1da177e4 LT |
122 | return ieee754dp_zero(0); |
123 | else | |
124 | return ieee754dp_min(1); | |
125 | } | |
126 | } | |
127 | ||
de2fc342 RB |
128 | if (xe == DP_EMIN - 1 && |
129 | ieee754dp_get_rounding(sn, xm) >> (DP_FBITS + 1 + 3)) | |
1da177e4 LT |
130 | { |
131 | /* Not tiny after rounding */ | |
9e8bad1f | 132 | ieee754_setcx(IEEE754_INEXACT); |
de2fc342 | 133 | xm = ieee754dp_get_rounding(sn, xm); |
1da177e4 LT |
134 | xm >>= 1; |
135 | /* Clear grs bits */ | |
136 | xm &= ~(DP_MBIT(3) - 1); | |
137 | xe++; | |
138 | } | |
139 | else { | |
140 | /* sticky right shift es bits | |
141 | */ | |
142 | xm = XDPSRS(xm, es); | |
143 | xe += es; | |
144 | assert((xm & (DP_HIDDEN_BIT << 3)) == 0); | |
145 | assert(xe == DP_EMIN); | |
146 | } | |
147 | } | |
148 | if (xm & (DP_MBIT(3) - 1)) { | |
9e8bad1f | 149 | ieee754_setcx(IEEE754_INEXACT); |
1da177e4 | 150 | if ((xm & (DP_HIDDEN_BIT << 3)) == 0) { |
9e8bad1f | 151 | ieee754_setcx(IEEE754_UNDERFLOW); |
1da177e4 LT |
152 | } |
153 | ||
154 | /* inexact must round of 3 bits | |
155 | */ | |
de2fc342 | 156 | xm = ieee754dp_get_rounding(sn, xm); |
1da177e4 LT |
157 | /* adjust exponent for rounding add overflowing |
158 | */ | |
ad8fb553 | 159 | if (xm >> (DP_FBITS + 3 + 1)) { |
1da177e4 LT |
160 | /* add causes mantissa overflow */ |
161 | xm >>= 1; | |
162 | xe++; | |
163 | } | |
164 | } | |
165 | /* strip grs bits */ | |
166 | xm >>= 3; | |
167 | ||
92a76f6d | 168 | assert((xm >> (DP_FBITS + 1)) == 0); /* no excess */ |
1da177e4 LT |
169 | assert(xe >= DP_EMIN); |
170 | ||
171 | if (xe > DP_EMAX) { | |
9e8bad1f RB |
172 | ieee754_setcx(IEEE754_OVERFLOW); |
173 | ieee754_setcx(IEEE754_INEXACT); | |
1da177e4 LT |
174 | /* -O can be table indexed by (rm,sn) */ |
175 | switch (ieee754_csr.rm) { | |
56a64733 | 176 | case FPU_CSR_RN: |
1da177e4 | 177 | return ieee754dp_inf(sn); |
56a64733 | 178 | case FPU_CSR_RZ: |
1da177e4 | 179 | return ieee754dp_max(sn); |
56a64733 | 180 | case FPU_CSR_RU: /* toward +Infinity */ |
1da177e4 LT |
181 | if (sn == 0) |
182 | return ieee754dp_inf(0); | |
183 | else | |
184 | return ieee754dp_max(1); | |
56a64733 | 185 | case FPU_CSR_RD: /* toward -Infinity */ |
1da177e4 LT |
186 | if (sn == 0) |
187 | return ieee754dp_max(0); | |
188 | else | |
189 | return ieee754dp_inf(1); | |
190 | } | |
191 | } | |
192 | /* gen norm/denorm/zero */ | |
193 | ||
194 | if ((xm & DP_HIDDEN_BIT) == 0) { | |
195 | /* we underflow (tiny/zero) */ | |
196 | assert(xe == DP_EMIN); | |
197 | if (ieee754_csr.mx & IEEE754_UNDERFLOW) | |
9e8bad1f | 198 | ieee754_setcx(IEEE754_UNDERFLOW); |
1da177e4 LT |
199 | return builddp(sn, DP_EMIN - 1 + DP_EBIAS, xm); |
200 | } else { | |
92a76f6d | 201 | assert((xm >> (DP_FBITS + 1)) == 0); /* no excess */ |
1da177e4 LT |
202 | assert(xm & DP_HIDDEN_BIT); |
203 | ||
204 | return builddp(sn, xe + DP_EBIAS, xm & ~DP_HIDDEN_BIT); | |
205 | } | |
206 | } |