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MIPS: math-emu: Header file weeding.
[linux-2.6-block.git] / arch / mips / math-emu / cp1emu.c
CommitLineData
1da177e4
LT		 1/*
2 * cp1emu.c: a MIPS coprocessor 1 (fpu) instruction emulator
3 *
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
1da177e4
LT		 6 *
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.
9 *
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
22 *
23 * A complete emulator for MIPS coprocessor 1 instructions. This is
24 * required for #float(switch) or #float(trap), where it catches all
25 * COP1 instructions via the "CoProcessor Unusable" exception.
26 *
27 * More surprisingly it is also required for #float(ieee), to help out
28 * the hardware fpu at the boundaries of the IEEE-754 representation
29 * (denormalised values, infinities, underflow, etc). It is made
30 * quite nasty because emulation of some non-COP1 instructions is
31 * required, e.g. in branch delay slots.
32 *
33 * Note if you know that you won't have an fpu, then you'll get much
34 * better performance by compiling with -msoft-float!
35 */
36#include <linux/sched.h>
83fd38ca 37#include <linux/debugfs.h>
7f788d2d 38#include <linux/perf_event.h>
1da177e4 39
cd8ee345 40#include <asm/branch.h>
1da177e4 41#include <asm/inst.h>
1da177e4
LT		 42#include <asm/ptrace.h>
43#include <asm/signal.h>
cd8ee345
RB		 44#include <asm/uaccess.h>
45
46#include <asm/processor.h>
1da177e4 47#include <asm/fpu_emulator.h>
102cedc3 48#include <asm/fpu.h>
1da177e4
LT		 49
50#include "ieee754.h"
1da177e4
LT		 51
52/* Strap kernel emulator for full MIPS IV emulation */
53
54#ifdef __mips
55#undef __mips
56#endif
57#define __mips 4
58
59/* Function which emulates a floating point instruction. */
60
eae89076 61static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
1da177e4
LT		 62 mips_instruction);
63
64#if __mips >= 4 && __mips != 32
65static int fpux_emu(struct pt_regs *,
515b029d 66 struct mips_fpu_struct *, mips_instruction, void *__user *);
1da177e4
LT		 67#endif
68
eae89076 69/* Further private data for which no space exists in mips_fpu_struct */
1da177e4 70
b6ee75ed
DD		 71#ifdef CONFIG_DEBUG_FS
72DEFINE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats);
73#endif
1da177e4
LT		 74
75/* Control registers */
76
77#define FPCREG_RID 0 /* $0 = revision id */
78#define FPCREG_CSR 31 /* $31 = csr */
79
95e8f634
SM		 80/* Determine rounding mode from the RM bits of the FCSR */
81#define modeindex(v) ((v) & FPU_CSR_RM)
82
102cedc3
LY		 83/* microMIPS bitfields */
84#define MM_POOL32A_MINOR_MASK 0x3f
85#define MM_POOL32A_MINOR_SHIFT 0x6
86#define MM_MIPS32_COND_FC 0x30
87
1da177e4
LT		 88/* Convert Mips rounding mode (0..3) to IEEE library modes. */
89static const unsigned char ieee_rm[4] = {
cd21dfcf
RB		 90 [FPU_CSR_RN] = IEEE754_RN,
91 [FPU_CSR_RZ] = IEEE754_RZ,
92 [FPU_CSR_RU] = IEEE754_RU,
93 [FPU_CSR_RD] = IEEE754_RD,
94};
95/* Convert IEEE library modes to Mips rounding mode (0..3). */
96static const unsigned char mips_rm[4] = {
97 [IEEE754_RN] = FPU_CSR_RN,
98 [IEEE754_RZ] = FPU_CSR_RZ,
99 [IEEE754_RD] = FPU_CSR_RD,
100 [IEEE754_RU] = FPU_CSR_RU,
1da177e4
LT		 101};
102
103#if __mips >= 4
104/* convert condition code register number to csr bit */
105static const unsigned int fpucondbit[8] = {
106 FPU_CSR_COND0,
107 FPU_CSR_COND1,
108 FPU_CSR_COND2,
109 FPU_CSR_COND3,
110 FPU_CSR_COND4,
111 FPU_CSR_COND5,
112 FPU_CSR_COND6,
113 FPU_CSR_COND7
114};
115#endif
116
102cedc3
LY		 117/* (microMIPS) Convert 16-bit register encoding to 32-bit register encoding. */
118static const unsigned int reg16to32map[8] = {16, 17, 2, 3, 4, 5, 6, 7};
119
120/* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
121static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0};
122static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0};
123static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0};
124static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0};
125
126/*
127 * This functions translates a 32-bit microMIPS instruction
128 * into a 32-bit MIPS32 instruction. Returns 0 on success
129 * and SIGILL otherwise.
130 */
131static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
132{
133 union mips_instruction insn = *insn_ptr;
134 union mips_instruction mips32_insn = insn;
135 int func, fmt, op;
136
137 switch (insn.mm_i_format.opcode) {
138 case mm_ldc132_op:
139 mips32_insn.mm_i_format.opcode = ldc1_op;
140 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
141 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
142 break;
143 case mm_lwc132_op:
144 mips32_insn.mm_i_format.opcode = lwc1_op;
145 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
146 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
147 break;
148 case mm_sdc132_op:
149 mips32_insn.mm_i_format.opcode = sdc1_op;
150 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
151 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
152 break;
153 case mm_swc132_op:
154 mips32_insn.mm_i_format.opcode = swc1_op;
155 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
156 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
157 break;
158 case mm_pool32i_op:
159 /* NOTE: offset is << by 1 if in microMIPS mode. */
160 if ((insn.mm_i_format.rt == mm_bc1f_op) ||
161 (insn.mm_i_format.rt == mm_bc1t_op)) {
162 mips32_insn.fb_format.opcode = cop1_op;
163 mips32_insn.fb_format.bc = bc_op;
164 mips32_insn.fb_format.flag =
165 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0;
166 } else
167 return SIGILL;
168 break;
169 case mm_pool32f_op:
170 switch (insn.mm_fp0_format.func) {
171 case mm_32f_01_op:
172 case mm_32f_11_op:
173 case mm_32f_02_op:
174 case mm_32f_12_op:
175 case mm_32f_41_op:
176 case mm_32f_51_op:
177 case mm_32f_42_op:
178 case mm_32f_52_op:
179 op = insn.mm_fp0_format.func;
180 if (op == mm_32f_01_op)
181 func = madd_s_op;
182 else if (op == mm_32f_11_op)
183 func = madd_d_op;
184 else if (op == mm_32f_02_op)
185 func = nmadd_s_op;
186 else if (op == mm_32f_12_op)
187 func = nmadd_d_op;
188 else if (op == mm_32f_41_op)
189 func = msub_s_op;
190 else if (op == mm_32f_51_op)
191 func = msub_d_op;
192 else if (op == mm_32f_42_op)
193 func = nmsub_s_op;
194 else
195 func = nmsub_d_op;
196 mips32_insn.fp6_format.opcode = cop1x_op;
197 mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr;
198 mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft;
199 mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs;
200 mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd;
201 mips32_insn.fp6_format.func = func;
202 break;
203 case mm_32f_10_op:
204 func = -1; /* Invalid */
205 op = insn.mm_fp5_format.op & 0x7;
206 if (op == mm_ldxc1_op)
207 func = ldxc1_op;
208 else if (op == mm_sdxc1_op)
209 func = sdxc1_op;
210 else if (op == mm_lwxc1_op)
211 func = lwxc1_op;
212 else if (op == mm_swxc1_op)
213 func = swxc1_op;
214
215 if (func != -1) {
216 mips32_insn.r_format.opcode = cop1x_op;
217 mips32_insn.r_format.rs =
218 insn.mm_fp5_format.base;
219 mips32_insn.r_format.rt =
220 insn.mm_fp5_format.index;
221 mips32_insn.r_format.rd = 0;
222 mips32_insn.r_format.re = insn.mm_fp5_format.fd;
223 mips32_insn.r_format.func = func;
224 } else
225 return SIGILL;
226 break;
227 case mm_32f_40_op:
228 op = -1; /* Invalid */
229 if (insn.mm_fp2_format.op == mm_fmovt_op)
230 op = 1;
231 else if (insn.mm_fp2_format.op == mm_fmovf_op)
232 op = 0;
233 if (op != -1) {
234 mips32_insn.fp0_format.opcode = cop1_op;
235 mips32_insn.fp0_format.fmt =
236 sdps_format[insn.mm_fp2_format.fmt];
237 mips32_insn.fp0_format.ft =
238 (insn.mm_fp2_format.cc<<2) + op;
239 mips32_insn.fp0_format.fs =
240 insn.mm_fp2_format.fs;
241 mips32_insn.fp0_format.fd =
242 insn.mm_fp2_format.fd;
243 mips32_insn.fp0_format.func = fmovc_op;
244 } else
245 return SIGILL;
246 break;
247 case mm_32f_60_op:
248 func = -1; /* Invalid */
249 if (insn.mm_fp0_format.op == mm_fadd_op)
250 func = fadd_op;
251 else if (insn.mm_fp0_format.op == mm_fsub_op)
252 func = fsub_op;
253 else if (insn.mm_fp0_format.op == mm_fmul_op)
254 func = fmul_op;
255 else if (insn.mm_fp0_format.op == mm_fdiv_op)
256 func = fdiv_op;
257 if (func != -1) {
258 mips32_insn.fp0_format.opcode = cop1_op;
259 mips32_insn.fp0_format.fmt =
260 sdps_format[insn.mm_fp0_format.fmt];
261 mips32_insn.fp0_format.ft =
262 insn.mm_fp0_format.ft;
263 mips32_insn.fp0_format.fs =
264 insn.mm_fp0_format.fs;
265 mips32_insn.fp0_format.fd =
266 insn.mm_fp0_format.fd;
267 mips32_insn.fp0_format.func = func;
268 } else
269 return SIGILL;
270 break;
271 case mm_32f_70_op:
272 func = -1; /* Invalid */
273 if (insn.mm_fp0_format.op == mm_fmovn_op)
274 func = fmovn_op;
275 else if (insn.mm_fp0_format.op == mm_fmovz_op)
276 func = fmovz_op;
277 if (func != -1) {
278 mips32_insn.fp0_format.opcode = cop1_op;
279 mips32_insn.fp0_format.fmt =
280 sdps_format[insn.mm_fp0_format.fmt];
281 mips32_insn.fp0_format.ft =
282 insn.mm_fp0_format.ft;
283 mips32_insn.fp0_format.fs =
284 insn.mm_fp0_format.fs;
285 mips32_insn.fp0_format.fd =
286 insn.mm_fp0_format.fd;
287 mips32_insn.fp0_format.func = func;
288 } else
289 return SIGILL;
290 break;
291 case mm_32f_73_op: /* POOL32FXF */
292 switch (insn.mm_fp1_format.op) {
293 case mm_movf0_op:
294 case mm_movf1_op:
295 case mm_movt0_op:
296 case mm_movt1_op:
297 if ((insn.mm_fp1_format.op & 0x7f) ==
298 mm_movf0_op)
299 op = 0;
300 else
301 op = 1;
302 mips32_insn.r_format.opcode = spec_op;
303 mips32_insn.r_format.rs = insn.mm_fp4_format.fs;
304 mips32_insn.r_format.rt =
305 (insn.mm_fp4_format.cc << 2) + op;
306 mips32_insn.r_format.rd = insn.mm_fp4_format.rt;
307 mips32_insn.r_format.re = 0;
308 mips32_insn.r_format.func = movc_op;
309 break;
310 case mm_fcvtd0_op:
311 case mm_fcvtd1_op:
312 case mm_fcvts0_op:
313 case mm_fcvts1_op:
314 if ((insn.mm_fp1_format.op & 0x7f) ==
315 mm_fcvtd0_op) {
316 func = fcvtd_op;
317 fmt = swl_format[insn.mm_fp3_format.fmt];
318 } else {
319 func = fcvts_op;
320 fmt = dwl_format[insn.mm_fp3_format.fmt];
321 }
322 mips32_insn.fp0_format.opcode = cop1_op;
323 mips32_insn.fp0_format.fmt = fmt;
324 mips32_insn.fp0_format.ft = 0;
325 mips32_insn.fp0_format.fs =
326 insn.mm_fp3_format.fs;
327 mips32_insn.fp0_format.fd =
328 insn.mm_fp3_format.rt;
329 mips32_insn.fp0_format.func = func;
330 break;
331 case mm_fmov0_op:
332 case mm_fmov1_op:
333 case mm_fabs0_op:
334 case mm_fabs1_op:
335 case mm_fneg0_op:
336 case mm_fneg1_op:
337 if ((insn.mm_fp1_format.op & 0x7f) ==
338 mm_fmov0_op)
339 func = fmov_op;
340 else if ((insn.mm_fp1_format.op & 0x7f) ==
341 mm_fabs0_op)
342 func = fabs_op;
343 else
344 func = fneg_op;
345 mips32_insn.fp0_format.opcode = cop1_op;
346 mips32_insn.fp0_format.fmt =
347 sdps_format[insn.mm_fp3_format.fmt];
348 mips32_insn.fp0_format.ft = 0;
349 mips32_insn.fp0_format.fs =
350 insn.mm_fp3_format.fs;
351 mips32_insn.fp0_format.fd =
352 insn.mm_fp3_format.rt;
353 mips32_insn.fp0_format.func = func;
354 break;
355 case mm_ffloorl_op:
356 case mm_ffloorw_op:
357 case mm_fceill_op:
358 case mm_fceilw_op:
359 case mm_ftruncl_op:
360 case mm_ftruncw_op:
361 case mm_froundl_op:
362 case mm_froundw_op:
363 case mm_fcvtl_op:
364 case mm_fcvtw_op:
365 if (insn.mm_fp1_format.op == mm_ffloorl_op)
366 func = ffloorl_op;
367 else if (insn.mm_fp1_format.op == mm_ffloorw_op)
368 func = ffloor_op;
369 else if (insn.mm_fp1_format.op == mm_fceill_op)
370 func = fceill_op;
371 else if (insn.mm_fp1_format.op == mm_fceilw_op)
372 func = fceil_op;
373 else if (insn.mm_fp1_format.op == mm_ftruncl_op)
374 func = ftruncl_op;
375 else if (insn.mm_fp1_format.op == mm_ftruncw_op)
376 func = ftrunc_op;
377 else if (insn.mm_fp1_format.op == mm_froundl_op)
378 func = froundl_op;
379 else if (insn.mm_fp1_format.op == mm_froundw_op)
380 func = fround_op;
381 else if (insn.mm_fp1_format.op == mm_fcvtl_op)
382 func = fcvtl_op;
383 else
384 func = fcvtw_op;
385 mips32_insn.fp0_format.opcode = cop1_op;
386 mips32_insn.fp0_format.fmt =
387 sd_format[insn.mm_fp1_format.fmt];
388 mips32_insn.fp0_format.ft = 0;
389 mips32_insn.fp0_format.fs =
390 insn.mm_fp1_format.fs;
391 mips32_insn.fp0_format.fd =
392 insn.mm_fp1_format.rt;
393 mips32_insn.fp0_format.func = func;
394 break;
395 case mm_frsqrt_op:
396 case mm_fsqrt_op:
397 case mm_frecip_op:
398 if (insn.mm_fp1_format.op == mm_frsqrt_op)
399 func = frsqrt_op;
400 else if (insn.mm_fp1_format.op == mm_fsqrt_op)
401 func = fsqrt_op;
402 else
403 func = frecip_op;
404 mips32_insn.fp0_format.opcode = cop1_op;
405 mips32_insn.fp0_format.fmt =
406 sdps_format[insn.mm_fp1_format.fmt];
407 mips32_insn.fp0_format.ft = 0;
408 mips32_insn.fp0_format.fs =
409 insn.mm_fp1_format.fs;
410 mips32_insn.fp0_format.fd =
411 insn.mm_fp1_format.rt;
412 mips32_insn.fp0_format.func = func;
413 break;
414 case mm_mfc1_op:
415 case mm_mtc1_op:
416 case mm_cfc1_op:
417 case mm_ctc1_op:
9355e59c
SH		 418 case mm_mfhc1_op:
419 case mm_mthc1_op:
102cedc3
LY		 420 if (insn.mm_fp1_format.op == mm_mfc1_op)
421 op = mfc_op;
422 else if (insn.mm_fp1_format.op == mm_mtc1_op)
423 op = mtc_op;
424 else if (insn.mm_fp1_format.op == mm_cfc1_op)
425 op = cfc_op;
9355e59c 426 else if (insn.mm_fp1_format.op == mm_ctc1_op)
102cedc3 427 op = ctc_op;
9355e59c
SH		 428 else if (insn.mm_fp1_format.op == mm_mfhc1_op)
429 op = mfhc_op;
430 else
431 op = mthc_op;
102cedc3
LY		 432 mips32_insn.fp1_format.opcode = cop1_op;
433 mips32_insn.fp1_format.op = op;
434 mips32_insn.fp1_format.rt =
435 insn.mm_fp1_format.rt;
436 mips32_insn.fp1_format.fs =
437 insn.mm_fp1_format.fs;
438 mips32_insn.fp1_format.fd = 0;
439 mips32_insn.fp1_format.func = 0;
440 break;
441 default:
442 return SIGILL;
102cedc3
LY		 443 }
444 break;
445 case mm_32f_74_op: /* c.cond.fmt */
446 mips32_insn.fp0_format.opcode = cop1_op;
447 mips32_insn.fp0_format.fmt =
448 sdps_format[insn.mm_fp4_format.fmt];
449 mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt;
450 mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs;
451 mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2;
452 mips32_insn.fp0_format.func =
453 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC;
454 break;
455 default:
456 return SIGILL;
102cedc3
LY		 457 }
458 break;
459 default:
460 return SIGILL;
102cedc3
LY		 461 }
462
463 *insn_ptr = mips32_insn;
464 return 0;
465}
466
467int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
468 unsigned long *contpc)
469{
470 union mips_instruction insn = (union mips_instruction)dec_insn.insn;
471 int bc_false = 0;
472 unsigned int fcr31;
473 unsigned int bit;
474
fe6d2909
DD		 475 if (!cpu_has_mmips)
476 return 0;
477
102cedc3
LY		 478 switch (insn.mm_i_format.opcode) {
479 case mm_pool32a_op:
480 if ((insn.mm_i_format.simmediate & MM_POOL32A_MINOR_MASK) ==
481 mm_pool32axf_op) {
482 switch (insn.mm_i_format.simmediate >>
483 MM_POOL32A_MINOR_SHIFT) {
484 case mm_jalr_op:
485 case mm_jalrhb_op:
486 case mm_jalrs_op:
487 case mm_jalrshb_op:
488 if (insn.mm_i_format.rt != 0) /* Not mm_jr */
489 regs->regs[insn.mm_i_format.rt] =
490 regs->cp0_epc +
491 dec_insn.pc_inc +
492 dec_insn.next_pc_inc;
493 *contpc = regs->regs[insn.mm_i_format.rs];
494 return 1;
102cedc3
LY		 495 }
496 }
497 break;
498 case mm_pool32i_op:
499 switch (insn.mm_i_format.rt) {
500 case mm_bltzals_op:
501 case mm_bltzal_op:
502 regs->regs[31] = regs->cp0_epc +
503 dec_insn.pc_inc +
504 dec_insn.next_pc_inc;
505 /* Fall through */
506 case mm_bltz_op:
507 if ((long)regs->regs[insn.mm_i_format.rs] < 0)
508 *contpc = regs->cp0_epc +
509 dec_insn.pc_inc +
510 (insn.mm_i_format.simmediate << 1);
511 else
512 *contpc = regs->cp0_epc +
513 dec_insn.pc_inc +
514 dec_insn.next_pc_inc;
515 return 1;
102cedc3
LY		 516 case mm_bgezals_op:
517 case mm_bgezal_op:
518 regs->regs[31] = regs->cp0_epc +
519 dec_insn.pc_inc +
520 dec_insn.next_pc_inc;
521 /* Fall through */
522 case mm_bgez_op:
523 if ((long)regs->regs[insn.mm_i_format.rs] >= 0)
524 *contpc = regs->cp0_epc +
525 dec_insn.pc_inc +
526 (insn.mm_i_format.simmediate << 1);
527 else
528 *contpc = regs->cp0_epc +
529 dec_insn.pc_inc +
530 dec_insn.next_pc_inc;
531 return 1;
102cedc3
LY		 532 case mm_blez_op:
533 if ((long)regs->regs[insn.mm_i_format.rs] <= 0)
534 *contpc = regs->cp0_epc +
535 dec_insn.pc_inc +
536 (insn.mm_i_format.simmediate << 1);
537 else
538 *contpc = regs->cp0_epc +
539 dec_insn.pc_inc +
540 dec_insn.next_pc_inc;
541 return 1;
102cedc3
LY		 542 case mm_bgtz_op:
543 if ((long)regs->regs[insn.mm_i_format.rs] <= 0)
544 *contpc = regs->cp0_epc +
545 dec_insn.pc_inc +
546 (insn.mm_i_format.simmediate << 1);
547 else
548 *contpc = regs->cp0_epc +
549 dec_insn.pc_inc +
550 dec_insn.next_pc_inc;
551 return 1;
102cedc3
LY		 552 case mm_bc2f_op:
553 case mm_bc1f_op:
554 bc_false = 1;
555 /* Fall through */
556 case mm_bc2t_op:
557 case mm_bc1t_op:
558 preempt_disable();
559 if (is_fpu_owner())
560 asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
561 else
562 fcr31 = current->thread.fpu.fcr31;
563 preempt_enable();
564
565 if (bc_false)
566 fcr31 = ~fcr31;
567
568 bit = (insn.mm_i_format.rs >> 2);
569 bit += (bit != 0);
570 bit += 23;
571 if (fcr31 & (1 << bit))
572 *contpc = regs->cp0_epc +
573 dec_insn.pc_inc +
574 (insn.mm_i_format.simmediate << 1);
575 else
576 *contpc = regs->cp0_epc +
577 dec_insn.pc_inc + dec_insn.next_pc_inc;
578 return 1;
102cedc3
LY		 579 }
580 break;
581 case mm_pool16c_op:
582 switch (insn.mm_i_format.rt) {
583 case mm_jalr16_op:
584 case mm_jalrs16_op:
585 regs->regs[31] = regs->cp0_epc +
586 dec_insn.pc_inc + dec_insn.next_pc_inc;
587 /* Fall through */
588 case mm_jr16_op:
589 *contpc = regs->regs[insn.mm_i_format.rs];
590 return 1;
102cedc3
LY		 591 }
592 break;
593 case mm_beqz16_op:
594 if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] == 0)
595 *contpc = regs->cp0_epc +
596 dec_insn.pc_inc +
597 (insn.mm_b1_format.simmediate << 1);
598 else
599 *contpc = regs->cp0_epc +
600 dec_insn.pc_inc + dec_insn.next_pc_inc;
601 return 1;
102cedc3
LY		 602 case mm_bnez16_op:
603 if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] != 0)
604 *contpc = regs->cp0_epc +
605 dec_insn.pc_inc +
606 (insn.mm_b1_format.simmediate << 1);
607 else
608 *contpc = regs->cp0_epc +
609 dec_insn.pc_inc + dec_insn.next_pc_inc;
610 return 1;
102cedc3
LY		 611 case mm_b16_op:
612 *contpc = regs->cp0_epc + dec_insn.pc_inc +
613 (insn.mm_b0_format.simmediate << 1);
614 return 1;
102cedc3
LY		 615 case mm_beq32_op:
616 if (regs->regs[insn.mm_i_format.rs] ==
617 regs->regs[insn.mm_i_format.rt])
618 *contpc = regs->cp0_epc +
619 dec_insn.pc_inc +
620 (insn.mm_i_format.simmediate << 1);
621 else
622 *contpc = regs->cp0_epc +
623 dec_insn.pc_inc +
624 dec_insn.next_pc_inc;
625 return 1;
102cedc3
LY		 626 case mm_bne32_op:
627 if (regs->regs[insn.mm_i_format.rs] !=
628 regs->regs[insn.mm_i_format.rt])
629 *contpc = regs->cp0_epc +
630 dec_insn.pc_inc +
631 (insn.mm_i_format.simmediate << 1);
632 else
633 *contpc = regs->cp0_epc +
634 dec_insn.pc_inc + dec_insn.next_pc_inc;
635 return 1;
102cedc3
LY		 636 case mm_jalx32_op:
637 regs->regs[31] = regs->cp0_epc +
638 dec_insn.pc_inc + dec_insn.next_pc_inc;
639 *contpc = regs->cp0_epc + dec_insn.pc_inc;
640 *contpc >>= 28;
641 *contpc <<= 28;
642 *contpc |= (insn.j_format.target << 2);
643 return 1;
102cedc3
LY		 644 case mm_jals32_op:
645 case mm_jal32_op:
646 regs->regs[31] = regs->cp0_epc +
647 dec_insn.pc_inc + dec_insn.next_pc_inc;
648 /* Fall through */
649 case mm_j32_op:
650 *contpc = regs->cp0_epc + dec_insn.pc_inc;
651 *contpc >>= 27;
652 *contpc <<= 27;
653 *contpc |= (insn.j_format.target << 1);
654 set_isa16_mode(*contpc);
655 return 1;
102cedc3
LY		 656 }
657 return 0;
658}
1da177e4
LT		 659
660/*
661 * Redundant with logic already in kernel/branch.c,
662 * embedded in compute_return_epc. At some point,
663 * a single subroutine should be used across both
664 * modules.
665 */
102cedc3
LY		 666static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
667 unsigned long *contpc)
1da177e4 668{
102cedc3
LY		 669 union mips_instruction insn = (union mips_instruction)dec_insn.insn;
670 unsigned int fcr31;
671 unsigned int bit = 0;
672
673 switch (insn.i_format.opcode) {
1da177e4 674 case spec_op:
102cedc3 675 switch (insn.r_format.func) {
1da177e4 676 case jalr_op:
102cedc3
LY		 677 regs->regs[insn.r_format.rd] =
678 regs->cp0_epc + dec_insn.pc_inc +
679 dec_insn.next_pc_inc;
680 /* Fall through */
1da177e4 681 case jr_op:
102cedc3 682 *contpc = regs->regs[insn.r_format.rs];
1da177e4
LT		 683 return 1;
684 }
685 break;
1da177e4 686 case bcond_op:
102cedc3
LY		 687 switch (insn.i_format.rt) {
688 case bltzal_op:
689 case bltzall_op:
690 regs->regs[31] = regs->cp0_epc +
691 dec_insn.pc_inc +
692 dec_insn.next_pc_inc;
693 /* Fall through */
1da177e4 694 case bltz_op:
1da177e4 695 case bltzl_op:
102cedc3
LY		 696 if ((long)regs->regs[insn.i_format.rs] < 0)
697 *contpc = regs->cp0_epc +
698 dec_insn.pc_inc +
699 (insn.i_format.simmediate << 2);
700 else
701 *contpc = regs->cp0_epc +
702 dec_insn.pc_inc +
703 dec_insn.next_pc_inc;
704 return 1;
1da177e4 705 case bgezal_op:
1da177e4 706 case bgezall_op:
102cedc3
LY		 707 regs->regs[31] = regs->cp0_epc +
708 dec_insn.pc_inc +
709 dec_insn.next_pc_inc;
710 /* Fall through */
711 case bgez_op:
712 case bgezl_op:
713 if ((long)regs->regs[insn.i_format.rs] >= 0)
714 *contpc = regs->cp0_epc +
715 dec_insn.pc_inc +
716 (insn.i_format.simmediate << 2);
717 else
718 *contpc = regs->cp0_epc +
719 dec_insn.pc_inc +
720 dec_insn.next_pc_inc;
1da177e4
LT		 721 return 1;
722 }
723 break;
1da177e4 724 case jalx_op:
102cedc3
LY		 725 set_isa16_mode(bit);
726 case jal_op:
727 regs->regs[31] = regs->cp0_epc +
728 dec_insn.pc_inc +
729 dec_insn.next_pc_inc;
730 /* Fall through */
731 case j_op:
732 *contpc = regs->cp0_epc + dec_insn.pc_inc;
733 *contpc >>= 28;
734 *contpc <<= 28;
735 *contpc |= (insn.j_format.target << 2);
736 /* Set microMIPS mode bit: XOR for jalx. */
737 *contpc ^= bit;
738 return 1;
1da177e4 739 case beq_op:
1da177e4 740 case beql_op:
102cedc3
LY		 741 if (regs->regs[insn.i_format.rs] ==
742 regs->regs[insn.i_format.rt])
743 *contpc = regs->cp0_epc +
744 dec_insn.pc_inc +
745 (insn.i_format.simmediate << 2);
746 else
747 *contpc = regs->cp0_epc +
748 dec_insn.pc_inc +
749 dec_insn.next_pc_inc;
750 return 1;
102cedc3 751 case bne_op:
1da177e4 752 case bnel_op:
102cedc3
LY		 753 if (regs->regs[insn.i_format.rs] !=
754 regs->regs[insn.i_format.rt])
755 *contpc = regs->cp0_epc +
756 dec_insn.pc_inc +
757 (insn.i_format.simmediate << 2);
758 else
759 *contpc = regs->cp0_epc +
760 dec_insn.pc_inc +
761 dec_insn.next_pc_inc;
762 return 1;
102cedc3 763 case blez_op:
1da177e4 764 case blezl_op:
102cedc3
LY		 765 if ((long)regs->regs[insn.i_format.rs] <= 0)
766 *contpc = regs->cp0_epc +
767 dec_insn.pc_inc +
768 (insn.i_format.simmediate << 2);
769 else
770 *contpc = regs->cp0_epc +
771 dec_insn.pc_inc +
772 dec_insn.next_pc_inc;
773 return 1;
102cedc3 774 case bgtz_op:
1da177e4 775 case bgtzl_op:
102cedc3
LY		 776 if ((long)regs->regs[insn.i_format.rs] > 0)
777 *contpc = regs->cp0_epc +
778 dec_insn.pc_inc +
779 (insn.i_format.simmediate << 2);
780 else
781 *contpc = regs->cp0_epc +
782 dec_insn.pc_inc +
783 dec_insn.next_pc_inc;
1da177e4 784 return 1;
c26d4219
DD		 785#ifdef CONFIG_CPU_CAVIUM_OCTEON
786 case lwc2_op: /* This is bbit0 on Octeon */
787 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
788 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
789 else
790 *contpc = regs->cp0_epc + 8;
791 return 1;
792 case ldc2_op: /* This is bbit032 on Octeon */
793 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)
794 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
795 else
796 *contpc = regs->cp0_epc + 8;
797 return 1;
798 case swc2_op: /* This is bbit1 on Octeon */
799 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
800 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
801 else
802 *contpc = regs->cp0_epc + 8;
803 return 1;
804 case sdc2_op: /* This is bbit132 on Octeon */
805 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))
806 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
807 else
808 *contpc = regs->cp0_epc + 8;
809 return 1;
810#endif
1da177e4
LT		 811 case cop0_op:
812 case cop1_op:
813 case cop2_op:
814 case cop1x_op:
102cedc3
LY		 815 if (insn.i_format.rs == bc_op) {
816 preempt_disable();
817 if (is_fpu_owner())
818 asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
819 else
820 fcr31 = current->thread.fpu.fcr31;
821 preempt_enable();
822
823 bit = (insn.i_format.rt >> 2);
824 bit += (bit != 0);
825 bit += 23;
826 switch (insn.i_format.rt & 3) {
827 case 0: /* bc1f */
828 case 2: /* bc1fl */
829 if (~fcr31 & (1 << bit))
830 *contpc = regs->cp0_epc +
831 dec_insn.pc_inc +
832 (insn.i_format.simmediate << 2);
833 else
834 *contpc = regs->cp0_epc +
835 dec_insn.pc_inc +
836 dec_insn.next_pc_inc;
837 return 1;
102cedc3
LY		 838 case 1: /* bc1t */
839 case 3: /* bc1tl */
840 if (fcr31 & (1 << bit))
841 *contpc = regs->cp0_epc +
842 dec_insn.pc_inc +
843 (insn.i_format.simmediate << 2);
844 else
845 *contpc = regs->cp0_epc +
846 dec_insn.pc_inc +
847 dec_insn.next_pc_inc;
848 return 1;
102cedc3
LY		 849 }
850 }
1da177e4
LT		 851 break;
852 }
1da177e4
LT		 853 return 0;
854}
855
856/*
857 * In the Linux kernel, we support selection of FPR format on the
70342287 858 * basis of the Status.FR bit. If an FPU is not present, the FR bit
da0bac33 859 * is hardwired to zero, which would imply a 32-bit FPU even for
597ce172 860 * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
51d943f0
RB		 861 * FPU emu is slow and bulky and optimizing this function offers fairly
862 * sizeable benefits so we try to be clever and make this function return
863 * a constant whenever possible, that is on 64-bit kernels without O32
597ce172 864 * compatibility enabled and on 32-bit without 64-bit FPU support.
1da177e4 865 */
da0bac33
DD		 866static inline int cop1_64bit(struct pt_regs *xcp)
867{
51d943f0
RB		 868#if defined(CONFIG_64BIT) && !defined(CONFIG_MIPS32_O32)
869 return 1;
597ce172 870#elif defined(CONFIG_32BIT) && !defined(CONFIG_MIPS_O32_FP64_SUPPORT)
da0bac33 871 return 0;
597ce172
PB		 872#else
873 return !test_thread_flag(TIF_32BIT_FPREGS);
1da177e4 874#endif
da0bac33
DD		 875}
876
bbd426f5
PB		 877#define SIFROMREG(si, x) do { \
878 if (cop1_64bit(xcp)) \
879 (si) = get_fpr32(&ctx->fpr[x], 0); \
880 else \
881 (si) = get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \
882} while (0)
1da177e4 883
bbd426f5 884#define SITOREG(si, x) do { \
ef1c47af
PB		 885 if (cop1_64bit(xcp)) { \
886 unsigned i; \
bbd426f5 887 set_fpr32(&ctx->fpr[x], 0, si); \
ef1c47af
PB		 888 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
889 set_fpr32(&ctx->fpr[x], i, 0); \
890 } else { \
bbd426f5 891 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \
ef1c47af 892 } \
bbd426f5 893} while (0)
1da177e4 894
bbd426f5 895#define SIFROMHREG(si, x) ((si) = get_fpr32(&ctx->fpr[x], 1))
ef1c47af
PB		 896
897#define SITOHREG(si, x) do { \
898 unsigned i; \
899 set_fpr32(&ctx->fpr[x], 1, si); \
900 for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
901 set_fpr32(&ctx->fpr[x], i, 0); \
902} while (0)
1ac94400 903
bbd426f5
PB		 904#define DIFROMREG(di, x) \
905 ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0))
906
ef1c47af
PB		 907#define DITOREG(di, x) do { \
908 unsigned fpr, i; \
909 fpr = (x) & ~(cop1_64bit(xcp) == 0); \
910 set_fpr64(&ctx->fpr[fpr], 0, di); \
911 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \
912 set_fpr64(&ctx->fpr[fpr], i, 0); \
913} while (0)
1da177e4 914
21a151d8
RB		 915#define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
916#define SPTOREG(sp, x) SITOREG((sp).bits, x)
917#define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
918#define DPTOREG(dp, x) DITOREG((dp).bits, x)
1da177e4
LT		 919
920/*
921 * Emulate the single floating point instruction pointed at by EPC.
922 * Two instructions if the instruction is in a branch delay slot.
923 */
924
515b029d 925static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
102cedc3 926 struct mm_decoded_insn dec_insn, void *__user *fault_addr)
1da177e4
LT		 927{
928 mips_instruction ir;
102cedc3 929 unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
1da177e4 930 unsigned int cond;
102cedc3 931 int pc_inc;
1da177e4
LT		 932
933 /* XXX NEC Vr54xx bug workaround */
e7e9cae5 934 if (delay_slot(xcp)) {
102cedc3
LY		 935 if (dec_insn.micro_mips_mode) {
936 if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
e7e9cae5 937 clear_delay_slot(xcp);
102cedc3
LY		 938 } else {
939 if (!isBranchInstr(xcp, dec_insn, &contpc))
e7e9cae5 940 clear_delay_slot(xcp);
102cedc3
LY		 941 }
942 }
1da177e4 943
e7e9cae5 944 if (delay_slot(xcp)) {
1da177e4
LT		 945 /*
946 * The instruction to be emulated is in a branch delay slot
70342287 947 * which means that we have to emulate the branch instruction
1da177e4
LT		 948 * BEFORE we do the cop1 instruction.
949 *
950 * This branch could be a COP1 branch, but in that case we
951 * would have had a trap for that instruction, and would not
952 * come through this route.
953 *
954 * Linux MIPS branch emulator operates on context, updating the
955 * cp0_epc.
956 */
102cedc3
LY		 957 ir = dec_insn.next_insn; /* process delay slot instr */
958 pc_inc = dec_insn.next_pc_inc;
959 } else {
960 ir = dec_insn.insn; /* process current instr */
961 pc_inc = dec_insn.pc_inc;
962 }
1da177e4 963
102cedc3
LY		 964 /*
965 * Since microMIPS FPU instructios are a subset of MIPS32 FPU
966 * instructions, we want to convert microMIPS FPU instructions
967 * into MIPS32 instructions so that we could reuse all of the
968 * FPU emulation code.
969 *
970 * NOTE: We cannot do this for branch instructions since they
971 * are not a subset. Example: Cannot emulate a 16-bit
972 * aligned target address with a MIPS32 instruction.
973 */
974 if (dec_insn.micro_mips_mode) {
975 /*
976 * If next instruction is a 16-bit instruction, then it
977 * it cannot be a FPU instruction. This could happen
978 * since we can be called for non-FPU instructions.
979 */
980 if ((pc_inc == 2) ||
981 (microMIPS32_to_MIPS32((union mips_instruction *)&ir)
982 == SIGILL))
1da177e4 983 return SIGILL;
1da177e4
LT		 984 }
985
986 emul:
a8b0ca17 987 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
b6ee75ed 988 MIPS_FPU_EMU_INC_STATS(emulated);
1da177e4 989 switch (MIPSInst_OPCODE(ir)) {
1da177e4 990 case ldc1_op:{
3fccc015 991 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1da177e4
LT		 992 MIPSInst_SIMM(ir));
993 u64 val;
994
b6ee75ed 995 MIPS_FPU_EMU_INC_STATS(loads);
515b029d
DD		 996
997 if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
b6ee75ed 998 MIPS_FPU_EMU_INC_STATS(errors);
515b029d 999 *fault_addr = va;
1da177e4
LT		 1000 return SIGBUS;
1001 }
515b029d
DD		 1002 if (__get_user(val, va)) {
1003 MIPS_FPU_EMU_INC_STATS(errors);
1004 *fault_addr = va;
1005 return SIGSEGV;
1006 }
1da177e4
LT		 1007 DITOREG(val, MIPSInst_RT(ir));
1008 break;
1009 }
1010
1011 case sdc1_op:{
3fccc015 1012 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1da177e4
LT		 1013 MIPSInst_SIMM(ir));
1014 u64 val;
1015
b6ee75ed 1016 MIPS_FPU_EMU_INC_STATS(stores);
1da177e4 1017 DIFROMREG(val, MIPSInst_RT(ir));
515b029d 1018 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
b6ee75ed 1019 MIPS_FPU_EMU_INC_STATS(errors);
515b029d 1020 *fault_addr = va;
1da177e4
LT		 1021 return SIGBUS;
1022 }
515b029d
DD		 1023 if (__put_user(val, va)) {
1024 MIPS_FPU_EMU_INC_STATS(errors);
1025 *fault_addr = va;
1026 return SIGSEGV;
1027 }
1da177e4
LT		 1028 break;
1029 }
1da177e4
LT		 1030
1031 case lwc1_op:{
3fccc015 1032 u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1da177e4
LT		 1033 MIPSInst_SIMM(ir));
1034 u32 val;
1035
b6ee75ed 1036 MIPS_FPU_EMU_INC_STATS(loads);
515b029d 1037 if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
b6ee75ed 1038 MIPS_FPU_EMU_INC_STATS(errors);
515b029d 1039 *fault_addr = va;
1da177e4
LT		 1040 return SIGBUS;
1041 }
515b029d
DD		 1042 if (__get_user(val, va)) {
1043 MIPS_FPU_EMU_INC_STATS(errors);
1044 *fault_addr = va;
1045 return SIGSEGV;
1046 }
1da177e4
LT		 1047 SITOREG(val, MIPSInst_RT(ir));
1048 break;
1049 }
1050
1051 case swc1_op:{
3fccc015 1052 u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1da177e4
LT		 1053 MIPSInst_SIMM(ir));
1054 u32 val;
1055
b6ee75ed 1056 MIPS_FPU_EMU_INC_STATS(stores);
1da177e4 1057 SIFROMREG(val, MIPSInst_RT(ir));
515b029d 1058 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
b6ee75ed 1059 MIPS_FPU_EMU_INC_STATS(errors);
515b029d 1060 *fault_addr = va;
1da177e4
LT		 1061 return SIGBUS;
1062 }
515b029d
DD		 1063 if (__put_user(val, va)) {
1064 MIPS_FPU_EMU_INC_STATS(errors);
1065 *fault_addr = va;
1066 return SIGSEGV;
1067 }
1da177e4
LT		 1068 break;
1069 }
1070
1071 case cop1_op:
1072 switch (MIPSInst_RS(ir)) {
1073
4b724efd 1074#if defined(__mips64)
1da177e4
LT		 1075 case dmfc_op:
1076 /* copregister fs -> gpr[rt] */
1077 if (MIPSInst_RT(ir) != 0) {
1078 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1079 MIPSInst_RD(ir));
1080 }
1081 break;
1082
1083 case dmtc_op:
1084 /* copregister fs <- rt */
1085 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1086 break;
1087#endif
1088
1ac94400
LY		 1089 case mfhc_op:
1090 if (!cpu_has_mips_r2)
1091 goto sigill;
1092
1093 /* copregister rd -> gpr[rt] */
1094 if (MIPSInst_RT(ir) != 0) {
1095 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
1096 MIPSInst_RD(ir));
1097 }
1098 break;
1099
1100 case mthc_op:
1101 if (!cpu_has_mips_r2)
1102 goto sigill;
1103
1104 /* copregister rd <- gpr[rt] */
1105 SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1106 break;
1107
1da177e4
LT		 1108 case mfc_op:
1109 /* copregister rd -> gpr[rt] */
1da177e4
LT		 1110 if (MIPSInst_RT(ir) != 0) {
1111 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1112 MIPSInst_RD(ir));
1113 }
1114 break;
1115
1116 case mtc_op:
1117 /* copregister rd <- rt */
1da177e4
LT		 1118 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1119 break;
1120
1121 case cfc_op:{
1122 /* cop control register rd -> gpr[rt] */
1123 u32 value;
1124
1da177e4
LT		 1125 if (MIPSInst_RD(ir) == FPCREG_CSR) {
1126 value = ctx->fcr31;
3f135530
SM		 1127 value = (value & ~FPU_CSR_RM) |
1128 mips_rm[modeindex(value)];
1da177e4
LT		 1129#ifdef CSRTRACE
1130 printk("%p gpr[%d]<-csr=%08x\n",
333d1f67 1131 (void *) (xcp->cp0_epc),
1da177e4
LT		 1132 MIPSInst_RT(ir), value);
1133#endif
1134 }
1135 else if (MIPSInst_RD(ir) == FPCREG_RID)
1136 value = 0;
1137 else
1138 value = 0;
1139 if (MIPSInst_RT(ir))
1140 xcp->regs[MIPSInst_RT(ir)] = value;
1141 break;
1142 }
1143
1144 case ctc_op:{
1145 /* copregister rd <- rt */
1146 u32 value;
1147
1148 if (MIPSInst_RT(ir) == 0)
1149 value = 0;
1150 else
1151 value = xcp->regs[MIPSInst_RT(ir)];
1152
1153 /* we only have one writable control reg
1154 */
1155 if (MIPSInst_RD(ir) == FPCREG_CSR) {
1156#ifdef CSRTRACE
1157 printk("%p gpr[%d]->csr=%08x\n",
333d1f67 1158 (void *) (xcp->cp0_epc),
1da177e4
LT		 1159 MIPSInst_RT(ir), value);
1160#endif
95e8f634
SM		 1161
1162 /*
1163 * Don't write reserved bits,
1164 * and convert to ieee library modes
1165 */
1166 ctx->fcr31 = (value &
1167 ~(FPU_CSR_RSVD | FPU_CSR_RM)) |
1168 ieee_rm[modeindex(value)];
1da177e4
LT		 1169 }
1170 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1171 return SIGFPE;
1172 }
1173 break;
1174 }
1175
1176 case bc_op:{
1177 int likely = 0;
1178
e7e9cae5 1179 if (delay_slot(xcp))
1da177e4
LT		 1180 return SIGILL;
1181
1182#if __mips >= 4
1183 cond = ctx->fcr31 & fpucondbit[MIPSInst_RT(ir) >> 2];
1184#else
1185 cond = ctx->fcr31 & FPU_CSR_COND;
1186#endif
1187 switch (MIPSInst_RT(ir) & 3) {
1188 case bcfl_op:
1189 likely = 1;
1190 case bcf_op:
1191 cond = !cond;
1192 break;
1193 case bctl_op:
1194 likely = 1;
1195 case bct_op:
1196 break;
1197 default:
1198 /* thats an illegal instruction */
1199 return SIGILL;
1200 }
1201
e7e9cae5 1202 set_delay_slot(xcp);
1da177e4
LT		 1203 if (cond) {
1204 /* branch taken: emulate dslot
1205 * instruction
1206 */
102cedc3
LY		 1207 xcp->cp0_epc += dec_insn.pc_inc;
1208
1209 contpc = MIPSInst_SIMM(ir);
1210 ir = dec_insn.next_insn;
1211 if (dec_insn.micro_mips_mode) {
1212 contpc = (xcp->cp0_epc + (contpc << 1));
1213
1214 /* If 16-bit instruction, not FPU. */
1215 if ((dec_insn.next_pc_inc == 2) ||
1216 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) {
1217
1218 /*
1219 * Since this instruction will
1220 * be put on the stack with
1221 * 32-bit words, get around
1222 * this problem by putting a
1223 * NOP16 as the second one.
1224 */
1225 if (dec_insn.next_pc_inc == 2)
1226 ir = (ir & (~0xffff)) | MM_NOP16;
1227
1228 /*
1229 * Single step the non-CP1
1230 * instruction in the dslot.
1231 */
1232 return mips_dsemul(xcp, ir, contpc);
1233 }
1234 } else
1235 contpc = (xcp->cp0_epc + (contpc << 2));
1da177e4
LT		 1236
1237 switch (MIPSInst_OPCODE(ir)) {
1238 case lwc1_op:
1239 case swc1_op:
4b724efd 1240#if (__mips >= 2 || defined(__mips64))
1da177e4
LT		 1241 case ldc1_op:
1242 case sdc1_op:
1243#endif
1244 case cop1_op:
1245#if __mips >= 4 && __mips != 32
1246 case cop1x_op:
1247#endif
1248 /* its one of ours */
1249 goto emul;
1250#if __mips >= 4
1251 case spec_op:
1252 if (MIPSInst_FUNC(ir) == movc_op)
1253 goto emul;
1254 break;
1255#endif
1256 }
1257
1258 /*
1259 * Single step the non-cp1
1260 * instruction in the dslot
1261 */
e70dfc10 1262 return mips_dsemul(xcp, ir, contpc);
1da177e4
LT		 1263 }
1264 else {
1265 /* branch not taken */
1266 if (likely) {
1267 /*
1268 * branch likely nullifies
1269 * dslot if not taken
1270 */
102cedc3
LY		 1271 xcp->cp0_epc += dec_insn.pc_inc;
1272 contpc += dec_insn.pc_inc;
1da177e4
LT		 1273 /*
1274 * else continue & execute
1275 * dslot as normal insn
1276 */
1277 }
1278 }
1279 break;
1280 }
1281
1282 default:
1283 if (!(MIPSInst_RS(ir) & 0x10))
1284 return SIGILL;
1285 {
1286 int sig;
1287
1288 /* a real fpu computation instruction */
1289 if ((sig = fpu_emu(xcp, ctx, ir)))
1290 return sig;
1291 }
1292 }
1293 break;
1294
1295#if __mips >= 4 && __mips != 32
1296 case cop1x_op:{
515b029d
DD		 1297 int sig = fpux_emu(xcp, ctx, ir, fault_addr);
1298 if (sig)
1da177e4
LT		 1299 return sig;
1300 break;
1301 }
1302#endif
1303
1304#if __mips >= 4
1305 case spec_op:
1306 if (MIPSInst_FUNC(ir) != movc_op)
1307 return SIGILL;
1308 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
1309 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
1310 xcp->regs[MIPSInst_RD(ir)] =
1311 xcp->regs[MIPSInst_RS(ir)];
1312 break;
1313#endif
1314
1315 default:
1ac94400 1316sigill:
1da177e4
LT		 1317 return SIGILL;
1318 }
1319
1320 /* we did it !! */
e70dfc10 1321 xcp->cp0_epc = contpc;
e7e9cae5 1322 clear_delay_slot(xcp);
333d1f67 1323
1da177e4
LT		 1324 return 0;
1325}
1326
1327/*
1328 * Conversion table from MIPS compare ops 48-63
1329 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1330 */
1331static const unsigned char cmptab[8] = {
1332 0, /* cmp_0 (sig) cmp_sf */
1333 IEEE754_CUN, /* cmp_un (sig) cmp_ngle */
1334 IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */
1335 IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */
1336 IEEE754_CLT, /* cmp_olt (sig) cmp_lt */
1337 IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */
1338 IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */
1339 IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */
1340};
1341
1342
1343#if __mips >= 4 && __mips != 32
1344
1345/*
1346 * Additional MIPS4 instructions
1347 */
1348
1349#define DEF3OP(name, p, f1, f2, f3) \
2209bcb1
RB		 1350static union ieee754##p fpemu_##p##_##name(union ieee754##p r, union ieee754##p s, \
1351 union ieee754##p t) \
1da177e4 1352{ \
cd21dfcf 1353 struct _ieee754_csr ieee754_csr_save; \
49a89efb 1354 s = f1(s, t); \
1da177e4 1355 ieee754_csr_save = ieee754_csr; \
49a89efb 1356 s = f2(s, r); \
1da177e4
LT		 1357 ieee754_csr_save.cx |= ieee754_csr.cx; \
1358 ieee754_csr_save.sx |= ieee754_csr.sx; \
49a89efb 1359 s = f3(s); \
1da177e4
LT		 1360 ieee754_csr.cx |= ieee754_csr_save.cx; \
1361 ieee754_csr.sx |= ieee754_csr_save.sx; \
1362 return s; \
1363}
1364
2209bcb1 1365static union ieee754dp fpemu_dp_recip(union ieee754dp d)
1da177e4
LT		 1366{
1367 return ieee754dp_div(ieee754dp_one(0), d);
1368}
1369
2209bcb1 1370static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d)
1da177e4
LT		 1371{
1372 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
1373}
1374
2209bcb1 1375static union ieee754sp fpemu_sp_recip(union ieee754sp s)
1da177e4
LT		 1376{
1377 return ieee754sp_div(ieee754sp_one(0), s);
1378}
1379
2209bcb1 1380static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s)
1da177e4
LT		 1381{
1382 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
1383}
1384
21a151d8
RB		 1385DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
1386DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
1da177e4
LT		 1387DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
1388DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
21a151d8
RB		 1389DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
1390DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
1da177e4
LT		 1391DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
1392DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
1393
eae89076 1394static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
515b029d 1395 mips_instruction ir, void *__user *fault_addr)
1da177e4
LT		 1396{
1397 unsigned rcsr = 0; /* resulting csr */
1398
b6ee75ed 1399 MIPS_FPU_EMU_INC_STATS(cp1xops);
1da177e4
LT		 1400
1401 switch (MIPSInst_FMA_FFMT(ir)) {
1402 case s_fmt:{ /* 0 */
1403
2209bcb1
RB		 1404 union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp);
1405 union ieee754sp fd, fr, fs, ft;
3fccc015 1406 u32 __user *va;
1da177e4
LT		 1407 u32 val;
1408
1409 switch (MIPSInst_FUNC(ir)) {
1410 case lwxc1_op:
3fccc015 1411 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1da177e4
LT		 1412 xcp->regs[MIPSInst_FT(ir)]);
1413
b6ee75ed 1414 MIPS_FPU_EMU_INC_STATS(loads);
515b029d 1415 if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
b6ee75ed 1416 MIPS_FPU_EMU_INC_STATS(errors);
515b029d 1417 *fault_addr = va;
1da177e4
LT		 1418 return SIGBUS;
1419 }
515b029d
DD		 1420 if (__get_user(val, va)) {
1421 MIPS_FPU_EMU_INC_STATS(errors);
1422 *fault_addr = va;
1423 return SIGSEGV;
1424 }
1da177e4
LT		 1425 SITOREG(val, MIPSInst_FD(ir));
1426 break;
1427
1428 case swxc1_op:
3fccc015 1429 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1da177e4
LT		 1430 xcp->regs[MIPSInst_FT(ir)]);
1431
b6ee75ed 1432 MIPS_FPU_EMU_INC_STATS(stores);
1da177e4
LT		 1433
1434 SIFROMREG(val, MIPSInst_FS(ir));
515b029d 1435 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
b6ee75ed 1436 MIPS_FPU_EMU_INC_STATS(errors);
515b029d 1437 *fault_addr = va;
1da177e4
LT		 1438 return SIGBUS;
1439 }
515b029d
DD		 1440 if (put_user(val, va)) {
1441 MIPS_FPU_EMU_INC_STATS(errors);
1442 *fault_addr = va;
1443 return SIGSEGV;
1444 }
1da177e4
LT		 1445 break;
1446
1447 case madd_s_op:
1448 handler = fpemu_sp_madd;
1449 goto scoptop;
1450 case msub_s_op:
1451 handler = fpemu_sp_msub;
1452 goto scoptop;
1453 case nmadd_s_op:
1454 handler = fpemu_sp_nmadd;
1455 goto scoptop;
1456 case nmsub_s_op:
1457 handler = fpemu_sp_nmsub;
1458 goto scoptop;
1459
1460 scoptop:
1461 SPFROMREG(fr, MIPSInst_FR(ir));
1462 SPFROMREG(fs, MIPSInst_FS(ir));
1463 SPFROMREG(ft, MIPSInst_FT(ir));
1464 fd = (*handler) (fr, fs, ft);
1465 SPTOREG(fd, MIPSInst_FD(ir));
1466
1467 copcsr:
1468 if (ieee754_cxtest(IEEE754_INEXACT))
1469 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1470 if (ieee754_cxtest(IEEE754_UNDERFLOW))
1471 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1472 if (ieee754_cxtest(IEEE754_OVERFLOW))
1473 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1474 if (ieee754_cxtest(IEEE754_INVALID_OPERATION))
1475 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1476
1477 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1da177e4
LT		 1478 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1479 /*printk ("SIGFPE: fpu csr = %08x\n",
1480 ctx->fcr31); */
1481 return SIGFPE;
1482 }
1483
1484 break;
1485
1486 default:
1487 return SIGILL;
1488 }
1489 break;
1490 }
1491
1da177e4 1492 case d_fmt:{ /* 1 */
2209bcb1
RB		 1493 union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp);
1494 union ieee754dp fd, fr, fs, ft;
3fccc015 1495 u64 __user *va;
1da177e4
LT		 1496 u64 val;
1497
1498 switch (MIPSInst_FUNC(ir)) {
1499 case ldxc1_op:
3fccc015 1500 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1da177e4
LT		 1501 xcp->regs[MIPSInst_FT(ir)]);
1502
b6ee75ed 1503 MIPS_FPU_EMU_INC_STATS(loads);
515b029d 1504 if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
b6ee75ed 1505 MIPS_FPU_EMU_INC_STATS(errors);
515b029d 1506 *fault_addr = va;
1da177e4
LT		 1507 return SIGBUS;
1508 }
515b029d
DD		 1509 if (__get_user(val, va)) {
1510 MIPS_FPU_EMU_INC_STATS(errors);
1511 *fault_addr = va;
1512 return SIGSEGV;
1513 }
1da177e4
LT		 1514 DITOREG(val, MIPSInst_FD(ir));
1515 break;
1516
1517 case sdxc1_op:
3fccc015 1518 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1da177e4
LT		 1519 xcp->regs[MIPSInst_FT(ir)]);
1520
b6ee75ed 1521 MIPS_FPU_EMU_INC_STATS(stores);
1da177e4 1522 DIFROMREG(val, MIPSInst_FS(ir));
515b029d 1523 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
b6ee75ed 1524 MIPS_FPU_EMU_INC_STATS(errors);
515b029d 1525 *fault_addr = va;
1da177e4
LT		 1526 return SIGBUS;
1527 }
515b029d
DD		 1528 if (__put_user(val, va)) {
1529 MIPS_FPU_EMU_INC_STATS(errors);
1530 *fault_addr = va;
1531 return SIGSEGV;
1532 }
1da177e4
LT		 1533 break;
1534
1535 case madd_d_op:
1536 handler = fpemu_dp_madd;
1537 goto dcoptop;
1538 case msub_d_op:
1539 handler = fpemu_dp_msub;
1540 goto dcoptop;
1541 case nmadd_d_op:
1542 handler = fpemu_dp_nmadd;
1543 goto dcoptop;
1544 case nmsub_d_op:
1545 handler = fpemu_dp_nmsub;
1546 goto dcoptop;
1547
1548 dcoptop:
1549 DPFROMREG(fr, MIPSInst_FR(ir));
1550 DPFROMREG(fs, MIPSInst_FS(ir));
1551 DPFROMREG(ft, MIPSInst_FT(ir));
1552 fd = (*handler) (fr, fs, ft);
1553 DPTOREG(fd, MIPSInst_FD(ir));
1554 goto copcsr;
1555
1556 default:
1557 return SIGILL;
1558 }
1559 break;
1560 }
1da177e4 1561
51061b88
DCZ		 1562 case 0x3:
1563 if (MIPSInst_FUNC(ir) != pfetch_op)
1da177e4 1564 return SIGILL;
51061b88 1565
1da177e4
LT		 1566 /* ignore prefx operation */
1567 break;
1568
1569 default:
1570 return SIGILL;
1571 }
1572
1573 return 0;
1574}
1575#endif
1576
1577
1578
1579/*
1580 * Emulate a single COP1 arithmetic instruction.
1581 */
eae89076 1582static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1da177e4
LT		 1583 mips_instruction ir)
1584{
1585 int rfmt; /* resulting format */
1586 unsigned rcsr = 0; /* resulting csr */
1587 unsigned cond;
1588 union {
2209bcb1
RB		 1589 union ieee754dp d;
1590 union ieee754sp s;
1da177e4 1591 int w;
766160c2 1592#ifdef __mips64
1da177e4
LT		 1593 s64 l;
1594#endif
1595 } rv; /* resulting value */
1596
b6ee75ed 1597 MIPS_FPU_EMU_INC_STATS(cp1ops);
1da177e4
LT		 1598 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
1599 case s_fmt:{ /* 0 */
1600 union {
2209bcb1
RB		 1601 union ieee754sp(*b) (union ieee754sp, union ieee754sp);
1602 union ieee754sp(*u) (union ieee754sp);
1da177e4
LT		 1603 } handler;
1604
1605 switch (MIPSInst_FUNC(ir)) {
1606 /* binary ops */
1607 case fadd_op:
1608 handler.b = ieee754sp_add;
1609 goto scopbop;
1610 case fsub_op:
1611 handler.b = ieee754sp_sub;
1612 goto scopbop;
1613 case fmul_op:
1614 handler.b = ieee754sp_mul;
1615 goto scopbop;
1616 case fdiv_op:
1617 handler.b = ieee754sp_div;
1618 goto scopbop;
1619
1620 /* unary ops */
587cb98f 1621#if __mips >= 2 || defined(__mips64)
1da177e4
LT		 1622 case fsqrt_op:
1623 handler.u = ieee754sp_sqrt;
1624 goto scopuop;
1625#endif
1626#if __mips >= 4 && __mips != 32
1627 case frsqrt_op:
1628 handler.u = fpemu_sp_rsqrt;
1629 goto scopuop;
1630 case frecip_op:
1631 handler.u = fpemu_sp_recip;
1632 goto scopuop;
1633#endif
1634#if __mips >= 4
1635 case fmovc_op:
1636 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1637 if (((ctx->fcr31 & cond) != 0) !=
1638 ((MIPSInst_FT(ir) & 1) != 0))
1639 return 0;
1640 SPFROMREG(rv.s, MIPSInst_FS(ir));
1641 break;
1642 case fmovz_op:
1643 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1644 return 0;
1645 SPFROMREG(rv.s, MIPSInst_FS(ir));
1646 break;
1647 case fmovn_op:
1648 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1649 return 0;
1650 SPFROMREG(rv.s, MIPSInst_FS(ir));
1651 break;
1652#endif
1653 case fabs_op:
1654 handler.u = ieee754sp_abs;
1655 goto scopuop;
1656 case fneg_op:
1657 handler.u = ieee754sp_neg;
1658 goto scopuop;
1659 case fmov_op:
1660 /* an easy one */
1661 SPFROMREG(rv.s, MIPSInst_FS(ir));
1662 goto copcsr;
1663
1664 /* binary op on handler */
1665 scopbop:
1666 {
2209bcb1 1667 union ieee754sp fs, ft;
1da177e4
LT		 1668
1669 SPFROMREG(fs, MIPSInst_FS(ir));
1670 SPFROMREG(ft, MIPSInst_FT(ir));
1671
1672 rv.s = (*handler.b) (fs, ft);
1673 goto copcsr;
1674 }
1675 scopuop:
1676 {
2209bcb1 1677 union ieee754sp fs;
1da177e4
LT		 1678
1679 SPFROMREG(fs, MIPSInst_FS(ir));
1680 rv.s = (*handler.u) (fs);
1681 goto copcsr;
1682 }
1683 copcsr:
1684 if (ieee754_cxtest(IEEE754_INEXACT))
1685 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1686 if (ieee754_cxtest(IEEE754_UNDERFLOW))
1687 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1688 if (ieee754_cxtest(IEEE754_OVERFLOW))
1689 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1690 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE))
1691 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
1692 if (ieee754_cxtest(IEEE754_INVALID_OPERATION))
1693 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1694 break;
1695
1696 /* unary conv ops */
1697 case fcvts_op:
1698 return SIGILL; /* not defined */
1699 case fcvtd_op:{
2209bcb1 1700 union ieee754sp fs;
1da177e4
LT		 1701
1702 SPFROMREG(fs, MIPSInst_FS(ir));
1703 rv.d = ieee754dp_fsp(fs);
1704 rfmt = d_fmt;
1705 goto copcsr;
1706 }
1da177e4 1707 case fcvtw_op:{
2209bcb1 1708 union ieee754sp fs;
1da177e4
LT		 1709
1710 SPFROMREG(fs, MIPSInst_FS(ir));
1711 rv.w = ieee754sp_tint(fs);
1712 rfmt = w_fmt;
1713 goto copcsr;
1714 }
1715
587cb98f 1716#if __mips >= 2 || defined(__mips64)
1da177e4
LT		 1717 case fround_op:
1718 case ftrunc_op:
1719 case fceil_op:
1720 case ffloor_op:{
1721 unsigned int oldrm = ieee754_csr.rm;
2209bcb1 1722 union ieee754sp fs;
1da177e4
LT		 1723
1724 SPFROMREG(fs, MIPSInst_FS(ir));
3f135530 1725 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1da177e4
LT		 1726 rv.w = ieee754sp_tint(fs);
1727 ieee754_csr.rm = oldrm;
1728 rfmt = w_fmt;
1729 goto copcsr;
1730 }
1731#endif /* __mips >= 2 */
1732
4b724efd 1733#if defined(__mips64)
1da177e4 1734 case fcvtl_op:{
2209bcb1 1735 union ieee754sp fs;
1da177e4
LT		 1736
1737 SPFROMREG(fs, MIPSInst_FS(ir));
1738 rv.l = ieee754sp_tlong(fs);
1739 rfmt = l_fmt;
1740 goto copcsr;
1741 }
1742
1743 case froundl_op:
1744 case ftruncl_op:
1745 case fceill_op:
1746 case ffloorl_op:{
1747 unsigned int oldrm = ieee754_csr.rm;
2209bcb1 1748 union ieee754sp fs;
1da177e4
LT		 1749
1750 SPFROMREG(fs, MIPSInst_FS(ir));
3f135530 1751 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1da177e4
LT		 1752 rv.l = ieee754sp_tlong(fs);
1753 ieee754_csr.rm = oldrm;
1754 rfmt = l_fmt;
1755 goto copcsr;
1756 }
4b724efd 1757#endif /* defined(__mips64) */
1da177e4
LT		 1758
1759 default:
1760 if (MIPSInst_FUNC(ir) >= fcmp_op) {
1761 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
2209bcb1 1762 union ieee754sp fs, ft;
1da177e4
LT		 1763
1764 SPFROMREG(fs, MIPSInst_FS(ir));
1765 SPFROMREG(ft, MIPSInst_FT(ir));
1766 rv.w = ieee754sp_cmp(fs, ft,
1767 cmptab[cmpop & 0x7], cmpop & 0x8);
1768 rfmt = -1;
1769 if ((cmpop & 0x8) && ieee754_cxtest
1770 (IEEE754_INVALID_OPERATION))
1771 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1772 else
1773 goto copcsr;
1774
1775 }
1776 else {
1777 return SIGILL;
1778 }
1779 break;
1780 }
1781 break;
1782 }
1783
1da177e4
LT		 1784 case d_fmt:{
1785 union {
2209bcb1
RB		 1786 union ieee754dp(*b) (union ieee754dp, union ieee754dp);
1787 union ieee754dp(*u) (union ieee754dp);
1da177e4
LT		 1788 } handler;
1789
1790 switch (MIPSInst_FUNC(ir)) {
1791 /* binary ops */
1792 case fadd_op:
1793 handler.b = ieee754dp_add;
1794 goto dcopbop;
1795 case fsub_op:
1796 handler.b = ieee754dp_sub;
1797 goto dcopbop;
1798 case fmul_op:
1799 handler.b = ieee754dp_mul;
1800 goto dcopbop;
1801 case fdiv_op:
1802 handler.b = ieee754dp_div;
1803 goto dcopbop;
1804
1805 /* unary ops */
587cb98f 1806#if __mips >= 2 || defined(__mips64)
1da177e4
LT		 1807 case fsqrt_op:
1808 handler.u = ieee754dp_sqrt;
1809 goto dcopuop;
1810#endif
1811#if __mips >= 4 && __mips != 32
1812 case frsqrt_op:
1813 handler.u = fpemu_dp_rsqrt;
1814 goto dcopuop;
1815 case frecip_op:
1816 handler.u = fpemu_dp_recip;
1817 goto dcopuop;
1818#endif
1819#if __mips >= 4
1820 case fmovc_op:
1821 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1822 if (((ctx->fcr31 & cond) != 0) !=
1823 ((MIPSInst_FT(ir) & 1) != 0))
1824 return 0;
1825 DPFROMREG(rv.d, MIPSInst_FS(ir));
1826 break;
1827 case fmovz_op:
1828 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1829 return 0;
1830 DPFROMREG(rv.d, MIPSInst_FS(ir));
1831 break;
1832 case fmovn_op:
1833 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1834 return 0;
1835 DPFROMREG(rv.d, MIPSInst_FS(ir));
1836 break;
1837#endif
1838 case fabs_op:
1839 handler.u = ieee754dp_abs;
1840 goto dcopuop;
1841
1842 case fneg_op:
1843 handler.u = ieee754dp_neg;
1844 goto dcopuop;
1845
1846 case fmov_op:
1847 /* an easy one */
1848 DPFROMREG(rv.d, MIPSInst_FS(ir));
1849 goto copcsr;
1850
1851 /* binary op on handler */
1852 dcopbop:{
2209bcb1 1853 union ieee754dp fs, ft;
1da177e4
LT		 1854
1855 DPFROMREG(fs, MIPSInst_FS(ir));
1856 DPFROMREG(ft, MIPSInst_FT(ir));
1857
1858 rv.d = (*handler.b) (fs, ft);
1859 goto copcsr;
1860 }
1861 dcopuop:{
2209bcb1 1862 union ieee754dp fs;
1da177e4
LT		 1863
1864 DPFROMREG(fs, MIPSInst_FS(ir));
1865 rv.d = (*handler.u) (fs);
1866 goto copcsr;
1867 }
1868
1869 /* unary conv ops */
1870 case fcvts_op:{
2209bcb1 1871 union ieee754dp fs;
1da177e4
LT		 1872
1873 DPFROMREG(fs, MIPSInst_FS(ir));
1874 rv.s = ieee754sp_fdp(fs);
1875 rfmt = s_fmt;
1876 goto copcsr;
1877 }
1878 case fcvtd_op:
1879 return SIGILL; /* not defined */
1880
1881 case fcvtw_op:{
2209bcb1 1882 union ieee754dp fs;
1da177e4
LT		 1883
1884 DPFROMREG(fs, MIPSInst_FS(ir));
1885 rv.w = ieee754dp_tint(fs); /* wrong */
1886 rfmt = w_fmt;
1887 goto copcsr;
1888 }
1889
587cb98f 1890#if __mips >= 2 || defined(__mips64)
1da177e4
LT		 1891 case fround_op:
1892 case ftrunc_op:
1893 case fceil_op:
1894 case ffloor_op:{
1895 unsigned int oldrm = ieee754_csr.rm;
2209bcb1 1896 union ieee754dp fs;
1da177e4
LT		 1897
1898 DPFROMREG(fs, MIPSInst_FS(ir));
3f135530 1899 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1da177e4
LT		 1900 rv.w = ieee754dp_tint(fs);
1901 ieee754_csr.rm = oldrm;
1902 rfmt = w_fmt;
1903 goto copcsr;
1904 }
1905#endif
1906
4b724efd 1907#if defined(__mips64)
1da177e4 1908 case fcvtl_op:{
2209bcb1 1909 union ieee754dp fs;
1da177e4
LT		 1910
1911 DPFROMREG(fs, MIPSInst_FS(ir));
1912 rv.l = ieee754dp_tlong(fs);
1913 rfmt = l_fmt;
1914 goto copcsr;
1915 }
1916
1917 case froundl_op:
1918 case ftruncl_op:
1919 case fceill_op:
1920 case ffloorl_op:{
1921 unsigned int oldrm = ieee754_csr.rm;
2209bcb1 1922 union ieee754dp fs;
1da177e4
LT		 1923
1924 DPFROMREG(fs, MIPSInst_FS(ir));
3f135530 1925 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1da177e4
LT		 1926 rv.l = ieee754dp_tlong(fs);
1927 ieee754_csr.rm = oldrm;
1928 rfmt = l_fmt;
1929 goto copcsr;
1930 }
4b724efd 1931#endif /* __mips >= 3 */
1da177e4
LT		 1932
1933 default:
1934 if (MIPSInst_FUNC(ir) >= fcmp_op) {
1935 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
2209bcb1 1936 union ieee754dp fs, ft;
1da177e4
LT		 1937
1938 DPFROMREG(fs, MIPSInst_FS(ir));
1939 DPFROMREG(ft, MIPSInst_FT(ir));
1940 rv.w = ieee754dp_cmp(fs, ft,
1941 cmptab[cmpop & 0x7], cmpop & 0x8);
1942 rfmt = -1;
1943 if ((cmpop & 0x8)
1944 &&
1945 ieee754_cxtest
1946 (IEEE754_INVALID_OPERATION))
1947 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1948 else
1949 goto copcsr;
1950
1951 }
1952 else {
1953 return SIGILL;
1954 }
1955 break;
1956 }
1957 break;
1958 }
1da177e4
LT		 1959
1960 case w_fmt:{
2209bcb1 1961 union ieee754sp fs;
1da177e4
LT		 1962
1963 switch (MIPSInst_FUNC(ir)) {
1964 case fcvts_op:
1965 /* convert word to single precision real */
1966 SPFROMREG(fs, MIPSInst_FS(ir));
1967 rv.s = ieee754sp_fint(fs.bits);
1968 rfmt = s_fmt;
1969 goto copcsr;
1da177e4
LT		 1970 case fcvtd_op:
1971 /* convert word to double precision real */
1972 SPFROMREG(fs, MIPSInst_FS(ir));
1973 rv.d = ieee754dp_fint(fs.bits);
1974 rfmt = d_fmt;
1975 goto copcsr;
1da177e4
LT		 1976 default:
1977 return SIGILL;
1978 }
1979 break;
1980 }
1981
4b724efd 1982#if defined(__mips64)
1da177e4 1983 case l_fmt:{
bbd426f5
PB		 1984 u64 bits;
1985 DIFROMREG(bits, MIPSInst_FS(ir));
1986
1da177e4
LT		 1987 switch (MIPSInst_FUNC(ir)) {
1988 case fcvts_op:
1989 /* convert long to single precision real */
bbd426f5 1990 rv.s = ieee754sp_flong(bits);
1da177e4
LT		 1991 rfmt = s_fmt;
1992 goto copcsr;
1993 case fcvtd_op:
1994 /* convert long to double precision real */
bbd426f5 1995 rv.d = ieee754dp_flong(bits);
1da177e4
LT		 1996 rfmt = d_fmt;
1997 goto copcsr;
1998 default:
1999 return SIGILL;
2000 }
2001 break;
2002 }
2003#endif
2004
2005 default:
2006 return SIGILL;
2007 }
2008
2009 /*
2010 * Update the fpu CSR register for this operation.
2011 * If an exception is required, generate a tidy SIGFPE exception,
2012 * without updating the result register.
2013 * Note: cause exception bits do not accumulate, they are rewritten
2014 * for each op; only the flag/sticky bits accumulate.
2015 */
2016 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
2017 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
2018 /*printk ("SIGFPE: fpu csr = %08x\n",ctx->fcr31); */
2019 return SIGFPE;
2020 }
2021
2022 /*
2023 * Now we can safely write the result back to the register file.
2024 */
2025 switch (rfmt) {
2026 case -1:{
2027#if __mips >= 4
2028 cond = fpucondbit[MIPSInst_FD(ir) >> 2];
2029#else
2030 cond = FPU_CSR_COND;
2031#endif
2032 if (rv.w)
2033 ctx->fcr31 |= cond;
2034 else
2035 ctx->fcr31 &= ~cond;
2036 break;
2037 }
1da177e4
LT		 2038 case d_fmt:
2039 DPTOREG(rv.d, MIPSInst_FD(ir));
2040 break;
1da177e4
LT		 2041 case s_fmt:
2042 SPTOREG(rv.s, MIPSInst_FD(ir));
2043 break;
2044 case w_fmt:
2045 SITOREG(rv.w, MIPSInst_FD(ir));
2046 break;
4b724efd 2047#if defined(__mips64)
1da177e4
LT		 2048 case l_fmt:
2049 DITOREG(rv.l, MIPSInst_FD(ir));
2050 break;
2051#endif
2052 default:
2053 return SIGILL;
2054 }
2055
2056 return 0;
2057}
2058
e04582b7 2059int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
515b029d 2060 int has_fpu, void *__user *fault_addr)
1da177e4 2061{
333d1f67 2062 unsigned long oldepc, prevepc;
102cedc3
LY		 2063 struct mm_decoded_insn dec_insn;
2064 u16 instr[4];
2065 u16 *instr_ptr;
1da177e4
LT		 2066 int sig = 0;
2067
2068 oldepc = xcp->cp0_epc;
2069 do {
2070 prevepc = xcp->cp0_epc;
2071
102cedc3
LY		 2072 if (get_isa16_mode(prevepc) && cpu_has_mmips) {
2073 /*
2074 * Get next 2 microMIPS instructions and convert them
2075 * into 32-bit instructions.
2076 */
2077 if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) ||
2078 (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) ||
2079 (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) ||
2080 (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) {
2081 MIPS_FPU_EMU_INC_STATS(errors);
2082 return SIGBUS;
2083 }
2084 instr_ptr = instr;
2085
2086 /* Get first instruction. */
2087 if (mm_insn_16bit(*instr_ptr)) {
2088 /* Duplicate the half-word. */
2089 dec_insn.insn = (*instr_ptr << 16) |
2090 (*instr_ptr);
2091 /* 16-bit instruction. */
2092 dec_insn.pc_inc = 2;
2093 instr_ptr += 1;
2094 } else {
2095 dec_insn.insn = (*instr_ptr << 16) |
2096 *(instr_ptr+1);
2097 /* 32-bit instruction. */
2098 dec_insn.pc_inc = 4;
2099 instr_ptr += 2;
2100 }
2101 /* Get second instruction. */
2102 if (mm_insn_16bit(*instr_ptr)) {
2103 /* Duplicate the half-word. */
2104 dec_insn.next_insn = (*instr_ptr << 16) |
2105 (*instr_ptr);
2106 /* 16-bit instruction. */
2107 dec_insn.next_pc_inc = 2;
2108 } else {
2109 dec_insn.next_insn = (*instr_ptr << 16) |
2110 *(instr_ptr+1);
2111 /* 32-bit instruction. */
2112 dec_insn.next_pc_inc = 4;
2113 }
2114 dec_insn.micro_mips_mode = 1;
2115 } else {
2116 if ((get_user(dec_insn.insn,
2117 (mips_instruction __user *) xcp->cp0_epc)) ||
2118 (get_user(dec_insn.next_insn,
2119 (mips_instruction __user *)(xcp->cp0_epc+4)))) {
2120 MIPS_FPU_EMU_INC_STATS(errors);
2121 return SIGBUS;
2122 }
2123 dec_insn.pc_inc = 4;
2124 dec_insn.next_pc_inc = 4;
2125 dec_insn.micro_mips_mode = 0;
515b029d 2126 }
102cedc3
LY		 2127
2128 if ((dec_insn.insn == 0) ||
2129 ((dec_insn.pc_inc == 2) &&
2130 ((dec_insn.insn & 0xffff) == MM_NOP16)))
2131 xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */
1da177e4 2132 else {
cd21dfcf
RB		 2133 /*
2134 * The 'ieee754_csr' is an alias of
70342287
RB		 2135 * ctx->fcr31. No need to copy ctx->fcr31 to
2136 * ieee754_csr. But ieee754_csr.rm is ieee
cd21dfcf
RB		 2137 * library modes. (not mips rounding mode)
2138 */
2139 /* convert to ieee library modes */
2140 ieee754_csr.rm = ieee_rm[ieee754_csr.rm];
102cedc3 2141 sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
cd21dfcf
RB		 2142 /* revert to mips rounding mode */
2143 ieee754_csr.rm = mips_rm[ieee754_csr.rm];
1da177e4
LT		 2144 }
2145
e04582b7 2146 if (has_fpu)
1da177e4
LT		 2147 break;
2148 if (sig)
2149 break;
2150
2151 cond_resched();
2152 } while (xcp->cp0_epc > prevepc);
2153
2154 /* SIGILL indicates a non-fpu instruction */
2155 if (sig == SIGILL && xcp->cp0_epc != oldepc)
2156 /* but if epc has advanced, then ignore it */
2157 sig = 0;
2158
2159 return sig;
2160}
83fd38ca
AN		 2161
2162#ifdef CONFIG_DEBUG_FS
b6ee75ed
DD		 2163
2164static int fpuemu_stat_get(void *data, u64 *val)
2165{
2166 int cpu;
2167 unsigned long sum = 0;
2168 for_each_online_cpu(cpu) {
2169 struct mips_fpu_emulator_stats *ps;
2170 local_t *pv;
2171 ps = &per_cpu(fpuemustats, cpu);
2172 pv = (void *)ps + (unsigned long)data;
2173 sum += local_read(pv);
2174 }
2175 *val = sum;
2176 return 0;
2177}
2178DEFINE_SIMPLE_ATTRIBUTE(fops_fpuemu_stat, fpuemu_stat_get, NULL, "%llu\n");
2179
83fd38ca
AN		 2180extern struct dentry *mips_debugfs_dir;
2181static int __init debugfs_fpuemu(void)
2182{
2183 struct dentry *d, *dir;
83fd38ca
AN		 2184
2185 if (!mips_debugfs_dir)
2186 return -ENODEV;
2187 dir = debugfs_create_dir("fpuemustats", mips_debugfs_dir);
ecab1f44
Z		 2188 if (!dir)
2189 return -ENOMEM;
b6ee75ed
DD		 2190
2191#define FPU_STAT_CREATE(M) \
2192 do { \
2193 d = debugfs_create_file(#M , S_IRUGO, dir, \
2194 (void *)offsetof(struct mips_fpu_emulator_stats, M), \
2195 &fops_fpuemu_stat); \
2196 if (!d) \
2197 return -ENOMEM; \
2198 } while (0)
2199
2200 FPU_STAT_CREATE(emulated);
2201 FPU_STAT_CREATE(loads);
2202 FPU_STAT_CREATE(stores);
2203 FPU_STAT_CREATE(cp1ops);
2204 FPU_STAT_CREATE(cp1xops);
2205 FPU_STAT_CREATE(errors);
2206
83fd38ca
AN		 2207 return 0;
2208}
2209__initcall(debugfs_fpuemu);
2210#endif
Linux 6.x block layer and io_uring tree(s)