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MIPS: math-emu: Turn macros into functions where possible.
[linux-2.6-block.git] / arch / mips / math-emu / cp1emu.c
CommitLineData
1da177e4
LT		 1/*
2 * cp1emu.c: a MIPS coprocessor 1 (fpu) instruction emulator
3 *
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
1da177e4
LT		 6 *
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.
9 *
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
22 *
23 * A complete emulator for MIPS coprocessor 1 instructions. This is
24 * required for #float(switch) or #float(trap), where it catches all
25 * COP1 instructions via the "CoProcessor Unusable" exception.
26 *
27 * More surprisingly it is also required for #float(ieee), to help out
28 * the hardware fpu at the boundaries of the IEEE-754 representation
29 * (denormalised values, infinities, underflow, etc). It is made
30 * quite nasty because emulation of some non-COP1 instructions is
31 * required, e.g. in branch delay slots.
32 *
33 * Note if you know that you won't have an fpu, then you'll get much
34 * better performance by compiling with -msoft-float!
35 */
36#include <linux/sched.h>
83fd38ca 37#include <linux/debugfs.h>
85c51c51 38#include <linux/percpu-defs.h>
7f788d2d 39#include <linux/perf_event.h>
1da177e4 40
cd8ee345 41#include <asm/branch.h>
1da177e4 42#include <asm/inst.h>
1da177e4
LT		 43#include <asm/ptrace.h>
44#include <asm/signal.h>
cd8ee345
RB		 45#include <asm/uaccess.h>
46
47#include <asm/processor.h>
1da177e4 48#include <asm/fpu_emulator.h>
102cedc3 49#include <asm/fpu.h>
1da177e4
LT		 50
51#include "ieee754.h"
1da177e4
LT		 52
53/* Strap kernel emulator for full MIPS IV emulation */
54
55#ifdef __mips
56#undef __mips
57#endif
58#define __mips 4
59
60/* Function which emulates a floating point instruction. */
61
eae89076 62static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
1da177e4
LT		 63 mips_instruction);
64
65#if __mips >= 4 && __mips != 32
66static int fpux_emu(struct pt_regs *,
515b029d 67 struct mips_fpu_struct *, mips_instruction, void *__user *);
1da177e4
LT		 68#endif
69
1da177e4
LT		 70/* Control registers */
71
72#define FPCREG_RID 0 /* $0 = revision id */
73#define FPCREG_CSR 31 /* $31 = csr */
74
95e8f634
SM		 75/* Determine rounding mode from the RM bits of the FCSR */
76#define modeindex(v) ((v) & FPU_CSR_RM)
77
102cedc3
LY		 78/* microMIPS bitfields */
79#define MM_POOL32A_MINOR_MASK 0x3f
80#define MM_POOL32A_MINOR_SHIFT 0x6
81#define MM_MIPS32_COND_FC 0x30
82
1da177e4
LT		 83/* Convert Mips rounding mode (0..3) to IEEE library modes. */
84static const unsigned char ieee_rm[4] = {
cd21dfcf
RB		 85 [FPU_CSR_RN] = IEEE754_RN,
86 [FPU_CSR_RZ] = IEEE754_RZ,
87 [FPU_CSR_RU] = IEEE754_RU,
88 [FPU_CSR_RD] = IEEE754_RD,
89};
90/* Convert IEEE library modes to Mips rounding mode (0..3). */
91static const unsigned char mips_rm[4] = {
92 [IEEE754_RN] = FPU_CSR_RN,
93 [IEEE754_RZ] = FPU_CSR_RZ,
94 [IEEE754_RD] = FPU_CSR_RD,
95 [IEEE754_RU] = FPU_CSR_RU,
1da177e4
LT		 96};
97
98#if __mips >= 4
99/* convert condition code register number to csr bit */
100static const unsigned int fpucondbit[8] = {
101 FPU_CSR_COND0,
102 FPU_CSR_COND1,
103 FPU_CSR_COND2,
104 FPU_CSR_COND3,
105 FPU_CSR_COND4,
106 FPU_CSR_COND5,
107 FPU_CSR_COND6,
108 FPU_CSR_COND7
109};
110#endif
111
102cedc3
LY		 112/* (microMIPS) Convert 16-bit register encoding to 32-bit register encoding. */
113static const unsigned int reg16to32map[8] = {16, 17, 2, 3, 4, 5, 6, 7};
114
115/* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
116static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0};
117static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0};
118static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0};
119static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0};
120
121/*
122 * This functions translates a 32-bit microMIPS instruction
123 * into a 32-bit MIPS32 instruction. Returns 0 on success
124 * and SIGILL otherwise.
125 */
126static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
127{
128 union mips_instruction insn = *insn_ptr;
129 union mips_instruction mips32_insn = insn;
130 int func, fmt, op;
131
132 switch (insn.mm_i_format.opcode) {
133 case mm_ldc132_op:
134 mips32_insn.mm_i_format.opcode = ldc1_op;
135 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
136 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
137 break;
138 case mm_lwc132_op:
139 mips32_insn.mm_i_format.opcode = lwc1_op;
140 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
141 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
142 break;
143 case mm_sdc132_op:
144 mips32_insn.mm_i_format.opcode = sdc1_op;
145 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
146 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
147 break;
148 case mm_swc132_op:
149 mips32_insn.mm_i_format.opcode = swc1_op;
150 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
151 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
152 break;
153 case mm_pool32i_op:
154 /* NOTE: offset is << by 1 if in microMIPS mode. */
155 if ((insn.mm_i_format.rt == mm_bc1f_op) ||
156 (insn.mm_i_format.rt == mm_bc1t_op)) {
157 mips32_insn.fb_format.opcode = cop1_op;
158 mips32_insn.fb_format.bc = bc_op;
159 mips32_insn.fb_format.flag =
160 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0;
161 } else
162 return SIGILL;
163 break;
164 case mm_pool32f_op:
165 switch (insn.mm_fp0_format.func) {
166 case mm_32f_01_op:
167 case mm_32f_11_op:
168 case mm_32f_02_op:
169 case mm_32f_12_op:
170 case mm_32f_41_op:
171 case mm_32f_51_op:
172 case mm_32f_42_op:
173 case mm_32f_52_op:
174 op = insn.mm_fp0_format.func;
175 if (op == mm_32f_01_op)
176 func = madd_s_op;
177 else if (op == mm_32f_11_op)
178 func = madd_d_op;
179 else if (op == mm_32f_02_op)
180 func = nmadd_s_op;
181 else if (op == mm_32f_12_op)
182 func = nmadd_d_op;
183 else if (op == mm_32f_41_op)
184 func = msub_s_op;
185 else if (op == mm_32f_51_op)
186 func = msub_d_op;
187 else if (op == mm_32f_42_op)
188 func = nmsub_s_op;
189 else
190 func = nmsub_d_op;
191 mips32_insn.fp6_format.opcode = cop1x_op;
192 mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr;
193 mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft;
194 mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs;
195 mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd;
196 mips32_insn.fp6_format.func = func;
197 break;
198 case mm_32f_10_op:
199 func = -1; /* Invalid */
200 op = insn.mm_fp5_format.op & 0x7;
201 if (op == mm_ldxc1_op)
202 func = ldxc1_op;
203 else if (op == mm_sdxc1_op)
204 func = sdxc1_op;
205 else if (op == mm_lwxc1_op)
206 func = lwxc1_op;
207 else if (op == mm_swxc1_op)
208 func = swxc1_op;
209
210 if (func != -1) {
211 mips32_insn.r_format.opcode = cop1x_op;
212 mips32_insn.r_format.rs =
213 insn.mm_fp5_format.base;
214 mips32_insn.r_format.rt =
215 insn.mm_fp5_format.index;
216 mips32_insn.r_format.rd = 0;
217 mips32_insn.r_format.re = insn.mm_fp5_format.fd;
218 mips32_insn.r_format.func = func;
219 } else
220 return SIGILL;
221 break;
222 case mm_32f_40_op:
223 op = -1; /* Invalid */
224 if (insn.mm_fp2_format.op == mm_fmovt_op)
225 op = 1;
226 else if (insn.mm_fp2_format.op == mm_fmovf_op)
227 op = 0;
228 if (op != -1) {
229 mips32_insn.fp0_format.opcode = cop1_op;
230 mips32_insn.fp0_format.fmt =
231 sdps_format[insn.mm_fp2_format.fmt];
232 mips32_insn.fp0_format.ft =
233 (insn.mm_fp2_format.cc<<2) + op;
234 mips32_insn.fp0_format.fs =
235 insn.mm_fp2_format.fs;
236 mips32_insn.fp0_format.fd =
237 insn.mm_fp2_format.fd;
238 mips32_insn.fp0_format.func = fmovc_op;
239 } else
240 return SIGILL;
241 break;
242 case mm_32f_60_op:
243 func = -1; /* Invalid */
244 if (insn.mm_fp0_format.op == mm_fadd_op)
245 func = fadd_op;
246 else if (insn.mm_fp0_format.op == mm_fsub_op)
247 func = fsub_op;
248 else if (insn.mm_fp0_format.op == mm_fmul_op)
249 func = fmul_op;
250 else if (insn.mm_fp0_format.op == mm_fdiv_op)
251 func = fdiv_op;
252 if (func != -1) {
253 mips32_insn.fp0_format.opcode = cop1_op;
254 mips32_insn.fp0_format.fmt =
255 sdps_format[insn.mm_fp0_format.fmt];
256 mips32_insn.fp0_format.ft =
257 insn.mm_fp0_format.ft;
258 mips32_insn.fp0_format.fs =
259 insn.mm_fp0_format.fs;
260 mips32_insn.fp0_format.fd =
261 insn.mm_fp0_format.fd;
262 mips32_insn.fp0_format.func = func;
263 } else
264 return SIGILL;
265 break;
266 case mm_32f_70_op:
267 func = -1; /* Invalid */
268 if (insn.mm_fp0_format.op == mm_fmovn_op)
269 func = fmovn_op;
270 else if (insn.mm_fp0_format.op == mm_fmovz_op)
271 func = fmovz_op;
272 if (func != -1) {
273 mips32_insn.fp0_format.opcode = cop1_op;
274 mips32_insn.fp0_format.fmt =
275 sdps_format[insn.mm_fp0_format.fmt];
276 mips32_insn.fp0_format.ft =
277 insn.mm_fp0_format.ft;
278 mips32_insn.fp0_format.fs =
279 insn.mm_fp0_format.fs;
280 mips32_insn.fp0_format.fd =
281 insn.mm_fp0_format.fd;
282 mips32_insn.fp0_format.func = func;
283 } else
284 return SIGILL;
285 break;
286 case mm_32f_73_op: /* POOL32FXF */
287 switch (insn.mm_fp1_format.op) {
288 case mm_movf0_op:
289 case mm_movf1_op:
290 case mm_movt0_op:
291 case mm_movt1_op:
292 if ((insn.mm_fp1_format.op & 0x7f) ==
293 mm_movf0_op)
294 op = 0;
295 else
296 op = 1;
297 mips32_insn.r_format.opcode = spec_op;
298 mips32_insn.r_format.rs = insn.mm_fp4_format.fs;
299 mips32_insn.r_format.rt =
300 (insn.mm_fp4_format.cc << 2) + op;
301 mips32_insn.r_format.rd = insn.mm_fp4_format.rt;
302 mips32_insn.r_format.re = 0;
303 mips32_insn.r_format.func = movc_op;
304 break;
305 case mm_fcvtd0_op:
306 case mm_fcvtd1_op:
307 case mm_fcvts0_op:
308 case mm_fcvts1_op:
309 if ((insn.mm_fp1_format.op & 0x7f) ==
310 mm_fcvtd0_op) {
311 func = fcvtd_op;
312 fmt = swl_format[insn.mm_fp3_format.fmt];
313 } else {
314 func = fcvts_op;
315 fmt = dwl_format[insn.mm_fp3_format.fmt];
316 }
317 mips32_insn.fp0_format.opcode = cop1_op;
318 mips32_insn.fp0_format.fmt = fmt;
319 mips32_insn.fp0_format.ft = 0;
320 mips32_insn.fp0_format.fs =
321 insn.mm_fp3_format.fs;
322 mips32_insn.fp0_format.fd =
323 insn.mm_fp3_format.rt;
324 mips32_insn.fp0_format.func = func;
325 break;
326 case mm_fmov0_op:
327 case mm_fmov1_op:
328 case mm_fabs0_op:
329 case mm_fabs1_op:
330 case mm_fneg0_op:
331 case mm_fneg1_op:
332 if ((insn.mm_fp1_format.op & 0x7f) ==
333 mm_fmov0_op)
334 func = fmov_op;
335 else if ((insn.mm_fp1_format.op & 0x7f) ==
336 mm_fabs0_op)
337 func = fabs_op;
338 else
339 func = fneg_op;
340 mips32_insn.fp0_format.opcode = cop1_op;
341 mips32_insn.fp0_format.fmt =
342 sdps_format[insn.mm_fp3_format.fmt];
343 mips32_insn.fp0_format.ft = 0;
344 mips32_insn.fp0_format.fs =
345 insn.mm_fp3_format.fs;
346 mips32_insn.fp0_format.fd =
347 insn.mm_fp3_format.rt;
348 mips32_insn.fp0_format.func = func;
349 break;
350 case mm_ffloorl_op:
351 case mm_ffloorw_op:
352 case mm_fceill_op:
353 case mm_fceilw_op:
354 case mm_ftruncl_op:
355 case mm_ftruncw_op:
356 case mm_froundl_op:
357 case mm_froundw_op:
358 case mm_fcvtl_op:
359 case mm_fcvtw_op:
360 if (insn.mm_fp1_format.op == mm_ffloorl_op)
361 func = ffloorl_op;
362 else if (insn.mm_fp1_format.op == mm_ffloorw_op)
363 func = ffloor_op;
364 else if (insn.mm_fp1_format.op == mm_fceill_op)
365 func = fceill_op;
366 else if (insn.mm_fp1_format.op == mm_fceilw_op)
367 func = fceil_op;
368 else if (insn.mm_fp1_format.op == mm_ftruncl_op)
369 func = ftruncl_op;
370 else if (insn.mm_fp1_format.op == mm_ftruncw_op)
371 func = ftrunc_op;
372 else if (insn.mm_fp1_format.op == mm_froundl_op)
373 func = froundl_op;
374 else if (insn.mm_fp1_format.op == mm_froundw_op)
375 func = fround_op;
376 else if (insn.mm_fp1_format.op == mm_fcvtl_op)
377 func = fcvtl_op;
378 else
379 func = fcvtw_op;
380 mips32_insn.fp0_format.opcode = cop1_op;
381 mips32_insn.fp0_format.fmt =
382 sd_format[insn.mm_fp1_format.fmt];
383 mips32_insn.fp0_format.ft = 0;
384 mips32_insn.fp0_format.fs =
385 insn.mm_fp1_format.fs;
386 mips32_insn.fp0_format.fd =
387 insn.mm_fp1_format.rt;
388 mips32_insn.fp0_format.func = func;
389 break;
390 case mm_frsqrt_op:
391 case mm_fsqrt_op:
392 case mm_frecip_op:
393 if (insn.mm_fp1_format.op == mm_frsqrt_op)
394 func = frsqrt_op;
395 else if (insn.mm_fp1_format.op == mm_fsqrt_op)
396 func = fsqrt_op;
397 else
398 func = frecip_op;
399 mips32_insn.fp0_format.opcode = cop1_op;
400 mips32_insn.fp0_format.fmt =
401 sdps_format[insn.mm_fp1_format.fmt];
402 mips32_insn.fp0_format.ft = 0;
403 mips32_insn.fp0_format.fs =
404 insn.mm_fp1_format.fs;
405 mips32_insn.fp0_format.fd =
406 insn.mm_fp1_format.rt;
407 mips32_insn.fp0_format.func = func;
408 break;
409 case mm_mfc1_op:
410 case mm_mtc1_op:
411 case mm_cfc1_op:
412 case mm_ctc1_op:
9355e59c
SH		 413 case mm_mfhc1_op:
414 case mm_mthc1_op:
102cedc3
LY		 415 if (insn.mm_fp1_format.op == mm_mfc1_op)
416 op = mfc_op;
417 else if (insn.mm_fp1_format.op == mm_mtc1_op)
418 op = mtc_op;
419 else if (insn.mm_fp1_format.op == mm_cfc1_op)
420 op = cfc_op;
9355e59c 421 else if (insn.mm_fp1_format.op == mm_ctc1_op)
102cedc3 422 op = ctc_op;
9355e59c
SH		 423 else if (insn.mm_fp1_format.op == mm_mfhc1_op)
424 op = mfhc_op;
425 else
426 op = mthc_op;
102cedc3
LY		 427 mips32_insn.fp1_format.opcode = cop1_op;
428 mips32_insn.fp1_format.op = op;
429 mips32_insn.fp1_format.rt =
430 insn.mm_fp1_format.rt;
431 mips32_insn.fp1_format.fs =
432 insn.mm_fp1_format.fs;
433 mips32_insn.fp1_format.fd = 0;
434 mips32_insn.fp1_format.func = 0;
435 break;
436 default:
437 return SIGILL;
102cedc3
LY		 438 }
439 break;
440 case mm_32f_74_op: /* c.cond.fmt */
441 mips32_insn.fp0_format.opcode = cop1_op;
442 mips32_insn.fp0_format.fmt =
443 sdps_format[insn.mm_fp4_format.fmt];
444 mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt;
445 mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs;
446 mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2;
447 mips32_insn.fp0_format.func =
448 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC;
449 break;
450 default:
451 return SIGILL;
102cedc3
LY		 452 }
453 break;
454 default:
455 return SIGILL;
102cedc3
LY		 456 }
457
458 *insn_ptr = mips32_insn;
459 return 0;
460}
461
462int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
463 unsigned long *contpc)
464{
465 union mips_instruction insn = (union mips_instruction)dec_insn.insn;
466 int bc_false = 0;
467 unsigned int fcr31;
468 unsigned int bit;
469
fe6d2909
DD		 470 if (!cpu_has_mmips)
471 return 0;
472
102cedc3
LY		 473 switch (insn.mm_i_format.opcode) {
474 case mm_pool32a_op:
475 if ((insn.mm_i_format.simmediate & MM_POOL32A_MINOR_MASK) ==
476 mm_pool32axf_op) {
477 switch (insn.mm_i_format.simmediate >>
478 MM_POOL32A_MINOR_SHIFT) {
479 case mm_jalr_op:
480 case mm_jalrhb_op:
481 case mm_jalrs_op:
482 case mm_jalrshb_op:
483 if (insn.mm_i_format.rt != 0) /* Not mm_jr */
484 regs->regs[insn.mm_i_format.rt] =
485 regs->cp0_epc +
486 dec_insn.pc_inc +
487 dec_insn.next_pc_inc;
488 *contpc = regs->regs[insn.mm_i_format.rs];
489 return 1;
102cedc3
LY		 490 }
491 }
492 break;
493 case mm_pool32i_op:
494 switch (insn.mm_i_format.rt) {
495 case mm_bltzals_op:
496 case mm_bltzal_op:
497 regs->regs[31] = regs->cp0_epc +
498 dec_insn.pc_inc +
499 dec_insn.next_pc_inc;
500 /* Fall through */
501 case mm_bltz_op:
502 if ((long)regs->regs[insn.mm_i_format.rs] < 0)
503 *contpc = regs->cp0_epc +
504 dec_insn.pc_inc +
505 (insn.mm_i_format.simmediate << 1);
506 else
507 *contpc = regs->cp0_epc +
508 dec_insn.pc_inc +
509 dec_insn.next_pc_inc;
510 return 1;
102cedc3
LY		 511 case mm_bgezals_op:
512 case mm_bgezal_op:
513 regs->regs[31] = regs->cp0_epc +
514 dec_insn.pc_inc +
515 dec_insn.next_pc_inc;
516 /* Fall through */
517 case mm_bgez_op:
518 if ((long)regs->regs[insn.mm_i_format.rs] >= 0)
519 *contpc = regs->cp0_epc +
520 dec_insn.pc_inc +
521 (insn.mm_i_format.simmediate << 1);
522 else
523 *contpc = regs->cp0_epc +
524 dec_insn.pc_inc +
525 dec_insn.next_pc_inc;
526 return 1;
102cedc3
LY		 527 case mm_blez_op:
528 if ((long)regs->regs[insn.mm_i_format.rs] <= 0)
529 *contpc = regs->cp0_epc +
530 dec_insn.pc_inc +
531 (insn.mm_i_format.simmediate << 1);
532 else
533 *contpc = regs->cp0_epc +
534 dec_insn.pc_inc +
535 dec_insn.next_pc_inc;
536 return 1;
102cedc3
LY		 537 case mm_bgtz_op:
538 if ((long)regs->regs[insn.mm_i_format.rs] <= 0)
539 *contpc = regs->cp0_epc +
540 dec_insn.pc_inc +
541 (insn.mm_i_format.simmediate << 1);
542 else
543 *contpc = regs->cp0_epc +
544 dec_insn.pc_inc +
545 dec_insn.next_pc_inc;
546 return 1;
102cedc3
LY		 547 case mm_bc2f_op:
548 case mm_bc1f_op:
549 bc_false = 1;
550 /* Fall through */
551 case mm_bc2t_op:
552 case mm_bc1t_op:
553 preempt_disable();
554 if (is_fpu_owner())
555 asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
556 else
557 fcr31 = current->thread.fpu.fcr31;
558 preempt_enable();
559
560 if (bc_false)
561 fcr31 = ~fcr31;
562
563 bit = (insn.mm_i_format.rs >> 2);
564 bit += (bit != 0);
565 bit += 23;
566 if (fcr31 & (1 << bit))
567 *contpc = regs->cp0_epc +
568 dec_insn.pc_inc +
569 (insn.mm_i_format.simmediate << 1);
570 else
571 *contpc = regs->cp0_epc +
572 dec_insn.pc_inc + dec_insn.next_pc_inc;
573 return 1;
102cedc3
LY		 574 }
575 break;
576 case mm_pool16c_op:
577 switch (insn.mm_i_format.rt) {
578 case mm_jalr16_op:
579 case mm_jalrs16_op:
580 regs->regs[31] = regs->cp0_epc +
581 dec_insn.pc_inc + dec_insn.next_pc_inc;
582 /* Fall through */
583 case mm_jr16_op:
584 *contpc = regs->regs[insn.mm_i_format.rs];
585 return 1;
102cedc3
LY		 586 }
587 break;
588 case mm_beqz16_op:
589 if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] == 0)
590 *contpc = regs->cp0_epc +
591 dec_insn.pc_inc +
592 (insn.mm_b1_format.simmediate << 1);
593 else
594 *contpc = regs->cp0_epc +
595 dec_insn.pc_inc + dec_insn.next_pc_inc;
596 return 1;
102cedc3
LY		 597 case mm_bnez16_op:
598 if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] != 0)
599 *contpc = regs->cp0_epc +
600 dec_insn.pc_inc +
601 (insn.mm_b1_format.simmediate << 1);
602 else
603 *contpc = regs->cp0_epc +
604 dec_insn.pc_inc + dec_insn.next_pc_inc;
605 return 1;
102cedc3
LY		 606 case mm_b16_op:
607 *contpc = regs->cp0_epc + dec_insn.pc_inc +
608 (insn.mm_b0_format.simmediate << 1);
609 return 1;
102cedc3
LY		 610 case mm_beq32_op:
611 if (regs->regs[insn.mm_i_format.rs] ==
612 regs->regs[insn.mm_i_format.rt])
613 *contpc = regs->cp0_epc +
614 dec_insn.pc_inc +
615 (insn.mm_i_format.simmediate << 1);
616 else
617 *contpc = regs->cp0_epc +
618 dec_insn.pc_inc +
619 dec_insn.next_pc_inc;
620 return 1;
102cedc3
LY		 621 case mm_bne32_op:
622 if (regs->regs[insn.mm_i_format.rs] !=
623 regs->regs[insn.mm_i_format.rt])
624 *contpc = regs->cp0_epc +
625 dec_insn.pc_inc +
626 (insn.mm_i_format.simmediate << 1);
627 else
628 *contpc = regs->cp0_epc +
629 dec_insn.pc_inc + dec_insn.next_pc_inc;
630 return 1;
102cedc3
LY		 631 case mm_jalx32_op:
632 regs->regs[31] = regs->cp0_epc +
633 dec_insn.pc_inc + dec_insn.next_pc_inc;
634 *contpc = regs->cp0_epc + dec_insn.pc_inc;
635 *contpc >>= 28;
636 *contpc <<= 28;
637 *contpc |= (insn.j_format.target << 2);
638 return 1;
102cedc3
LY		 639 case mm_jals32_op:
640 case mm_jal32_op:
641 regs->regs[31] = regs->cp0_epc +
642 dec_insn.pc_inc + dec_insn.next_pc_inc;
643 /* Fall through */
644 case mm_j32_op:
645 *contpc = regs->cp0_epc + dec_insn.pc_inc;
646 *contpc >>= 27;
647 *contpc <<= 27;
648 *contpc |= (insn.j_format.target << 1);
649 set_isa16_mode(*contpc);
650 return 1;
102cedc3
LY		 651 }
652 return 0;
653}
1da177e4
LT		 654
655/*
656 * Redundant with logic already in kernel/branch.c,
657 * embedded in compute_return_epc. At some point,
658 * a single subroutine should be used across both
659 * modules.
660 */
102cedc3
LY		 661static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
662 unsigned long *contpc)
1da177e4 663{
102cedc3
LY		 664 union mips_instruction insn = (union mips_instruction)dec_insn.insn;
665 unsigned int fcr31;
666 unsigned int bit = 0;
667
668 switch (insn.i_format.opcode) {
1da177e4 669 case spec_op:
102cedc3 670 switch (insn.r_format.func) {
1da177e4 671 case jalr_op:
102cedc3
LY		 672 regs->regs[insn.r_format.rd] =
673 regs->cp0_epc + dec_insn.pc_inc +
674 dec_insn.next_pc_inc;
675 /* Fall through */
1da177e4 676 case jr_op:
102cedc3 677 *contpc = regs->regs[insn.r_format.rs];
1da177e4
LT		 678 return 1;
679 }
680 break;
1da177e4 681 case bcond_op:
102cedc3
LY		 682 switch (insn.i_format.rt) {
683 case bltzal_op:
684 case bltzall_op:
685 regs->regs[31] = regs->cp0_epc +
686 dec_insn.pc_inc +
687 dec_insn.next_pc_inc;
688 /* Fall through */
1da177e4 689 case bltz_op:
1da177e4 690 case bltzl_op:
102cedc3
LY		 691 if ((long)regs->regs[insn.i_format.rs] < 0)
692 *contpc = regs->cp0_epc +
693 dec_insn.pc_inc +
694 (insn.i_format.simmediate << 2);
695 else
696 *contpc = regs->cp0_epc +
697 dec_insn.pc_inc +
698 dec_insn.next_pc_inc;
699 return 1;
1da177e4 700 case bgezal_op:
1da177e4 701 case bgezall_op:
102cedc3
LY		 702 regs->regs[31] = regs->cp0_epc +
703 dec_insn.pc_inc +
704 dec_insn.next_pc_inc;
705 /* Fall through */
706 case bgez_op:
707 case bgezl_op:
708 if ((long)regs->regs[insn.i_format.rs] >= 0)
709 *contpc = regs->cp0_epc +
710 dec_insn.pc_inc +
711 (insn.i_format.simmediate << 2);
712 else
713 *contpc = regs->cp0_epc +
714 dec_insn.pc_inc +
715 dec_insn.next_pc_inc;
1da177e4
LT		 716 return 1;
717 }
718 break;
1da177e4 719 case jalx_op:
102cedc3
LY		 720 set_isa16_mode(bit);
721 case jal_op:
722 regs->regs[31] = regs->cp0_epc +
723 dec_insn.pc_inc +
724 dec_insn.next_pc_inc;
725 /* Fall through */
726 case j_op:
727 *contpc = regs->cp0_epc + dec_insn.pc_inc;
728 *contpc >>= 28;
729 *contpc <<= 28;
730 *contpc |= (insn.j_format.target << 2);
731 /* Set microMIPS mode bit: XOR for jalx. */
732 *contpc ^= bit;
733 return 1;
1da177e4 734 case beq_op:
1da177e4 735 case beql_op:
102cedc3
LY		 736 if (regs->regs[insn.i_format.rs] ==
737 regs->regs[insn.i_format.rt])
738 *contpc = regs->cp0_epc +
739 dec_insn.pc_inc +
740 (insn.i_format.simmediate << 2);
741 else
742 *contpc = regs->cp0_epc +
743 dec_insn.pc_inc +
744 dec_insn.next_pc_inc;
745 return 1;
102cedc3 746 case bne_op:
1da177e4 747 case bnel_op:
102cedc3
LY		 748 if (regs->regs[insn.i_format.rs] !=
749 regs->regs[insn.i_format.rt])
750 *contpc = regs->cp0_epc +
751 dec_insn.pc_inc +
752 (insn.i_format.simmediate << 2);
753 else
754 *contpc = regs->cp0_epc +
755 dec_insn.pc_inc +
756 dec_insn.next_pc_inc;
757 return 1;
102cedc3 758 case blez_op:
1da177e4 759 case blezl_op:
102cedc3
LY		 760 if ((long)regs->regs[insn.i_format.rs] <= 0)
761 *contpc = regs->cp0_epc +
762 dec_insn.pc_inc +
763 (insn.i_format.simmediate << 2);
764 else
765 *contpc = regs->cp0_epc +
766 dec_insn.pc_inc +
767 dec_insn.next_pc_inc;
768 return 1;
102cedc3 769 case bgtz_op:
1da177e4 770 case bgtzl_op:
102cedc3
LY		 771 if ((long)regs->regs[insn.i_format.rs] > 0)
772 *contpc = regs->cp0_epc +
773 dec_insn.pc_inc +
774 (insn.i_format.simmediate << 2);
775 else
776 *contpc = regs->cp0_epc +
777 dec_insn.pc_inc +
778 dec_insn.next_pc_inc;
1da177e4 779 return 1;
c26d4219
DD		 780#ifdef CONFIG_CPU_CAVIUM_OCTEON
781 case lwc2_op: /* This is bbit0 on Octeon */
782 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
783 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
784 else
785 *contpc = regs->cp0_epc + 8;
786 return 1;
787 case ldc2_op: /* This is bbit032 on Octeon */
788 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)
789 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
790 else
791 *contpc = regs->cp0_epc + 8;
792 return 1;
793 case swc2_op: /* This is bbit1 on Octeon */
794 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
795 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
796 else
797 *contpc = regs->cp0_epc + 8;
798 return 1;
799 case sdc2_op: /* This is bbit132 on Octeon */
800 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))
801 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
802 else
803 *contpc = regs->cp0_epc + 8;
804 return 1;
805#endif
1da177e4
LT		 806 case cop0_op:
807 case cop1_op:
808 case cop2_op:
809 case cop1x_op:
102cedc3
LY		 810 if (insn.i_format.rs == bc_op) {
811 preempt_disable();
812 if (is_fpu_owner())
813 asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
814 else
815 fcr31 = current->thread.fpu.fcr31;
816 preempt_enable();
817
818 bit = (insn.i_format.rt >> 2);
819 bit += (bit != 0);
820 bit += 23;
821 switch (insn.i_format.rt & 3) {
822 case 0: /* bc1f */
823 case 2: /* bc1fl */
824 if (~fcr31 & (1 << bit))
825 *contpc = regs->cp0_epc +
826 dec_insn.pc_inc +
827 (insn.i_format.simmediate << 2);
828 else
829 *contpc = regs->cp0_epc +
830 dec_insn.pc_inc +
831 dec_insn.next_pc_inc;
832 return 1;
102cedc3
LY		 833 case 1: /* bc1t */
834 case 3: /* bc1tl */
835 if (fcr31 & (1 << bit))
836 *contpc = regs->cp0_epc +
837 dec_insn.pc_inc +
838 (insn.i_format.simmediate << 2);
839 else
840 *contpc = regs->cp0_epc +
841 dec_insn.pc_inc +
842 dec_insn.next_pc_inc;
843 return 1;
102cedc3
LY		 844 }
845 }
1da177e4
LT		 846 break;
847 }
1da177e4
LT		 848 return 0;
849}
850
851/*
852 * In the Linux kernel, we support selection of FPR format on the
70342287 853 * basis of the Status.FR bit. If an FPU is not present, the FR bit
da0bac33 854 * is hardwired to zero, which would imply a 32-bit FPU even for
597ce172 855 * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
51d943f0
RB		 856 * FPU emu is slow and bulky and optimizing this function offers fairly
857 * sizeable benefits so we try to be clever and make this function return
858 * a constant whenever possible, that is on 64-bit kernels without O32
597ce172 859 * compatibility enabled and on 32-bit without 64-bit FPU support.
1da177e4 860 */
da0bac33
DD		 861static inline int cop1_64bit(struct pt_regs *xcp)
862{
51d943f0
RB		 863#if defined(CONFIG_64BIT) && !defined(CONFIG_MIPS32_O32)
864 return 1;
597ce172 865#elif defined(CONFIG_32BIT) && !defined(CONFIG_MIPS_O32_FP64_SUPPORT)
da0bac33 866 return 0;
597ce172
PB		 867#else
868 return !test_thread_flag(TIF_32BIT_FPREGS);
1da177e4 869#endif
da0bac33
DD		 870}
871
47fa0c02
RB		 872#define SIFROMREG(si, x) \
873do { \
bbd426f5
PB		 874 if (cop1_64bit(xcp)) \
875 (si) = get_fpr32(&ctx->fpr[x], 0); \
876 else \
877 (si) = get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \
878} while (0)
1da177e4 879
47fa0c02
RB		 880#define SITOREG(si, x) \
881do { \
ef1c47af
PB		 882 if (cop1_64bit(xcp)) { \
883 unsigned i; \
bbd426f5 884 set_fpr32(&ctx->fpr[x], 0, si); \
ef1c47af
PB		 885 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
886 set_fpr32(&ctx->fpr[x], i, 0); \
887 } else { \
bbd426f5 888 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \
ef1c47af 889 } \
bbd426f5 890} while (0)
1da177e4 891
bbd426f5 892#define SIFROMHREG(si, x) ((si) = get_fpr32(&ctx->fpr[x], 1))
ef1c47af 893
47fa0c02
RB		 894#define SITOHREG(si, x) \
895do { \
ef1c47af
PB		 896 unsigned i; \
897 set_fpr32(&ctx->fpr[x], 1, si); \
898 for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
899 set_fpr32(&ctx->fpr[x], i, 0); \
900} while (0)
1ac94400 901
47fa0c02 902#define DIFROMREG(di, x) \
bbd426f5
PB		 903 ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0))
904
47fa0c02
RB		 905#define DITOREG(di, x) \
906do { \
ef1c47af
PB		 907 unsigned fpr, i; \
908 fpr = (x) & ~(cop1_64bit(xcp) == 0); \
909 set_fpr64(&ctx->fpr[fpr], 0, di); \
910 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \
911 set_fpr64(&ctx->fpr[fpr], i, 0); \
912} while (0)
1da177e4 913
21a151d8
RB		 914#define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
915#define SPTOREG(sp, x) SITOREG((sp).bits, x)
916#define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
917#define DPTOREG(dp, x) DITOREG((dp).bits, x)
1da177e4
LT		 918
919/*
920 * Emulate the single floating point instruction pointed at by EPC.
921 * Two instructions if the instruction is in a branch delay slot.
922 */
923
515b029d 924static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
102cedc3 925 struct mm_decoded_insn dec_insn, void *__user *fault_addr)
1da177e4
LT		 926{
927 mips_instruction ir;
102cedc3 928 unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
1da177e4 929 unsigned int cond;
102cedc3 930 int pc_inc;
1da177e4
LT		 931
932 /* XXX NEC Vr54xx bug workaround */
e7e9cae5 933 if (delay_slot(xcp)) {
102cedc3
LY		 934 if (dec_insn.micro_mips_mode) {
935 if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
e7e9cae5 936 clear_delay_slot(xcp);
102cedc3
LY		 937 } else {
938 if (!isBranchInstr(xcp, dec_insn, &contpc))
e7e9cae5 939 clear_delay_slot(xcp);
102cedc3
LY		 940 }
941 }
1da177e4 942
e7e9cae5 943 if (delay_slot(xcp)) {
1da177e4
LT		 944 /*
945 * The instruction to be emulated is in a branch delay slot
70342287 946 * which means that we have to emulate the branch instruction
1da177e4
LT		 947 * BEFORE we do the cop1 instruction.
948 *
949 * This branch could be a COP1 branch, but in that case we
950 * would have had a trap for that instruction, and would not
951 * come through this route.
952 *
953 * Linux MIPS branch emulator operates on context, updating the
954 * cp0_epc.
955 */
102cedc3
LY		 956 ir = dec_insn.next_insn; /* process delay slot instr */
957 pc_inc = dec_insn.next_pc_inc;
958 } else {
959 ir = dec_insn.insn; /* process current instr */
960 pc_inc = dec_insn.pc_inc;
961 }
1da177e4 962
102cedc3
LY		 963 /*
964 * Since microMIPS FPU instructios are a subset of MIPS32 FPU
965 * instructions, we want to convert microMIPS FPU instructions
966 * into MIPS32 instructions so that we could reuse all of the
967 * FPU emulation code.
968 *
969 * NOTE: We cannot do this for branch instructions since they
970 * are not a subset. Example: Cannot emulate a 16-bit
971 * aligned target address with a MIPS32 instruction.
972 */
973 if (dec_insn.micro_mips_mode) {
974 /*
975 * If next instruction is a 16-bit instruction, then it
976 * it cannot be a FPU instruction. This could happen
977 * since we can be called for non-FPU instructions.
978 */
979 if ((pc_inc == 2) ||
980 (microMIPS32_to_MIPS32((union mips_instruction *)&ir)
981 == SIGILL))
1da177e4 982 return SIGILL;
1da177e4
LT		 983 }
984
985 emul:
a8b0ca17 986 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
b6ee75ed 987 MIPS_FPU_EMU_INC_STATS(emulated);
1da177e4 988 switch (MIPSInst_OPCODE(ir)) {
1da177e4 989 case ldc1_op:{
3fccc015 990 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1da177e4
LT		 991 MIPSInst_SIMM(ir));
992 u64 val;
993
b6ee75ed 994 MIPS_FPU_EMU_INC_STATS(loads);
515b029d
DD		 995
996 if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
b6ee75ed 997 MIPS_FPU_EMU_INC_STATS(errors);
515b029d 998 *fault_addr = va;
1da177e4
LT		 999 return SIGBUS;
1000 }
515b029d
DD		 1001 if (__get_user(val, va)) {
1002 MIPS_FPU_EMU_INC_STATS(errors);
1003 *fault_addr = va;
1004 return SIGSEGV;
1005 }
1da177e4
LT		 1006 DITOREG(val, MIPSInst_RT(ir));
1007 break;
1008 }
1009
1010 case sdc1_op:{
3fccc015 1011 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1da177e4
LT		 1012 MIPSInst_SIMM(ir));
1013 u64 val;
1014
b6ee75ed 1015 MIPS_FPU_EMU_INC_STATS(stores);
1da177e4 1016 DIFROMREG(val, MIPSInst_RT(ir));
515b029d 1017 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
b6ee75ed 1018 MIPS_FPU_EMU_INC_STATS(errors);
515b029d 1019 *fault_addr = va;
1da177e4
LT		 1020 return SIGBUS;
1021 }
515b029d
DD		 1022 if (__put_user(val, va)) {
1023 MIPS_FPU_EMU_INC_STATS(errors);
1024 *fault_addr = va;
1025 return SIGSEGV;
1026 }
1da177e4
LT		 1027 break;
1028 }
1da177e4
LT		 1029
1030 case lwc1_op:{
3fccc015 1031 u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1da177e4
LT		 1032 MIPSInst_SIMM(ir));
1033 u32 val;
1034
b6ee75ed 1035 MIPS_FPU_EMU_INC_STATS(loads);
515b029d 1036 if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
b6ee75ed 1037 MIPS_FPU_EMU_INC_STATS(errors);
515b029d 1038 *fault_addr = va;
1da177e4
LT		 1039 return SIGBUS;
1040 }
515b029d
DD		 1041 if (__get_user(val, va)) {
1042 MIPS_FPU_EMU_INC_STATS(errors);
1043 *fault_addr = va;
1044 return SIGSEGV;
1045 }
1da177e4
LT		 1046 SITOREG(val, MIPSInst_RT(ir));
1047 break;
1048 }
1049
1050 case swc1_op:{
3fccc015 1051 u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1da177e4
LT		 1052 MIPSInst_SIMM(ir));
1053 u32 val;
1054
b6ee75ed 1055 MIPS_FPU_EMU_INC_STATS(stores);
1da177e4 1056 SIFROMREG(val, MIPSInst_RT(ir));
515b029d 1057 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
b6ee75ed 1058 MIPS_FPU_EMU_INC_STATS(errors);
515b029d 1059 *fault_addr = va;
1da177e4
LT		 1060 return SIGBUS;
1061 }
515b029d
DD		 1062 if (__put_user(val, va)) {
1063 MIPS_FPU_EMU_INC_STATS(errors);
1064 *fault_addr = va;
1065 return SIGSEGV;
1066 }
1da177e4
LT		 1067 break;
1068 }
1069
1070 case cop1_op:
1071 switch (MIPSInst_RS(ir)) {
1072
4b724efd 1073#if defined(__mips64)
1da177e4
LT		 1074 case dmfc_op:
1075 /* copregister fs -> gpr[rt] */
1076 if (MIPSInst_RT(ir) != 0) {
1077 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1078 MIPSInst_RD(ir));
1079 }
1080 break;
1081
1082 case dmtc_op:
1083 /* copregister fs <- rt */
1084 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1085 break;
1086#endif
1087
1ac94400
LY		 1088 case mfhc_op:
1089 if (!cpu_has_mips_r2)
1090 goto sigill;
1091
1092 /* copregister rd -> gpr[rt] */
1093 if (MIPSInst_RT(ir) != 0) {
1094 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
1095 MIPSInst_RD(ir));
1096 }
1097 break;
1098
1099 case mthc_op:
1100 if (!cpu_has_mips_r2)
1101 goto sigill;
1102
1103 /* copregister rd <- gpr[rt] */
1104 SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1105 break;
1106
1da177e4
LT		 1107 case mfc_op:
1108 /* copregister rd -> gpr[rt] */
1da177e4
LT		 1109 if (MIPSInst_RT(ir) != 0) {
1110 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1111 MIPSInst_RD(ir));
1112 }
1113 break;
1114
1115 case mtc_op:
1116 /* copregister rd <- rt */
1da177e4
LT		 1117 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1118 break;
1119
1120 case cfc_op:{
1121 /* cop control register rd -> gpr[rt] */
1122 u32 value;
1123
1da177e4
LT		 1124 if (MIPSInst_RD(ir) == FPCREG_CSR) {
1125 value = ctx->fcr31;
3f135530
SM		 1126 value = (value & ~FPU_CSR_RM) |
1127 mips_rm[modeindex(value)];
1da177e4
LT		 1128#ifdef CSRTRACE
1129 printk("%p gpr[%d]<-csr=%08x\n",
333d1f67 1130 (void *) (xcp->cp0_epc),
1da177e4
LT		 1131 MIPSInst_RT(ir), value);
1132#endif
1133 }
1134 else if (MIPSInst_RD(ir) == FPCREG_RID)
1135 value = 0;
1136 else
1137 value = 0;
1138 if (MIPSInst_RT(ir))
1139 xcp->regs[MIPSInst_RT(ir)] = value;
1140 break;
1141 }
1142
1143 case ctc_op:{
1144 /* copregister rd <- rt */
1145 u32 value;
1146
1147 if (MIPSInst_RT(ir) == 0)
1148 value = 0;
1149 else
1150 value = xcp->regs[MIPSInst_RT(ir)];
1151
1152 /* we only have one writable control reg
1153 */
1154 if (MIPSInst_RD(ir) == FPCREG_CSR) {
1155#ifdef CSRTRACE
1156 printk("%p gpr[%d]->csr=%08x\n",
333d1f67 1157 (void *) (xcp->cp0_epc),
1da177e4
LT		 1158 MIPSInst_RT(ir), value);
1159#endif
95e8f634
SM		 1160
1161 /*
1162 * Don't write reserved bits,
1163 * and convert to ieee library modes
1164 */
1165 ctx->fcr31 = (value &
1166 ~(FPU_CSR_RSVD | FPU_CSR_RM)) |
1167 ieee_rm[modeindex(value)];
1da177e4
LT		 1168 }
1169 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1170 return SIGFPE;
1171 }
1172 break;
1173 }
1174
1175 case bc_op:{
1176 int likely = 0;
1177
e7e9cae5 1178 if (delay_slot(xcp))
1da177e4
LT		 1179 return SIGILL;
1180
1181#if __mips >= 4
1182 cond = ctx->fcr31 & fpucondbit[MIPSInst_RT(ir) >> 2];
1183#else
1184 cond = ctx->fcr31 & FPU_CSR_COND;
1185#endif
1186 switch (MIPSInst_RT(ir) & 3) {
1187 case bcfl_op:
1188 likely = 1;
1189 case bcf_op:
1190 cond = !cond;
1191 break;
1192 case bctl_op:
1193 likely = 1;
1194 case bct_op:
1195 break;
1196 default:
1197 /* thats an illegal instruction */
1198 return SIGILL;
1199 }
1200
e7e9cae5 1201 set_delay_slot(xcp);
1da177e4
LT		 1202 if (cond) {
1203 /* branch taken: emulate dslot
1204 * instruction
1205 */
102cedc3
LY		 1206 xcp->cp0_epc += dec_insn.pc_inc;
1207
1208 contpc = MIPSInst_SIMM(ir);
1209 ir = dec_insn.next_insn;
1210 if (dec_insn.micro_mips_mode) {
1211 contpc = (xcp->cp0_epc + (contpc << 1));
1212
1213 /* If 16-bit instruction, not FPU. */
1214 if ((dec_insn.next_pc_inc == 2) ||
1215 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) {
1216
1217 /*
1218 * Since this instruction will
1219 * be put on the stack with
1220 * 32-bit words, get around
1221 * this problem by putting a
1222 * NOP16 as the second one.
1223 */
1224 if (dec_insn.next_pc_inc == 2)
1225 ir = (ir & (~0xffff)) | MM_NOP16;
1226
1227 /*
1228 * Single step the non-CP1
1229 * instruction in the dslot.
1230 */
1231 return mips_dsemul(xcp, ir, contpc);
1232 }
1233 } else
1234 contpc = (xcp->cp0_epc + (contpc << 2));
1da177e4
LT		 1235
1236 switch (MIPSInst_OPCODE(ir)) {
1237 case lwc1_op:
1238 case swc1_op:
4b724efd 1239#if (__mips >= 2 || defined(__mips64))
1da177e4
LT		 1240 case ldc1_op:
1241 case sdc1_op:
1242#endif
1243 case cop1_op:
1244#if __mips >= 4 && __mips != 32
1245 case cop1x_op:
1246#endif
1247 /* its one of ours */
1248 goto emul;
1249#if __mips >= 4
1250 case spec_op:
1251 if (MIPSInst_FUNC(ir) == movc_op)
1252 goto emul;
1253 break;
1254#endif
1255 }
1256
1257 /*
1258 * Single step the non-cp1
1259 * instruction in the dslot
1260 */
e70dfc10 1261 return mips_dsemul(xcp, ir, contpc);
1da177e4
LT		 1262 }
1263 else {
1264 /* branch not taken */
1265 if (likely) {
1266 /*
1267 * branch likely nullifies
1268 * dslot if not taken
1269 */
102cedc3
LY		 1270 xcp->cp0_epc += dec_insn.pc_inc;
1271 contpc += dec_insn.pc_inc;
1da177e4
LT		 1272 /*
1273 * else continue & execute
1274 * dslot as normal insn
1275 */
1276 }
1277 }
1278 break;
1279 }
1280
1281 default:
1282 if (!(MIPSInst_RS(ir) & 0x10))
1283 return SIGILL;
1284 {
1285 int sig;
1286
1287 /* a real fpu computation instruction */
1288 if ((sig = fpu_emu(xcp, ctx, ir)))
1289 return sig;
1290 }
1291 }
1292 break;
1293
1294#if __mips >= 4 && __mips != 32
1295 case cop1x_op:{
515b029d
DD		 1296 int sig = fpux_emu(xcp, ctx, ir, fault_addr);
1297 if (sig)
1da177e4
LT		 1298 return sig;
1299 break;
1300 }
1301#endif
1302
1303#if __mips >= 4
1304 case spec_op:
1305 if (MIPSInst_FUNC(ir) != movc_op)
1306 return SIGILL;
1307 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
1308 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
1309 xcp->regs[MIPSInst_RD(ir)] =
1310 xcp->regs[MIPSInst_RS(ir)];
1311 break;
1312#endif
1313
1314 default:
1ac94400 1315sigill:
1da177e4
LT		 1316 return SIGILL;
1317 }
1318
1319 /* we did it !! */
e70dfc10 1320 xcp->cp0_epc = contpc;
e7e9cae5 1321 clear_delay_slot(xcp);
333d1f67 1322
1da177e4
LT		 1323 return 0;
1324}
1325
1326/*
1327 * Conversion table from MIPS compare ops 48-63
1328 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1329 */
1330static const unsigned char cmptab[8] = {
1331 0, /* cmp_0 (sig) cmp_sf */
1332 IEEE754_CUN, /* cmp_un (sig) cmp_ngle */
1333 IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */
1334 IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */
1335 IEEE754_CLT, /* cmp_olt (sig) cmp_lt */
1336 IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */
1337 IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */
1338 IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */
1339};
1340
1341
1342#if __mips >= 4 && __mips != 32
1343
1344/*
1345 * Additional MIPS4 instructions
1346 */
1347
47fa0c02
RB		 1348#define DEF3OP(name, p, f1, f2, f3) \
1349static union ieee754##p fpemu_##p##_##name(union ieee754##p r, \
1350 union ieee754##p s, union ieee754##p t) \
1351{ \
1352 struct _ieee754_csr ieee754_csr_save; \
1353 s = f1(s, t); \
1354 ieee754_csr_save = ieee754_csr; \
1355 s = f2(s, r); \
1356 ieee754_csr_save.cx |= ieee754_csr.cx; \
1357 ieee754_csr_save.sx |= ieee754_csr.sx; \
1358 s = f3(s); \
1359 ieee754_csr.cx |= ieee754_csr_save.cx; \
1360 ieee754_csr.sx |= ieee754_csr_save.sx; \
1361 return s; \
1da177e4
LT		 1362}
1363
2209bcb1 1364static union ieee754dp fpemu_dp_recip(union ieee754dp d)
1da177e4
LT		 1365{
1366 return ieee754dp_div(ieee754dp_one(0), d);
1367}
1368
2209bcb1 1369static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d)
1da177e4
LT		 1370{
1371 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
1372}
1373
2209bcb1 1374static union ieee754sp fpemu_sp_recip(union ieee754sp s)
1da177e4
LT		 1375{
1376 return ieee754sp_div(ieee754sp_one(0), s);
1377}
1378
2209bcb1 1379static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s)
1da177e4
LT		 1380{
1381 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
1382}
1383
21a151d8
RB		 1384DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
1385DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
1da177e4
LT		 1386DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
1387DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
21a151d8
RB		 1388DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
1389DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
1da177e4
LT		 1390DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
1391DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
1392
eae89076 1393static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
515b029d 1394 mips_instruction ir, void *__user *fault_addr)
1da177e4
LT		 1395{
1396 unsigned rcsr = 0; /* resulting csr */
1397
b6ee75ed 1398 MIPS_FPU_EMU_INC_STATS(cp1xops);
1da177e4
LT		 1399
1400 switch (MIPSInst_FMA_FFMT(ir)) {
1401 case s_fmt:{ /* 0 */
1402
2209bcb1
RB		 1403 union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp);
1404 union ieee754sp fd, fr, fs, ft;
3fccc015 1405 u32 __user *va;
1da177e4
LT		 1406 u32 val;
1407
1408 switch (MIPSInst_FUNC(ir)) {
1409 case lwxc1_op:
3fccc015 1410 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1da177e4
LT		 1411 xcp->regs[MIPSInst_FT(ir)]);
1412
b6ee75ed 1413 MIPS_FPU_EMU_INC_STATS(loads);
515b029d 1414 if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
b6ee75ed 1415 MIPS_FPU_EMU_INC_STATS(errors);
515b029d 1416 *fault_addr = va;
1da177e4
LT		 1417 return SIGBUS;
1418 }
515b029d
DD		 1419 if (__get_user(val, va)) {
1420 MIPS_FPU_EMU_INC_STATS(errors);
1421 *fault_addr = va;
1422 return SIGSEGV;
1423 }
1da177e4
LT		 1424 SITOREG(val, MIPSInst_FD(ir));
1425 break;
1426
1427 case swxc1_op:
3fccc015 1428 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1da177e4
LT		 1429 xcp->regs[MIPSInst_FT(ir)]);
1430
b6ee75ed 1431 MIPS_FPU_EMU_INC_STATS(stores);
1da177e4
LT		 1432
1433 SIFROMREG(val, MIPSInst_FS(ir));
515b029d 1434 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
b6ee75ed 1435 MIPS_FPU_EMU_INC_STATS(errors);
515b029d 1436 *fault_addr = va;
1da177e4
LT		 1437 return SIGBUS;
1438 }
515b029d
DD		 1439 if (put_user(val, va)) {
1440 MIPS_FPU_EMU_INC_STATS(errors);
1441 *fault_addr = va;
1442 return SIGSEGV;
1443 }
1da177e4
LT		 1444 break;
1445
1446 case madd_s_op:
1447 handler = fpemu_sp_madd;
1448 goto scoptop;
1449 case msub_s_op:
1450 handler = fpemu_sp_msub;
1451 goto scoptop;
1452 case nmadd_s_op:
1453 handler = fpemu_sp_nmadd;
1454 goto scoptop;
1455 case nmsub_s_op:
1456 handler = fpemu_sp_nmsub;
1457 goto scoptop;
1458
1459 scoptop:
1460 SPFROMREG(fr, MIPSInst_FR(ir));
1461 SPFROMREG(fs, MIPSInst_FS(ir));
1462 SPFROMREG(ft, MIPSInst_FT(ir));
1463 fd = (*handler) (fr, fs, ft);
1464 SPTOREG(fd, MIPSInst_FD(ir));
1465
1466 copcsr:
1467 if (ieee754_cxtest(IEEE754_INEXACT))
1468 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1469 if (ieee754_cxtest(IEEE754_UNDERFLOW))
1470 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1471 if (ieee754_cxtest(IEEE754_OVERFLOW))
1472 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1473 if (ieee754_cxtest(IEEE754_INVALID_OPERATION))
1474 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1475
1476 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1da177e4
LT		 1477 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1478 /*printk ("SIGFPE: fpu csr = %08x\n",
1479 ctx->fcr31); */
1480 return SIGFPE;
1481 }
1482
1483 break;
1484
1485 default:
1486 return SIGILL;
1487 }
1488 break;
1489 }
1490
1da177e4 1491 case d_fmt:{ /* 1 */
2209bcb1
RB		 1492 union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp);
1493 union ieee754dp fd, fr, fs, ft;
3fccc015 1494 u64 __user *va;
1da177e4
LT		 1495 u64 val;
1496
1497 switch (MIPSInst_FUNC(ir)) {
1498 case ldxc1_op:
3fccc015 1499 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1da177e4
LT		 1500 xcp->regs[MIPSInst_FT(ir)]);
1501
b6ee75ed 1502 MIPS_FPU_EMU_INC_STATS(loads);
515b029d 1503 if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
b6ee75ed 1504 MIPS_FPU_EMU_INC_STATS(errors);
515b029d 1505 *fault_addr = va;
1da177e4
LT		 1506 return SIGBUS;
1507 }
515b029d
DD		 1508 if (__get_user(val, va)) {
1509 MIPS_FPU_EMU_INC_STATS(errors);
1510 *fault_addr = va;
1511 return SIGSEGV;
1512 }
1da177e4
LT		 1513 DITOREG(val, MIPSInst_FD(ir));
1514 break;
1515
1516 case sdxc1_op:
3fccc015 1517 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1da177e4
LT		 1518 xcp->regs[MIPSInst_FT(ir)]);
1519
b6ee75ed 1520 MIPS_FPU_EMU_INC_STATS(stores);
1da177e4 1521 DIFROMREG(val, MIPSInst_FS(ir));
515b029d 1522 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
b6ee75ed 1523 MIPS_FPU_EMU_INC_STATS(errors);
515b029d 1524 *fault_addr = va;
1da177e4
LT		 1525 return SIGBUS;
1526 }
515b029d
DD		 1527 if (__put_user(val, va)) {
1528 MIPS_FPU_EMU_INC_STATS(errors);
1529 *fault_addr = va;
1530 return SIGSEGV;
1531 }
1da177e4
LT		 1532 break;
1533
1534 case madd_d_op:
1535 handler = fpemu_dp_madd;
1536 goto dcoptop;
1537 case msub_d_op:
1538 handler = fpemu_dp_msub;
1539 goto dcoptop;
1540 case nmadd_d_op:
1541 handler = fpemu_dp_nmadd;
1542 goto dcoptop;
1543 case nmsub_d_op:
1544 handler = fpemu_dp_nmsub;
1545 goto dcoptop;
1546
1547 dcoptop:
1548 DPFROMREG(fr, MIPSInst_FR(ir));
1549 DPFROMREG(fs, MIPSInst_FS(ir));
1550 DPFROMREG(ft, MIPSInst_FT(ir));
1551 fd = (*handler) (fr, fs, ft);
1552 DPTOREG(fd, MIPSInst_FD(ir));
1553 goto copcsr;
1554
1555 default:
1556 return SIGILL;
1557 }
1558 break;
1559 }
1da177e4 1560
51061b88
DCZ		 1561 case 0x3:
1562 if (MIPSInst_FUNC(ir) != pfetch_op)
1da177e4 1563 return SIGILL;
51061b88 1564
1da177e4
LT		 1565 /* ignore prefx operation */
1566 break;
1567
1568 default:
1569 return SIGILL;
1570 }
1571
1572 return 0;
1573}
1574#endif
1575
1576
1577
1578/*
1579 * Emulate a single COP1 arithmetic instruction.
1580 */
eae89076 1581static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1da177e4
LT		 1582 mips_instruction ir)
1583{
1584 int rfmt; /* resulting format */
1585 unsigned rcsr = 0; /* resulting csr */
1586 unsigned cond;
1587 union {
2209bcb1
RB		 1588 union ieee754dp d;
1589 union ieee754sp s;
1da177e4 1590 int w;
766160c2 1591#ifdef __mips64
1da177e4
LT		 1592 s64 l;
1593#endif
1594 } rv; /* resulting value */
1595
b6ee75ed 1596 MIPS_FPU_EMU_INC_STATS(cp1ops);
1da177e4
LT		 1597 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
1598 case s_fmt:{ /* 0 */
1599 union {
2209bcb1
RB		 1600 union ieee754sp(*b) (union ieee754sp, union ieee754sp);
1601 union ieee754sp(*u) (union ieee754sp);
1da177e4
LT		 1602 } handler;
1603
1604 switch (MIPSInst_FUNC(ir)) {
1605 /* binary ops */
1606 case fadd_op:
1607 handler.b = ieee754sp_add;
1608 goto scopbop;
1609 case fsub_op:
1610 handler.b = ieee754sp_sub;
1611 goto scopbop;
1612 case fmul_op:
1613 handler.b = ieee754sp_mul;
1614 goto scopbop;
1615 case fdiv_op:
1616 handler.b = ieee754sp_div;
1617 goto scopbop;
1618
1619 /* unary ops */
587cb98f 1620#if __mips >= 2 || defined(__mips64)
1da177e4
LT		 1621 case fsqrt_op:
1622 handler.u = ieee754sp_sqrt;
1623 goto scopuop;
1624#endif
1625#if __mips >= 4 && __mips != 32
1626 case frsqrt_op:
1627 handler.u = fpemu_sp_rsqrt;
1628 goto scopuop;
1629 case frecip_op:
1630 handler.u = fpemu_sp_recip;
1631 goto scopuop;
1632#endif
1633#if __mips >= 4
1634 case fmovc_op:
1635 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1636 if (((ctx->fcr31 & cond) != 0) !=
1637 ((MIPSInst_FT(ir) & 1) != 0))
1638 return 0;
1639 SPFROMREG(rv.s, MIPSInst_FS(ir));
1640 break;
1641 case fmovz_op:
1642 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1643 return 0;
1644 SPFROMREG(rv.s, MIPSInst_FS(ir));
1645 break;
1646 case fmovn_op:
1647 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1648 return 0;
1649 SPFROMREG(rv.s, MIPSInst_FS(ir));
1650 break;
1651#endif
1652 case fabs_op:
1653 handler.u = ieee754sp_abs;
1654 goto scopuop;
1655 case fneg_op:
1656 handler.u = ieee754sp_neg;
1657 goto scopuop;
1658 case fmov_op:
1659 /* an easy one */
1660 SPFROMREG(rv.s, MIPSInst_FS(ir));
1661 goto copcsr;
1662
1663 /* binary op on handler */
1664 scopbop:
1665 {
2209bcb1 1666 union ieee754sp fs, ft;
1da177e4
LT		 1667
1668 SPFROMREG(fs, MIPSInst_FS(ir));
1669 SPFROMREG(ft, MIPSInst_FT(ir));
1670
1671 rv.s = (*handler.b) (fs, ft);
1672 goto copcsr;
1673 }
1674 scopuop:
1675 {
2209bcb1 1676 union ieee754sp fs;
1da177e4
LT		 1677
1678 SPFROMREG(fs, MIPSInst_FS(ir));
1679 rv.s = (*handler.u) (fs);
1680 goto copcsr;
1681 }
1682 copcsr:
1683 if (ieee754_cxtest(IEEE754_INEXACT))
1684 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1685 if (ieee754_cxtest(IEEE754_UNDERFLOW))
1686 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1687 if (ieee754_cxtest(IEEE754_OVERFLOW))
1688 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1689 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE))
1690 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
1691 if (ieee754_cxtest(IEEE754_INVALID_OPERATION))
1692 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1693 break;
1694
1695 /* unary conv ops */
1696 case fcvts_op:
1697 return SIGILL; /* not defined */
1698 case fcvtd_op:{
2209bcb1 1699 union ieee754sp fs;
1da177e4
LT		 1700
1701 SPFROMREG(fs, MIPSInst_FS(ir));
1702 rv.d = ieee754dp_fsp(fs);
1703 rfmt = d_fmt;
1704 goto copcsr;
1705 }
1da177e4 1706 case fcvtw_op:{
2209bcb1 1707 union ieee754sp fs;
1da177e4
LT		 1708
1709 SPFROMREG(fs, MIPSInst_FS(ir));
1710 rv.w = ieee754sp_tint(fs);
1711 rfmt = w_fmt;
1712 goto copcsr;
1713 }
1714
587cb98f 1715#if __mips >= 2 || defined(__mips64)
1da177e4
LT		 1716 case fround_op:
1717 case ftrunc_op:
1718 case fceil_op:
1719 case ffloor_op:{
1720 unsigned int oldrm = ieee754_csr.rm;
2209bcb1 1721 union ieee754sp fs;
1da177e4
LT		 1722
1723 SPFROMREG(fs, MIPSInst_FS(ir));
3f135530 1724 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1da177e4
LT		 1725 rv.w = ieee754sp_tint(fs);
1726 ieee754_csr.rm = oldrm;
1727 rfmt = w_fmt;
1728 goto copcsr;
1729 }
1730#endif /* __mips >= 2 */
1731
4b724efd 1732#if defined(__mips64)
1da177e4 1733 case fcvtl_op:{
2209bcb1 1734 union ieee754sp fs;
1da177e4
LT		 1735
1736 SPFROMREG(fs, MIPSInst_FS(ir));
1737 rv.l = ieee754sp_tlong(fs);
1738 rfmt = l_fmt;
1739 goto copcsr;
1740 }
1741
1742 case froundl_op:
1743 case ftruncl_op:
1744 case fceill_op:
1745 case ffloorl_op:{
1746 unsigned int oldrm = ieee754_csr.rm;
2209bcb1 1747 union ieee754sp fs;
1da177e4
LT		 1748
1749 SPFROMREG(fs, MIPSInst_FS(ir));
3f135530 1750 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1da177e4
LT		 1751 rv.l = ieee754sp_tlong(fs);
1752 ieee754_csr.rm = oldrm;
1753 rfmt = l_fmt;
1754 goto copcsr;
1755 }
4b724efd 1756#endif /* defined(__mips64) */
1da177e4
LT		 1757
1758 default:
1759 if (MIPSInst_FUNC(ir) >= fcmp_op) {
1760 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
2209bcb1 1761 union ieee754sp fs, ft;
1da177e4
LT		 1762
1763 SPFROMREG(fs, MIPSInst_FS(ir));
1764 SPFROMREG(ft, MIPSInst_FT(ir));
1765 rv.w = ieee754sp_cmp(fs, ft,
1766 cmptab[cmpop & 0x7], cmpop & 0x8);
1767 rfmt = -1;
1768 if ((cmpop & 0x8) && ieee754_cxtest
1769 (IEEE754_INVALID_OPERATION))
1770 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1771 else
1772 goto copcsr;
1773
1774 }
1775 else {
1776 return SIGILL;
1777 }
1778 break;
1779 }
1780 break;
1781 }
1782
1da177e4
LT		 1783 case d_fmt:{
1784 union {
2209bcb1
RB		 1785 union ieee754dp(*b) (union ieee754dp, union ieee754dp);
1786 union ieee754dp(*u) (union ieee754dp);
1da177e4
LT		 1787 } handler;
1788
1789 switch (MIPSInst_FUNC(ir)) {
1790 /* binary ops */
1791 case fadd_op:
1792 handler.b = ieee754dp_add;
1793 goto dcopbop;
1794 case fsub_op:
1795 handler.b = ieee754dp_sub;
1796 goto dcopbop;
1797 case fmul_op:
1798 handler.b = ieee754dp_mul;
1799 goto dcopbop;
1800 case fdiv_op:
1801 handler.b = ieee754dp_div;
1802 goto dcopbop;
1803
1804 /* unary ops */
587cb98f 1805#if __mips >= 2 || defined(__mips64)
1da177e4
LT		 1806 case fsqrt_op:
1807 handler.u = ieee754dp_sqrt;
1808 goto dcopuop;
1809#endif
1810#if __mips >= 4 && __mips != 32
1811 case frsqrt_op:
1812 handler.u = fpemu_dp_rsqrt;
1813 goto dcopuop;
1814 case frecip_op:
1815 handler.u = fpemu_dp_recip;
1816 goto dcopuop;
1817#endif
1818#if __mips >= 4
1819 case fmovc_op:
1820 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1821 if (((ctx->fcr31 & cond) != 0) !=
1822 ((MIPSInst_FT(ir) & 1) != 0))
1823 return 0;
1824 DPFROMREG(rv.d, MIPSInst_FS(ir));
1825 break;
1826 case fmovz_op:
1827 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1828 return 0;
1829 DPFROMREG(rv.d, MIPSInst_FS(ir));
1830 break;
1831 case fmovn_op:
1832 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1833 return 0;
1834 DPFROMREG(rv.d, MIPSInst_FS(ir));
1835 break;
1836#endif
1837 case fabs_op:
1838 handler.u = ieee754dp_abs;
1839 goto dcopuop;
1840
1841 case fneg_op:
1842 handler.u = ieee754dp_neg;
1843 goto dcopuop;
1844
1845 case fmov_op:
1846 /* an easy one */
1847 DPFROMREG(rv.d, MIPSInst_FS(ir));
1848 goto copcsr;
1849
1850 /* binary op on handler */
1851 dcopbop:{
2209bcb1 1852 union ieee754dp fs, ft;
1da177e4
LT		 1853
1854 DPFROMREG(fs, MIPSInst_FS(ir));
1855 DPFROMREG(ft, MIPSInst_FT(ir));
1856
1857 rv.d = (*handler.b) (fs, ft);
1858 goto copcsr;
1859 }
1860 dcopuop:{
2209bcb1 1861 union ieee754dp fs;
1da177e4
LT		 1862
1863 DPFROMREG(fs, MIPSInst_FS(ir));
1864 rv.d = (*handler.u) (fs);
1865 goto copcsr;
1866 }
1867
1868 /* unary conv ops */
1869 case fcvts_op:{
2209bcb1 1870 union ieee754dp fs;
1da177e4
LT		 1871
1872 DPFROMREG(fs, MIPSInst_FS(ir));
1873 rv.s = ieee754sp_fdp(fs);
1874 rfmt = s_fmt;
1875 goto copcsr;
1876 }
1877 case fcvtd_op:
1878 return SIGILL; /* not defined */
1879
1880 case fcvtw_op:{
2209bcb1 1881 union ieee754dp fs;
1da177e4
LT		 1882
1883 DPFROMREG(fs, MIPSInst_FS(ir));
1884 rv.w = ieee754dp_tint(fs); /* wrong */
1885 rfmt = w_fmt;
1886 goto copcsr;
1887 }
1888
587cb98f 1889#if __mips >= 2 || defined(__mips64)
1da177e4
LT		 1890 case fround_op:
1891 case ftrunc_op:
1892 case fceil_op:
1893 case ffloor_op:{
1894 unsigned int oldrm = ieee754_csr.rm;
2209bcb1 1895 union ieee754dp fs;
1da177e4
LT		 1896
1897 DPFROMREG(fs, MIPSInst_FS(ir));
3f135530 1898 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1da177e4
LT		 1899 rv.w = ieee754dp_tint(fs);
1900 ieee754_csr.rm = oldrm;
1901 rfmt = w_fmt;
1902 goto copcsr;
1903 }
1904#endif
1905
4b724efd 1906#if defined(__mips64)
1da177e4 1907 case fcvtl_op:{
2209bcb1 1908 union ieee754dp fs;
1da177e4
LT		 1909
1910 DPFROMREG(fs, MIPSInst_FS(ir));
1911 rv.l = ieee754dp_tlong(fs);
1912 rfmt = l_fmt;
1913 goto copcsr;
1914 }
1915
1916 case froundl_op:
1917 case ftruncl_op:
1918 case fceill_op:
1919 case ffloorl_op:{
1920 unsigned int oldrm = ieee754_csr.rm;
2209bcb1 1921 union ieee754dp fs;
1da177e4
LT		 1922
1923 DPFROMREG(fs, MIPSInst_FS(ir));
3f135530 1924 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1da177e4
LT		 1925 rv.l = ieee754dp_tlong(fs);
1926 ieee754_csr.rm = oldrm;
1927 rfmt = l_fmt;
1928 goto copcsr;
1929 }
4b724efd 1930#endif /* __mips >= 3 */
1da177e4
LT		 1931
1932 default:
1933 if (MIPSInst_FUNC(ir) >= fcmp_op) {
1934 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
2209bcb1 1935 union ieee754dp fs, ft;
1da177e4
LT		 1936
1937 DPFROMREG(fs, MIPSInst_FS(ir));
1938 DPFROMREG(ft, MIPSInst_FT(ir));
1939 rv.w = ieee754dp_cmp(fs, ft,
1940 cmptab[cmpop & 0x7], cmpop & 0x8);
1941 rfmt = -1;
1942 if ((cmpop & 0x8)
1943 &&
1944 ieee754_cxtest
1945 (IEEE754_INVALID_OPERATION))
1946 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1947 else
1948 goto copcsr;
1949
1950 }
1951 else {
1952 return SIGILL;
1953 }
1954 break;
1955 }
1956 break;
1957 }
1da177e4
LT		 1958
1959 case w_fmt:{
2209bcb1 1960 union ieee754sp fs;
1da177e4
LT		 1961
1962 switch (MIPSInst_FUNC(ir)) {
1963 case fcvts_op:
1964 /* convert word to single precision real */
1965 SPFROMREG(fs, MIPSInst_FS(ir));
1966 rv.s = ieee754sp_fint(fs.bits);
1967 rfmt = s_fmt;
1968 goto copcsr;
1da177e4
LT		 1969 case fcvtd_op:
1970 /* convert word to double precision real */
1971 SPFROMREG(fs, MIPSInst_FS(ir));
1972 rv.d = ieee754dp_fint(fs.bits);
1973 rfmt = d_fmt;
1974 goto copcsr;
1da177e4
LT		 1975 default:
1976 return SIGILL;
1977 }
1978 break;
1979 }
1980
4b724efd 1981#if defined(__mips64)
1da177e4 1982 case l_fmt:{
bbd426f5
PB		 1983 u64 bits;
1984 DIFROMREG(bits, MIPSInst_FS(ir));
1985
1da177e4
LT		 1986 switch (MIPSInst_FUNC(ir)) {
1987 case fcvts_op:
1988 /* convert long to single precision real */
bbd426f5 1989 rv.s = ieee754sp_flong(bits);
1da177e4
LT		 1990 rfmt = s_fmt;
1991 goto copcsr;
1992 case fcvtd_op:
1993 /* convert long to double precision real */
bbd426f5 1994 rv.d = ieee754dp_flong(bits);
1da177e4
LT		 1995 rfmt = d_fmt;
1996 goto copcsr;
1997 default:
1998 return SIGILL;
1999 }
2000 break;
2001 }
2002#endif
2003
2004 default:
2005 return SIGILL;
2006 }
2007
2008 /*
2009 * Update the fpu CSR register for this operation.
2010 * If an exception is required, generate a tidy SIGFPE exception,
2011 * without updating the result register.
2012 * Note: cause exception bits do not accumulate, they are rewritten
2013 * for each op; only the flag/sticky bits accumulate.
2014 */
2015 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
2016 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
2017 /*printk ("SIGFPE: fpu csr = %08x\n",ctx->fcr31); */
2018 return SIGFPE;
2019 }
2020
2021 /*
2022 * Now we can safely write the result back to the register file.
2023 */
2024 switch (rfmt) {
2025 case -1:{
2026#if __mips >= 4
2027 cond = fpucondbit[MIPSInst_FD(ir) >> 2];
2028#else
2029 cond = FPU_CSR_COND;
2030#endif
2031 if (rv.w)
2032 ctx->fcr31 |= cond;
2033 else
2034 ctx->fcr31 &= ~cond;
2035 break;
2036 }
1da177e4
LT		 2037 case d_fmt:
2038 DPTOREG(rv.d, MIPSInst_FD(ir));
2039 break;
1da177e4
LT		 2040 case s_fmt:
2041 SPTOREG(rv.s, MIPSInst_FD(ir));
2042 break;
2043 case w_fmt:
2044 SITOREG(rv.w, MIPSInst_FD(ir));
2045 break;
4b724efd 2046#if defined(__mips64)
1da177e4
LT		 2047 case l_fmt:
2048 DITOREG(rv.l, MIPSInst_FD(ir));
2049 break;
2050#endif
2051 default:
2052 return SIGILL;
2053 }
2054
2055 return 0;
2056}
2057
e04582b7 2058int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
515b029d 2059 int has_fpu, void *__user *fault_addr)
1da177e4 2060{
333d1f67 2061 unsigned long oldepc, prevepc;
102cedc3
LY		 2062 struct mm_decoded_insn dec_insn;
2063 u16 instr[4];
2064 u16 *instr_ptr;
1da177e4
LT		 2065 int sig = 0;
2066
2067 oldepc = xcp->cp0_epc;
2068 do {
2069 prevepc = xcp->cp0_epc;
2070
102cedc3
LY		 2071 if (get_isa16_mode(prevepc) && cpu_has_mmips) {
2072 /*
2073 * Get next 2 microMIPS instructions and convert them
2074 * into 32-bit instructions.
2075 */
2076 if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) ||
2077 (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) ||
2078 (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) ||
2079 (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) {
2080 MIPS_FPU_EMU_INC_STATS(errors);
2081 return SIGBUS;
2082 }
2083 instr_ptr = instr;
2084
2085 /* Get first instruction. */
2086 if (mm_insn_16bit(*instr_ptr)) {
2087 /* Duplicate the half-word. */
2088 dec_insn.insn = (*instr_ptr << 16) |
2089 (*instr_ptr);
2090 /* 16-bit instruction. */
2091 dec_insn.pc_inc = 2;
2092 instr_ptr += 1;
2093 } else {
2094 dec_insn.insn = (*instr_ptr << 16) |
2095 *(instr_ptr+1);
2096 /* 32-bit instruction. */
2097 dec_insn.pc_inc = 4;
2098 instr_ptr += 2;
2099 }
2100 /* Get second instruction. */
2101 if (mm_insn_16bit(*instr_ptr)) {
2102 /* Duplicate the half-word. */
2103 dec_insn.next_insn = (*instr_ptr << 16) |
2104 (*instr_ptr);
2105 /* 16-bit instruction. */
2106 dec_insn.next_pc_inc = 2;
2107 } else {
2108 dec_insn.next_insn = (*instr_ptr << 16) |
2109 *(instr_ptr+1);
2110 /* 32-bit instruction. */
2111 dec_insn.next_pc_inc = 4;
2112 }
2113 dec_insn.micro_mips_mode = 1;
2114 } else {
2115 if ((get_user(dec_insn.insn,
2116 (mips_instruction __user *) xcp->cp0_epc)) ||
2117 (get_user(dec_insn.next_insn,
2118 (mips_instruction __user *)(xcp->cp0_epc+4)))) {
2119 MIPS_FPU_EMU_INC_STATS(errors);
2120 return SIGBUS;
2121 }
2122 dec_insn.pc_inc = 4;
2123 dec_insn.next_pc_inc = 4;
2124 dec_insn.micro_mips_mode = 0;
515b029d 2125 }
102cedc3
LY		 2126
2127 if ((dec_insn.insn == 0) ||
2128 ((dec_insn.pc_inc == 2) &&
2129 ((dec_insn.insn & 0xffff) == MM_NOP16)))
2130 xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */
1da177e4 2131 else {
cd21dfcf
RB		 2132 /*
2133 * The 'ieee754_csr' is an alias of
70342287
RB		 2134 * ctx->fcr31. No need to copy ctx->fcr31 to
2135 * ieee754_csr. But ieee754_csr.rm is ieee
cd21dfcf
RB		 2136 * library modes. (not mips rounding mode)
2137 */
2138 /* convert to ieee library modes */
2139 ieee754_csr.rm = ieee_rm[ieee754_csr.rm];
102cedc3 2140 sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
cd21dfcf
RB		 2141 /* revert to mips rounding mode */
2142 ieee754_csr.rm = mips_rm[ieee754_csr.rm];
1da177e4
LT		 2143 }
2144
e04582b7 2145 if (has_fpu)
1da177e4
LT		 2146 break;
2147 if (sig)
2148 break;
2149
2150 cond_resched();
2151 } while (xcp->cp0_epc > prevepc);
2152
2153 /* SIGILL indicates a non-fpu instruction */
2154 if (sig == SIGILL && xcp->cp0_epc != oldepc)
2155 /* but if epc has advanced, then ignore it */
2156 sig = 0;
2157
2158 return sig;
2159}
Linux 6.x block layer and io_uring tree(s)