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1da177e4 LT |
1 | /* |
2 | * cp1emu.c: a MIPS coprocessor 1 (fpu) instruction emulator | |
3 | * | |
4 | * MIPS floating point support | |
5 | * Copyright (C) 1994-2000 Algorithmics Ltd. | |
1da177e4 LT |
6 | * |
7 | * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com | |
8 | * Copyright (C) 2000 MIPS Technologies, Inc. | |
9 | * | |
10 | * This program is free software; you can distribute it and/or modify it | |
11 | * under the terms of the GNU General Public License (Version 2) as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope it will be useful, but WITHOUT | |
15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | * for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License along | |
20 | * with this program; if not, write to the Free Software Foundation, Inc., | |
21 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. | |
22 | * | |
23 | * A complete emulator for MIPS coprocessor 1 instructions. This is | |
24 | * required for #float(switch) or #float(trap), where it catches all | |
25 | * COP1 instructions via the "CoProcessor Unusable" exception. | |
26 | * | |
27 | * More surprisingly it is also required for #float(ieee), to help out | |
28 | * the hardware fpu at the boundaries of the IEEE-754 representation | |
29 | * (denormalised values, infinities, underflow, etc). It is made | |
30 | * quite nasty because emulation of some non-COP1 instructions is | |
31 | * required, e.g. in branch delay slots. | |
32 | * | |
33 | * Note if you know that you won't have an fpu, then you'll get much | |
34 | * better performance by compiling with -msoft-float! | |
35 | */ | |
36 | #include <linux/sched.h> | |
83fd38ca | 37 | #include <linux/debugfs.h> |
08a07904 | 38 | #include <linux/kconfig.h> |
85c51c51 | 39 | #include <linux/percpu-defs.h> |
7f788d2d | 40 | #include <linux/perf_event.h> |
1da177e4 | 41 | |
cd8ee345 | 42 | #include <asm/branch.h> |
1da177e4 | 43 | #include <asm/inst.h> |
1da177e4 LT |
44 | #include <asm/ptrace.h> |
45 | #include <asm/signal.h> | |
cd8ee345 RB |
46 | #include <asm/uaccess.h> |
47 | ||
48 | #include <asm/processor.h> | |
1da177e4 | 49 | #include <asm/fpu_emulator.h> |
102cedc3 | 50 | #include <asm/fpu.h> |
1da177e4 LT |
51 | |
52 | #include "ieee754.h" | |
1da177e4 | 53 | |
1da177e4 LT |
54 | /* Function which emulates a floating point instruction. */ |
55 | ||
eae89076 | 56 | static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *, |
1da177e4 LT |
57 | mips_instruction); |
58 | ||
1da177e4 | 59 | static int fpux_emu(struct pt_regs *, |
515b029d | 60 | struct mips_fpu_struct *, mips_instruction, void *__user *); |
1da177e4 | 61 | |
1da177e4 LT |
62 | /* Control registers */ |
63 | ||
64 | #define FPCREG_RID 0 /* $0 = revision id */ | |
65 | #define FPCREG_CSR 31 /* $31 = csr */ | |
66 | ||
95e8f634 SM |
67 | /* Determine rounding mode from the RM bits of the FCSR */ |
68 | #define modeindex(v) ((v) & FPU_CSR_RM) | |
69 | ||
102cedc3 LY |
70 | /* microMIPS bitfields */ |
71 | #define MM_POOL32A_MINOR_MASK 0x3f | |
72 | #define MM_POOL32A_MINOR_SHIFT 0x6 | |
73 | #define MM_MIPS32_COND_FC 0x30 | |
74 | ||
1da177e4 LT |
75 | /* Convert Mips rounding mode (0..3) to IEEE library modes. */ |
76 | static const unsigned char ieee_rm[4] = { | |
cd21dfcf RB |
77 | [FPU_CSR_RN] = IEEE754_RN, |
78 | [FPU_CSR_RZ] = IEEE754_RZ, | |
79 | [FPU_CSR_RU] = IEEE754_RU, | |
80 | [FPU_CSR_RD] = IEEE754_RD, | |
81 | }; | |
82 | /* Convert IEEE library modes to Mips rounding mode (0..3). */ | |
83 | static const unsigned char mips_rm[4] = { | |
84 | [IEEE754_RN] = FPU_CSR_RN, | |
85 | [IEEE754_RZ] = FPU_CSR_RZ, | |
86 | [IEEE754_RD] = FPU_CSR_RD, | |
87 | [IEEE754_RU] = FPU_CSR_RU, | |
1da177e4 LT |
88 | }; |
89 | ||
1da177e4 LT |
90 | /* convert condition code register number to csr bit */ |
91 | static const unsigned int fpucondbit[8] = { | |
92 | FPU_CSR_COND0, | |
93 | FPU_CSR_COND1, | |
94 | FPU_CSR_COND2, | |
95 | FPU_CSR_COND3, | |
96 | FPU_CSR_COND4, | |
97 | FPU_CSR_COND5, | |
98 | FPU_CSR_COND6, | |
99 | FPU_CSR_COND7 | |
100 | }; | |
1da177e4 | 101 | |
102cedc3 LY |
102 | /* (microMIPS) Convert 16-bit register encoding to 32-bit register encoding. */ |
103 | static const unsigned int reg16to32map[8] = {16, 17, 2, 3, 4, 5, 6, 7}; | |
104 | ||
105 | /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */ | |
106 | static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0}; | |
107 | static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0}; | |
108 | static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0}; | |
109 | static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0}; | |
110 | ||
111 | /* | |
112 | * This functions translates a 32-bit microMIPS instruction | |
113 | * into a 32-bit MIPS32 instruction. Returns 0 on success | |
114 | * and SIGILL otherwise. | |
115 | */ | |
116 | static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr) | |
117 | { | |
118 | union mips_instruction insn = *insn_ptr; | |
119 | union mips_instruction mips32_insn = insn; | |
120 | int func, fmt, op; | |
121 | ||
122 | switch (insn.mm_i_format.opcode) { | |
123 | case mm_ldc132_op: | |
124 | mips32_insn.mm_i_format.opcode = ldc1_op; | |
125 | mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; | |
126 | mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; | |
127 | break; | |
128 | case mm_lwc132_op: | |
129 | mips32_insn.mm_i_format.opcode = lwc1_op; | |
130 | mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; | |
131 | mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; | |
132 | break; | |
133 | case mm_sdc132_op: | |
134 | mips32_insn.mm_i_format.opcode = sdc1_op; | |
135 | mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; | |
136 | mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; | |
137 | break; | |
138 | case mm_swc132_op: | |
139 | mips32_insn.mm_i_format.opcode = swc1_op; | |
140 | mips32_insn.mm_i_format.rt = insn.mm_i_format.rs; | |
141 | mips32_insn.mm_i_format.rs = insn.mm_i_format.rt; | |
142 | break; | |
143 | case mm_pool32i_op: | |
144 | /* NOTE: offset is << by 1 if in microMIPS mode. */ | |
145 | if ((insn.mm_i_format.rt == mm_bc1f_op) || | |
146 | (insn.mm_i_format.rt == mm_bc1t_op)) { | |
147 | mips32_insn.fb_format.opcode = cop1_op; | |
148 | mips32_insn.fb_format.bc = bc_op; | |
149 | mips32_insn.fb_format.flag = | |
150 | (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0; | |
151 | } else | |
152 | return SIGILL; | |
153 | break; | |
154 | case mm_pool32f_op: | |
155 | switch (insn.mm_fp0_format.func) { | |
156 | case mm_32f_01_op: | |
157 | case mm_32f_11_op: | |
158 | case mm_32f_02_op: | |
159 | case mm_32f_12_op: | |
160 | case mm_32f_41_op: | |
161 | case mm_32f_51_op: | |
162 | case mm_32f_42_op: | |
163 | case mm_32f_52_op: | |
164 | op = insn.mm_fp0_format.func; | |
165 | if (op == mm_32f_01_op) | |
166 | func = madd_s_op; | |
167 | else if (op == mm_32f_11_op) | |
168 | func = madd_d_op; | |
169 | else if (op == mm_32f_02_op) | |
170 | func = nmadd_s_op; | |
171 | else if (op == mm_32f_12_op) | |
172 | func = nmadd_d_op; | |
173 | else if (op == mm_32f_41_op) | |
174 | func = msub_s_op; | |
175 | else if (op == mm_32f_51_op) | |
176 | func = msub_d_op; | |
177 | else if (op == mm_32f_42_op) | |
178 | func = nmsub_s_op; | |
179 | else | |
180 | func = nmsub_d_op; | |
181 | mips32_insn.fp6_format.opcode = cop1x_op; | |
182 | mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr; | |
183 | mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft; | |
184 | mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs; | |
185 | mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd; | |
186 | mips32_insn.fp6_format.func = func; | |
187 | break; | |
188 | case mm_32f_10_op: | |
189 | func = -1; /* Invalid */ | |
190 | op = insn.mm_fp5_format.op & 0x7; | |
191 | if (op == mm_ldxc1_op) | |
192 | func = ldxc1_op; | |
193 | else if (op == mm_sdxc1_op) | |
194 | func = sdxc1_op; | |
195 | else if (op == mm_lwxc1_op) | |
196 | func = lwxc1_op; | |
197 | else if (op == mm_swxc1_op) | |
198 | func = swxc1_op; | |
199 | ||
200 | if (func != -1) { | |
201 | mips32_insn.r_format.opcode = cop1x_op; | |
202 | mips32_insn.r_format.rs = | |
203 | insn.mm_fp5_format.base; | |
204 | mips32_insn.r_format.rt = | |
205 | insn.mm_fp5_format.index; | |
206 | mips32_insn.r_format.rd = 0; | |
207 | mips32_insn.r_format.re = insn.mm_fp5_format.fd; | |
208 | mips32_insn.r_format.func = func; | |
209 | } else | |
210 | return SIGILL; | |
211 | break; | |
212 | case mm_32f_40_op: | |
213 | op = -1; /* Invalid */ | |
214 | if (insn.mm_fp2_format.op == mm_fmovt_op) | |
215 | op = 1; | |
216 | else if (insn.mm_fp2_format.op == mm_fmovf_op) | |
217 | op = 0; | |
218 | if (op != -1) { | |
219 | mips32_insn.fp0_format.opcode = cop1_op; | |
220 | mips32_insn.fp0_format.fmt = | |
221 | sdps_format[insn.mm_fp2_format.fmt]; | |
222 | mips32_insn.fp0_format.ft = | |
223 | (insn.mm_fp2_format.cc<<2) + op; | |
224 | mips32_insn.fp0_format.fs = | |
225 | insn.mm_fp2_format.fs; | |
226 | mips32_insn.fp0_format.fd = | |
227 | insn.mm_fp2_format.fd; | |
228 | mips32_insn.fp0_format.func = fmovc_op; | |
229 | } else | |
230 | return SIGILL; | |
231 | break; | |
232 | case mm_32f_60_op: | |
233 | func = -1; /* Invalid */ | |
234 | if (insn.mm_fp0_format.op == mm_fadd_op) | |
235 | func = fadd_op; | |
236 | else if (insn.mm_fp0_format.op == mm_fsub_op) | |
237 | func = fsub_op; | |
238 | else if (insn.mm_fp0_format.op == mm_fmul_op) | |
239 | func = fmul_op; | |
240 | else if (insn.mm_fp0_format.op == mm_fdiv_op) | |
241 | func = fdiv_op; | |
242 | if (func != -1) { | |
243 | mips32_insn.fp0_format.opcode = cop1_op; | |
244 | mips32_insn.fp0_format.fmt = | |
245 | sdps_format[insn.mm_fp0_format.fmt]; | |
246 | mips32_insn.fp0_format.ft = | |
247 | insn.mm_fp0_format.ft; | |
248 | mips32_insn.fp0_format.fs = | |
249 | insn.mm_fp0_format.fs; | |
250 | mips32_insn.fp0_format.fd = | |
251 | insn.mm_fp0_format.fd; | |
252 | mips32_insn.fp0_format.func = func; | |
253 | } else | |
254 | return SIGILL; | |
255 | break; | |
256 | case mm_32f_70_op: | |
257 | func = -1; /* Invalid */ | |
258 | if (insn.mm_fp0_format.op == mm_fmovn_op) | |
259 | func = fmovn_op; | |
260 | else if (insn.mm_fp0_format.op == mm_fmovz_op) | |
261 | func = fmovz_op; | |
262 | if (func != -1) { | |
263 | mips32_insn.fp0_format.opcode = cop1_op; | |
264 | mips32_insn.fp0_format.fmt = | |
265 | sdps_format[insn.mm_fp0_format.fmt]; | |
266 | mips32_insn.fp0_format.ft = | |
267 | insn.mm_fp0_format.ft; | |
268 | mips32_insn.fp0_format.fs = | |
269 | insn.mm_fp0_format.fs; | |
270 | mips32_insn.fp0_format.fd = | |
271 | insn.mm_fp0_format.fd; | |
272 | mips32_insn.fp0_format.func = func; | |
273 | } else | |
274 | return SIGILL; | |
275 | break; | |
276 | case mm_32f_73_op: /* POOL32FXF */ | |
277 | switch (insn.mm_fp1_format.op) { | |
278 | case mm_movf0_op: | |
279 | case mm_movf1_op: | |
280 | case mm_movt0_op: | |
281 | case mm_movt1_op: | |
282 | if ((insn.mm_fp1_format.op & 0x7f) == | |
283 | mm_movf0_op) | |
284 | op = 0; | |
285 | else | |
286 | op = 1; | |
287 | mips32_insn.r_format.opcode = spec_op; | |
288 | mips32_insn.r_format.rs = insn.mm_fp4_format.fs; | |
289 | mips32_insn.r_format.rt = | |
290 | (insn.mm_fp4_format.cc << 2) + op; | |
291 | mips32_insn.r_format.rd = insn.mm_fp4_format.rt; | |
292 | mips32_insn.r_format.re = 0; | |
293 | mips32_insn.r_format.func = movc_op; | |
294 | break; | |
295 | case mm_fcvtd0_op: | |
296 | case mm_fcvtd1_op: | |
297 | case mm_fcvts0_op: | |
298 | case mm_fcvts1_op: | |
299 | if ((insn.mm_fp1_format.op & 0x7f) == | |
300 | mm_fcvtd0_op) { | |
301 | func = fcvtd_op; | |
302 | fmt = swl_format[insn.mm_fp3_format.fmt]; | |
303 | } else { | |
304 | func = fcvts_op; | |
305 | fmt = dwl_format[insn.mm_fp3_format.fmt]; | |
306 | } | |
307 | mips32_insn.fp0_format.opcode = cop1_op; | |
308 | mips32_insn.fp0_format.fmt = fmt; | |
309 | mips32_insn.fp0_format.ft = 0; | |
310 | mips32_insn.fp0_format.fs = | |
311 | insn.mm_fp3_format.fs; | |
312 | mips32_insn.fp0_format.fd = | |
313 | insn.mm_fp3_format.rt; | |
314 | mips32_insn.fp0_format.func = func; | |
315 | break; | |
316 | case mm_fmov0_op: | |
317 | case mm_fmov1_op: | |
318 | case mm_fabs0_op: | |
319 | case mm_fabs1_op: | |
320 | case mm_fneg0_op: | |
321 | case mm_fneg1_op: | |
322 | if ((insn.mm_fp1_format.op & 0x7f) == | |
323 | mm_fmov0_op) | |
324 | func = fmov_op; | |
325 | else if ((insn.mm_fp1_format.op & 0x7f) == | |
326 | mm_fabs0_op) | |
327 | func = fabs_op; | |
328 | else | |
329 | func = fneg_op; | |
330 | mips32_insn.fp0_format.opcode = cop1_op; | |
331 | mips32_insn.fp0_format.fmt = | |
332 | sdps_format[insn.mm_fp3_format.fmt]; | |
333 | mips32_insn.fp0_format.ft = 0; | |
334 | mips32_insn.fp0_format.fs = | |
335 | insn.mm_fp3_format.fs; | |
336 | mips32_insn.fp0_format.fd = | |
337 | insn.mm_fp3_format.rt; | |
338 | mips32_insn.fp0_format.func = func; | |
339 | break; | |
340 | case mm_ffloorl_op: | |
341 | case mm_ffloorw_op: | |
342 | case mm_fceill_op: | |
343 | case mm_fceilw_op: | |
344 | case mm_ftruncl_op: | |
345 | case mm_ftruncw_op: | |
346 | case mm_froundl_op: | |
347 | case mm_froundw_op: | |
348 | case mm_fcvtl_op: | |
349 | case mm_fcvtw_op: | |
350 | if (insn.mm_fp1_format.op == mm_ffloorl_op) | |
351 | func = ffloorl_op; | |
352 | else if (insn.mm_fp1_format.op == mm_ffloorw_op) | |
353 | func = ffloor_op; | |
354 | else if (insn.mm_fp1_format.op == mm_fceill_op) | |
355 | func = fceill_op; | |
356 | else if (insn.mm_fp1_format.op == mm_fceilw_op) | |
357 | func = fceil_op; | |
358 | else if (insn.mm_fp1_format.op == mm_ftruncl_op) | |
359 | func = ftruncl_op; | |
360 | else if (insn.mm_fp1_format.op == mm_ftruncw_op) | |
361 | func = ftrunc_op; | |
362 | else if (insn.mm_fp1_format.op == mm_froundl_op) | |
363 | func = froundl_op; | |
364 | else if (insn.mm_fp1_format.op == mm_froundw_op) | |
365 | func = fround_op; | |
366 | else if (insn.mm_fp1_format.op == mm_fcvtl_op) | |
367 | func = fcvtl_op; | |
368 | else | |
369 | func = fcvtw_op; | |
370 | mips32_insn.fp0_format.opcode = cop1_op; | |
371 | mips32_insn.fp0_format.fmt = | |
372 | sd_format[insn.mm_fp1_format.fmt]; | |
373 | mips32_insn.fp0_format.ft = 0; | |
374 | mips32_insn.fp0_format.fs = | |
375 | insn.mm_fp1_format.fs; | |
376 | mips32_insn.fp0_format.fd = | |
377 | insn.mm_fp1_format.rt; | |
378 | mips32_insn.fp0_format.func = func; | |
379 | break; | |
380 | case mm_frsqrt_op: | |
381 | case mm_fsqrt_op: | |
382 | case mm_frecip_op: | |
383 | if (insn.mm_fp1_format.op == mm_frsqrt_op) | |
384 | func = frsqrt_op; | |
385 | else if (insn.mm_fp1_format.op == mm_fsqrt_op) | |
386 | func = fsqrt_op; | |
387 | else | |
388 | func = frecip_op; | |
389 | mips32_insn.fp0_format.opcode = cop1_op; | |
390 | mips32_insn.fp0_format.fmt = | |
391 | sdps_format[insn.mm_fp1_format.fmt]; | |
392 | mips32_insn.fp0_format.ft = 0; | |
393 | mips32_insn.fp0_format.fs = | |
394 | insn.mm_fp1_format.fs; | |
395 | mips32_insn.fp0_format.fd = | |
396 | insn.mm_fp1_format.rt; | |
397 | mips32_insn.fp0_format.func = func; | |
398 | break; | |
399 | case mm_mfc1_op: | |
400 | case mm_mtc1_op: | |
401 | case mm_cfc1_op: | |
402 | case mm_ctc1_op: | |
9355e59c SH |
403 | case mm_mfhc1_op: |
404 | case mm_mthc1_op: | |
102cedc3 LY |
405 | if (insn.mm_fp1_format.op == mm_mfc1_op) |
406 | op = mfc_op; | |
407 | else if (insn.mm_fp1_format.op == mm_mtc1_op) | |
408 | op = mtc_op; | |
409 | else if (insn.mm_fp1_format.op == mm_cfc1_op) | |
410 | op = cfc_op; | |
9355e59c | 411 | else if (insn.mm_fp1_format.op == mm_ctc1_op) |
102cedc3 | 412 | op = ctc_op; |
9355e59c SH |
413 | else if (insn.mm_fp1_format.op == mm_mfhc1_op) |
414 | op = mfhc_op; | |
415 | else | |
416 | op = mthc_op; | |
102cedc3 LY |
417 | mips32_insn.fp1_format.opcode = cop1_op; |
418 | mips32_insn.fp1_format.op = op; | |
419 | mips32_insn.fp1_format.rt = | |
420 | insn.mm_fp1_format.rt; | |
421 | mips32_insn.fp1_format.fs = | |
422 | insn.mm_fp1_format.fs; | |
423 | mips32_insn.fp1_format.fd = 0; | |
424 | mips32_insn.fp1_format.func = 0; | |
425 | break; | |
426 | default: | |
427 | return SIGILL; | |
102cedc3 LY |
428 | } |
429 | break; | |
430 | case mm_32f_74_op: /* c.cond.fmt */ | |
431 | mips32_insn.fp0_format.opcode = cop1_op; | |
432 | mips32_insn.fp0_format.fmt = | |
433 | sdps_format[insn.mm_fp4_format.fmt]; | |
434 | mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt; | |
435 | mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs; | |
436 | mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2; | |
437 | mips32_insn.fp0_format.func = | |
438 | insn.mm_fp4_format.cond | MM_MIPS32_COND_FC; | |
439 | break; | |
440 | default: | |
441 | return SIGILL; | |
102cedc3 LY |
442 | } |
443 | break; | |
444 | default: | |
445 | return SIGILL; | |
102cedc3 LY |
446 | } |
447 | ||
448 | *insn_ptr = mips32_insn; | |
449 | return 0; | |
450 | } | |
451 | ||
452 | int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, | |
453 | unsigned long *contpc) | |
454 | { | |
455 | union mips_instruction insn = (union mips_instruction)dec_insn.insn; | |
456 | int bc_false = 0; | |
457 | unsigned int fcr31; | |
458 | unsigned int bit; | |
459 | ||
fe6d2909 DD |
460 | if (!cpu_has_mmips) |
461 | return 0; | |
462 | ||
102cedc3 LY |
463 | switch (insn.mm_i_format.opcode) { |
464 | case mm_pool32a_op: | |
465 | if ((insn.mm_i_format.simmediate & MM_POOL32A_MINOR_MASK) == | |
466 | mm_pool32axf_op) { | |
467 | switch (insn.mm_i_format.simmediate >> | |
468 | MM_POOL32A_MINOR_SHIFT) { | |
469 | case mm_jalr_op: | |
470 | case mm_jalrhb_op: | |
471 | case mm_jalrs_op: | |
472 | case mm_jalrshb_op: | |
473 | if (insn.mm_i_format.rt != 0) /* Not mm_jr */ | |
474 | regs->regs[insn.mm_i_format.rt] = | |
475 | regs->cp0_epc + | |
476 | dec_insn.pc_inc + | |
477 | dec_insn.next_pc_inc; | |
478 | *contpc = regs->regs[insn.mm_i_format.rs]; | |
479 | return 1; | |
102cedc3 LY |
480 | } |
481 | } | |
482 | break; | |
483 | case mm_pool32i_op: | |
484 | switch (insn.mm_i_format.rt) { | |
485 | case mm_bltzals_op: | |
486 | case mm_bltzal_op: | |
487 | regs->regs[31] = regs->cp0_epc + | |
488 | dec_insn.pc_inc + | |
489 | dec_insn.next_pc_inc; | |
490 | /* Fall through */ | |
491 | case mm_bltz_op: | |
492 | if ((long)regs->regs[insn.mm_i_format.rs] < 0) | |
493 | *contpc = regs->cp0_epc + | |
494 | dec_insn.pc_inc + | |
495 | (insn.mm_i_format.simmediate << 1); | |
496 | else | |
497 | *contpc = regs->cp0_epc + | |
498 | dec_insn.pc_inc + | |
499 | dec_insn.next_pc_inc; | |
500 | return 1; | |
102cedc3 LY |
501 | case mm_bgezals_op: |
502 | case mm_bgezal_op: | |
503 | regs->regs[31] = regs->cp0_epc + | |
504 | dec_insn.pc_inc + | |
505 | dec_insn.next_pc_inc; | |
506 | /* Fall through */ | |
507 | case mm_bgez_op: | |
508 | if ((long)regs->regs[insn.mm_i_format.rs] >= 0) | |
509 | *contpc = regs->cp0_epc + | |
510 | dec_insn.pc_inc + | |
511 | (insn.mm_i_format.simmediate << 1); | |
512 | else | |
513 | *contpc = regs->cp0_epc + | |
514 | dec_insn.pc_inc + | |
515 | dec_insn.next_pc_inc; | |
516 | return 1; | |
102cedc3 LY |
517 | case mm_blez_op: |
518 | if ((long)regs->regs[insn.mm_i_format.rs] <= 0) | |
519 | *contpc = regs->cp0_epc + | |
520 | dec_insn.pc_inc + | |
521 | (insn.mm_i_format.simmediate << 1); | |
522 | else | |
523 | *contpc = regs->cp0_epc + | |
524 | dec_insn.pc_inc + | |
525 | dec_insn.next_pc_inc; | |
526 | return 1; | |
102cedc3 LY |
527 | case mm_bgtz_op: |
528 | if ((long)regs->regs[insn.mm_i_format.rs] <= 0) | |
529 | *contpc = regs->cp0_epc + | |
530 | dec_insn.pc_inc + | |
531 | (insn.mm_i_format.simmediate << 1); | |
532 | else | |
533 | *contpc = regs->cp0_epc + | |
534 | dec_insn.pc_inc + | |
535 | dec_insn.next_pc_inc; | |
536 | return 1; | |
102cedc3 LY |
537 | case mm_bc2f_op: |
538 | case mm_bc1f_op: | |
539 | bc_false = 1; | |
540 | /* Fall through */ | |
541 | case mm_bc2t_op: | |
542 | case mm_bc1t_op: | |
543 | preempt_disable(); | |
544 | if (is_fpu_owner()) | |
545 | asm volatile("cfc1\t%0,$31" : "=r" (fcr31)); | |
546 | else | |
547 | fcr31 = current->thread.fpu.fcr31; | |
548 | preempt_enable(); | |
549 | ||
550 | if (bc_false) | |
551 | fcr31 = ~fcr31; | |
552 | ||
553 | bit = (insn.mm_i_format.rs >> 2); | |
554 | bit += (bit != 0); | |
555 | bit += 23; | |
556 | if (fcr31 & (1 << bit)) | |
557 | *contpc = regs->cp0_epc + | |
558 | dec_insn.pc_inc + | |
559 | (insn.mm_i_format.simmediate << 1); | |
560 | else | |
561 | *contpc = regs->cp0_epc + | |
562 | dec_insn.pc_inc + dec_insn.next_pc_inc; | |
563 | return 1; | |
102cedc3 LY |
564 | } |
565 | break; | |
566 | case mm_pool16c_op: | |
567 | switch (insn.mm_i_format.rt) { | |
568 | case mm_jalr16_op: | |
569 | case mm_jalrs16_op: | |
570 | regs->regs[31] = regs->cp0_epc + | |
571 | dec_insn.pc_inc + dec_insn.next_pc_inc; | |
572 | /* Fall through */ | |
573 | case mm_jr16_op: | |
574 | *contpc = regs->regs[insn.mm_i_format.rs]; | |
575 | return 1; | |
102cedc3 LY |
576 | } |
577 | break; | |
578 | case mm_beqz16_op: | |
579 | if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] == 0) | |
580 | *contpc = regs->cp0_epc + | |
581 | dec_insn.pc_inc + | |
582 | (insn.mm_b1_format.simmediate << 1); | |
583 | else | |
584 | *contpc = regs->cp0_epc + | |
585 | dec_insn.pc_inc + dec_insn.next_pc_inc; | |
586 | return 1; | |
102cedc3 LY |
587 | case mm_bnez16_op: |
588 | if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] != 0) | |
589 | *contpc = regs->cp0_epc + | |
590 | dec_insn.pc_inc + | |
591 | (insn.mm_b1_format.simmediate << 1); | |
592 | else | |
593 | *contpc = regs->cp0_epc + | |
594 | dec_insn.pc_inc + dec_insn.next_pc_inc; | |
595 | return 1; | |
102cedc3 LY |
596 | case mm_b16_op: |
597 | *contpc = regs->cp0_epc + dec_insn.pc_inc + | |
598 | (insn.mm_b0_format.simmediate << 1); | |
599 | return 1; | |
102cedc3 LY |
600 | case mm_beq32_op: |
601 | if (regs->regs[insn.mm_i_format.rs] == | |
602 | regs->regs[insn.mm_i_format.rt]) | |
603 | *contpc = regs->cp0_epc + | |
604 | dec_insn.pc_inc + | |
605 | (insn.mm_i_format.simmediate << 1); | |
606 | else | |
607 | *contpc = regs->cp0_epc + | |
608 | dec_insn.pc_inc + | |
609 | dec_insn.next_pc_inc; | |
610 | return 1; | |
102cedc3 LY |
611 | case mm_bne32_op: |
612 | if (regs->regs[insn.mm_i_format.rs] != | |
613 | regs->regs[insn.mm_i_format.rt]) | |
614 | *contpc = regs->cp0_epc + | |
615 | dec_insn.pc_inc + | |
616 | (insn.mm_i_format.simmediate << 1); | |
617 | else | |
618 | *contpc = regs->cp0_epc + | |
619 | dec_insn.pc_inc + dec_insn.next_pc_inc; | |
620 | return 1; | |
102cedc3 LY |
621 | case mm_jalx32_op: |
622 | regs->regs[31] = regs->cp0_epc + | |
623 | dec_insn.pc_inc + dec_insn.next_pc_inc; | |
624 | *contpc = regs->cp0_epc + dec_insn.pc_inc; | |
625 | *contpc >>= 28; | |
626 | *contpc <<= 28; | |
627 | *contpc |= (insn.j_format.target << 2); | |
628 | return 1; | |
102cedc3 LY |
629 | case mm_jals32_op: |
630 | case mm_jal32_op: | |
631 | regs->regs[31] = regs->cp0_epc + | |
632 | dec_insn.pc_inc + dec_insn.next_pc_inc; | |
633 | /* Fall through */ | |
634 | case mm_j32_op: | |
635 | *contpc = regs->cp0_epc + dec_insn.pc_inc; | |
636 | *contpc >>= 27; | |
637 | *contpc <<= 27; | |
638 | *contpc |= (insn.j_format.target << 1); | |
639 | set_isa16_mode(*contpc); | |
640 | return 1; | |
102cedc3 LY |
641 | } |
642 | return 0; | |
643 | } | |
1da177e4 LT |
644 | |
645 | /* | |
646 | * Redundant with logic already in kernel/branch.c, | |
647 | * embedded in compute_return_epc. At some point, | |
648 | * a single subroutine should be used across both | |
649 | * modules. | |
650 | */ | |
102cedc3 LY |
651 | static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn, |
652 | unsigned long *contpc) | |
1da177e4 | 653 | { |
102cedc3 LY |
654 | union mips_instruction insn = (union mips_instruction)dec_insn.insn; |
655 | unsigned int fcr31; | |
656 | unsigned int bit = 0; | |
657 | ||
658 | switch (insn.i_format.opcode) { | |
1da177e4 | 659 | case spec_op: |
102cedc3 | 660 | switch (insn.r_format.func) { |
1da177e4 | 661 | case jalr_op: |
102cedc3 LY |
662 | regs->regs[insn.r_format.rd] = |
663 | regs->cp0_epc + dec_insn.pc_inc + | |
664 | dec_insn.next_pc_inc; | |
665 | /* Fall through */ | |
1da177e4 | 666 | case jr_op: |
102cedc3 | 667 | *contpc = regs->regs[insn.r_format.rs]; |
1da177e4 LT |
668 | return 1; |
669 | } | |
670 | break; | |
1da177e4 | 671 | case bcond_op: |
102cedc3 LY |
672 | switch (insn.i_format.rt) { |
673 | case bltzal_op: | |
674 | case bltzall_op: | |
675 | regs->regs[31] = regs->cp0_epc + | |
676 | dec_insn.pc_inc + | |
677 | dec_insn.next_pc_inc; | |
678 | /* Fall through */ | |
1da177e4 | 679 | case bltz_op: |
1da177e4 | 680 | case bltzl_op: |
102cedc3 LY |
681 | if ((long)regs->regs[insn.i_format.rs] < 0) |
682 | *contpc = regs->cp0_epc + | |
683 | dec_insn.pc_inc + | |
684 | (insn.i_format.simmediate << 2); | |
685 | else | |
686 | *contpc = regs->cp0_epc + | |
687 | dec_insn.pc_inc + | |
688 | dec_insn.next_pc_inc; | |
689 | return 1; | |
1da177e4 | 690 | case bgezal_op: |
1da177e4 | 691 | case bgezall_op: |
102cedc3 LY |
692 | regs->regs[31] = regs->cp0_epc + |
693 | dec_insn.pc_inc + | |
694 | dec_insn.next_pc_inc; | |
695 | /* Fall through */ | |
696 | case bgez_op: | |
697 | case bgezl_op: | |
698 | if ((long)regs->regs[insn.i_format.rs] >= 0) | |
699 | *contpc = regs->cp0_epc + | |
700 | dec_insn.pc_inc + | |
701 | (insn.i_format.simmediate << 2); | |
702 | else | |
703 | *contpc = regs->cp0_epc + | |
704 | dec_insn.pc_inc + | |
705 | dec_insn.next_pc_inc; | |
1da177e4 LT |
706 | return 1; |
707 | } | |
708 | break; | |
1da177e4 | 709 | case jalx_op: |
102cedc3 LY |
710 | set_isa16_mode(bit); |
711 | case jal_op: | |
712 | regs->regs[31] = regs->cp0_epc + | |
713 | dec_insn.pc_inc + | |
714 | dec_insn.next_pc_inc; | |
715 | /* Fall through */ | |
716 | case j_op: | |
717 | *contpc = regs->cp0_epc + dec_insn.pc_inc; | |
718 | *contpc >>= 28; | |
719 | *contpc <<= 28; | |
720 | *contpc |= (insn.j_format.target << 2); | |
721 | /* Set microMIPS mode bit: XOR for jalx. */ | |
722 | *contpc ^= bit; | |
723 | return 1; | |
1da177e4 | 724 | case beq_op: |
1da177e4 | 725 | case beql_op: |
102cedc3 LY |
726 | if (regs->regs[insn.i_format.rs] == |
727 | regs->regs[insn.i_format.rt]) | |
728 | *contpc = regs->cp0_epc + | |
729 | dec_insn.pc_inc + | |
730 | (insn.i_format.simmediate << 2); | |
731 | else | |
732 | *contpc = regs->cp0_epc + | |
733 | dec_insn.pc_inc + | |
734 | dec_insn.next_pc_inc; | |
735 | return 1; | |
102cedc3 | 736 | case bne_op: |
1da177e4 | 737 | case bnel_op: |
102cedc3 LY |
738 | if (regs->regs[insn.i_format.rs] != |
739 | regs->regs[insn.i_format.rt]) | |
740 | *contpc = regs->cp0_epc + | |
741 | dec_insn.pc_inc + | |
742 | (insn.i_format.simmediate << 2); | |
743 | else | |
744 | *contpc = regs->cp0_epc + | |
745 | dec_insn.pc_inc + | |
746 | dec_insn.next_pc_inc; | |
747 | return 1; | |
102cedc3 | 748 | case blez_op: |
1da177e4 | 749 | case blezl_op: |
102cedc3 LY |
750 | if ((long)regs->regs[insn.i_format.rs] <= 0) |
751 | *contpc = regs->cp0_epc + | |
752 | dec_insn.pc_inc + | |
753 | (insn.i_format.simmediate << 2); | |
754 | else | |
755 | *contpc = regs->cp0_epc + | |
756 | dec_insn.pc_inc + | |
757 | dec_insn.next_pc_inc; | |
758 | return 1; | |
102cedc3 | 759 | case bgtz_op: |
1da177e4 | 760 | case bgtzl_op: |
102cedc3 LY |
761 | if ((long)regs->regs[insn.i_format.rs] > 0) |
762 | *contpc = regs->cp0_epc + | |
763 | dec_insn.pc_inc + | |
764 | (insn.i_format.simmediate << 2); | |
765 | else | |
766 | *contpc = regs->cp0_epc + | |
767 | dec_insn.pc_inc + | |
768 | dec_insn.next_pc_inc; | |
1da177e4 | 769 | return 1; |
c26d4219 DD |
770 | #ifdef CONFIG_CPU_CAVIUM_OCTEON |
771 | case lwc2_op: /* This is bbit0 on Octeon */ | |
772 | if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0) | |
773 | *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); | |
774 | else | |
775 | *contpc = regs->cp0_epc + 8; | |
776 | return 1; | |
777 | case ldc2_op: /* This is bbit032 on Octeon */ | |
778 | if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0) | |
779 | *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); | |
780 | else | |
781 | *contpc = regs->cp0_epc + 8; | |
782 | return 1; | |
783 | case swc2_op: /* This is bbit1 on Octeon */ | |
784 | if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) | |
785 | *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); | |
786 | else | |
787 | *contpc = regs->cp0_epc + 8; | |
788 | return 1; | |
789 | case sdc2_op: /* This is bbit132 on Octeon */ | |
790 | if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) | |
791 | *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); | |
792 | else | |
793 | *contpc = regs->cp0_epc + 8; | |
794 | return 1; | |
795 | #endif | |
1da177e4 LT |
796 | case cop0_op: |
797 | case cop1_op: | |
798 | case cop2_op: | |
799 | case cop1x_op: | |
102cedc3 LY |
800 | if (insn.i_format.rs == bc_op) { |
801 | preempt_disable(); | |
802 | if (is_fpu_owner()) | |
803 | asm volatile("cfc1\t%0,$31" : "=r" (fcr31)); | |
804 | else | |
805 | fcr31 = current->thread.fpu.fcr31; | |
806 | preempt_enable(); | |
807 | ||
808 | bit = (insn.i_format.rt >> 2); | |
809 | bit += (bit != 0); | |
810 | bit += 23; | |
811 | switch (insn.i_format.rt & 3) { | |
812 | case 0: /* bc1f */ | |
813 | case 2: /* bc1fl */ | |
814 | if (~fcr31 & (1 << bit)) | |
815 | *contpc = regs->cp0_epc + | |
816 | dec_insn.pc_inc + | |
817 | (insn.i_format.simmediate << 2); | |
818 | else | |
819 | *contpc = regs->cp0_epc + | |
820 | dec_insn.pc_inc + | |
821 | dec_insn.next_pc_inc; | |
822 | return 1; | |
102cedc3 LY |
823 | case 1: /* bc1t */ |
824 | case 3: /* bc1tl */ | |
825 | if (fcr31 & (1 << bit)) | |
826 | *contpc = regs->cp0_epc + | |
827 | dec_insn.pc_inc + | |
828 | (insn.i_format.simmediate << 2); | |
829 | else | |
830 | *contpc = regs->cp0_epc + | |
831 | dec_insn.pc_inc + | |
832 | dec_insn.next_pc_inc; | |
833 | return 1; | |
102cedc3 LY |
834 | } |
835 | } | |
1da177e4 LT |
836 | break; |
837 | } | |
1da177e4 LT |
838 | return 0; |
839 | } | |
840 | ||
841 | /* | |
842 | * In the Linux kernel, we support selection of FPR format on the | |
70342287 | 843 | * basis of the Status.FR bit. If an FPU is not present, the FR bit |
da0bac33 | 844 | * is hardwired to zero, which would imply a 32-bit FPU even for |
597ce172 | 845 | * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS. |
51d943f0 RB |
846 | * FPU emu is slow and bulky and optimizing this function offers fairly |
847 | * sizeable benefits so we try to be clever and make this function return | |
848 | * a constant whenever possible, that is on 64-bit kernels without O32 | |
597ce172 | 849 | * compatibility enabled and on 32-bit without 64-bit FPU support. |
1da177e4 | 850 | */ |
da0bac33 DD |
851 | static inline int cop1_64bit(struct pt_regs *xcp) |
852 | { | |
08a07904 RB |
853 | if (config_enabled(CONFIG_64BIT) && !config_enabled(CONFIG_MIPS32_O32)) |
854 | return 1; | |
855 | else if (config_enabled(CONFIG_32BIT) && | |
856 | !config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT)) | |
857 | return 0; | |
858 | ||
597ce172 | 859 | return !test_thread_flag(TIF_32BIT_FPREGS); |
da0bac33 DD |
860 | } |
861 | ||
47fa0c02 RB |
862 | #define SIFROMREG(si, x) \ |
863 | do { \ | |
bbd426f5 PB |
864 | if (cop1_64bit(xcp)) \ |
865 | (si) = get_fpr32(&ctx->fpr[x], 0); \ | |
866 | else \ | |
867 | (si) = get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \ | |
868 | } while (0) | |
1da177e4 | 869 | |
47fa0c02 RB |
870 | #define SITOREG(si, x) \ |
871 | do { \ | |
ef1c47af PB |
872 | if (cop1_64bit(xcp)) { \ |
873 | unsigned i; \ | |
bbd426f5 | 874 | set_fpr32(&ctx->fpr[x], 0, si); \ |
ef1c47af PB |
875 | for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \ |
876 | set_fpr32(&ctx->fpr[x], i, 0); \ | |
877 | } else { \ | |
bbd426f5 | 878 | set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \ |
ef1c47af | 879 | } \ |
bbd426f5 | 880 | } while (0) |
1da177e4 | 881 | |
bbd426f5 | 882 | #define SIFROMHREG(si, x) ((si) = get_fpr32(&ctx->fpr[x], 1)) |
ef1c47af | 883 | |
47fa0c02 RB |
884 | #define SITOHREG(si, x) \ |
885 | do { \ | |
ef1c47af PB |
886 | unsigned i; \ |
887 | set_fpr32(&ctx->fpr[x], 1, si); \ | |
888 | for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \ | |
889 | set_fpr32(&ctx->fpr[x], i, 0); \ | |
890 | } while (0) | |
1ac94400 | 891 | |
47fa0c02 | 892 | #define DIFROMREG(di, x) \ |
bbd426f5 PB |
893 | ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0)) |
894 | ||
47fa0c02 RB |
895 | #define DITOREG(di, x) \ |
896 | do { \ | |
ef1c47af PB |
897 | unsigned fpr, i; \ |
898 | fpr = (x) & ~(cop1_64bit(xcp) == 0); \ | |
899 | set_fpr64(&ctx->fpr[fpr], 0, di); \ | |
900 | for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \ | |
901 | set_fpr64(&ctx->fpr[fpr], i, 0); \ | |
902 | } while (0) | |
1da177e4 | 903 | |
21a151d8 RB |
904 | #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x) |
905 | #define SPTOREG(sp, x) SITOREG((sp).bits, x) | |
906 | #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x) | |
907 | #define DPTOREG(dp, x) DITOREG((dp).bits, x) | |
1da177e4 LT |
908 | |
909 | /* | |
910 | * Emulate the single floating point instruction pointed at by EPC. | |
911 | * Two instructions if the instruction is in a branch delay slot. | |
912 | */ | |
913 | ||
515b029d | 914 | static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx, |
102cedc3 | 915 | struct mm_decoded_insn dec_insn, void *__user *fault_addr) |
1da177e4 LT |
916 | { |
917 | mips_instruction ir; | |
102cedc3 | 918 | unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc; |
1da177e4 | 919 | unsigned int cond; |
102cedc3 | 920 | int pc_inc; |
1da177e4 LT |
921 | |
922 | /* XXX NEC Vr54xx bug workaround */ | |
e7e9cae5 | 923 | if (delay_slot(xcp)) { |
102cedc3 LY |
924 | if (dec_insn.micro_mips_mode) { |
925 | if (!mm_isBranchInstr(xcp, dec_insn, &contpc)) | |
e7e9cae5 | 926 | clear_delay_slot(xcp); |
102cedc3 LY |
927 | } else { |
928 | if (!isBranchInstr(xcp, dec_insn, &contpc)) | |
e7e9cae5 | 929 | clear_delay_slot(xcp); |
102cedc3 LY |
930 | } |
931 | } | |
1da177e4 | 932 | |
e7e9cae5 | 933 | if (delay_slot(xcp)) { |
1da177e4 LT |
934 | /* |
935 | * The instruction to be emulated is in a branch delay slot | |
70342287 | 936 | * which means that we have to emulate the branch instruction |
1da177e4 LT |
937 | * BEFORE we do the cop1 instruction. |
938 | * | |
939 | * This branch could be a COP1 branch, but in that case we | |
940 | * would have had a trap for that instruction, and would not | |
941 | * come through this route. | |
942 | * | |
943 | * Linux MIPS branch emulator operates on context, updating the | |
944 | * cp0_epc. | |
945 | */ | |
102cedc3 LY |
946 | ir = dec_insn.next_insn; /* process delay slot instr */ |
947 | pc_inc = dec_insn.next_pc_inc; | |
948 | } else { | |
949 | ir = dec_insn.insn; /* process current instr */ | |
950 | pc_inc = dec_insn.pc_inc; | |
951 | } | |
1da177e4 | 952 | |
102cedc3 LY |
953 | /* |
954 | * Since microMIPS FPU instructios are a subset of MIPS32 FPU | |
955 | * instructions, we want to convert microMIPS FPU instructions | |
956 | * into MIPS32 instructions so that we could reuse all of the | |
957 | * FPU emulation code. | |
958 | * | |
959 | * NOTE: We cannot do this for branch instructions since they | |
960 | * are not a subset. Example: Cannot emulate a 16-bit | |
961 | * aligned target address with a MIPS32 instruction. | |
962 | */ | |
963 | if (dec_insn.micro_mips_mode) { | |
964 | /* | |
965 | * If next instruction is a 16-bit instruction, then it | |
966 | * it cannot be a FPU instruction. This could happen | |
967 | * since we can be called for non-FPU instructions. | |
968 | */ | |
969 | if ((pc_inc == 2) || | |
970 | (microMIPS32_to_MIPS32((union mips_instruction *)&ir) | |
971 | == SIGILL)) | |
1da177e4 | 972 | return SIGILL; |
1da177e4 LT |
973 | } |
974 | ||
975 | emul: | |
a8b0ca17 | 976 | perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0); |
b6ee75ed | 977 | MIPS_FPU_EMU_INC_STATS(emulated); |
1da177e4 | 978 | switch (MIPSInst_OPCODE(ir)) { |
1da177e4 | 979 | case ldc1_op:{ |
3fccc015 | 980 | u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + |
1da177e4 LT |
981 | MIPSInst_SIMM(ir)); |
982 | u64 val; | |
983 | ||
b6ee75ed | 984 | MIPS_FPU_EMU_INC_STATS(loads); |
515b029d DD |
985 | |
986 | if (!access_ok(VERIFY_READ, va, sizeof(u64))) { | |
b6ee75ed | 987 | MIPS_FPU_EMU_INC_STATS(errors); |
515b029d | 988 | *fault_addr = va; |
1da177e4 LT |
989 | return SIGBUS; |
990 | } | |
515b029d DD |
991 | if (__get_user(val, va)) { |
992 | MIPS_FPU_EMU_INC_STATS(errors); | |
993 | *fault_addr = va; | |
994 | return SIGSEGV; | |
995 | } | |
1da177e4 LT |
996 | DITOREG(val, MIPSInst_RT(ir)); |
997 | break; | |
998 | } | |
999 | ||
1000 | case sdc1_op:{ | |
3fccc015 | 1001 | u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + |
1da177e4 LT |
1002 | MIPSInst_SIMM(ir)); |
1003 | u64 val; | |
1004 | ||
b6ee75ed | 1005 | MIPS_FPU_EMU_INC_STATS(stores); |
1da177e4 | 1006 | DIFROMREG(val, MIPSInst_RT(ir)); |
515b029d | 1007 | if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) { |
b6ee75ed | 1008 | MIPS_FPU_EMU_INC_STATS(errors); |
515b029d | 1009 | *fault_addr = va; |
1da177e4 LT |
1010 | return SIGBUS; |
1011 | } | |
515b029d DD |
1012 | if (__put_user(val, va)) { |
1013 | MIPS_FPU_EMU_INC_STATS(errors); | |
1014 | *fault_addr = va; | |
1015 | return SIGSEGV; | |
1016 | } | |
1da177e4 LT |
1017 | break; |
1018 | } | |
1da177e4 LT |
1019 | |
1020 | case lwc1_op:{ | |
3fccc015 | 1021 | u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + |
1da177e4 LT |
1022 | MIPSInst_SIMM(ir)); |
1023 | u32 val; | |
1024 | ||
b6ee75ed | 1025 | MIPS_FPU_EMU_INC_STATS(loads); |
515b029d | 1026 | if (!access_ok(VERIFY_READ, va, sizeof(u32))) { |
b6ee75ed | 1027 | MIPS_FPU_EMU_INC_STATS(errors); |
515b029d | 1028 | *fault_addr = va; |
1da177e4 LT |
1029 | return SIGBUS; |
1030 | } | |
515b029d DD |
1031 | if (__get_user(val, va)) { |
1032 | MIPS_FPU_EMU_INC_STATS(errors); | |
1033 | *fault_addr = va; | |
1034 | return SIGSEGV; | |
1035 | } | |
1da177e4 LT |
1036 | SITOREG(val, MIPSInst_RT(ir)); |
1037 | break; | |
1038 | } | |
1039 | ||
1040 | case swc1_op:{ | |
3fccc015 | 1041 | u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + |
1da177e4 LT |
1042 | MIPSInst_SIMM(ir)); |
1043 | u32 val; | |
1044 | ||
b6ee75ed | 1045 | MIPS_FPU_EMU_INC_STATS(stores); |
1da177e4 | 1046 | SIFROMREG(val, MIPSInst_RT(ir)); |
515b029d | 1047 | if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) { |
b6ee75ed | 1048 | MIPS_FPU_EMU_INC_STATS(errors); |
515b029d | 1049 | *fault_addr = va; |
1da177e4 LT |
1050 | return SIGBUS; |
1051 | } | |
515b029d DD |
1052 | if (__put_user(val, va)) { |
1053 | MIPS_FPU_EMU_INC_STATS(errors); | |
1054 | *fault_addr = va; | |
1055 | return SIGSEGV; | |
1056 | } | |
1da177e4 LT |
1057 | break; |
1058 | } | |
1059 | ||
1060 | case cop1_op: | |
1061 | switch (MIPSInst_RS(ir)) { | |
1062 | ||
1da177e4 | 1063 | case dmfc_op: |
08a07904 RB |
1064 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) |
1065 | return SIGILL; | |
1066 | ||
1da177e4 LT |
1067 | /* copregister fs -> gpr[rt] */ |
1068 | if (MIPSInst_RT(ir) != 0) { | |
1069 | DIFROMREG(xcp->regs[MIPSInst_RT(ir)], | |
1070 | MIPSInst_RD(ir)); | |
1071 | } | |
1072 | break; | |
1073 | ||
1074 | case dmtc_op: | |
08a07904 RB |
1075 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) |
1076 | return SIGILL; | |
1077 | ||
1da177e4 LT |
1078 | /* copregister fs <- rt */ |
1079 | DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); | |
1080 | break; | |
1da177e4 | 1081 | |
1ac94400 LY |
1082 | case mfhc_op: |
1083 | if (!cpu_has_mips_r2) | |
1084 | goto sigill; | |
1085 | ||
1086 | /* copregister rd -> gpr[rt] */ | |
1087 | if (MIPSInst_RT(ir) != 0) { | |
1088 | SIFROMHREG(xcp->regs[MIPSInst_RT(ir)], | |
1089 | MIPSInst_RD(ir)); | |
1090 | } | |
1091 | break; | |
1092 | ||
1093 | case mthc_op: | |
1094 | if (!cpu_has_mips_r2) | |
1095 | goto sigill; | |
1096 | ||
1097 | /* copregister rd <- gpr[rt] */ | |
1098 | SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); | |
1099 | break; | |
1100 | ||
1da177e4 LT |
1101 | case mfc_op: |
1102 | /* copregister rd -> gpr[rt] */ | |
1da177e4 LT |
1103 | if (MIPSInst_RT(ir) != 0) { |
1104 | SIFROMREG(xcp->regs[MIPSInst_RT(ir)], | |
1105 | MIPSInst_RD(ir)); | |
1106 | } | |
1107 | break; | |
1108 | ||
1109 | case mtc_op: | |
1110 | /* copregister rd <- rt */ | |
1da177e4 LT |
1111 | SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); |
1112 | break; | |
1113 | ||
1114 | case cfc_op:{ | |
1115 | /* cop control register rd -> gpr[rt] */ | |
1116 | u32 value; | |
1117 | ||
1da177e4 LT |
1118 | if (MIPSInst_RD(ir) == FPCREG_CSR) { |
1119 | value = ctx->fcr31; | |
3f135530 SM |
1120 | value = (value & ~FPU_CSR_RM) | |
1121 | mips_rm[modeindex(value)]; | |
92df0f8b RB |
1122 | pr_debug("%p gpr[%d]<-csr=%08x\n", |
1123 | (void *) (xcp->cp0_epc), | |
1124 | MIPSInst_RT(ir), value); | |
1da177e4 LT |
1125 | } |
1126 | else if (MIPSInst_RD(ir) == FPCREG_RID) | |
1127 | value = 0; | |
1128 | else | |
1129 | value = 0; | |
1130 | if (MIPSInst_RT(ir)) | |
1131 | xcp->regs[MIPSInst_RT(ir)] = value; | |
1132 | break; | |
1133 | } | |
1134 | ||
1135 | case ctc_op:{ | |
1136 | /* copregister rd <- rt */ | |
1137 | u32 value; | |
1138 | ||
1139 | if (MIPSInst_RT(ir) == 0) | |
1140 | value = 0; | |
1141 | else | |
1142 | value = xcp->regs[MIPSInst_RT(ir)]; | |
1143 | ||
1144 | /* we only have one writable control reg | |
1145 | */ | |
1146 | if (MIPSInst_RD(ir) == FPCREG_CSR) { | |
92df0f8b RB |
1147 | pr_debug("%p gpr[%d]->csr=%08x\n", |
1148 | (void *) (xcp->cp0_epc), | |
1149 | MIPSInst_RT(ir), value); | |
95e8f634 SM |
1150 | |
1151 | /* | |
1152 | * Don't write reserved bits, | |
1153 | * and convert to ieee library modes | |
1154 | */ | |
1155 | ctx->fcr31 = (value & | |
1156 | ~(FPU_CSR_RSVD | FPU_CSR_RM)) | | |
1157 | ieee_rm[modeindex(value)]; | |
1da177e4 LT |
1158 | } |
1159 | if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { | |
1160 | return SIGFPE; | |
1161 | } | |
1162 | break; | |
1163 | } | |
1164 | ||
1165 | case bc_op:{ | |
08a07904 | 1166 | unsigned int cbit; |
1da177e4 LT |
1167 | int likely = 0; |
1168 | ||
e7e9cae5 | 1169 | if (delay_slot(xcp)) |
1da177e4 LT |
1170 | return SIGILL; |
1171 | ||
08a07904 RB |
1172 | if (cpu_has_mips_4_5_r) |
1173 | cbit = fpucondbit[MIPSInst_RT(ir) >> 2]; | |
1174 | else | |
1175 | cbit = FPU_CSR_COND; | |
1176 | cond = ctx->fcr31 & cbit; | |
1177 | ||
1da177e4 LT |
1178 | switch (MIPSInst_RT(ir) & 3) { |
1179 | case bcfl_op: | |
1180 | likely = 1; | |
1181 | case bcf_op: | |
1182 | cond = !cond; | |
1183 | break; | |
1184 | case bctl_op: | |
1185 | likely = 1; | |
1186 | case bct_op: | |
1187 | break; | |
1188 | default: | |
1189 | /* thats an illegal instruction */ | |
1190 | return SIGILL; | |
1191 | } | |
1192 | ||
e7e9cae5 | 1193 | set_delay_slot(xcp); |
1da177e4 LT |
1194 | if (cond) { |
1195 | /* branch taken: emulate dslot | |
1196 | * instruction | |
1197 | */ | |
102cedc3 LY |
1198 | xcp->cp0_epc += dec_insn.pc_inc; |
1199 | ||
1200 | contpc = MIPSInst_SIMM(ir); | |
1201 | ir = dec_insn.next_insn; | |
1202 | if (dec_insn.micro_mips_mode) { | |
1203 | contpc = (xcp->cp0_epc + (contpc << 1)); | |
1204 | ||
1205 | /* If 16-bit instruction, not FPU. */ | |
1206 | if ((dec_insn.next_pc_inc == 2) || | |
1207 | (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) { | |
1208 | ||
1209 | /* | |
1210 | * Since this instruction will | |
1211 | * be put on the stack with | |
1212 | * 32-bit words, get around | |
1213 | * this problem by putting a | |
1214 | * NOP16 as the second one. | |
1215 | */ | |
1216 | if (dec_insn.next_pc_inc == 2) | |
1217 | ir = (ir & (~0xffff)) | MM_NOP16; | |
1218 | ||
1219 | /* | |
1220 | * Single step the non-CP1 | |
1221 | * instruction in the dslot. | |
1222 | */ | |
1223 | return mips_dsemul(xcp, ir, contpc); | |
1224 | } | |
1225 | } else | |
1226 | contpc = (xcp->cp0_epc + (contpc << 2)); | |
1da177e4 LT |
1227 | |
1228 | switch (MIPSInst_OPCODE(ir)) { | |
1229 | case lwc1_op: | |
08a07904 | 1230 | goto emul; |
1da177e4 | 1231 | case swc1_op: |
08a07904 | 1232 | goto emul; |
1da177e4 LT |
1233 | case ldc1_op: |
1234 | case sdc1_op: | |
08a07904 RB |
1235 | if (cpu_has_mips_2_3_4_5 || |
1236 | cpu_has_mips64) | |
1237 | goto emul; | |
1238 | ||
1239 | return SIGILL; | |
1240 | goto emul; | |
1da177e4 | 1241 | case cop1_op: |
1da177e4 | 1242 | goto emul; |
08a07904 RB |
1243 | case cop1x_op: |
1244 | if (cpu_has_mips_4_5 || cpu_has_mips64) | |
1245 | /* its one of ours */ | |
1246 | goto emul; | |
1247 | ||
1248 | return SIGILL; | |
1da177e4 | 1249 | case spec_op: |
08a07904 RB |
1250 | if (!cpu_has_mips_4_5_r) |
1251 | return SIGILL; | |
1252 | ||
1da177e4 LT |
1253 | if (MIPSInst_FUNC(ir) == movc_op) |
1254 | goto emul; | |
1255 | break; | |
1da177e4 LT |
1256 | } |
1257 | ||
1258 | /* | |
1259 | * Single step the non-cp1 | |
1260 | * instruction in the dslot | |
1261 | */ | |
e70dfc10 | 1262 | return mips_dsemul(xcp, ir, contpc); |
1da177e4 LT |
1263 | } |
1264 | else { | |
1265 | /* branch not taken */ | |
1266 | if (likely) { | |
1267 | /* | |
1268 | * branch likely nullifies | |
1269 | * dslot if not taken | |
1270 | */ | |
102cedc3 LY |
1271 | xcp->cp0_epc += dec_insn.pc_inc; |
1272 | contpc += dec_insn.pc_inc; | |
1da177e4 LT |
1273 | /* |
1274 | * else continue & execute | |
1275 | * dslot as normal insn | |
1276 | */ | |
1277 | } | |
1278 | } | |
1279 | break; | |
1280 | } | |
1281 | ||
1282 | default: | |
1283 | if (!(MIPSInst_RS(ir) & 0x10)) | |
1284 | return SIGILL; | |
1285 | { | |
1286 | int sig; | |
1287 | ||
1288 | /* a real fpu computation instruction */ | |
1289 | if ((sig = fpu_emu(xcp, ctx, ir))) | |
1290 | return sig; | |
1291 | } | |
1292 | } | |
1293 | break; | |
1294 | ||
1da177e4 | 1295 | case cop1x_op:{ |
08a07904 RB |
1296 | int sig; |
1297 | ||
1298 | if (!cpu_has_mips_4_5 && !cpu_has_mips64) | |
1299 | return SIGILL; | |
1300 | ||
1301 | sig = fpux_emu(xcp, ctx, ir, fault_addr); | |
515b029d | 1302 | if (sig) |
1da177e4 LT |
1303 | return sig; |
1304 | break; | |
1305 | } | |
1da177e4 | 1306 | |
1da177e4 | 1307 | case spec_op: |
08a07904 RB |
1308 | if (!cpu_has_mips_4_5_r) |
1309 | return SIGILL; | |
1310 | ||
1da177e4 LT |
1311 | if (MIPSInst_FUNC(ir) != movc_op) |
1312 | return SIGILL; | |
1313 | cond = fpucondbit[MIPSInst_RT(ir) >> 2]; | |
1314 | if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0)) | |
1315 | xcp->regs[MIPSInst_RD(ir)] = | |
1316 | xcp->regs[MIPSInst_RS(ir)]; | |
1317 | break; | |
1da177e4 | 1318 | default: |
1ac94400 | 1319 | sigill: |
1da177e4 LT |
1320 | return SIGILL; |
1321 | } | |
1322 | ||
1323 | /* we did it !! */ | |
e70dfc10 | 1324 | xcp->cp0_epc = contpc; |
e7e9cae5 | 1325 | clear_delay_slot(xcp); |
333d1f67 | 1326 | |
1da177e4 LT |
1327 | return 0; |
1328 | } | |
1329 | ||
1330 | /* | |
1331 | * Conversion table from MIPS compare ops 48-63 | |
1332 | * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig); | |
1333 | */ | |
1334 | static const unsigned char cmptab[8] = { | |
1335 | 0, /* cmp_0 (sig) cmp_sf */ | |
1336 | IEEE754_CUN, /* cmp_un (sig) cmp_ngle */ | |
1337 | IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */ | |
1338 | IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */ | |
1339 | IEEE754_CLT, /* cmp_olt (sig) cmp_lt */ | |
1340 | IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */ | |
1341 | IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */ | |
1342 | IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */ | |
1343 | }; | |
1344 | ||
1345 | ||
1da177e4 LT |
1346 | /* |
1347 | * Additional MIPS4 instructions | |
1348 | */ | |
1349 | ||
47fa0c02 RB |
1350 | #define DEF3OP(name, p, f1, f2, f3) \ |
1351 | static union ieee754##p fpemu_##p##_##name(union ieee754##p r, \ | |
1352 | union ieee754##p s, union ieee754##p t) \ | |
1353 | { \ | |
1354 | struct _ieee754_csr ieee754_csr_save; \ | |
1355 | s = f1(s, t); \ | |
1356 | ieee754_csr_save = ieee754_csr; \ | |
1357 | s = f2(s, r); \ | |
1358 | ieee754_csr_save.cx |= ieee754_csr.cx; \ | |
1359 | ieee754_csr_save.sx |= ieee754_csr.sx; \ | |
1360 | s = f3(s); \ | |
1361 | ieee754_csr.cx |= ieee754_csr_save.cx; \ | |
1362 | ieee754_csr.sx |= ieee754_csr_save.sx; \ | |
1363 | return s; \ | |
1da177e4 LT |
1364 | } |
1365 | ||
2209bcb1 | 1366 | static union ieee754dp fpemu_dp_recip(union ieee754dp d) |
1da177e4 LT |
1367 | { |
1368 | return ieee754dp_div(ieee754dp_one(0), d); | |
1369 | } | |
1370 | ||
2209bcb1 | 1371 | static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d) |
1da177e4 LT |
1372 | { |
1373 | return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d)); | |
1374 | } | |
1375 | ||
2209bcb1 | 1376 | static union ieee754sp fpemu_sp_recip(union ieee754sp s) |
1da177e4 LT |
1377 | { |
1378 | return ieee754sp_div(ieee754sp_one(0), s); | |
1379 | } | |
1380 | ||
2209bcb1 | 1381 | static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s) |
1da177e4 LT |
1382 | { |
1383 | return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s)); | |
1384 | } | |
1385 | ||
21a151d8 RB |
1386 | DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, ); |
1387 | DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, ); | |
1da177e4 LT |
1388 | DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg); |
1389 | DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg); | |
21a151d8 RB |
1390 | DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, ); |
1391 | DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, ); | |
1da177e4 LT |
1392 | DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg); |
1393 | DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg); | |
1394 | ||
eae89076 | 1395 | static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, |
515b029d | 1396 | mips_instruction ir, void *__user *fault_addr) |
1da177e4 LT |
1397 | { |
1398 | unsigned rcsr = 0; /* resulting csr */ | |
1399 | ||
b6ee75ed | 1400 | MIPS_FPU_EMU_INC_STATS(cp1xops); |
1da177e4 LT |
1401 | |
1402 | switch (MIPSInst_FMA_FFMT(ir)) { | |
1403 | case s_fmt:{ /* 0 */ | |
1404 | ||
2209bcb1 RB |
1405 | union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp); |
1406 | union ieee754sp fd, fr, fs, ft; | |
3fccc015 | 1407 | u32 __user *va; |
1da177e4 LT |
1408 | u32 val; |
1409 | ||
1410 | switch (MIPSInst_FUNC(ir)) { | |
1411 | case lwxc1_op: | |
3fccc015 | 1412 | va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + |
1da177e4 LT |
1413 | xcp->regs[MIPSInst_FT(ir)]); |
1414 | ||
b6ee75ed | 1415 | MIPS_FPU_EMU_INC_STATS(loads); |
515b029d | 1416 | if (!access_ok(VERIFY_READ, va, sizeof(u32))) { |
b6ee75ed | 1417 | MIPS_FPU_EMU_INC_STATS(errors); |
515b029d | 1418 | *fault_addr = va; |
1da177e4 LT |
1419 | return SIGBUS; |
1420 | } | |
515b029d DD |
1421 | if (__get_user(val, va)) { |
1422 | MIPS_FPU_EMU_INC_STATS(errors); | |
1423 | *fault_addr = va; | |
1424 | return SIGSEGV; | |
1425 | } | |
1da177e4 LT |
1426 | SITOREG(val, MIPSInst_FD(ir)); |
1427 | break; | |
1428 | ||
1429 | case swxc1_op: | |
3fccc015 | 1430 | va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + |
1da177e4 LT |
1431 | xcp->regs[MIPSInst_FT(ir)]); |
1432 | ||
b6ee75ed | 1433 | MIPS_FPU_EMU_INC_STATS(stores); |
1da177e4 LT |
1434 | |
1435 | SIFROMREG(val, MIPSInst_FS(ir)); | |
515b029d | 1436 | if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) { |
b6ee75ed | 1437 | MIPS_FPU_EMU_INC_STATS(errors); |
515b029d | 1438 | *fault_addr = va; |
1da177e4 LT |
1439 | return SIGBUS; |
1440 | } | |
515b029d DD |
1441 | if (put_user(val, va)) { |
1442 | MIPS_FPU_EMU_INC_STATS(errors); | |
1443 | *fault_addr = va; | |
1444 | return SIGSEGV; | |
1445 | } | |
1da177e4 LT |
1446 | break; |
1447 | ||
1448 | case madd_s_op: | |
1449 | handler = fpemu_sp_madd; | |
1450 | goto scoptop; | |
1451 | case msub_s_op: | |
1452 | handler = fpemu_sp_msub; | |
1453 | goto scoptop; | |
1454 | case nmadd_s_op: | |
1455 | handler = fpemu_sp_nmadd; | |
1456 | goto scoptop; | |
1457 | case nmsub_s_op: | |
1458 | handler = fpemu_sp_nmsub; | |
1459 | goto scoptop; | |
1460 | ||
1461 | scoptop: | |
1462 | SPFROMREG(fr, MIPSInst_FR(ir)); | |
1463 | SPFROMREG(fs, MIPSInst_FS(ir)); | |
1464 | SPFROMREG(ft, MIPSInst_FT(ir)); | |
1465 | fd = (*handler) (fr, fs, ft); | |
1466 | SPTOREG(fd, MIPSInst_FD(ir)); | |
1467 | ||
1468 | copcsr: | |
1469 | if (ieee754_cxtest(IEEE754_INEXACT)) | |
1470 | rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; | |
1471 | if (ieee754_cxtest(IEEE754_UNDERFLOW)) | |
1472 | rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; | |
1473 | if (ieee754_cxtest(IEEE754_OVERFLOW)) | |
1474 | rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; | |
1475 | if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) | |
1476 | rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; | |
1477 | ||
1478 | ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; | |
1da177e4 LT |
1479 | if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { |
1480 | /*printk ("SIGFPE: fpu csr = %08x\n", | |
1481 | ctx->fcr31); */ | |
1482 | return SIGFPE; | |
1483 | } | |
1484 | ||
1485 | break; | |
1486 | ||
1487 | default: | |
1488 | return SIGILL; | |
1489 | } | |
1490 | break; | |
1491 | } | |
1492 | ||
1da177e4 | 1493 | case d_fmt:{ /* 1 */ |
2209bcb1 RB |
1494 | union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp); |
1495 | union ieee754dp fd, fr, fs, ft; | |
3fccc015 | 1496 | u64 __user *va; |
1da177e4 LT |
1497 | u64 val; |
1498 | ||
1499 | switch (MIPSInst_FUNC(ir)) { | |
1500 | case ldxc1_op: | |
3fccc015 | 1501 | va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + |
1da177e4 LT |
1502 | xcp->regs[MIPSInst_FT(ir)]); |
1503 | ||
b6ee75ed | 1504 | MIPS_FPU_EMU_INC_STATS(loads); |
515b029d | 1505 | if (!access_ok(VERIFY_READ, va, sizeof(u64))) { |
b6ee75ed | 1506 | MIPS_FPU_EMU_INC_STATS(errors); |
515b029d | 1507 | *fault_addr = va; |
1da177e4 LT |
1508 | return SIGBUS; |
1509 | } | |
515b029d DD |
1510 | if (__get_user(val, va)) { |
1511 | MIPS_FPU_EMU_INC_STATS(errors); | |
1512 | *fault_addr = va; | |
1513 | return SIGSEGV; | |
1514 | } | |
1da177e4 LT |
1515 | DITOREG(val, MIPSInst_FD(ir)); |
1516 | break; | |
1517 | ||
1518 | case sdxc1_op: | |
3fccc015 | 1519 | va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + |
1da177e4 LT |
1520 | xcp->regs[MIPSInst_FT(ir)]); |
1521 | ||
b6ee75ed | 1522 | MIPS_FPU_EMU_INC_STATS(stores); |
1da177e4 | 1523 | DIFROMREG(val, MIPSInst_FS(ir)); |
515b029d | 1524 | if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) { |
b6ee75ed | 1525 | MIPS_FPU_EMU_INC_STATS(errors); |
515b029d | 1526 | *fault_addr = va; |
1da177e4 LT |
1527 | return SIGBUS; |
1528 | } | |
515b029d DD |
1529 | if (__put_user(val, va)) { |
1530 | MIPS_FPU_EMU_INC_STATS(errors); | |
1531 | *fault_addr = va; | |
1532 | return SIGSEGV; | |
1533 | } | |
1da177e4 LT |
1534 | break; |
1535 | ||
1536 | case madd_d_op: | |
1537 | handler = fpemu_dp_madd; | |
1538 | goto dcoptop; | |
1539 | case msub_d_op: | |
1540 | handler = fpemu_dp_msub; | |
1541 | goto dcoptop; | |
1542 | case nmadd_d_op: | |
1543 | handler = fpemu_dp_nmadd; | |
1544 | goto dcoptop; | |
1545 | case nmsub_d_op: | |
1546 | handler = fpemu_dp_nmsub; | |
1547 | goto dcoptop; | |
1548 | ||
1549 | dcoptop: | |
1550 | DPFROMREG(fr, MIPSInst_FR(ir)); | |
1551 | DPFROMREG(fs, MIPSInst_FS(ir)); | |
1552 | DPFROMREG(ft, MIPSInst_FT(ir)); | |
1553 | fd = (*handler) (fr, fs, ft); | |
1554 | DPTOREG(fd, MIPSInst_FD(ir)); | |
1555 | goto copcsr; | |
1556 | ||
1557 | default: | |
1558 | return SIGILL; | |
1559 | } | |
1560 | break; | |
1561 | } | |
1da177e4 | 1562 | |
51061b88 DCZ |
1563 | case 0x3: |
1564 | if (MIPSInst_FUNC(ir) != pfetch_op) | |
1da177e4 | 1565 | return SIGILL; |
51061b88 | 1566 | |
1da177e4 LT |
1567 | /* ignore prefx operation */ |
1568 | break; | |
1569 | ||
1570 | default: | |
1571 | return SIGILL; | |
1572 | } | |
1573 | ||
1574 | return 0; | |
1575 | } | |
1da177e4 LT |
1576 | |
1577 | ||
1578 | ||
1579 | /* | |
1580 | * Emulate a single COP1 arithmetic instruction. | |
1581 | */ | |
eae89076 | 1582 | static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, |
1da177e4 LT |
1583 | mips_instruction ir) |
1584 | { | |
1585 | int rfmt; /* resulting format */ | |
1586 | unsigned rcsr = 0; /* resulting csr */ | |
1587 | unsigned cond; | |
1588 | union { | |
2209bcb1 RB |
1589 | union ieee754dp d; |
1590 | union ieee754sp s; | |
1da177e4 | 1591 | int w; |
1da177e4 | 1592 | s64 l; |
1da177e4 LT |
1593 | } rv; /* resulting value */ |
1594 | ||
b6ee75ed | 1595 | MIPS_FPU_EMU_INC_STATS(cp1ops); |
1da177e4 LT |
1596 | switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) { |
1597 | case s_fmt:{ /* 0 */ | |
1598 | union { | |
2209bcb1 RB |
1599 | union ieee754sp(*b) (union ieee754sp, union ieee754sp); |
1600 | union ieee754sp(*u) (union ieee754sp); | |
1da177e4 LT |
1601 | } handler; |
1602 | ||
1603 | switch (MIPSInst_FUNC(ir)) { | |
1604 | /* binary ops */ | |
1605 | case fadd_op: | |
1606 | handler.b = ieee754sp_add; | |
1607 | goto scopbop; | |
1608 | case fsub_op: | |
1609 | handler.b = ieee754sp_sub; | |
1610 | goto scopbop; | |
1611 | case fmul_op: | |
1612 | handler.b = ieee754sp_mul; | |
1613 | goto scopbop; | |
1614 | case fdiv_op: | |
1615 | handler.b = ieee754sp_div; | |
1616 | goto scopbop; | |
1617 | ||
1618 | /* unary ops */ | |
1da177e4 | 1619 | case fsqrt_op: |
08a07904 RB |
1620 | if (!cpu_has_mips_4_5_r) |
1621 | return SIGILL; | |
1622 | ||
1da177e4 LT |
1623 | handler.u = ieee754sp_sqrt; |
1624 | goto scopuop; | |
08a07904 RB |
1625 | /* |
1626 | * Note that on some MIPS IV implementations such as the | |
1627 | * R5000 and R8000 the FSQRT and FRECIP instructions do not | |
1628 | * achieve full IEEE-754 accuracy - however this emulator does. | |
1629 | */ | |
1da177e4 | 1630 | case frsqrt_op: |
08a07904 RB |
1631 | if (!cpu_has_mips_4_5_r2) |
1632 | return SIGILL; | |
1633 | ||
1da177e4 LT |
1634 | handler.u = fpemu_sp_rsqrt; |
1635 | goto scopuop; | |
1636 | case frecip_op: | |
08a07904 RB |
1637 | if (!cpu_has_mips_4_5_r2) |
1638 | return SIGILL; | |
1639 | ||
1da177e4 LT |
1640 | handler.u = fpemu_sp_recip; |
1641 | goto scopuop; | |
08a07904 | 1642 | |
1da177e4 | 1643 | case fmovc_op: |
08a07904 RB |
1644 | if (!cpu_has_mips_4_5_r) |
1645 | return SIGILL; | |
1646 | ||
1da177e4 LT |
1647 | cond = fpucondbit[MIPSInst_FT(ir) >> 2]; |
1648 | if (((ctx->fcr31 & cond) != 0) != | |
1649 | ((MIPSInst_FT(ir) & 1) != 0)) | |
1650 | return 0; | |
1651 | SPFROMREG(rv.s, MIPSInst_FS(ir)); | |
1652 | break; | |
1653 | case fmovz_op: | |
08a07904 RB |
1654 | if (!cpu_has_mips_4_5_r) |
1655 | return SIGILL; | |
1656 | ||
1da177e4 LT |
1657 | if (xcp->regs[MIPSInst_FT(ir)] != 0) |
1658 | return 0; | |
1659 | SPFROMREG(rv.s, MIPSInst_FS(ir)); | |
1660 | break; | |
1661 | case fmovn_op: | |
08a07904 RB |
1662 | if (!cpu_has_mips_4_5_r) |
1663 | return SIGILL; | |
1664 | ||
1da177e4 LT |
1665 | if (xcp->regs[MIPSInst_FT(ir)] == 0) |
1666 | return 0; | |
1667 | SPFROMREG(rv.s, MIPSInst_FS(ir)); | |
1668 | break; | |
1da177e4 LT |
1669 | case fabs_op: |
1670 | handler.u = ieee754sp_abs; | |
1671 | goto scopuop; | |
1672 | case fneg_op: | |
1673 | handler.u = ieee754sp_neg; | |
1674 | goto scopuop; | |
1675 | case fmov_op: | |
1676 | /* an easy one */ | |
1677 | SPFROMREG(rv.s, MIPSInst_FS(ir)); | |
1678 | goto copcsr; | |
1679 | ||
1680 | /* binary op on handler */ | |
1681 | scopbop: | |
1682 | { | |
2209bcb1 | 1683 | union ieee754sp fs, ft; |
1da177e4 LT |
1684 | |
1685 | SPFROMREG(fs, MIPSInst_FS(ir)); | |
1686 | SPFROMREG(ft, MIPSInst_FT(ir)); | |
1687 | ||
1688 | rv.s = (*handler.b) (fs, ft); | |
1689 | goto copcsr; | |
1690 | } | |
1691 | scopuop: | |
1692 | { | |
2209bcb1 | 1693 | union ieee754sp fs; |
1da177e4 LT |
1694 | |
1695 | SPFROMREG(fs, MIPSInst_FS(ir)); | |
1696 | rv.s = (*handler.u) (fs); | |
1697 | goto copcsr; | |
1698 | } | |
1699 | copcsr: | |
1700 | if (ieee754_cxtest(IEEE754_INEXACT)) | |
1701 | rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S; | |
1702 | if (ieee754_cxtest(IEEE754_UNDERFLOW)) | |
1703 | rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S; | |
1704 | if (ieee754_cxtest(IEEE754_OVERFLOW)) | |
1705 | rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S; | |
1706 | if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) | |
1707 | rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S; | |
1708 | if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) | |
1709 | rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S; | |
1710 | break; | |
1711 | ||
1712 | /* unary conv ops */ | |
1713 | case fcvts_op: | |
1714 | return SIGILL; /* not defined */ | |
1715 | case fcvtd_op:{ | |
2209bcb1 | 1716 | union ieee754sp fs; |
1da177e4 LT |
1717 | |
1718 | SPFROMREG(fs, MIPSInst_FS(ir)); | |
1719 | rv.d = ieee754dp_fsp(fs); | |
1720 | rfmt = d_fmt; | |
1721 | goto copcsr; | |
1722 | } | |
1da177e4 | 1723 | case fcvtw_op:{ |
2209bcb1 | 1724 | union ieee754sp fs; |
1da177e4 LT |
1725 | |
1726 | SPFROMREG(fs, MIPSInst_FS(ir)); | |
1727 | rv.w = ieee754sp_tint(fs); | |
1728 | rfmt = w_fmt; | |
1729 | goto copcsr; | |
1730 | } | |
1731 | ||
1da177e4 LT |
1732 | case fround_op: |
1733 | case ftrunc_op: | |
1734 | case fceil_op: | |
1735 | case ffloor_op:{ | |
1736 | unsigned int oldrm = ieee754_csr.rm; | |
2209bcb1 | 1737 | union ieee754sp fs; |
1da177e4 | 1738 | |
08a07904 RB |
1739 | if (!cpu_has_mips_2_3_4_5 && !cpu_has_mips64) |
1740 | return SIGILL; | |
1741 | ||
1da177e4 | 1742 | SPFROMREG(fs, MIPSInst_FS(ir)); |
3f135530 | 1743 | ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))]; |
1da177e4 LT |
1744 | rv.w = ieee754sp_tint(fs); |
1745 | ieee754_csr.rm = oldrm; | |
1746 | rfmt = w_fmt; | |
1747 | goto copcsr; | |
1748 | } | |
1da177e4 | 1749 | |
1da177e4 | 1750 | case fcvtl_op:{ |
2209bcb1 | 1751 | union ieee754sp fs; |
1da177e4 | 1752 | |
08a07904 RB |
1753 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) |
1754 | return SIGILL; | |
1755 | ||
1da177e4 LT |
1756 | SPFROMREG(fs, MIPSInst_FS(ir)); |
1757 | rv.l = ieee754sp_tlong(fs); | |
1758 | rfmt = l_fmt; | |
1759 | goto copcsr; | |
1760 | } | |
1761 | ||
1762 | case froundl_op: | |
1763 | case ftruncl_op: | |
1764 | case fceill_op: | |
1765 | case ffloorl_op:{ | |
1766 | unsigned int oldrm = ieee754_csr.rm; | |
2209bcb1 | 1767 | union ieee754sp fs; |
1da177e4 | 1768 | |
08a07904 RB |
1769 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) |
1770 | return SIGILL; | |
1771 | ||
1da177e4 | 1772 | SPFROMREG(fs, MIPSInst_FS(ir)); |
3f135530 | 1773 | ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))]; |
1da177e4 LT |
1774 | rv.l = ieee754sp_tlong(fs); |
1775 | ieee754_csr.rm = oldrm; | |
1776 | rfmt = l_fmt; | |
1777 | goto copcsr; | |
1778 | } | |
1da177e4 LT |
1779 | |
1780 | default: | |
1781 | if (MIPSInst_FUNC(ir) >= fcmp_op) { | |
1782 | unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; | |
2209bcb1 | 1783 | union ieee754sp fs, ft; |
1da177e4 LT |
1784 | |
1785 | SPFROMREG(fs, MIPSInst_FS(ir)); | |
1786 | SPFROMREG(ft, MIPSInst_FT(ir)); | |
1787 | rv.w = ieee754sp_cmp(fs, ft, | |
1788 | cmptab[cmpop & 0x7], cmpop & 0x8); | |
1789 | rfmt = -1; | |
1790 | if ((cmpop & 0x8) && ieee754_cxtest | |
1791 | (IEEE754_INVALID_OPERATION)) | |
1792 | rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; | |
1793 | else | |
1794 | goto copcsr; | |
1795 | ||
1796 | } | |
1797 | else { | |
1798 | return SIGILL; | |
1799 | } | |
1800 | break; | |
1801 | } | |
1802 | break; | |
1803 | } | |
1804 | ||
1da177e4 LT |
1805 | case d_fmt:{ |
1806 | union { | |
2209bcb1 RB |
1807 | union ieee754dp(*b) (union ieee754dp, union ieee754dp); |
1808 | union ieee754dp(*u) (union ieee754dp); | |
1da177e4 LT |
1809 | } handler; |
1810 | ||
1811 | switch (MIPSInst_FUNC(ir)) { | |
1812 | /* binary ops */ | |
1813 | case fadd_op: | |
1814 | handler.b = ieee754dp_add; | |
1815 | goto dcopbop; | |
1816 | case fsub_op: | |
1817 | handler.b = ieee754dp_sub; | |
1818 | goto dcopbop; | |
1819 | case fmul_op: | |
1820 | handler.b = ieee754dp_mul; | |
1821 | goto dcopbop; | |
1822 | case fdiv_op: | |
1823 | handler.b = ieee754dp_div; | |
1824 | goto dcopbop; | |
1825 | ||
1826 | /* unary ops */ | |
1da177e4 | 1827 | case fsqrt_op: |
08a07904 RB |
1828 | if (!cpu_has_mips_2_3_4_5_r) |
1829 | return SIGILL; | |
1830 | ||
1da177e4 LT |
1831 | handler.u = ieee754dp_sqrt; |
1832 | goto dcopuop; | |
08a07904 RB |
1833 | /* |
1834 | * Note that on some MIPS IV implementations such as the | |
1835 | * R5000 and R8000 the FSQRT and FRECIP instructions do not | |
1836 | * achieve full IEEE-754 accuracy - however this emulator does. | |
1837 | */ | |
1da177e4 | 1838 | case frsqrt_op: |
08a07904 RB |
1839 | if (!cpu_has_mips_4_5_r2) |
1840 | return SIGILL; | |
1841 | ||
1da177e4 LT |
1842 | handler.u = fpemu_dp_rsqrt; |
1843 | goto dcopuop; | |
1844 | case frecip_op: | |
08a07904 RB |
1845 | if (!cpu_has_mips_4_5_r2) |
1846 | return SIGILL; | |
1847 | ||
1da177e4 LT |
1848 | handler.u = fpemu_dp_recip; |
1849 | goto dcopuop; | |
1da177e4 | 1850 | case fmovc_op: |
08a07904 RB |
1851 | if (!cpu_has_mips_4_5_r) |
1852 | return SIGILL; | |
1853 | ||
1da177e4 LT |
1854 | cond = fpucondbit[MIPSInst_FT(ir) >> 2]; |
1855 | if (((ctx->fcr31 & cond) != 0) != | |
1856 | ((MIPSInst_FT(ir) & 1) != 0)) | |
1857 | return 0; | |
1858 | DPFROMREG(rv.d, MIPSInst_FS(ir)); | |
1859 | break; | |
1860 | case fmovz_op: | |
08a07904 RB |
1861 | if (!cpu_has_mips_4_5_r) |
1862 | return SIGILL; | |
1863 | ||
1da177e4 LT |
1864 | if (xcp->regs[MIPSInst_FT(ir)] != 0) |
1865 | return 0; | |
1866 | DPFROMREG(rv.d, MIPSInst_FS(ir)); | |
1867 | break; | |
1868 | case fmovn_op: | |
08a07904 RB |
1869 | if (!cpu_has_mips_4_5_r) |
1870 | return SIGILL; | |
1871 | ||
1da177e4 LT |
1872 | if (xcp->regs[MIPSInst_FT(ir)] == 0) |
1873 | return 0; | |
1874 | DPFROMREG(rv.d, MIPSInst_FS(ir)); | |
1875 | break; | |
1da177e4 LT |
1876 | case fabs_op: |
1877 | handler.u = ieee754dp_abs; | |
1878 | goto dcopuop; | |
1879 | ||
1880 | case fneg_op: | |
1881 | handler.u = ieee754dp_neg; | |
1882 | goto dcopuop; | |
1883 | ||
1884 | case fmov_op: | |
1885 | /* an easy one */ | |
1886 | DPFROMREG(rv.d, MIPSInst_FS(ir)); | |
1887 | goto copcsr; | |
1888 | ||
1889 | /* binary op on handler */ | |
1890 | dcopbop:{ | |
2209bcb1 | 1891 | union ieee754dp fs, ft; |
1da177e4 LT |
1892 | |
1893 | DPFROMREG(fs, MIPSInst_FS(ir)); | |
1894 | DPFROMREG(ft, MIPSInst_FT(ir)); | |
1895 | ||
1896 | rv.d = (*handler.b) (fs, ft); | |
1897 | goto copcsr; | |
1898 | } | |
1899 | dcopuop:{ | |
2209bcb1 | 1900 | union ieee754dp fs; |
1da177e4 LT |
1901 | |
1902 | DPFROMREG(fs, MIPSInst_FS(ir)); | |
1903 | rv.d = (*handler.u) (fs); | |
1904 | goto copcsr; | |
1905 | } | |
1906 | ||
1907 | /* unary conv ops */ | |
1908 | case fcvts_op:{ | |
2209bcb1 | 1909 | union ieee754dp fs; |
1da177e4 LT |
1910 | |
1911 | DPFROMREG(fs, MIPSInst_FS(ir)); | |
1912 | rv.s = ieee754sp_fdp(fs); | |
1913 | rfmt = s_fmt; | |
1914 | goto copcsr; | |
1915 | } | |
1916 | case fcvtd_op: | |
1917 | return SIGILL; /* not defined */ | |
1918 | ||
1919 | case fcvtw_op:{ | |
2209bcb1 | 1920 | union ieee754dp fs; |
1da177e4 LT |
1921 | |
1922 | DPFROMREG(fs, MIPSInst_FS(ir)); | |
1923 | rv.w = ieee754dp_tint(fs); /* wrong */ | |
1924 | rfmt = w_fmt; | |
1925 | goto copcsr; | |
1926 | } | |
1927 | ||
1da177e4 LT |
1928 | case fround_op: |
1929 | case ftrunc_op: | |
1930 | case fceil_op: | |
1931 | case ffloor_op:{ | |
1932 | unsigned int oldrm = ieee754_csr.rm; | |
2209bcb1 | 1933 | union ieee754dp fs; |
1da177e4 | 1934 | |
08a07904 RB |
1935 | if (!cpu_has_mips_2_3_4_5_r) |
1936 | return SIGILL; | |
1937 | ||
1da177e4 | 1938 | DPFROMREG(fs, MIPSInst_FS(ir)); |
3f135530 | 1939 | ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))]; |
1da177e4 LT |
1940 | rv.w = ieee754dp_tint(fs); |
1941 | ieee754_csr.rm = oldrm; | |
1942 | rfmt = w_fmt; | |
1943 | goto copcsr; | |
1944 | } | |
1da177e4 | 1945 | |
1da177e4 | 1946 | case fcvtl_op:{ |
2209bcb1 | 1947 | union ieee754dp fs; |
1da177e4 | 1948 | |
08a07904 RB |
1949 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) |
1950 | return SIGILL; | |
1951 | ||
1da177e4 LT |
1952 | DPFROMREG(fs, MIPSInst_FS(ir)); |
1953 | rv.l = ieee754dp_tlong(fs); | |
1954 | rfmt = l_fmt; | |
1955 | goto copcsr; | |
1956 | } | |
1957 | ||
1958 | case froundl_op: | |
1959 | case ftruncl_op: | |
1960 | case fceill_op: | |
1961 | case ffloorl_op:{ | |
1962 | unsigned int oldrm = ieee754_csr.rm; | |
2209bcb1 | 1963 | union ieee754dp fs; |
1da177e4 | 1964 | |
08a07904 RB |
1965 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) |
1966 | return SIGILL; | |
1967 | ||
1da177e4 | 1968 | DPFROMREG(fs, MIPSInst_FS(ir)); |
3f135530 | 1969 | ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))]; |
1da177e4 LT |
1970 | rv.l = ieee754dp_tlong(fs); |
1971 | ieee754_csr.rm = oldrm; | |
1972 | rfmt = l_fmt; | |
1973 | goto copcsr; | |
1974 | } | |
1da177e4 LT |
1975 | |
1976 | default: | |
1977 | if (MIPSInst_FUNC(ir) >= fcmp_op) { | |
1978 | unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op; | |
2209bcb1 | 1979 | union ieee754dp fs, ft; |
1da177e4 LT |
1980 | |
1981 | DPFROMREG(fs, MIPSInst_FS(ir)); | |
1982 | DPFROMREG(ft, MIPSInst_FT(ir)); | |
1983 | rv.w = ieee754dp_cmp(fs, ft, | |
1984 | cmptab[cmpop & 0x7], cmpop & 0x8); | |
1985 | rfmt = -1; | |
1986 | if ((cmpop & 0x8) | |
1987 | && | |
1988 | ieee754_cxtest | |
1989 | (IEEE754_INVALID_OPERATION)) | |
1990 | rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S; | |
1991 | else | |
1992 | goto copcsr; | |
1993 | ||
1994 | } | |
1995 | else { | |
1996 | return SIGILL; | |
1997 | } | |
1998 | break; | |
1999 | } | |
2000 | break; | |
2001 | } | |
1da177e4 LT |
2002 | |
2003 | case w_fmt:{ | |
2209bcb1 | 2004 | union ieee754sp fs; |
1da177e4 LT |
2005 | |
2006 | switch (MIPSInst_FUNC(ir)) { | |
2007 | case fcvts_op: | |
2008 | /* convert word to single precision real */ | |
2009 | SPFROMREG(fs, MIPSInst_FS(ir)); | |
2010 | rv.s = ieee754sp_fint(fs.bits); | |
2011 | rfmt = s_fmt; | |
2012 | goto copcsr; | |
1da177e4 LT |
2013 | case fcvtd_op: |
2014 | /* convert word to double precision real */ | |
2015 | SPFROMREG(fs, MIPSInst_FS(ir)); | |
2016 | rv.d = ieee754dp_fint(fs.bits); | |
2017 | rfmt = d_fmt; | |
2018 | goto copcsr; | |
1da177e4 LT |
2019 | default: |
2020 | return SIGILL; | |
2021 | } | |
2022 | break; | |
2023 | } | |
2024 | ||
1da177e4 | 2025 | case l_fmt:{ |
bbd426f5 | 2026 | u64 bits; |
08a07904 RB |
2027 | |
2028 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) | |
2029 | return SIGILL; | |
2030 | ||
bbd426f5 PB |
2031 | DIFROMREG(bits, MIPSInst_FS(ir)); |
2032 | ||
1da177e4 LT |
2033 | switch (MIPSInst_FUNC(ir)) { |
2034 | case fcvts_op: | |
2035 | /* convert long to single precision real */ | |
bbd426f5 | 2036 | rv.s = ieee754sp_flong(bits); |
1da177e4 LT |
2037 | rfmt = s_fmt; |
2038 | goto copcsr; | |
2039 | case fcvtd_op: | |
2040 | /* convert long to double precision real */ | |
bbd426f5 | 2041 | rv.d = ieee754dp_flong(bits); |
1da177e4 LT |
2042 | rfmt = d_fmt; |
2043 | goto copcsr; | |
2044 | default: | |
2045 | return SIGILL; | |
2046 | } | |
2047 | break; | |
2048 | } | |
1da177e4 LT |
2049 | |
2050 | default: | |
2051 | return SIGILL; | |
2052 | } | |
2053 | ||
2054 | /* | |
2055 | * Update the fpu CSR register for this operation. | |
2056 | * If an exception is required, generate a tidy SIGFPE exception, | |
2057 | * without updating the result register. | |
2058 | * Note: cause exception bits do not accumulate, they are rewritten | |
2059 | * for each op; only the flag/sticky bits accumulate. | |
2060 | */ | |
2061 | ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr; | |
2062 | if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { | |
2063 | /*printk ("SIGFPE: fpu csr = %08x\n",ctx->fcr31); */ | |
2064 | return SIGFPE; | |
2065 | } | |
2066 | ||
2067 | /* | |
2068 | * Now we can safely write the result back to the register file. | |
2069 | */ | |
2070 | switch (rfmt) { | |
08a07904 RB |
2071 | unsigned int cbit; |
2072 | case -1: | |
2073 | ||
2074 | if (cpu_has_mips_4_5_r) | |
2075 | cbit = fpucondbit[MIPSInst_RT(ir) >> 2]; | |
2076 | else | |
2077 | cbit = FPU_CSR_COND; | |
1da177e4 | 2078 | if (rv.w) |
08a07904 | 2079 | ctx->fcr31 |= cbit; |
1da177e4 | 2080 | else |
08a07904 | 2081 | ctx->fcr31 &= ~cbit; |
1da177e4 | 2082 | break; |
08a07904 | 2083 | |
1da177e4 LT |
2084 | case d_fmt: |
2085 | DPTOREG(rv.d, MIPSInst_FD(ir)); | |
2086 | break; | |
1da177e4 LT |
2087 | case s_fmt: |
2088 | SPTOREG(rv.s, MIPSInst_FD(ir)); | |
2089 | break; | |
2090 | case w_fmt: | |
2091 | SITOREG(rv.w, MIPSInst_FD(ir)); | |
2092 | break; | |
1da177e4 | 2093 | case l_fmt: |
08a07904 RB |
2094 | if (!cpu_has_mips_3_4_5 && !cpu_has_mips64) |
2095 | return SIGILL; | |
2096 | ||
1da177e4 LT |
2097 | DITOREG(rv.l, MIPSInst_FD(ir)); |
2098 | break; | |
1da177e4 LT |
2099 | default: |
2100 | return SIGILL; | |
2101 | } | |
2102 | ||
2103 | return 0; | |
2104 | } | |
2105 | ||
e04582b7 | 2106 | int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, |
515b029d | 2107 | int has_fpu, void *__user *fault_addr) |
1da177e4 | 2108 | { |
333d1f67 | 2109 | unsigned long oldepc, prevepc; |
102cedc3 LY |
2110 | struct mm_decoded_insn dec_insn; |
2111 | u16 instr[4]; | |
2112 | u16 *instr_ptr; | |
1da177e4 LT |
2113 | int sig = 0; |
2114 | ||
2115 | oldepc = xcp->cp0_epc; | |
2116 | do { | |
2117 | prevepc = xcp->cp0_epc; | |
2118 | ||
102cedc3 LY |
2119 | if (get_isa16_mode(prevepc) && cpu_has_mmips) { |
2120 | /* | |
2121 | * Get next 2 microMIPS instructions and convert them | |
2122 | * into 32-bit instructions. | |
2123 | */ | |
2124 | if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) || | |
2125 | (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) || | |
2126 | (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) || | |
2127 | (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) { | |
2128 | MIPS_FPU_EMU_INC_STATS(errors); | |
2129 | return SIGBUS; | |
2130 | } | |
2131 | instr_ptr = instr; | |
2132 | ||
2133 | /* Get first instruction. */ | |
2134 | if (mm_insn_16bit(*instr_ptr)) { | |
2135 | /* Duplicate the half-word. */ | |
2136 | dec_insn.insn = (*instr_ptr << 16) | | |
2137 | (*instr_ptr); | |
2138 | /* 16-bit instruction. */ | |
2139 | dec_insn.pc_inc = 2; | |
2140 | instr_ptr += 1; | |
2141 | } else { | |
2142 | dec_insn.insn = (*instr_ptr << 16) | | |
2143 | *(instr_ptr+1); | |
2144 | /* 32-bit instruction. */ | |
2145 | dec_insn.pc_inc = 4; | |
2146 | instr_ptr += 2; | |
2147 | } | |
2148 | /* Get second instruction. */ | |
2149 | if (mm_insn_16bit(*instr_ptr)) { | |
2150 | /* Duplicate the half-word. */ | |
2151 | dec_insn.next_insn = (*instr_ptr << 16) | | |
2152 | (*instr_ptr); | |
2153 | /* 16-bit instruction. */ | |
2154 | dec_insn.next_pc_inc = 2; | |
2155 | } else { | |
2156 | dec_insn.next_insn = (*instr_ptr << 16) | | |
2157 | *(instr_ptr+1); | |
2158 | /* 32-bit instruction. */ | |
2159 | dec_insn.next_pc_inc = 4; | |
2160 | } | |
2161 | dec_insn.micro_mips_mode = 1; | |
2162 | } else { | |
2163 | if ((get_user(dec_insn.insn, | |
2164 | (mips_instruction __user *) xcp->cp0_epc)) || | |
2165 | (get_user(dec_insn.next_insn, | |
2166 | (mips_instruction __user *)(xcp->cp0_epc+4)))) { | |
2167 | MIPS_FPU_EMU_INC_STATS(errors); | |
2168 | return SIGBUS; | |
2169 | } | |
2170 | dec_insn.pc_inc = 4; | |
2171 | dec_insn.next_pc_inc = 4; | |
2172 | dec_insn.micro_mips_mode = 0; | |
515b029d | 2173 | } |
102cedc3 LY |
2174 | |
2175 | if ((dec_insn.insn == 0) || | |
2176 | ((dec_insn.pc_inc == 2) && | |
2177 | ((dec_insn.insn & 0xffff) == MM_NOP16))) | |
2178 | xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */ | |
1da177e4 | 2179 | else { |
cd21dfcf RB |
2180 | /* |
2181 | * The 'ieee754_csr' is an alias of | |
70342287 RB |
2182 | * ctx->fcr31. No need to copy ctx->fcr31 to |
2183 | * ieee754_csr. But ieee754_csr.rm is ieee | |
cd21dfcf RB |
2184 | * library modes. (not mips rounding mode) |
2185 | */ | |
2186 | /* convert to ieee library modes */ | |
2187 | ieee754_csr.rm = ieee_rm[ieee754_csr.rm]; | |
102cedc3 | 2188 | sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr); |
cd21dfcf RB |
2189 | /* revert to mips rounding mode */ |
2190 | ieee754_csr.rm = mips_rm[ieee754_csr.rm]; | |
1da177e4 LT |
2191 | } |
2192 | ||
e04582b7 | 2193 | if (has_fpu) |
1da177e4 LT |
2194 | break; |
2195 | if (sig) | |
2196 | break; | |
2197 | ||
2198 | cond_resched(); | |
2199 | } while (xcp->cp0_epc > prevepc); | |
2200 | ||
2201 | /* SIGILL indicates a non-fpu instruction */ | |
2202 | if (sig == SIGILL && xcp->cp0_epc != oldepc) | |
2203 | /* but if epc has advanced, then ignore it */ | |
2204 | sig = 0; | |
2205 | ||
2206 | return sig; | |
2207 | } |