[linux-block.git] / arch / mips / loongson64 / env.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Based on Ocelot Linux port, which is
 * Copyright 2001 MontaVista Software Inc.
 * Author: jsun@mvista.com or jsun@junsun.net
 *
 * Copyright 2003 ICT CAS
 * Author: Michael Guo <guoyi@ict.ac.cn>
 *
 * Copyright (C) 2007 Lemote Inc. & Institute of Computing Technology
 * Author: Fuxin Zhang, zhangfx@lemote.com
 *
 * Copyright (C) 2009 Lemote Inc.
 * Author: Wu Zhangjin, wuzhangjin@gmail.com
 */
#include <linux/export.h>
#include <linux/pci_ids.h>
#include <asm/bootinfo.h>
#include <loongson.h>
#include <boot_param.h>
#include <builtin_dtbs.h>
#include <workarounds.h>

#define HOST_BRIDGE_CONFIG_ADDR	((void __iomem *)TO_UNCAC(0x1a000000))

u32 cpu_clock_freq;
EXPORT_SYMBOL(cpu_clock_freq);
struct efi_memory_map_loongson *loongson_memmap;
struct loongson_system_configuration loongson_sysconf;

struct board_devices *eboard;
struct interface_info *einter;
struct loongson_special_attribute *especial;

u64 loongson_chipcfg[MAX_PACKAGES] = {0xffffffffbfc00180};
u64 loongson_chiptemp[MAX_PACKAGES];
u64 loongson_freqctrl[MAX_PACKAGES];

unsigned long long smp_group[4];

const char *get_system_type(void)
{
	return "Generic Loongson64 System";
}


void __init prom_dtb_init_env(void)
{
	if ((fw_arg2 < CKSEG0 || fw_arg2 > CKSEG1)
		&& (fw_arg2 < XKPHYS || fw_arg2 > XKSEG))

		loongson_fdt_blob = __dtb_loongson64_2core_2k1000_begin;
	else
		loongson_fdt_blob = (void *)fw_arg2;
}

void __init prom_lefi_init_env(void)
{
	struct boot_params *boot_p;
	struct loongson_params *loongson_p;
	struct system_loongson *esys;
	struct efi_cpuinfo_loongson *ecpu;
	struct irq_source_routing_table *eirq_source;
	u32 id;
	u16 vendor;

	/* firmware arguments are initialized in head.S */
	boot_p = (struct boot_params *)fw_arg2;
	loongson_p = &(boot_p->efi.smbios.lp);

	esys = (struct system_loongson *)
		((u64)loongson_p + loongson_p->system_offset);
	ecpu = (struct efi_cpuinfo_loongson *)
		((u64)loongson_p + loongson_p->cpu_offset);
	eboard = (struct board_devices *)
		((u64)loongson_p + loongson_p->boarddev_table_offset);
	einter = (struct interface_info *)
		((u64)loongson_p + loongson_p->interface_offset);
	especial = (struct loongson_special_attribute *)
		((u64)loongson_p + loongson_p->special_offset);
	eirq_source = (struct irq_source_routing_table *)
		((u64)loongson_p + loongson_p->irq_offset);
	loongson_memmap = (struct efi_memory_map_loongson *)
		((u64)loongson_p + loongson_p->memory_offset);

	cpu_clock_freq = ecpu->cpu_clock_freq;
	loongson_sysconf.cputype = ecpu->cputype;
	switch (ecpu->cputype) {
	case Legacy_3A:
	case Loongson_3A:
		loongson_sysconf.cores_per_node = 4;
		loongson_sysconf.cores_per_package = 4;
		smp_group[0] = 0x900000003ff01000;
		smp_group[1] = 0x900010003ff01000;
		smp_group[2] = 0x900020003ff01000;
		smp_group[3] = 0x900030003ff01000;
		loongson_chipcfg[0] = 0x900000001fe00180;
		loongson_chipcfg[1] = 0x900010001fe00180;
		loongson_chipcfg[2] = 0x900020001fe00180;
		loongson_chipcfg[3] = 0x900030001fe00180;
		loongson_chiptemp[0] = 0x900000001fe0019c;
		loongson_chiptemp[1] = 0x900010001fe0019c;
		loongson_chiptemp[2] = 0x900020001fe0019c;
		loongson_chiptemp[3] = 0x900030001fe0019c;
		loongson_freqctrl[0] = 0x900000001fe001d0;
		loongson_freqctrl[1] = 0x900010001fe001d0;
		loongson_freqctrl[2] = 0x900020001fe001d0;
		loongson_freqctrl[3] = 0x900030001fe001d0;
		loongson_sysconf.workarounds = WORKAROUND_CPUFREQ;
		break;
	case Legacy_3B:
	case Loongson_3B:
		loongson_sysconf.cores_per_node = 4; /* One chip has 2 nodes */
		loongson_sysconf.cores_per_package = 8;
		smp_group[0] = 0x900000003ff01000;
		smp_group[1] = 0x900010003ff05000;
		smp_group[2] = 0x900020003ff09000;
		smp_group[3] = 0x900030003ff0d000;
		loongson_chipcfg[0] = 0x900000001fe00180;
		loongson_chipcfg[1] = 0x900020001fe00180;
		loongson_chipcfg[2] = 0x900040001fe00180;
		loongson_chipcfg[3] = 0x900060001fe00180;
		loongson_chiptemp[0] = 0x900000001fe0019c;
		loongson_chiptemp[1] = 0x900020001fe0019c;
		loongson_chiptemp[2] = 0x900040001fe0019c;
		loongson_chiptemp[3] = 0x900060001fe0019c;
		loongson_freqctrl[0] = 0x900000001fe001d0;
		loongson_freqctrl[1] = 0x900020001fe001d0;
		loongson_freqctrl[2] = 0x900040001fe001d0;
		loongson_freqctrl[3] = 0x900060001fe001d0;
		loongson_sysconf.workarounds = WORKAROUND_CPUHOTPLUG;
		break;
	default:
		loongson_sysconf.cores_per_node = 1;
		loongson_sysconf.cores_per_package = 1;
		loongson_chipcfg[0] = 0x900000001fe00180;
	}

	loongson_sysconf.nr_cpus = ecpu->nr_cpus;
	loongson_sysconf.boot_cpu_id = ecpu->cpu_startup_core_id;
	loongson_sysconf.reserved_cpus_mask = ecpu->reserved_cores_mask;
	if (ecpu->nr_cpus > NR_CPUS || ecpu->nr_cpus == 0)
		loongson_sysconf.nr_cpus = NR_CPUS;
	loongson_sysconf.nr_nodes = (loongson_sysconf.nr_cpus +
		loongson_sysconf.cores_per_node - 1) /
		loongson_sysconf.cores_per_node;

	loongson_sysconf.dma_mask_bits = eirq_source->dma_mask_bits;
	if (loongson_sysconf.dma_mask_bits < 32 ||
		loongson_sysconf.dma_mask_bits > 64)
		loongson_sysconf.dma_mask_bits = 32;

	loongson_sysconf.restart_addr = boot_p->reset_system.ResetWarm;
	loongson_sysconf.poweroff_addr = boot_p->reset_system.Shutdown;
	loongson_sysconf.suspend_addr = boot_p->reset_system.DoSuspend;

	loongson_sysconf.vgabios_addr = boot_p->efi.smbios.vga_bios;
	pr_debug("Shutdown Addr: %llx, Restart Addr: %llx, VBIOS Addr: %llx\n",
		loongson_sysconf.poweroff_addr, loongson_sysconf.restart_addr,
		loongson_sysconf.vgabios_addr);

	loongson_sysconf.workarounds |= esys->workarounds;

	pr_info("CpuClock = %u\n", cpu_clock_freq);

	/* Read the ID of PCI host bridge to detect bridge type */
	id = readl(HOST_BRIDGE_CONFIG_ADDR);
	vendor = id & 0xffff;

	switch (vendor) {
	case PCI_VENDOR_ID_LOONGSON:
		pr_info("The bridge chip is LS7A\n");
		loongson_sysconf.bridgetype = LS7A;
		loongson_sysconf.early_config = ls7a_early_config;
		break;
	case PCI_VENDOR_ID_AMD:
	case PCI_VENDOR_ID_ATI:
		pr_info("The bridge chip is RS780E or SR5690\n");
		loongson_sysconf.bridgetype = RS780E;
		loongson_sysconf.early_config = rs780e_early_config;
		break;
	default:
		pr_info("The bridge chip is VIRTUAL\n");
		loongson_sysconf.bridgetype = VIRTUAL;
		loongson_sysconf.early_config = virtual_early_config;
		loongson_fdt_blob = __dtb_loongson64v_4core_virtio_begin;
		break;
	}

	if ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64C) {
		switch (read_c0_prid() & PRID_REV_MASK) {
		case PRID_REV_LOONGSON3A_R1:
		case PRID_REV_LOONGSON3A_R2_0:
		case PRID_REV_LOONGSON3A_R2_1:
		case PRID_REV_LOONGSON3A_R3_0:
		case PRID_REV_LOONGSON3A_R3_1:
			switch (loongson_sysconf.bridgetype) {
			case LS7A:
				loongson_fdt_blob = __dtb_loongson64c_4core_ls7a_begin;
				break;
			case RS780E:
				loongson_fdt_blob = __dtb_loongson64c_4core_rs780e_begin;
				break;
			default:
				break;
			}
			break;
		case PRID_REV_LOONGSON3B_R1:
		case PRID_REV_LOONGSON3B_R2:
			if (loongson_sysconf.bridgetype == RS780E)
				loongson_fdt_blob = __dtb_loongson64c_8core_rs780e_begin;
			break;
		default:
			break;
		}
	} else if ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64G) {
		if (loongson_sysconf.bridgetype == LS7A)
			loongson_fdt_blob = __dtb_loongson64g_4core_ls7a_begin;
	}

	if (!loongson_fdt_blob)
		pr_err("Failed to determine built-in Loongson64 dtb\n");
}
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
bd92aa01 WZ	2	/*
	3	* Based on Ocelot Linux port, which is
	4	* Copyright 2001 MontaVista Software Inc.
	5	* Author: jsun@mvista.com or jsun@junsun.net
	6	*
	7	* Copyright 2003 ICT CAS
	8	* Author: Michael Guo <guoyi@ict.ac.cn>
	9	*
0bb383a2	10	* Copyright (C) 2007 Lemote Inc. & Institute of Computing Technology
bd92aa01 WZ	11	* Author: Fuxin Zhang, zhangfx@lemote.com
bd92aa01 WZ	12	*
f7a904df WZ	13	* Copyright (C) 2009 Lemote Inc.
f7a904df WZ	14	* Author: Wu Zhangjin, wuzhangjin@gmail.com
bd92aa01	15	*/
26dd3e4f	16	#include <linux/export.h>
8c88cc53	17	#include <linux/pci_ids.h>
bd92aa01	18	#include <asm/bootinfo.h>
5e983ff6	19	#include <loongson.h>
1a08f152	20	#include <boot_param.h>
fcecdcd3	21	#include <builtin_dtbs.h>
3adeb256	22	#include <workarounds.h>
5e983ff6	23
8c88cc53 TY	24	#define HOST_BRIDGE_CONFIG_ADDR ((void __iomem *)TO_UNCAC(0x1a000000))
8c88cc53 TY	25
1a08f152	26	u32 cpu_clock_freq;
f8ede0f7	27	EXPORT_SYMBOL(cpu_clock_freq);
1a08f152 HC	28	struct efi_memory_map_loongson *loongson_memmap;
1a08f152 HC	29	struct loongson_system_configuration loongson_sysconf;
bd92aa01	30
6c1bfbd9 TY	31	struct board_devices *eboard;
	32	struct interface_info *einter;
	33	struct loongson_special_attribute *especial;
	34
140e39c1	35	u64 loongson_chipcfg[MAX_PACKAGES] = {0xffffffffbfc00180};
64f09aa9	36	u64 loongson_chiptemp[MAX_PACKAGES];
e7841be5 HC	37	u64 loongson_freqctrl[MAX_PACKAGES];
	38
	39	unsigned long long smp_group[4];
140e39c1	40
1bdb7b76 JY	41	const char *get_system_type(void)
	42	{
	43	return "Generic Loongson64 System";
	44	}
bd92aa01	45
8e2fe0ec QZ	46
	47	void __init prom_dtb_init_env(void)
	48	{
	49	if ((fw_arg2 < CKSEG0 \|\| fw_arg2 > CKSEG1)
	50	&& (fw_arg2 < XKPHYS \|\| fw_arg2 > XKSEG))
	51
	52	loongson_fdt_blob = __dtb_loongson64_2core_2k1000_begin;
	53	else
	54	loongson_fdt_blob = (void *)fw_arg2;
	55	}
	56
	57	void __init prom_lefi_init_env(void)
bd92aa01	58	{
1a08f152 HC	59	struct boot_params *boot_p;
1a08f152 HC	60	struct loongson_params *loongson_p;
3adeb256	61	struct system_loongson *esys;
1a08f152 HC	62	struct efi_cpuinfo_loongson *ecpu;
1a08f152 HC	63	struct irq_source_routing_table *eirq_source;
8c88cc53	64	u32 id;
4f5d31ce	65	u16 vendor;
1a08f152 HC	66
	67	/* firmware arguments are initialized in head.S */
	68	boot_p = (struct boot_params *)fw_arg2;
	69	loongson_p = &(boot_p->efi.smbios.lp);
	70
3adeb256 HC	71	esys = (struct system_loongson *)
3adeb256 HC	72	((u64)loongson_p + loongson_p->system_offset);
1a08f152 HC	73	ecpu = (struct efi_cpuinfo_loongson *)
1a08f152 HC	74	((u64)loongson_p + loongson_p->cpu_offset);
6c1bfbd9 TY	75	eboard = (struct board_devices *)
	76	((u64)loongson_p + loongson_p->boarddev_table_offset);
	77	einter = (struct interface_info *)
	78	((u64)loongson_p + loongson_p->interface_offset);
	79	especial = (struct loongson_special_attribute *)
	80	((u64)loongson_p + loongson_p->special_offset);
1a08f152 HC	81	eirq_source = (struct irq_source_routing_table *)
	82	((u64)loongson_p + loongson_p->irq_offset);
	83	loongson_memmap = (struct efi_memory_map_loongson *)
	84	((u64)loongson_p + loongson_p->memory_offset);
	85
	86	cpu_clock_freq = ecpu->cpu_clock_freq;
	87	loongson_sysconf.cputype = ecpu->cputype;
b9c4dc2c HC	88	switch (ecpu->cputype) {
	89	case Legacy_3A:
	90	case Loongson_3A:
c4617318 HC	91	loongson_sysconf.cores_per_node = 4;
c4617318 HC	92	loongson_sysconf.cores_per_package = 4;
e7841be5 HC	93	smp_group[0] = 0x900000003ff01000;
	94	smp_group[1] = 0x900010003ff01000;
	95	smp_group[2] = 0x900020003ff01000;
	96	smp_group[3] = 0x900030003ff01000;
140e39c1 HC	97	loongson_chipcfg[0] = 0x900000001fe00180;
	98	loongson_chipcfg[1] = 0x900010001fe00180;
	99	loongson_chipcfg[2] = 0x900020001fe00180;
	100	loongson_chipcfg[3] = 0x900030001fe00180;
64f09aa9 HC	101	loongson_chiptemp[0] = 0x900000001fe0019c;
	102	loongson_chiptemp[1] = 0x900010001fe0019c;
	103	loongson_chiptemp[2] = 0x900020001fe0019c;
	104	loongson_chiptemp[3] = 0x900030001fe0019c;
b2edcfc8 HC	105	loongson_freqctrl[0] = 0x900000001fe001d0;
	106	loongson_freqctrl[1] = 0x900010001fe001d0;
	107	loongson_freqctrl[2] = 0x900020001fe001d0;
	108	loongson_freqctrl[3] = 0x900030001fe001d0;
3adeb256	109	loongson_sysconf.workarounds = WORKAROUND_CPUFREQ;
b9c4dc2c HC	110	break;
	111	case Legacy_3B:
	112	case Loongson_3B:
e7841be5 HC	113	loongson_sysconf.cores_per_node = 4; /* One chip has 2 nodes */
	114	loongson_sysconf.cores_per_package = 8;
	115	smp_group[0] = 0x900000003ff01000;
	116	smp_group[1] = 0x900010003ff05000;
	117	smp_group[2] = 0x900020003ff09000;
	118	smp_group[3] = 0x900030003ff0d000;
	119	loongson_chipcfg[0] = 0x900000001fe00180;
	120	loongson_chipcfg[1] = 0x900020001fe00180;
	121	loongson_chipcfg[2] = 0x900040001fe00180;
	122	loongson_chipcfg[3] = 0x900060001fe00180;
64f09aa9 HC	123	loongson_chiptemp[0] = 0x900000001fe0019c;
	124	loongson_chiptemp[1] = 0x900020001fe0019c;
	125	loongson_chiptemp[2] = 0x900040001fe0019c;
	126	loongson_chiptemp[3] = 0x900060001fe0019c;
e7841be5 HC	127	loongson_freqctrl[0] = 0x900000001fe001d0;
	128	loongson_freqctrl[1] = 0x900020001fe001d0;
	129	loongson_freqctrl[2] = 0x900040001fe001d0;
	130	loongson_freqctrl[3] = 0x900060001fe001d0;
3adeb256	131	loongson_sysconf.workarounds = WORKAROUND_CPUHOTPLUG;
b9c4dc2c HC	132	break;
b9c4dc2c HC	133	default:
c4617318 HC	134	loongson_sysconf.cores_per_node = 1;
c4617318 HC	135	loongson_sysconf.cores_per_package = 1;
140e39c1 HC	136	loongson_chipcfg[0] = 0x900000001fe00180;
	137	}
	138
1a08f152	139	loongson_sysconf.nr_cpus = ecpu->nr_cpus;
ec0f8d3f HC	140	loongson_sysconf.boot_cpu_id = ecpu->cpu_startup_core_id;
ec0f8d3f HC	141	loongson_sysconf.reserved_cpus_mask = ecpu->reserved_cores_mask;
1a08f152 HC	142	if (ecpu->nr_cpus > NR_CPUS \|\| ecpu->nr_cpus == 0)
1a08f152 HC	143	loongson_sysconf.nr_cpus = NR_CPUS;
c4617318 HC	144	loongson_sysconf.nr_nodes = (loongson_sysconf.nr_cpus +
	145	loongson_sysconf.cores_per_node - 1) /
	146	loongson_sysconf.cores_per_node;
1a08f152	147
1a08f152 HC	148	loongson_sysconf.dma_mask_bits = eirq_source->dma_mask_bits;
	149	if (loongson_sysconf.dma_mask_bits < 32 \|\|
	150	loongson_sysconf.dma_mask_bits > 64)
	151	loongson_sysconf.dma_mask_bits = 32;
	152
	153	loongson_sysconf.restart_addr = boot_p->reset_system.ResetWarm;
	154	loongson_sysconf.poweroff_addr = boot_p->reset_system.Shutdown;
	155	loongson_sysconf.suspend_addr = boot_p->reset_system.DoSuspend;
	156
1a08f152 HC	157	loongson_sysconf.vgabios_addr = boot_p->efi.smbios.vga_bios;
	158	pr_debug("Shutdown Addr: %llx, Restart Addr: %llx, VBIOS Addr: %llx\n",
	159	loongson_sysconf.poweroff_addr, loongson_sysconf.restart_addr,
	160	loongson_sysconf.vgabios_addr);
3adeb256	161
3adeb256 HC	162	loongson_sysconf.workarounds \|= esys->workarounds;
3adeb256 HC	163
1a08f152	164	pr_info("CpuClock = %u\n", cpu_clock_freq);
8c88cc53 TY	165
	166	/* Read the ID of PCI host bridge to detect bridge type */
	167	id = readl(HOST_BRIDGE_CONFIG_ADDR);
	168	vendor = id & 0xffff;
8c88cc53	169
39c1485c HC	170	switch (vendor) {
39c1485c HC	171	case PCI_VENDOR_ID_LOONGSON:
8c88cc53 TY	172	pr_info("The bridge chip is LS7A\n");
8c88cc53 TY	173	loongson_sysconf.bridgetype = LS7A;
68fbb972	174	loongson_sysconf.early_config = ls7a_early_config;
39c1485c HC	175	break;
	176	case PCI_VENDOR_ID_AMD:
	177	case PCI_VENDOR_ID_ATI:
8c88cc53 TY	178	pr_info("The bridge chip is RS780E or SR5690\n");
8c88cc53 TY	179	loongson_sysconf.bridgetype = RS780E;
68fbb972	180	loongson_sysconf.early_config = rs780e_early_config;
39c1485c HC	181	break;
	182	default:
	183	pr_info("The bridge chip is VIRTUAL\n");
	184	loongson_sysconf.bridgetype = VIRTUAL;
	185	loongson_sysconf.early_config = virtual_early_config;
	186	loongson_fdt_blob = __dtb_loongson64v_4core_virtio_begin;
	187	break;
8c88cc53	188	}
770a697c JY	189
	190	if ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64C) {
	191	switch (read_c0_prid() & PRID_REV_MASK) {
	192	case PRID_REV_LOONGSON3A_R1:
	193	case PRID_REV_LOONGSON3A_R2_0:
	194	case PRID_REV_LOONGSON3A_R2_1:
	195	case PRID_REV_LOONGSON3A_R3_0:
	196	case PRID_REV_LOONGSON3A_R3_1:
	197	switch (loongson_sysconf.bridgetype) {
	198	case LS7A:
	199	loongson_fdt_blob = __dtb_loongson64c_4core_ls7a_begin;
	200	break;
	201	case RS780E:
	202	loongson_fdt_blob = __dtb_loongson64c_4core_rs780e_begin;
	203	break;
	204	default:
	205	break;
	206	}
	207	break;
	208	case PRID_REV_LOONGSON3B_R1:
	209	case PRID_REV_LOONGSON3B_R2:
	210	if (loongson_sysconf.bridgetype == RS780E)
	211	loongson_fdt_blob = __dtb_loongson64c_8core_rs780e_begin;
	212	break;
	213	default:
	214	break;
	215	}
	216	} else if ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64G) {
	217	if (loongson_sysconf.bridgetype == LS7A)
	218	loongson_fdt_blob = __dtb_loongson64g_4core_ls7a_begin;
	219	}
	220
	221	if (!loongson_fdt_blob)
	222	pr_err("Failed to determine built-in Loongson64 dtb\n");
bd92aa01	223	}