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1 | /* |
2 | * CS5536 General timer functions | |
3 | * | |
0bb383a2 | 4 | * Copyright (C) 2007 Lemote Inc. & Institute of Computing Technology |
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5 | * Author: Yanhua, yanh@lemote.com |
6 | * | |
7 | * Copyright (C) 2009 Lemote Inc. | |
f7a904df | 8 | * Author: Wu zhangjin, wuzhangjin@gmail.com |
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9 | * |
10 | * Reference: AMD Geode(TM) CS5536 Companion Device Data Book | |
11 | * | |
70342287 RB |
12 | * This program is free software; you can redistribute it and/or modify it |
13 | * under the terms of the GNU General Public License as published by the | |
14 | * Free Software Foundation; either version 2 of the License, or (at your | |
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15 | * option) any later version. |
16 | */ | |
17 | ||
18 | #include <linux/io.h> | |
19 | #include <linux/init.h> | |
26dd3e4f | 20 | #include <linux/export.h> |
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21 | #include <linux/jiffies.h> |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/clockchips.h> | |
25 | ||
26 | #include <asm/time.h> | |
27 | ||
28 | #include <cs5536/cs5536_mfgpt.h> | |
29 | ||
f02ffb19 | 30 | static DEFINE_RAW_SPINLOCK(mfgpt_lock); |
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31 | |
32 | static u32 mfgpt_base; | |
33 | ||
34 | /* | |
35 | * Initialize the MFGPT timer. | |
36 | * | |
37 | * This is also called after resume to bring the MFGPT into operation again. | |
38 | */ | |
39 | ||
40 | /* disable counter */ | |
41 | void disable_mfgpt0_counter(void) | |
42 | { | |
43 | outw(inw(MFGPT0_SETUP) & 0x7fff, MFGPT0_SETUP); | |
44 | } | |
45 | EXPORT_SYMBOL(disable_mfgpt0_counter); | |
46 | ||
47 | /* enable counter, comparator2 to event mode, 14.318MHz clock */ | |
48 | void enable_mfgpt0_counter(void) | |
49 | { | |
50 | outw(0xe310, MFGPT0_SETUP); | |
51 | } | |
52 | EXPORT_SYMBOL(enable_mfgpt0_counter); | |
53 | ||
e3280b2a | 54 | static int mfgpt_timer_set_periodic(struct clock_event_device *evt) |
916daba8 | 55 | { |
f02ffb19 | 56 | raw_spin_lock(&mfgpt_lock); |
916daba8 | 57 | |
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58 | outw(COMPARE, MFGPT0_CMP2); /* set comparator2 */ |
59 | outw(0, MFGPT0_CNT); /* set counter to 0 */ | |
60 | enable_mfgpt0_counter(); | |
61 | ||
f02ffb19 | 62 | raw_spin_unlock(&mfgpt_lock); |
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63 | return 0; |
64 | } | |
65 | ||
66 | static int mfgpt_timer_shutdown(struct clock_event_device *evt) | |
67 | { | |
68 | if (clockevent_state_periodic(evt) || clockevent_state_oneshot(evt)) { | |
69 | raw_spin_lock(&mfgpt_lock); | |
70 | disable_mfgpt0_counter(); | |
71 | raw_spin_unlock(&mfgpt_lock); | |
72 | } | |
73 | ||
74 | return 0; | |
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75 | } |
76 | ||
77 | static struct clock_event_device mfgpt_clockevent = { | |
78 | .name = "mfgpt", | |
79 | .features = CLOCK_EVT_FEAT_PERIODIC, | |
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80 | |
81 | /* The oneshot mode have very high deviation, don't use it! */ | |
82 | .set_state_shutdown = mfgpt_timer_shutdown, | |
83 | .set_state_periodic = mfgpt_timer_set_periodic, | |
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84 | .irq = CS5536_MFGPT_INTR, |
85 | }; | |
86 | ||
87 | static irqreturn_t timer_interrupt(int irq, void *dev_id) | |
88 | { | |
89 | u32 basehi; | |
90 | ||
91 | /* | |
92 | * get MFGPT base address | |
93 | * | |
94 | * NOTE: do not remove me, it's need for the value of mfgpt_base is | |
95 | * variable | |
96 | */ | |
97 | _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), &basehi, &mfgpt_base); | |
98 | ||
99 | /* ack */ | |
100 | outw(inw(MFGPT0_SETUP) | 0x4000, MFGPT0_SETUP); | |
101 | ||
102 | mfgpt_clockevent.event_handler(&mfgpt_clockevent); | |
103 | ||
104 | return IRQ_HANDLED; | |
105 | } | |
106 | ||
107 | static struct irqaction irq5 = { | |
108 | .handler = timer_interrupt, | |
8b5690f8 | 109 | .flags = IRQF_NOBALANCING | IRQF_TIMER, |
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110 | .name = "timer" |
111 | }; | |
112 | ||
113 | /* | |
114 | * Initialize the conversion factor and the min/max deltas of the clock event | |
115 | * structure and register the clock event source with the framework. | |
116 | */ | |
117 | void __init setup_mfgpt0_timer(void) | |
118 | { | |
119 | u32 basehi; | |
120 | struct clock_event_device *cd = &mfgpt_clockevent; | |
121 | unsigned int cpu = smp_processor_id(); | |
122 | ||
123 | cd->cpumask = cpumask_of(cpu); | |
124 | clockevent_set_clock(cd, MFGPT_TICK_RATE); | |
125 | cd->max_delta_ns = clockevent_delta2ns(0xffff, cd); | |
126 | cd->min_delta_ns = clockevent_delta2ns(0xf, cd); | |
127 | ||
128 | /* Enable MFGPT0 Comparator 2 Output to the Interrupt Mapper */ | |
129 | _wrmsr(DIVIL_MSR_REG(MFGPT_IRQ), 0, 0x100); | |
130 | ||
131 | /* Enable Interrupt Gate 5 */ | |
132 | _wrmsr(DIVIL_MSR_REG(PIC_ZSEL_LOW), 0, 0x50000); | |
133 | ||
134 | /* get MFGPT base address */ | |
135 | _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), &basehi, &mfgpt_base); | |
136 | ||
137 | clockevents_register_device(cd); | |
138 | ||
139 | setup_irq(CS5536_MFGPT_INTR, &irq5); | |
140 | } | |
141 | ||
142 | /* | |
143 | * Since the MFGPT overflows every tick, its not very useful | |
144 | * to just read by itself. So use jiffies to emulate a free | |
145 | * running counter: | |
146 | */ | |
a5a1d1c2 | 147 | static u64 mfgpt_read(struct clocksource *cs) |
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148 | { |
149 | unsigned long flags; | |
150 | int count; | |
151 | u32 jifs; | |
152 | static int old_count; | |
153 | static u32 old_jifs; | |
154 | ||
f02ffb19 | 155 | raw_spin_lock_irqsave(&mfgpt_lock, flags); |
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156 | /* |
157 | * Although our caller may have the read side of xtime_lock, | |
158 | * this is now a seqlock, and we are cheating in this routine | |
159 | * by having side effects on state that we cannot undo if | |
160 | * there is a collision on the seqlock and our caller has to | |
161 | * retry. (Namely, old_jifs and old_count.) So we must treat | |
162 | * jiffies as volatile despite the lock. We read jiffies | |
163 | * before latching the timer count to guarantee that although | |
164 | * the jiffies value might be older than the count (that is, | |
165 | * the counter may underflow between the last point where | |
166 | * jiffies was incremented and the point where we latch the | |
167 | * count), it cannot be newer. | |
168 | */ | |
169 | jifs = jiffies; | |
170 | /* read the count */ | |
171 | count = inw(MFGPT0_CNT); | |
172 | ||
173 | /* | |
174 | * It's possible for count to appear to go the wrong way for this | |
175 | * reason: | |
176 | * | |
177 | * The timer counter underflows, but we haven't handled the resulting | |
178 | * interrupt and incremented jiffies yet. | |
179 | * | |
180 | * Previous attempts to handle these cases intelligently were buggy, so | |
181 | * we just do the simple thing now. | |
182 | */ | |
183 | if (count < old_count && jifs == old_jifs) | |
184 | count = old_count; | |
185 | ||
186 | old_count = count; | |
187 | old_jifs = jifs; | |
188 | ||
f02ffb19 | 189 | raw_spin_unlock_irqrestore(&mfgpt_lock, flags); |
916daba8 | 190 | |
a5a1d1c2 | 191 | return (u64) (jifs * COMPARE) + count; |
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192 | } |
193 | ||
194 | static struct clocksource clocksource_mfgpt = { | |
195 | .name = "mfgpt", | |
196 | .rating = 120, /* Functional for real use, but not desired */ | |
197 | .read = mfgpt_read, | |
198 | .mask = CLOCKSOURCE_MASK(32), | |
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199 | }; |
200 | ||
201 | int __init init_mfgpt_clocksource(void) | |
202 | { | |
203 | if (num_possible_cpus() > 1) /* MFGPT does not scale! */ | |
204 | return 0; | |
205 | ||
75c4fd8c | 206 | return clocksource_register_hz(&clocksource_mfgpt, MFGPT_TICK_RATE); |
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207 | } |
208 | ||
209 | arch_initcall(init_mfgpt_clocksource); |