[linux-block.git] / arch / mips / lib / mips-atomic.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003 by Ralf Baechle
 * Copyright (C) 1996 by Paul M. Antoine
 * Copyright (C) 1999 Silicon Graphics
 * Copyright (C) 2000 MIPS Technologies, Inc.
 */
#include <asm/irqflags.h>
#include <asm/hazards.h>
#include <linux/compiler.h>
#include <linux/preempt.h>
#include <linux/export.h>
#include <linux/stringify.h>

#ifndef CONFIG_CPU_MIPSR2

/*
 * For cli() we have to insert nops to make sure that the new value
 * has actually arrived in the status register before the end of this
 * macro.
 * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs
 * no nops at all.
 */
/*
 * For TX49, operating only IE bit is not enough.
 *
 * If mfc0 $12 follows store and the mfc0 is last instruction of a
 * page and fetching the next instruction causes TLB miss, the result
 * of the mfc0 might wrongly contain EXL bit.
 *
 * ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008
 *
 * Workaround: mask EXL bit of the result or place a nop before mfc0.
 */
notrace void arch_local_irq_disable(void)
{
	preempt_disable();

	__asm__ __volatile__(
	"	.set	push						\n"
	"	.set	noat						\n"
	"	mfc0	$1,$12						\n"
	"	ori	$1,0x1f						\n"
	"	xori	$1,0x1f						\n"
	"	.set	noreorder					\n"
	"	mtc0	$1,$12						\n"
	"	" __stringify(__irq_disable_hazard) "			\n"
	"	.set	pop						\n"
	: /* no outputs */
	: /* no inputs */
	: "memory");

	preempt_enable();
}
EXPORT_SYMBOL(arch_local_irq_disable);


notrace unsigned long arch_local_irq_save(void)
{
	unsigned long flags;

	preempt_disable();

	__asm__ __volatile__(
	"	.set	push						\n"
	"	.set	reorder						\n"
	"	.set	noat						\n"
	"	mfc0	%[flags], $12					\n"
	"	ori	$1, %[flags], 0x1f				\n"
	"	xori	$1, 0x1f					\n"
	"	.set	noreorder					\n"
	"	mtc0	$1, $12						\n"
	"	" __stringify(__irq_disable_hazard) "			\n"
	"	.set	pop						\n"
	: [flags] "=r" (flags)
	: /* no inputs */
	: "memory");

	preempt_enable();

	return flags;
}
EXPORT_SYMBOL(arch_local_irq_save);

notrace void arch_local_irq_restore(unsigned long flags)
{
	unsigned long __tmp1;

	preempt_disable();

	__asm__ __volatile__(
	"	.set	push						\n"
	"	.set	noreorder					\n"
	"	.set	noat						\n"
	"	mfc0	$1, $12						\n"
	"	andi	%[flags], 1					\n"
	"	ori	$1, 0x1f					\n"
	"	xori	$1, 0x1f					\n"
	"	or	%[flags], $1					\n"
	"	mtc0	%[flags], $12					\n"
	"	" __stringify(__irq_disable_hazard) "			\n"
	"	.set	pop						\n"
	: [flags] "=r" (__tmp1)
	: "0" (flags)
	: "memory");

	preempt_enable();
}
EXPORT_SYMBOL(arch_local_irq_restore);


notrace void __arch_local_irq_restore(unsigned long flags)
{
	unsigned long __tmp1;

	preempt_disable();

	__asm__ __volatile__(
	"	.set	push						\n"
	"	.set	noreorder					\n"
	"	.set	noat						\n"
	"	mfc0	$1, $12						\n"
	"	andi	%[flags], 1					\n"
	"	ori	$1, 0x1f					\n"
	"	xori	$1, 0x1f					\n"
	"	or	%[flags], $1					\n"
	"	mtc0	%[flags], $12					\n"
	"	" __stringify(__irq_disable_hazard) "			\n"
	"	.set	pop						\n"
	: [flags] "=r" (__tmp1)
	: "0" (flags)
	: "memory");

	preempt_enable();
}
EXPORT_SYMBOL(__arch_local_irq_restore);

#endif /* !CONFIG_CPU_MIPSR2 */
Commit	Line	Data
e97c5b60 JQ	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 1994, 95, 96, 97, 98, 99, 2003 by Ralf Baechle
	7	* Copyright (C) 1996 by Paul M. Antoine
	8	* Copyright (C) 1999 Silicon Graphics
	9	* Copyright (C) 2000 MIPS Technologies, Inc.
	10	*/
	11	#include <asm/irqflags.h>
	12	#include <asm/hazards.h>
	13	#include <linux/compiler.h>
	14	#include <linux/preempt.h>
	15	#include <linux/export.h>
02b849f7	16	#include <linux/stringify.h>
e97c5b60	17
b633648c	18	#ifndef CONFIG_CPU_MIPSR2
e97c5b60 JQ	19
	20	/*
	21	* For cli() we have to insert nops to make sure that the new value
	22	* has actually arrived in the status register before the end of this
	23	* macro.
	24	* R4000/R4400 need three nops, the R4600 two nops and the R10000 needs
	25	* no nops at all.
	26	*/
	27	/*
	28	* For TX49, operating only IE bit is not enough.
	29	*
	30	* If mfc0 $12 follows store and the mfc0 is last instruction of a
	31	* page and fetching the next instruction causes TLB miss, the result
	32	* of the mfc0 might wrongly contain EXL bit.
	33	*
	34	* ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008
	35	*
	36	* Workaround: mask EXL bit of the result or place a nop before mfc0.
	37	*/
02b849f7 RB	38	notrace void arch_local_irq_disable(void)
	39	{
	40	preempt_disable();
	41
	42	__asm__ __volatile__(
e97c5b60 JQ	43	" .set push \n"
e97c5b60 JQ	44	" .set noat \n"
e97c5b60 JQ	45	" mfc0 $1,$12 \n"
	46	" ori $1,0x1f \n"
	47	" xori $1,0x1f \n"
	48	" .set noreorder \n"
	49	" mtc0 $1,$12 \n"
02b849f7	50	" " __stringify(__irq_disable_hazard) " \n"
e97c5b60	51	" .set pop \n"
02b849f7 RB	52	: /* no outputs */
	53	: /* no inputs */
	54	: "memory");
e97c5b60	55
e97c5b60 JQ	56	preempt_enable();
	57	}
	58	EXPORT_SYMBOL(arch_local_irq_disable);
	59
	60
02b849f7 RB	61	notrace unsigned long arch_local_irq_save(void)
	62	{
	63	unsigned long flags;
	64
	65	preempt_disable();
	66
	67	__asm__ __volatile__(
e97c5b60 JQ	68	" .set push \n"
	69	" .set reorder \n"
	70	" .set noat \n"
02b849f7 RB	71	" mfc0 %[flags], $12 \n"
02b849f7 RB	72	" ori $1, %[flags], 0x1f \n"
e97c5b60 JQ	73	" xori $1, 0x1f \n"
	74	" .set noreorder \n"
	75	" mtc0 $1, $12 \n"
02b849f7	76	" " __stringify(__irq_disable_hazard) " \n"
e97c5b60	77	" .set pop \n"
02b849f7 RB	78	: [flags] "=r" (flags)
	79	: /* no inputs */
	80	: "memory");
e97c5b60	81
e97c5b60	82	preempt_enable();
02b849f7	83
e97c5b60 JQ	84	return flags;
	85	}
	86	EXPORT_SYMBOL(arch_local_irq_save);
	87
02b849f7 RB	88	notrace void arch_local_irq_restore(unsigned long flags)
	89	{
	90	unsigned long __tmp1;
	91
02b849f7	92	preempt_disable();
e97c5b60	93
02b849f7	94	__asm__ __volatile__(
e97c5b60 JQ	95	" .set push \n"
	96	" .set noreorder \n"
	97	" .set noat \n"
e97c5b60	98	" mfc0 $1, $12 \n"
02b849f7	99	" andi %[flags], 1 \n"
e97c5b60 JQ	100	" ori $1, 0x1f \n"
e97c5b60 JQ	101	" xori $1, 0x1f \n"
02b849f7 RB	102	" or %[flags], $1 \n"
02b849f7 RB	103	" mtc0 %[flags], $12 \n"
02b849f7	104	" " __stringify(__irq_disable_hazard) " \n"
e97c5b60	105	" .set pop \n"
02b849f7 RB	106	: [flags] "=r" (__tmp1)
	107	: "0" (flags)
	108	: "memory");
e97c5b60	109
e97c5b60 JQ	110	preempt_enable();
	111	}
	112	EXPORT_SYMBOL(arch_local_irq_restore);
	113
	114
f93a1a00	115	notrace void __arch_local_irq_restore(unsigned long flags)
e97c5b60 JQ	116	{
	117	unsigned long __tmp1;
	118
	119	preempt_disable();
02b849f7	120
e97c5b60	121	__asm__ __volatile__(
02b849f7 RB	122	" .set push \n"
	123	" .set noreorder \n"
	124	" .set noat \n"
02b849f7 RB	125	" mfc0 $1, $12 \n"
	126	" andi %[flags], 1 \n"
	127	" ori $1, 0x1f \n"
	128	" xori $1, 0x1f \n"
	129	" or %[flags], $1 \n"
	130	" mtc0 %[flags], $12 \n"
02b849f7 RB	131	" " __stringify(__irq_disable_hazard) " \n"
	132	" .set pop \n"
	133	: [flags] "=r" (__tmp1)
	134	: "0" (flags)
	135	: "memory");
	136
e97c5b60 JQ	137	preempt_enable();
	138	}
	139	EXPORT_SYMBOL(__arch_local_irq_restore);
	140
b633648c	141	#endif /* !CONFIG_CPU_MIPSR2 */