mm: remove include/linux/bootmem.h
[linux-2.6-block.git] / arch / mips / lantiq / prom.c
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1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
97b92108 6 * Copyright (C) 2010 John Crispin <john@phrozen.org>
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7 */
8
4af92e7a 9#include <linux/export.h>
171bb2f1 10#include <linux/clk.h>
57c8a661 11#include <linux/memblock.h>
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12#include <linux/of_fdt.h>
13
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14#include <asm/bootinfo.h>
15#include <asm/time.h>
089a49b6 16#include <asm/prom.h>
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17
18#include <lantiq.h>
19
20#include "prom.h"
21#include "clk.h"
22
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23/* access to the ebu needs to be locked between different drivers */
24DEFINE_SPINLOCK(ebu_lock);
25EXPORT_SYMBOL_GPL(ebu_lock);
171bb2f1 26
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27/*
28 * This is needed by the VPE loader code, just set it to 0 and assume
29 * that the firmware hardcodes this value to something useful.
30 */
31unsigned long physical_memsize = 0L;
32
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33/*
34 * this struct is filled by the soc specific detection code and holds
35 * information about the specific soc type, revision and name
36 */
37static struct ltq_soc_info soc_info;
171bb2f1 38
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39const char *get_system_type(void)
40{
41 return soc_info.sys_type;
42}
43
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44int ltq_soc_type(void)
45{
46 return soc_info.type;
47}
48
aa816c1b 49void __init prom_free_prom_memory(void)
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50{
51}
52
53static void __init prom_init_cmdline(void)
54{
55 int argc = fw_arg0;
56 char **argv = (char **) KSEG1ADDR(fw_arg1);
57 int i;
58
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59 arcs_cmdline[0] = '\0';
60
171bb2f1 61 for (i = 0; i < argc; i++) {
730fa039 62 char *p = (char *) KSEG1ADDR(argv[i]);
171bb2f1 63
730fa039 64 if (CPHYSADDR(p) && *p) {
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65 strlcat(arcs_cmdline, p, sizeof(arcs_cmdline));
66 strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline));
67 }
68 }
69}
70
a0392222 71void __init plat_mem_setup(void)
171bb2f1 72{
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73 void *dtb;
74
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75 ioport_resource.start = IOPORT_RESOURCE_START;
76 ioport_resource.end = IOPORT_RESOURCE_END;
77 iomem_resource.start = IOMEM_RESOURCE_START;
78 iomem_resource.end = IOMEM_RESOURCE_END;
79
80 set_io_port_base((unsigned long) KSEG1);
81
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82 if (fw_passed_dtb) /* UHI interface */
83 dtb = (void *)fw_passed_dtb;
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84 else if (__dtb_start != __dtb_end)
85 dtb = (void *)__dtb_start;
86 else
87 panic("no dtb found");
88
a0392222 89 /*
84f47cf4 90 * Load the devicetree. This causes the chosen node to be
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91 * parsed resulting in our memory appearing
92 */
84f47cf4 93 __dt_setup_arch(dtb);
a0392222 94}
171bb2f1 95
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96void __init device_tree_init(void)
97{
10fbdaab 98 unflatten_and_copy_device_tree();
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99}
100
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101void __init prom_init(void)
102{
103 /* call the soc specific detetcion code and get it to fill soc_info */
171bb2f1 104 ltq_soc_detect(&soc_info);
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105 snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev %s",
106 soc_info.name, soc_info.rev_type);
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107 soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0';
108 pr_info("SoC: %s\n", soc_info.sys_type);
109 prom_init_cmdline();
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110
111#if defined(CONFIG_MIPS_MT_SMP)
112 if (register_vsmp_smp_ops())
113 panic("failed to register_vsmp_smp_ops()");
114#endif
171bb2f1 115}