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MIPS: KVM: Expose MSA registers
[linux-2.6-block.git] / arch / mips / kvm / mips.c
CommitLineData
669e846e
SL		 1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * KVM/MIPS: MIPS specific KVM APIs
7 *
8 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
9 * Authors: Sanjay Lal <sanjayl@kymasys.com>
d116e812 10 */
669e846e
SL		 11
12#include <linux/errno.h>
13#include <linux/err.h>
98e91b84 14#include <linux/kdebug.h>
669e846e
SL		 15#include <linux/module.h>
16#include <linux/vmalloc.h>
17#include <linux/fs.h>
18#include <linux/bootmem.h>
f798217d 19#include <asm/fpu.h>
669e846e
SL		 20#include <asm/page.h>
21#include <asm/cacheflush.h>
22#include <asm/mmu_context.h>
c4c6f2ca 23#include <asm/pgtable.h>
669e846e
SL		 24
25#include <linux/kvm_host.h>
26
d7d5b05f
DCZ		 27#include "interrupt.h"
28#include "commpage.h"
669e846e
SL		 29
30#define CREATE_TRACE_POINTS
31#include "trace.h"
32
33#ifndef VECTORSPACING
34#define VECTORSPACING 0x100 /* for EI/VI mode */
35#endif
36
d116e812 37#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x)
669e846e 38struct kvm_stats_debugfs_item debugfs_entries[] = {
d116e812
DCZ		 39 { "wait", VCPU_STAT(wait_exits), KVM_STAT_VCPU },
40 { "cache", VCPU_STAT(cache_exits), KVM_STAT_VCPU },
41 { "signal", VCPU_STAT(signal_exits), KVM_STAT_VCPU },
42 { "interrupt", VCPU_STAT(int_exits), KVM_STAT_VCPU },
43 { "cop_unsuable", VCPU_STAT(cop_unusable_exits), KVM_STAT_VCPU },
44 { "tlbmod", VCPU_STAT(tlbmod_exits), KVM_STAT_VCPU },
45 { "tlbmiss_ld", VCPU_STAT(tlbmiss_ld_exits), KVM_STAT_VCPU },
46 { "tlbmiss_st", VCPU_STAT(tlbmiss_st_exits), KVM_STAT_VCPU },
47 { "addrerr_st", VCPU_STAT(addrerr_st_exits), KVM_STAT_VCPU },
48 { "addrerr_ld", VCPU_STAT(addrerr_ld_exits), KVM_STAT_VCPU },
49 { "syscall", VCPU_STAT(syscall_exits), KVM_STAT_VCPU },
50 { "resvd_inst", VCPU_STAT(resvd_inst_exits), KVM_STAT_VCPU },
51 { "break_inst", VCPU_STAT(break_inst_exits), KVM_STAT_VCPU },
0a560427 52 { "trap_inst", VCPU_STAT(trap_inst_exits), KVM_STAT_VCPU },
c2537ed9 53 { "msa_fpe", VCPU_STAT(msa_fpe_exits), KVM_STAT_VCPU },
1c0cd66a 54 { "fpe", VCPU_STAT(fpe_exits), KVM_STAT_VCPU },
c2537ed9 55 { "msa_disabled", VCPU_STAT(msa_disabled_exits), KVM_STAT_VCPU },
d116e812 56 { "flush_dcache", VCPU_STAT(flush_dcache_exits), KVM_STAT_VCPU },
f7819512 57 { "halt_successful_poll", VCPU_STAT(halt_successful_poll), KVM_STAT_VCPU },
d116e812 58 { "halt_wakeup", VCPU_STAT(halt_wakeup), KVM_STAT_VCPU },
669e846e
SL		 59 {NULL}
60};
61
62static int kvm_mips_reset_vcpu(struct kvm_vcpu *vcpu)
63{
64 int i;
d116e812 65
669e846e
SL		 66 for_each_possible_cpu(i) {
67 vcpu->arch.guest_kernel_asid[i] = 0;
68 vcpu->arch.guest_user_asid[i] = 0;
69 }
d116e812 70
669e846e
SL		 71 return 0;
72}
73
d116e812
DCZ		 74/*
75 * XXXKYMA: We are simulatoring a processor that has the WII bit set in
76 * Config7, so we are "runnable" if interrupts are pending
669e846e
SL		 77 */
78int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
79{
80 return !!(vcpu->arch.pending_exceptions);
81}
82
83int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
84{
85 return 1;
86}
87
13a34e06 88int kvm_arch_hardware_enable(void)
669e846e
SL		 89{
90 return 0;
91}
92
669e846e
SL		 93int kvm_arch_hardware_setup(void)
94{
95 return 0;
96}
97
669e846e
SL		 98void kvm_arch_check_processor_compat(void *rtn)
99{
d98403a5 100 *(int *)rtn = 0;
669e846e
SL		 101}
102
103static void kvm_mips_init_tlbs(struct kvm *kvm)
104{
105 unsigned long wired;
106
d116e812
DCZ		 107 /*
108 * Add a wired entry to the TLB, it is used to map the commpage to
109 * the Guest kernel
110 */
669e846e
SL		 111 wired = read_c0_wired();
112 write_c0_wired(wired + 1);
113 mtc0_tlbw_hazard();
114 kvm->arch.commpage_tlb = wired;
115
116 kvm_debug("[%d] commpage TLB: %d\n", smp_processor_id(),
117 kvm->arch.commpage_tlb);
118}
119
120static void kvm_mips_init_vm_percpu(void *arg)
121{
122 struct kvm *kvm = (struct kvm *)arg;
123
124 kvm_mips_init_tlbs(kvm);
125 kvm_mips_callbacks->vm_init(kvm);
126
127}
128
129int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
130{
131 if (atomic_inc_return(&kvm_mips_instance) == 1) {
6e95bfd2
JH		 132 kvm_debug("%s: 1st KVM instance, setup host TLB parameters\n",
133 __func__);
669e846e
SL		 134 on_each_cpu(kvm_mips_init_vm_percpu, kvm, 1);
135 }
136
669e846e
SL		 137 return 0;
138}
139
140void kvm_mips_free_vcpus(struct kvm *kvm)
141{
142 unsigned int i;
143 struct kvm_vcpu *vcpu;
144
145 /* Put the pages we reserved for the guest pmap */
146 for (i = 0; i < kvm->arch.guest_pmap_npages; i++) {
147 if (kvm->arch.guest_pmap[i] != KVM_INVALID_PAGE)
148 kvm_mips_release_pfn_clean(kvm->arch.guest_pmap[i]);
149 }
c6c0a663 150 kfree(kvm->arch.guest_pmap);
669e846e
SL		 151
152 kvm_for_each_vcpu(i, vcpu, kvm) {
153 kvm_arch_vcpu_free(vcpu);
154 }
155
156 mutex_lock(&kvm->lock);
157
158 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
159 kvm->vcpus[i] = NULL;
160
161 atomic_set(&kvm->online_vcpus, 0);
162
163 mutex_unlock(&kvm->lock);
164}
165
669e846e
SL		 166static void kvm_mips_uninit_tlbs(void *arg)
167{
168 /* Restore wired count */
169 write_c0_wired(0);
170 mtc0_tlbw_hazard();
171 /* Clear out all the TLBs */
172 kvm_local_flush_tlb_all();
173}
174
175void kvm_arch_destroy_vm(struct kvm *kvm)
176{
177 kvm_mips_free_vcpus(kvm);
178
179 /* If this is the last instance, restore wired count */
180 if (atomic_dec_return(&kvm_mips_instance) == 0) {
6e95bfd2
JH		 181 kvm_debug("%s: last KVM instance, restoring TLB parameters\n",
182 __func__);
669e846e
SL		 183 on_each_cpu(kvm_mips_uninit_tlbs, NULL, 1);
184 }
185}
186
d116e812
DCZ		 187long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl,
188 unsigned long arg)
669e846e 189{
ed829857 190 return -ENOIOCTLCMD;
669e846e
SL		 191}
192
5587027c
AK		 193int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
194 unsigned long npages)
669e846e
SL		 195{
196 return 0;
197}
198
199int kvm_arch_prepare_memory_region(struct kvm *kvm,
d116e812
DCZ		 200 struct kvm_memory_slot *memslot,
201 struct kvm_userspace_memory_region *mem,
202 enum kvm_mr_change change)
669e846e
SL		 203{
204 return 0;
205}
206
207void kvm_arch_commit_memory_region(struct kvm *kvm,
d116e812
DCZ		 208 struct kvm_userspace_memory_region *mem,
209 const struct kvm_memory_slot *old,
210 enum kvm_mr_change change)
669e846e
SL		 211{
212 unsigned long npages = 0;
d98403a5 213 int i;
669e846e
SL		 214
215 kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n",
216 __func__, kvm, mem->slot, mem->guest_phys_addr,
217 mem->memory_size, mem->userspace_addr);
218
219 /* Setup Guest PMAP table */
220 if (!kvm->arch.guest_pmap) {
221 if (mem->slot == 0)
222 npages = mem->memory_size >> PAGE_SHIFT;
223
224 if (npages) {
225 kvm->arch.guest_pmap_npages = npages;
226 kvm->arch.guest_pmap =
227 kzalloc(npages * sizeof(unsigned long), GFP_KERNEL);
228
229 if (!kvm->arch.guest_pmap) {
230 kvm_err("Failed to allocate guest PMAP");
d98403a5 231 return;
669e846e
SL		 232 }
233
6e95bfd2
JH		 234 kvm_debug("Allocated space for Guest PMAP Table (%ld pages) @ %p\n",
235 npages, kvm->arch.guest_pmap);
669e846e
SL		 236
237 /* Now setup the page table */
d116e812 238 for (i = 0; i < npages; i++)
669e846e 239 kvm->arch.guest_pmap[i] = KVM_INVALID_PAGE;
669e846e
SL		 240 }
241 }
669e846e
SL		 242}
243
669e846e
SL		 244struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id)
245{
669e846e
SL		 246 int err, size, offset;
247 void *gebase;
248 int i;
249
250 struct kvm_vcpu *vcpu = kzalloc(sizeof(struct kvm_vcpu), GFP_KERNEL);
251
252 if (!vcpu) {
253 err = -ENOMEM;
254 goto out;
255 }
256
257 err = kvm_vcpu_init(vcpu, kvm, id);
258
259 if (err)
260 goto out_free_cpu;
261
6e95bfd2 262 kvm_debug("kvm @ %p: create cpu %d at %p\n", kvm, id, vcpu);
669e846e 263
d116e812
DCZ		 264 /*
265 * Allocate space for host mode exception handlers that handle
669e846e
SL		 266 * guest mode exits
267 */
d116e812 268 if (cpu_has_veic || cpu_has_vint)
669e846e 269 size = 0x200 + VECTORSPACING * 64;
d116e812 270 else
7006e2df 271 size = 0x4000;
669e846e
SL		 272
273 /* Save Linux EBASE */
274 vcpu->arch.host_ebase = (void *)read_c0_ebase();
275
276 gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL);
277
278 if (!gebase) {
279 err = -ENOMEM;
280 goto out_free_cpu;
281 }
6e95bfd2
JH		 282 kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n",
283 ALIGN(size, PAGE_SIZE), gebase);
669e846e
SL		 284
285 /* Save new ebase */
286 vcpu->arch.guest_ebase = gebase;
287
288 /* Copy L1 Guest Exception handler to correct offset */
289
290 /* TLB Refill, EXL = 0 */
291 memcpy(gebase, mips32_exception,
292 mips32_exceptionEnd - mips32_exception);
293
294 /* General Exception Entry point */
295 memcpy(gebase + 0x180, mips32_exception,
296 mips32_exceptionEnd - mips32_exception);
297
298 /* For vectored interrupts poke the exception code @ all offsets 0-7 */
299 for (i = 0; i < 8; i++) {
300 kvm_debug("L1 Vectored handler @ %p\n",
301 gebase + 0x200 + (i * VECTORSPACING));
302 memcpy(gebase + 0x200 + (i * VECTORSPACING), mips32_exception,
303 mips32_exceptionEnd - mips32_exception);
304 }
305
306 /* General handler, relocate to unmapped space for sanity's sake */
307 offset = 0x2000;
6e95bfd2
JH		 308 kvm_debug("Installing KVM Exception handlers @ %p, %#x bytes\n",
309 gebase + offset,
310 mips32_GuestExceptionEnd - mips32_GuestException);
669e846e
SL		 311
312 memcpy(gebase + offset, mips32_GuestException,
313 mips32_GuestExceptionEnd - mips32_GuestException);
314
315 /* Invalidate the icache for these ranges */
facaaec1
JH		 316 local_flush_icache_range((unsigned long)gebase,
317 (unsigned long)gebase + ALIGN(size, PAGE_SIZE));
669e846e 318
d116e812
DCZ		 319 /*
320 * Allocate comm page for guest kernel, a TLB will be reserved for
321 * mapping GVA @ 0xFFFF8000 to this page
322 */
669e846e
SL		 323 vcpu->arch.kseg0_commpage = kzalloc(PAGE_SIZE << 1, GFP_KERNEL);
324
325 if (!vcpu->arch.kseg0_commpage) {
326 err = -ENOMEM;
327 goto out_free_gebase;
328 }
329
6e95bfd2 330 kvm_debug("Allocated COMM page @ %p\n", vcpu->arch.kseg0_commpage);
669e846e
SL		 331 kvm_mips_commpage_init(vcpu);
332
333 /* Init */
334 vcpu->arch.last_sched_cpu = -1;
335
336 /* Start off the timer */
e30492bb 337 kvm_mips_init_count(vcpu);
669e846e
SL		 338
339 return vcpu;
340
341out_free_gebase:
342 kfree(gebase);
343
344out_free_cpu:
345 kfree(vcpu);
346
347out:
348 return ERR_PTR(err);
349}
350
351void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
352{
353 hrtimer_cancel(&vcpu->arch.comparecount_timer);
354
355 kvm_vcpu_uninit(vcpu);
356
357 kvm_mips_dump_stats(vcpu);
358
c6c0a663
JH		 359 kfree(vcpu->arch.guest_ebase);
360 kfree(vcpu->arch.kseg0_commpage);
8c9eb041 361 kfree(vcpu);
669e846e
SL		 362}
363
364void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
365{
366 kvm_arch_vcpu_free(vcpu);
367}
368
d116e812
DCZ		 369int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
370 struct kvm_guest_debug *dbg)
669e846e 371{
ed829857 372 return -ENOIOCTLCMD;
669e846e
SL		 373}
374
375int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
376{
377 int r = 0;
378 sigset_t sigsaved;
379
380 if (vcpu->sigset_active)
381 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
382
383 if (vcpu->mmio_needed) {
384 if (!vcpu->mmio_is_write)
385 kvm_mips_complete_mmio_load(vcpu, run);
386 vcpu->mmio_needed = 0;
387 }
388
f798217d
JH		 389 lose_fpu(1);
390
044f0f03 391 local_irq_disable();
669e846e
SL		 392 /* Check if we have any exceptions/interrupts pending */
393 kvm_mips_deliver_interrupts(vcpu,
394 kvm_read_c0_guest_cause(vcpu->arch.cop0));
395
669e846e
SL		 396 kvm_guest_enter();
397
c4c6f2ca
JH		 398 /* Disable hardware page table walking while in guest */
399 htw_stop();
400
669e846e
SL		 401 r = __kvm_mips_vcpu_run(run, vcpu);
402
c4c6f2ca
JH		 403 /* Re-enable HTW before enabling interrupts */
404 htw_start();
405
669e846e
SL		 406 kvm_guest_exit();
407 local_irq_enable();
408
409 if (vcpu->sigset_active)
410 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
411
412 return r;
413}
414
d116e812
DCZ		 415int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
416 struct kvm_mips_interrupt *irq)
669e846e
SL		 417{
418 int intr = (int)irq->irq;
419 struct kvm_vcpu *dvcpu = NULL;
420
421 if (intr == 3 || intr == -3 || intr == 4 || intr == -4)
422 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu,
423 (int)intr);
424
425 if (irq->cpu == -1)
426 dvcpu = vcpu;
427 else
428 dvcpu = vcpu->kvm->vcpus[irq->cpu];
429
430 if (intr == 2 || intr == 3 || intr == 4) {
431 kvm_mips_callbacks->queue_io_int(dvcpu, irq);
432
433 } else if (intr == -2 || intr == -3 || intr == -4) {
434 kvm_mips_callbacks->dequeue_io_int(dvcpu, irq);
435 } else {
436 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__,
437 irq->cpu, irq->irq);
438 return -EINVAL;
439 }
440
441 dvcpu->arch.wait = 0;
442
d116e812 443 if (waitqueue_active(&dvcpu->wq))
669e846e 444 wake_up_interruptible(&dvcpu->wq);
669e846e
SL		 445
446 return 0;
447}
448
d116e812
DCZ		 449int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
450 struct kvm_mp_state *mp_state)
669e846e 451{
ed829857 452 return -ENOIOCTLCMD;
669e846e
SL		 453}
454
d116e812
DCZ		 455int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
456 struct kvm_mp_state *mp_state)
669e846e 457{
ed829857 458 return -ENOIOCTLCMD;
669e846e
SL		 459}
460
4c73fb2b
DD		 461static u64 kvm_mips_get_one_regs[] = {
462 KVM_REG_MIPS_R0,
463 KVM_REG_MIPS_R1,
464 KVM_REG_MIPS_R2,
465 KVM_REG_MIPS_R3,
466 KVM_REG_MIPS_R4,
467 KVM_REG_MIPS_R5,
468 KVM_REG_MIPS_R6,
469 KVM_REG_MIPS_R7,
470 KVM_REG_MIPS_R8,
471 KVM_REG_MIPS_R9,
472 KVM_REG_MIPS_R10,
473 KVM_REG_MIPS_R11,
474 KVM_REG_MIPS_R12,
475 KVM_REG_MIPS_R13,
476 KVM_REG_MIPS_R14,
477 KVM_REG_MIPS_R15,
478 KVM_REG_MIPS_R16,
479 KVM_REG_MIPS_R17,
480 KVM_REG_MIPS_R18,
481 KVM_REG_MIPS_R19,
482 KVM_REG_MIPS_R20,
483 KVM_REG_MIPS_R21,
484 KVM_REG_MIPS_R22,
485 KVM_REG_MIPS_R23,
486 KVM_REG_MIPS_R24,
487 KVM_REG_MIPS_R25,
488 KVM_REG_MIPS_R26,
489 KVM_REG_MIPS_R27,
490 KVM_REG_MIPS_R28,
491 KVM_REG_MIPS_R29,
492 KVM_REG_MIPS_R30,
493 KVM_REG_MIPS_R31,
494
495 KVM_REG_MIPS_HI,
496 KVM_REG_MIPS_LO,
497 KVM_REG_MIPS_PC,
498
499 KVM_REG_MIPS_CP0_INDEX,
500 KVM_REG_MIPS_CP0_CONTEXT,
7767b7d2 501 KVM_REG_MIPS_CP0_USERLOCAL,
4c73fb2b
DD		 502 KVM_REG_MIPS_CP0_PAGEMASK,
503 KVM_REG_MIPS_CP0_WIRED,
16fd5c1d 504 KVM_REG_MIPS_CP0_HWRENA,
4c73fb2b 505 KVM_REG_MIPS_CP0_BADVADDR,
f8be02da 506 KVM_REG_MIPS_CP0_COUNT,
4c73fb2b 507 KVM_REG_MIPS_CP0_ENTRYHI,
f8be02da 508 KVM_REG_MIPS_CP0_COMPARE,
4c73fb2b
DD		 509 KVM_REG_MIPS_CP0_STATUS,
510 KVM_REG_MIPS_CP0_CAUSE,
fb6df0cd 511 KVM_REG_MIPS_CP0_EPC,
1068eaaf 512 KVM_REG_MIPS_CP0_PRID,
4c73fb2b
DD		 513 KVM_REG_MIPS_CP0_CONFIG,
514 KVM_REG_MIPS_CP0_CONFIG1,
515 KVM_REG_MIPS_CP0_CONFIG2,
516 KVM_REG_MIPS_CP0_CONFIG3,
c771607a
JH		 517 KVM_REG_MIPS_CP0_CONFIG4,
518 KVM_REG_MIPS_CP0_CONFIG5,
4c73fb2b 519 KVM_REG_MIPS_CP0_CONFIG7,
f8239342
JH		 520 KVM_REG_MIPS_CP0_ERROREPC,
521
522 KVM_REG_MIPS_COUNT_CTL,
523 KVM_REG_MIPS_COUNT_RESUME,
f74a8e22 524 KVM_REG_MIPS_COUNT_HZ,
4c73fb2b
DD		 525};
526
527static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
528 const struct kvm_one_reg *reg)
529{
4c73fb2b 530 struct mips_coproc *cop0 = vcpu->arch.cop0;
379245cd 531 struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
f8be02da 532 int ret;
4c73fb2b 533 s64 v;
ab86bd60 534 s64 vs[2];
379245cd 535 unsigned int idx;
4c73fb2b
DD		 536
537 switch (reg->id) {
379245cd 538 /* General purpose registers */
4c73fb2b
DD		 539 case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31:
540 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0];
541 break;
542 case KVM_REG_MIPS_HI:
543 v = (long)vcpu->arch.hi;
544 break;
545 case KVM_REG_MIPS_LO:
546 v = (long)vcpu->arch.lo;
547 break;
548 case KVM_REG_MIPS_PC:
549 v = (long)vcpu->arch.pc;
550 break;
551
379245cd
JH		 552 /* Floating point registers */
553 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
554 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
555 return -EINVAL;
556 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
557 /* Odd singles in top of even double when FR=0 */
558 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
559 v = get_fpr32(&fpu->fpr[idx], 0);
560 else
561 v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1);
562 break;
563 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
564 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
565 return -EINVAL;
566 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
567 /* Can't access odd doubles in FR=0 mode */
568 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
569 return -EINVAL;
570 v = get_fpr64(&fpu->fpr[idx], 0);
571 break;
572 case KVM_REG_MIPS_FCR_IR:
573 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
574 return -EINVAL;
575 v = boot_cpu_data.fpu_id;
576 break;
577 case KVM_REG_MIPS_FCR_CSR:
578 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
579 return -EINVAL;
580 v = fpu->fcr31;
581 break;
582
ab86bd60
JH		 583 /* MIPS SIMD Architecture (MSA) registers */
584 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
585 if (!kvm_mips_guest_has_msa(&vcpu->arch))
586 return -EINVAL;
587 /* Can't access MSA registers in FR=0 mode */
588 if (!(kvm_read_c0_guest_status(cop0) & ST0_FR))
589 return -EINVAL;
590 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
591#ifdef CONFIG_CPU_LITTLE_ENDIAN
592 /* least significant byte first */
593 vs[0] = get_fpr64(&fpu->fpr[idx], 0);
594 vs[1] = get_fpr64(&fpu->fpr[idx], 1);
595#else
596 /* most significant byte first */
597 vs[0] = get_fpr64(&fpu->fpr[idx], 1);
598 vs[1] = get_fpr64(&fpu->fpr[idx], 0);
599#endif
600 break;
601 case KVM_REG_MIPS_MSA_IR:
602 if (!kvm_mips_guest_has_msa(&vcpu->arch))
603 return -EINVAL;
604 v = boot_cpu_data.msa_id;
605 break;
606 case KVM_REG_MIPS_MSA_CSR:
607 if (!kvm_mips_guest_has_msa(&vcpu->arch))
608 return -EINVAL;
609 v = fpu->msacsr;
610 break;
611
379245cd 612 /* Co-processor 0 registers */
4c73fb2b
DD		 613 case KVM_REG_MIPS_CP0_INDEX:
614 v = (long)kvm_read_c0_guest_index(cop0);
615 break;
616 case KVM_REG_MIPS_CP0_CONTEXT:
617 v = (long)kvm_read_c0_guest_context(cop0);
618 break;
7767b7d2
JH		 619 case KVM_REG_MIPS_CP0_USERLOCAL:
620 v = (long)kvm_read_c0_guest_userlocal(cop0);
621 break;
4c73fb2b
DD		 622 case KVM_REG_MIPS_CP0_PAGEMASK:
623 v = (long)kvm_read_c0_guest_pagemask(cop0);
624 break;
625 case KVM_REG_MIPS_CP0_WIRED:
626 v = (long)kvm_read_c0_guest_wired(cop0);
627 break;
16fd5c1d
JH		 628 case KVM_REG_MIPS_CP0_HWRENA:
629 v = (long)kvm_read_c0_guest_hwrena(cop0);
630 break;
4c73fb2b
DD		 631 case KVM_REG_MIPS_CP0_BADVADDR:
632 v = (long)kvm_read_c0_guest_badvaddr(cop0);
633 break;
634 case KVM_REG_MIPS_CP0_ENTRYHI:
635 v = (long)kvm_read_c0_guest_entryhi(cop0);
636 break;
f8be02da
JH		 637 case KVM_REG_MIPS_CP0_COMPARE:
638 v = (long)kvm_read_c0_guest_compare(cop0);
639 break;
4c73fb2b
DD		 640 case KVM_REG_MIPS_CP0_STATUS:
641 v = (long)kvm_read_c0_guest_status(cop0);
642 break;
643 case KVM_REG_MIPS_CP0_CAUSE:
644 v = (long)kvm_read_c0_guest_cause(cop0);
645 break;
fb6df0cd
JH		 646 case KVM_REG_MIPS_CP0_EPC:
647 v = (long)kvm_read_c0_guest_epc(cop0);
648 break;
1068eaaf
JH		 649 case KVM_REG_MIPS_CP0_PRID:
650 v = (long)kvm_read_c0_guest_prid(cop0);
651 break;
4c73fb2b
DD		 652 case KVM_REG_MIPS_CP0_CONFIG:
653 v = (long)kvm_read_c0_guest_config(cop0);
654 break;
655 case KVM_REG_MIPS_CP0_CONFIG1:
656 v = (long)kvm_read_c0_guest_config1(cop0);
657 break;
658 case KVM_REG_MIPS_CP0_CONFIG2:
659 v = (long)kvm_read_c0_guest_config2(cop0);
660 break;
661 case KVM_REG_MIPS_CP0_CONFIG3:
662 v = (long)kvm_read_c0_guest_config3(cop0);
663 break;
c771607a
JH		 664 case KVM_REG_MIPS_CP0_CONFIG4:
665 v = (long)kvm_read_c0_guest_config4(cop0);
666 break;
667 case KVM_REG_MIPS_CP0_CONFIG5:
668 v = (long)kvm_read_c0_guest_config5(cop0);
669 break;
4c73fb2b
DD		 670 case KVM_REG_MIPS_CP0_CONFIG7:
671 v = (long)kvm_read_c0_guest_config7(cop0);
672 break;
e93d4c15
JH		 673 case KVM_REG_MIPS_CP0_ERROREPC:
674 v = (long)kvm_read_c0_guest_errorepc(cop0);
675 break;
f8be02da
JH		 676 /* registers to be handled specially */
677 case KVM_REG_MIPS_CP0_COUNT:
f8239342
JH		 678 case KVM_REG_MIPS_COUNT_CTL:
679 case KVM_REG_MIPS_COUNT_RESUME:
f74a8e22 680 case KVM_REG_MIPS_COUNT_HZ:
f8be02da
JH		 681 ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v);
682 if (ret)
683 return ret;
684 break;
4c73fb2b
DD		 685 default:
686 return -EINVAL;
687 }
681865d4
DD		 688 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
689 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
d116e812 690
681865d4
DD		 691 return put_user(v, uaddr64);
692 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
693 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
694 u32 v32 = (u32)v;
d116e812 695
681865d4 696 return put_user(v32, uaddr32);
ab86bd60
JH		 697 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
698 void __user *uaddr = (void __user *)(long)reg->addr;
699
700 return copy_to_user(uaddr, vs, 16);
681865d4
DD		 701 } else {
702 return -EINVAL;
703 }
4c73fb2b
DD		 704}
705
706static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
707 const struct kvm_one_reg *reg)
708{
4c73fb2b 709 struct mips_coproc *cop0 = vcpu->arch.cop0;
379245cd
JH		 710 struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
711 s64 v;
ab86bd60 712 s64 vs[2];
379245cd 713 unsigned int idx;
4c73fb2b 714
681865d4
DD		 715 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
716 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
717
718 if (get_user(v, uaddr64) != 0)
719 return -EFAULT;
720 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
721 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
722 s32 v32;
723
724 if (get_user(v32, uaddr32) != 0)
725 return -EFAULT;
726 v = (s64)v32;
ab86bd60
JH		 727 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
728 void __user *uaddr = (void __user *)(long)reg->addr;
729
730 return copy_from_user(vs, uaddr, 16);
681865d4
DD		 731 } else {
732 return -EINVAL;
733 }
4c73fb2b
DD		 734
735 switch (reg->id) {
379245cd 736 /* General purpose registers */
4c73fb2b
DD		 737 case KVM_REG_MIPS_R0:
738 /* Silently ignore requests to set $0 */
739 break;
740 case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31:
741 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v;
742 break;
743 case KVM_REG_MIPS_HI:
744 vcpu->arch.hi = v;
745 break;
746 case KVM_REG_MIPS_LO:
747 vcpu->arch.lo = v;
748 break;
749 case KVM_REG_MIPS_PC:
750 vcpu->arch.pc = v;
751 break;
752
379245cd
JH		 753 /* Floating point registers */
754 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
755 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
756 return -EINVAL;
757 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
758 /* Odd singles in top of even double when FR=0 */
759 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
760 set_fpr32(&fpu->fpr[idx], 0, v);
761 else
762 set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v);
763 break;
764 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
765 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
766 return -EINVAL;
767 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
768 /* Can't access odd doubles in FR=0 mode */
769 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
770 return -EINVAL;
771 set_fpr64(&fpu->fpr[idx], 0, v);
772 break;
773 case KVM_REG_MIPS_FCR_IR:
774 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
775 return -EINVAL;
776 /* Read-only */
777 break;
778 case KVM_REG_MIPS_FCR_CSR:
779 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
780 return -EINVAL;
781 fpu->fcr31 = v;
782 break;
783
ab86bd60
JH		 784 /* MIPS SIMD Architecture (MSA) registers */
785 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
786 if (!kvm_mips_guest_has_msa(&vcpu->arch))
787 return -EINVAL;
788 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
789#ifdef CONFIG_CPU_LITTLE_ENDIAN
790 /* least significant byte first */
791 set_fpr64(&fpu->fpr[idx], 0, vs[0]);
792 set_fpr64(&fpu->fpr[idx], 1, vs[1]);
793#else
794 /* most significant byte first */
795 set_fpr64(&fpu->fpr[idx], 1, vs[0]);
796 set_fpr64(&fpu->fpr[idx], 0, vs[1]);
797#endif
798 break;
799 case KVM_REG_MIPS_MSA_IR:
800 if (!kvm_mips_guest_has_msa(&vcpu->arch))
801 return -EINVAL;
802 /* Read-only */
803 break;
804 case KVM_REG_MIPS_MSA_CSR:
805 if (!kvm_mips_guest_has_msa(&vcpu->arch))
806 return -EINVAL;
807 fpu->msacsr = v;
808 break;
809
379245cd 810 /* Co-processor 0 registers */
4c73fb2b
DD		 811 case KVM_REG_MIPS_CP0_INDEX:
812 kvm_write_c0_guest_index(cop0, v);
813 break;
814 case KVM_REG_MIPS_CP0_CONTEXT:
815 kvm_write_c0_guest_context(cop0, v);
816 break;
7767b7d2
JH		 817 case KVM_REG_MIPS_CP0_USERLOCAL:
818 kvm_write_c0_guest_userlocal(cop0, v);
819 break;
4c73fb2b
DD		 820 case KVM_REG_MIPS_CP0_PAGEMASK:
821 kvm_write_c0_guest_pagemask(cop0, v);
822 break;
823 case KVM_REG_MIPS_CP0_WIRED:
824 kvm_write_c0_guest_wired(cop0, v);
825 break;
16fd5c1d
JH		 826 case KVM_REG_MIPS_CP0_HWRENA:
827 kvm_write_c0_guest_hwrena(cop0, v);
828 break;
4c73fb2b
DD		 829 case KVM_REG_MIPS_CP0_BADVADDR:
830 kvm_write_c0_guest_badvaddr(cop0, v);
831 break;
832 case KVM_REG_MIPS_CP0_ENTRYHI:
833 kvm_write_c0_guest_entryhi(cop0, v);
834 break;
835 case KVM_REG_MIPS_CP0_STATUS:
836 kvm_write_c0_guest_status(cop0, v);
837 break;
fb6df0cd
JH		 838 case KVM_REG_MIPS_CP0_EPC:
839 kvm_write_c0_guest_epc(cop0, v);
840 break;
1068eaaf
JH		 841 case KVM_REG_MIPS_CP0_PRID:
842 kvm_write_c0_guest_prid(cop0, v);
843 break;
4c73fb2b
DD		 844 case KVM_REG_MIPS_CP0_ERROREPC:
845 kvm_write_c0_guest_errorepc(cop0, v);
846 break;
f8be02da
JH		 847 /* registers to be handled specially */
848 case KVM_REG_MIPS_CP0_COUNT:
849 case KVM_REG_MIPS_CP0_COMPARE:
e30492bb 850 case KVM_REG_MIPS_CP0_CAUSE:
c771607a
JH		 851 case KVM_REG_MIPS_CP0_CONFIG:
852 case KVM_REG_MIPS_CP0_CONFIG1:
853 case KVM_REG_MIPS_CP0_CONFIG2:
854 case KVM_REG_MIPS_CP0_CONFIG3:
855 case KVM_REG_MIPS_CP0_CONFIG4:
856 case KVM_REG_MIPS_CP0_CONFIG5:
f8239342
JH		 857 case KVM_REG_MIPS_COUNT_CTL:
858 case KVM_REG_MIPS_COUNT_RESUME:
f74a8e22 859 case KVM_REG_MIPS_COUNT_HZ:
f8be02da 860 return kvm_mips_callbacks->set_one_reg(vcpu, reg, v);
4c73fb2b
DD		 861 default:
862 return -EINVAL;
863 }
864 return 0;
865}
866
5fafd874
JH		 867static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
868 struct kvm_enable_cap *cap)
869{
870 int r = 0;
871
872 if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap))
873 return -EINVAL;
874 if (cap->flags)
875 return -EINVAL;
876 if (cap->args[0])
877 return -EINVAL;
878
879 switch (cap->cap) {
880 case KVM_CAP_MIPS_FPU:
881 vcpu->arch.fpu_enabled = true;
882 break;
883 default:
884 r = -EINVAL;
885 break;
886 }
887
888 return r;
889}
890
d116e812
DCZ		 891long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl,
892 unsigned long arg)
669e846e
SL		 893{
894 struct kvm_vcpu *vcpu = filp->private_data;
895 void __user *argp = (void __user *)arg;
896 long r;
669e846e
SL		 897
898 switch (ioctl) {
4c73fb2b
DD		 899 case KVM_SET_ONE_REG:
900 case KVM_GET_ONE_REG: {
901 struct kvm_one_reg reg;
d116e812 902
4c73fb2b
DD		 903 if (copy_from_user(&reg, argp, sizeof(reg)))
904 return -EFAULT;
905 if (ioctl == KVM_SET_ONE_REG)
906 return kvm_mips_set_reg(vcpu, &reg);
907 else
908 return kvm_mips_get_reg(vcpu, &reg);
909 }
910 case KVM_GET_REG_LIST: {
911 struct kvm_reg_list __user *user_list = argp;
912 u64 __user *reg_dest;
913 struct kvm_reg_list reg_list;
914 unsigned n;
915
916 if (copy_from_user(&reg_list, user_list, sizeof(reg_list)))
917 return -EFAULT;
918 n = reg_list.n;
919 reg_list.n = ARRAY_SIZE(kvm_mips_get_one_regs);
920 if (copy_to_user(user_list, &reg_list, sizeof(reg_list)))
921 return -EFAULT;
922 if (n < reg_list.n)
923 return -E2BIG;
924 reg_dest = user_list->reg;
925 if (copy_to_user(reg_dest, kvm_mips_get_one_regs,
926 sizeof(kvm_mips_get_one_regs)))
927 return -EFAULT;
928 return 0;
929 }
669e846e
SL		 930 case KVM_NMI:
931 /* Treat the NMI as a CPU reset */
932 r = kvm_mips_reset_vcpu(vcpu);
933 break;
934 case KVM_INTERRUPT:
935 {
936 struct kvm_mips_interrupt irq;
d116e812 937
669e846e
SL		 938 r = -EFAULT;
939 if (copy_from_user(&irq, argp, sizeof(irq)))
940 goto out;
941
669e846e
SL		 942 kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__,
943 irq.irq);
944
945 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
946 break;
947 }
5fafd874
JH		 948 case KVM_ENABLE_CAP: {
949 struct kvm_enable_cap cap;
950
951 r = -EFAULT;
952 if (copy_from_user(&cap, argp, sizeof(cap)))
953 goto out;
954 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
955 break;
956 }
669e846e 957 default:
4c73fb2b 958 r = -ENOIOCTLCMD;
669e846e
SL		 959 }
960
961out:
962 return r;
963}
964
d116e812 965/* Get (and clear) the dirty memory log for a memory slot. */
669e846e
SL		 966int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
967{
968 struct kvm_memory_slot *memslot;
969 unsigned long ga, ga_end;
970 int is_dirty = 0;
971 int r;
972 unsigned long n;
973
974 mutex_lock(&kvm->slots_lock);
975
976 r = kvm_get_dirty_log(kvm, log, &is_dirty);
977 if (r)
978 goto out;
979
980 /* If nothing is dirty, don't bother messing with page tables. */
981 if (is_dirty) {
982 memslot = &kvm->memslots->memslots[log->slot];
983
984 ga = memslot->base_gfn << PAGE_SHIFT;
985 ga_end = ga + (memslot->npages << PAGE_SHIFT);
986
6ad78a5c
DCZ		 987 kvm_info("%s: dirty, ga: %#lx, ga_end %#lx\n", __func__, ga,
988 ga_end);
669e846e
SL		 989
990 n = kvm_dirty_bitmap_bytes(memslot);
991 memset(memslot->dirty_bitmap, 0, n);
992 }
993
994 r = 0;
995out:
996 mutex_unlock(&kvm->slots_lock);
997 return r;
998
999}
1000
1001long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
1002{
1003 long r;
1004
1005 switch (ioctl) {
1006 default:
ed829857 1007 r = -ENOIOCTLCMD;
669e846e
SL		 1008 }
1009
1010 return r;
1011}
1012
1013int kvm_arch_init(void *opaque)
1014{
669e846e
SL		 1015 if (kvm_mips_callbacks) {
1016 kvm_err("kvm: module already exists\n");
1017 return -EEXIST;
1018 }
1019
d98403a5 1020 return kvm_mips_emulation_init(&kvm_mips_callbacks);
669e846e
SL		 1021}
1022
1023void kvm_arch_exit(void)
1024{
1025 kvm_mips_callbacks = NULL;
1026}
1027
d116e812
DCZ		 1028int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
1029 struct kvm_sregs *sregs)
669e846e 1030{
ed829857 1031 return -ENOIOCTLCMD;
669e846e
SL		 1032}
1033
d116e812
DCZ		 1034int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
1035 struct kvm_sregs *sregs)
669e846e 1036{
ed829857 1037 return -ENOIOCTLCMD;
669e846e
SL		 1038}
1039
31928aa5 1040void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
669e846e 1041{
669e846e
SL		 1042}
1043
1044int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1045{
ed829857 1046 return -ENOIOCTLCMD;
669e846e
SL		 1047}
1048
1049int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1050{
ed829857 1051 return -ENOIOCTLCMD;
669e846e
SL		 1052}
1053
1054int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
1055{
1056 return VM_FAULT_SIGBUS;
1057}
1058
784aa3d7 1059int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
669e846e
SL		 1060{
1061 int r;
1062
1063 switch (ext) {
4c73fb2b 1064 case KVM_CAP_ONE_REG:
5fafd874 1065 case KVM_CAP_ENABLE_CAP:
4c73fb2b
DD		 1066 r = 1;
1067 break;
669e846e
SL		 1068 case KVM_CAP_COALESCED_MMIO:
1069 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1070 break;
5fafd874
JH		 1071 case KVM_CAP_MIPS_FPU:
1072 r = !!cpu_has_fpu;
1073 break;
669e846e
SL		 1074 default:
1075 r = 0;
1076 break;
1077 }
1078 return r;
669e846e
SL		 1079}
1080
1081int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
1082{
1083 return kvm_mips_pending_timer(vcpu);
1084}
1085
1086int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu)
1087{
1088 int i;
1089 struct mips_coproc *cop0;
1090
1091 if (!vcpu)
1092 return -1;
1093
6ad78a5c
DCZ		 1094 kvm_debug("VCPU Register Dump:\n");
1095 kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc);
1096 kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions);
669e846e
SL		 1097
1098 for (i = 0; i < 32; i += 4) {
6ad78a5c 1099 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i,
669e846e
SL		 1100 vcpu->arch.gprs[i],
1101 vcpu->arch.gprs[i + 1],
1102 vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]);
1103 }
6ad78a5c
DCZ		 1104 kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi);
1105 kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo);
669e846e
SL		 1106
1107 cop0 = vcpu->arch.cop0;
6ad78a5c
DCZ		 1108 kvm_debug("\tStatus: 0x%08lx, Cause: 0x%08lx\n",
1109 kvm_read_c0_guest_status(cop0),
1110 kvm_read_c0_guest_cause(cop0));
669e846e 1111
6ad78a5c 1112 kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0));
669e846e
SL		 1113
1114 return 0;
1115}
1116
1117int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1118{
1119 int i;
1120
8d17dd04 1121 for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
bf32ebf6 1122 vcpu->arch.gprs[i] = regs->gpr[i];
8d17dd04 1123 vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */
669e846e
SL		 1124 vcpu->arch.hi = regs->hi;
1125 vcpu->arch.lo = regs->lo;
1126 vcpu->arch.pc = regs->pc;
1127
4c73fb2b 1128 return 0;
669e846e
SL		 1129}
1130
1131int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1132{
1133 int i;
1134
8d17dd04 1135 for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
bf32ebf6 1136 regs->gpr[i] = vcpu->arch.gprs[i];
669e846e
SL		 1137
1138 regs->hi = vcpu->arch.hi;
1139 regs->lo = vcpu->arch.lo;
1140 regs->pc = vcpu->arch.pc;
1141
4c73fb2b 1142 return 0;
669e846e
SL		 1143}
1144
0fae34f4 1145static void kvm_mips_comparecount_func(unsigned long data)
669e846e
SL		 1146{
1147 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
1148
1149 kvm_mips_callbacks->queue_timer_int(vcpu);
1150
1151 vcpu->arch.wait = 0;
d116e812 1152 if (waitqueue_active(&vcpu->wq))
669e846e 1153 wake_up_interruptible(&vcpu->wq);
669e846e
SL		 1154}
1155
d116e812 1156/* low level hrtimer wake routine */
0fae34f4 1157static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer)
669e846e
SL		 1158{
1159 struct kvm_vcpu *vcpu;
1160
1161 vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer);
1162 kvm_mips_comparecount_func((unsigned long) vcpu);
e30492bb 1163 return kvm_mips_count_timeout(vcpu);
669e846e
SL		 1164}
1165
1166int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
1167{
1168 kvm_mips_callbacks->vcpu_init(vcpu);
1169 hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC,
1170 HRTIMER_MODE_REL);
1171 vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup;
669e846e
SL		 1172 return 0;
1173}
1174
d116e812
DCZ		 1175int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
1176 struct kvm_translation *tr)
669e846e
SL		 1177{
1178 return 0;
1179}
1180
1181/* Initial guest state */
1182int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
1183{
1184 return kvm_mips_callbacks->vcpu_setup(vcpu);
1185}
1186
d116e812 1187static void kvm_mips_set_c0_status(void)
669e846e
SL		 1188{
1189 uint32_t status = read_c0_status();
1190
669e846e
SL		 1191 if (cpu_has_dsp)
1192 status |= (ST0_MX);
1193
1194 write_c0_status(status);
1195 ehb();
1196}
1197
1198/*
1199 * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
1200 */
1201int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu)
1202{
1203 uint32_t cause = vcpu->arch.host_cp0_cause;
1204 uint32_t exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
1205 uint32_t __user *opc = (uint32_t __user *) vcpu->arch.pc;
1206 unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
1207 enum emulation_result er = EMULATE_DONE;
1208 int ret = RESUME_GUEST;
1209
c4c6f2ca
JH		 1210 /* re-enable HTW before enabling interrupts */
1211 htw_start();
1212
669e846e
SL		 1213 /* Set a default exit reason */
1214 run->exit_reason = KVM_EXIT_UNKNOWN;
1215 run->ready_for_interrupt_injection = 1;
1216
d116e812
DCZ		 1217 /*
1218 * Set the appropriate status bits based on host CPU features,
1219 * before we hit the scheduler
1220 */
669e846e
SL		 1221 kvm_mips_set_c0_status();
1222
1223 local_irq_enable();
1224
1225 kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n",
1226 cause, opc, run, vcpu);
1227
d116e812
DCZ		 1228 /*
1229 * Do a privilege check, if in UM most of these exit conditions end up
669e846e
SL		 1230 * causing an exception to be delivered to the Guest Kernel
1231 */
1232 er = kvm_mips_check_privilege(cause, opc, run, vcpu);
1233 if (er == EMULATE_PRIV_FAIL) {
1234 goto skip_emul;
1235 } else if (er == EMULATE_FAIL) {
1236 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1237 ret = RESUME_HOST;
1238 goto skip_emul;
1239 }
1240
1241 switch (exccode) {
1242 case T_INT:
1243 kvm_debug("[%d]T_INT @ %p\n", vcpu->vcpu_id, opc);
1244
1245 ++vcpu->stat.int_exits;
1246 trace_kvm_exit(vcpu, INT_EXITS);
1247
d116e812 1248 if (need_resched())
669e846e 1249 cond_resched();
669e846e
SL		 1250
1251 ret = RESUME_GUEST;
1252 break;
1253
1254 case T_COP_UNUSABLE:
1255 kvm_debug("T_COP_UNUSABLE: @ PC: %p\n", opc);
1256
1257 ++vcpu->stat.cop_unusable_exits;
1258 trace_kvm_exit(vcpu, COP_UNUSABLE_EXITS);
1259 ret = kvm_mips_callbacks->handle_cop_unusable(vcpu);
1260 /* XXXKYMA: Might need to return to user space */
d116e812 1261 if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN)
669e846e 1262 ret = RESUME_HOST;
669e846e
SL		 1263 break;
1264
1265 case T_TLB_MOD:
1266 ++vcpu->stat.tlbmod_exits;
1267 trace_kvm_exit(vcpu, TLBMOD_EXITS);
1268 ret = kvm_mips_callbacks->handle_tlb_mod(vcpu);
1269 break;
1270
1271 case T_TLB_ST_MISS:
d116e812
DCZ		 1272 kvm_debug("TLB ST fault: cause %#x, status %#lx, PC: %p, BadVaddr: %#lx\n",
1273 cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc,
1274 badvaddr);
669e846e
SL		 1275
1276 ++vcpu->stat.tlbmiss_st_exits;
1277 trace_kvm_exit(vcpu, TLBMISS_ST_EXITS);
1278 ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu);
1279 break;
1280
1281 case T_TLB_LD_MISS:
1282 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n",
1283 cause, opc, badvaddr);
1284
1285 ++vcpu->stat.tlbmiss_ld_exits;
1286 trace_kvm_exit(vcpu, TLBMISS_LD_EXITS);
1287 ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu);
1288 break;
1289
1290 case T_ADDR_ERR_ST:
1291 ++vcpu->stat.addrerr_st_exits;
1292 trace_kvm_exit(vcpu, ADDRERR_ST_EXITS);
1293 ret = kvm_mips_callbacks->handle_addr_err_st(vcpu);
1294 break;
1295
1296 case T_ADDR_ERR_LD:
1297 ++vcpu->stat.addrerr_ld_exits;
1298 trace_kvm_exit(vcpu, ADDRERR_LD_EXITS);
1299 ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu);
1300 break;
1301
1302 case T_SYSCALL:
1303 ++vcpu->stat.syscall_exits;
1304 trace_kvm_exit(vcpu, SYSCALL_EXITS);
1305 ret = kvm_mips_callbacks->handle_syscall(vcpu);
1306 break;
1307
1308 case T_RES_INST:
1309 ++vcpu->stat.resvd_inst_exits;
1310 trace_kvm_exit(vcpu, RESVD_INST_EXITS);
1311 ret = kvm_mips_callbacks->handle_res_inst(vcpu);
1312 break;
1313
1314 case T_BREAK:
1315 ++vcpu->stat.break_inst_exits;
1316 trace_kvm_exit(vcpu, BREAK_INST_EXITS);
1317 ret = kvm_mips_callbacks->handle_break(vcpu);
1318 break;
1319
0a560427
JH		 1320 case T_TRAP:
1321 ++vcpu->stat.trap_inst_exits;
1322 trace_kvm_exit(vcpu, TRAP_INST_EXITS);
1323 ret = kvm_mips_callbacks->handle_trap(vcpu);
1324 break;
1325
c2537ed9
JH		 1326 case T_MSAFPE:
1327 ++vcpu->stat.msa_fpe_exits;
1328 trace_kvm_exit(vcpu, MSA_FPE_EXITS);
1329 ret = kvm_mips_callbacks->handle_msa_fpe(vcpu);
1330 break;
1331
1c0cd66a
JH		 1332 case T_FPE:
1333 ++vcpu->stat.fpe_exits;
1334 trace_kvm_exit(vcpu, FPE_EXITS);
1335 ret = kvm_mips_callbacks->handle_fpe(vcpu);
1336 break;
1337
98119ad5 1338 case T_MSADIS:
c2537ed9
JH		 1339 ++vcpu->stat.msa_disabled_exits;
1340 trace_kvm_exit(vcpu, MSA_DISABLED_EXITS);
98119ad5
JH		 1341 ret = kvm_mips_callbacks->handle_msa_disabled(vcpu);
1342 break;
1343
669e846e 1344 default:
d116e812
DCZ		 1345 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x BadVaddr: %#lx Status: %#lx\n",
1346 exccode, opc, kvm_get_inst(opc, vcpu), badvaddr,
1347 kvm_read_c0_guest_status(vcpu->arch.cop0));
669e846e
SL		 1348 kvm_arch_vcpu_dump_regs(vcpu);
1349 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1350 ret = RESUME_HOST;
1351 break;
1352
1353 }
1354
1355skip_emul:
1356 local_irq_disable();
1357
1358 if (er == EMULATE_DONE && !(ret & RESUME_HOST))
1359 kvm_mips_deliver_interrupts(vcpu, cause);
1360
1361 if (!(ret & RESUME_HOST)) {
d116e812 1362 /* Only check for signals if not already exiting to userspace */
669e846e
SL		 1363 if (signal_pending(current)) {
1364 run->exit_reason = KVM_EXIT_INTR;
1365 ret = (-EINTR << 2) | RESUME_HOST;
1366 ++vcpu->stat.signal_exits;
1367 trace_kvm_exit(vcpu, SIGNAL_EXITS);
1368 }
1369 }
1370
98e91b84
JH		 1371 if (ret == RESUME_GUEST) {
1372 /*
539cb89f
JH		 1373 * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context
1374 * is live), restore FCR31 / MSACSR.
98e91b84
JH		 1375 *
1376 * This should be before returning to the guest exception
539cb89f
JH		 1377 * vector, as it may well cause an [MSA] FP exception if there
1378 * are pending exception bits unmasked. (see
98e91b84
JH		 1379 * kvm_mips_csr_die_notifier() for how that is handled).
1380 */
1381 if (kvm_mips_guest_has_fpu(&vcpu->arch) &&
1382 read_c0_status() & ST0_CU1)
1383 __kvm_restore_fcsr(&vcpu->arch);
539cb89f
JH		 1384
1385 if (kvm_mips_guest_has_msa(&vcpu->arch) &&
1386 read_c0_config5() & MIPS_CONF5_MSAEN)
1387 __kvm_restore_msacsr(&vcpu->arch);
98e91b84
JH		 1388 }
1389
c4c6f2ca
JH		 1390 /* Disable HTW before returning to guest or host */
1391 htw_stop();
1392
669e846e
SL		 1393 return ret;
1394}
1395
98e91b84
JH		 1396/* Enable FPU for guest and restore context */
1397void kvm_own_fpu(struct kvm_vcpu *vcpu)
1398{
1399 struct mips_coproc *cop0 = vcpu->arch.cop0;
1400 unsigned int sr, cfg5;
1401
1402 preempt_disable();
1403
539cb89f
JH		 1404 sr = kvm_read_c0_guest_status(cop0);
1405
1406 /*
1407 * If MSA state is already live, it is undefined how it interacts with
1408 * FR=0 FPU state, and we don't want to hit reserved instruction
1409 * exceptions trying to save the MSA state later when CU=1 && FR=1, so
1410 * play it safe and save it first.
1411 *
1412 * In theory we shouldn't ever hit this case since kvm_lose_fpu() should
1413 * get called when guest CU1 is set, however we can't trust the guest
1414 * not to clobber the status register directly via the commpage.
1415 */
1416 if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) &&
1417 vcpu->arch.fpu_inuse & KVM_MIPS_FPU_MSA)
1418 kvm_lose_fpu(vcpu);
1419
98e91b84
JH		 1420 /*
1421 * Enable FPU for guest
1422 * We set FR and FRE according to guest context
1423 */
98e91b84
JH		 1424 change_c0_status(ST0_CU1 | ST0_FR, sr);
1425 if (cpu_has_fre) {
1426 cfg5 = kvm_read_c0_guest_config5(cop0);
1427 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1428 }
1429 enable_fpu_hazard();
1430
1431 /* If guest FPU state not active, restore it now */
1432 if (!(vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU)) {
1433 __kvm_restore_fpu(&vcpu->arch);
1434 vcpu->arch.fpu_inuse |= KVM_MIPS_FPU_FPU;
1435 }
1436
1437 preempt_enable();
1438}
1439
539cb89f
JH		 1440#ifdef CONFIG_CPU_HAS_MSA
1441/* Enable MSA for guest and restore context */
1442void kvm_own_msa(struct kvm_vcpu *vcpu)
1443{
1444 struct mips_coproc *cop0 = vcpu->arch.cop0;
1445 unsigned int sr, cfg5;
1446
1447 preempt_disable();
1448
1449 /*
1450 * Enable FPU if enabled in guest, since we're restoring FPU context
1451 * anyway. We set FR and FRE according to guest context.
1452 */
1453 if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
1454 sr = kvm_read_c0_guest_status(cop0);
1455
1456 /*
1457 * If FR=0 FPU state is already live, it is undefined how it
1458 * interacts with MSA state, so play it safe and save it first.
1459 */
1460 if (!(sr & ST0_FR) &&
1461 (vcpu->arch.fpu_inuse & (KVM_MIPS_FPU_FPU |
1462 KVM_MIPS_FPU_MSA)) == KVM_MIPS_FPU_FPU)
1463 kvm_lose_fpu(vcpu);
1464
1465 change_c0_status(ST0_CU1 | ST0_FR, sr);
1466 if (sr & ST0_CU1 && cpu_has_fre) {
1467 cfg5 = kvm_read_c0_guest_config5(cop0);
1468 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1469 }
1470 }
1471
1472 /* Enable MSA for guest */
1473 set_c0_config5(MIPS_CONF5_MSAEN);
1474 enable_fpu_hazard();
1475
1476 switch (vcpu->arch.fpu_inuse & (KVM_MIPS_FPU_FPU | KVM_MIPS_FPU_MSA)) {
1477 case KVM_MIPS_FPU_FPU:
1478 /*
1479 * Guest FPU state already loaded, only restore upper MSA state
1480 */
1481 __kvm_restore_msa_upper(&vcpu->arch);
1482 vcpu->arch.fpu_inuse |= KVM_MIPS_FPU_MSA;
1483 break;
1484 case 0:
1485 /* Neither FPU or MSA already active, restore full MSA state */
1486 __kvm_restore_msa(&vcpu->arch);
1487 vcpu->arch.fpu_inuse |= KVM_MIPS_FPU_MSA;
1488 if (kvm_mips_guest_has_fpu(&vcpu->arch))
1489 vcpu->arch.fpu_inuse |= KVM_MIPS_FPU_FPU;
1490 break;
1491 default:
1492 break;
1493 }
1494
1495 preempt_enable();
1496}
1497#endif
1498
1499/* Drop FPU & MSA without saving it */
98e91b84
JH		 1500void kvm_drop_fpu(struct kvm_vcpu *vcpu)
1501{
1502 preempt_disable();
539cb89f
JH		 1503 if (cpu_has_msa && vcpu->arch.fpu_inuse & KVM_MIPS_FPU_MSA) {
1504 disable_msa();
1505 vcpu->arch.fpu_inuse &= ~KVM_MIPS_FPU_MSA;
1506 }
98e91b84
JH		 1507 if (vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU) {
1508 clear_c0_status(ST0_CU1 | ST0_FR);
1509 vcpu->arch.fpu_inuse &= ~KVM_MIPS_FPU_FPU;
1510 }
1511 preempt_enable();
1512}
1513
539cb89f 1514/* Save and disable FPU & MSA */
98e91b84
JH		 1515void kvm_lose_fpu(struct kvm_vcpu *vcpu)
1516{
1517 /*
539cb89f
JH		 1518 * FPU & MSA get disabled in root context (hardware) when it is disabled
1519 * in guest context (software), but the register state in the hardware
1520 * may still be in use. This is why we explicitly re-enable the hardware
98e91b84
JH		 1521 * before saving.
1522 */
1523
1524 preempt_disable();
539cb89f
JH		 1525 if (cpu_has_msa && vcpu->arch.fpu_inuse & KVM_MIPS_FPU_MSA) {
1526 set_c0_config5(MIPS_CONF5_MSAEN);
1527 enable_fpu_hazard();
1528
1529 __kvm_save_msa(&vcpu->arch);
1530
1531 /* Disable MSA & FPU */
1532 disable_msa();
1533 if (vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU)
1534 clear_c0_status(ST0_CU1 | ST0_FR);
1535 vcpu->arch.fpu_inuse &= ~(KVM_MIPS_FPU_FPU | KVM_MIPS_FPU_MSA);
1536 } else if (vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU) {
98e91b84
JH		 1537 set_c0_status(ST0_CU1);
1538 enable_fpu_hazard();
1539
1540 __kvm_save_fpu(&vcpu->arch);
1541 vcpu->arch.fpu_inuse &= ~KVM_MIPS_FPU_FPU;
1542
1543 /* Disable FPU */
1544 clear_c0_status(ST0_CU1 | ST0_FR);
1545 }
1546 preempt_enable();
1547}
1548
1549/*
539cb89f
JH		 1550 * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are
1551 * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP
1552 * exception if cause bits are set in the value being written.
98e91b84
JH		 1553 */
1554static int kvm_mips_csr_die_notify(struct notifier_block *self,
1555 unsigned long cmd, void *ptr)
1556{
1557 struct die_args *args = (struct die_args *)ptr;
1558 struct pt_regs *regs = args->regs;
1559 unsigned long pc;
1560
539cb89f
JH		 1561 /* Only interested in FPE and MSAFPE */
1562 if (cmd != DIE_FP && cmd != DIE_MSAFP)
98e91b84
JH		 1563 return NOTIFY_DONE;
1564
1565 /* Return immediately if guest context isn't active */
1566 if (!(current->flags & PF_VCPU))
1567 return NOTIFY_DONE;
1568
1569 /* Should never get here from user mode */
1570 BUG_ON(user_mode(regs));
1571
1572 pc = instruction_pointer(regs);
1573 switch (cmd) {
1574 case DIE_FP:
1575 /* match 2nd instruction in __kvm_restore_fcsr */
1576 if (pc != (unsigned long)&__kvm_restore_fcsr + 4)
1577 return NOTIFY_DONE;
1578 break;
539cb89f
JH		 1579 case DIE_MSAFP:
1580 /* match 2nd/3rd instruction in __kvm_restore_msacsr */
1581 if (!cpu_has_msa ||
1582 pc < (unsigned long)&__kvm_restore_msacsr + 4 ||
1583 pc > (unsigned long)&__kvm_restore_msacsr + 8)
1584 return NOTIFY_DONE;
1585 break;
98e91b84
JH		 1586 }
1587
1588 /* Move PC forward a little and continue executing */
1589 instruction_pointer(regs) += 4;
1590
1591 return NOTIFY_STOP;
1592}
1593
1594static struct notifier_block kvm_mips_csr_die_notifier = {
1595 .notifier_call = kvm_mips_csr_die_notify,
1596};
1597
669e846e
SL		 1598int __init kvm_mips_init(void)
1599{
1600 int ret;
1601
1602 ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE);
1603
1604 if (ret)
1605 return ret;
1606
98e91b84
JH		 1607 register_die_notifier(&kvm_mips_csr_die_notifier);
1608
d116e812
DCZ		 1609 /*
1610 * On MIPS, kernel modules are executed from "mapped space", which
1611 * requires TLBs. The TLB handling code is statically linked with
d7d5b05f 1612 * the rest of the kernel (tlb.c) to avoid the possibility of
d116e812
DCZ		 1613 * double faulting. The issue is that the TLB code references
1614 * routines that are part of the the KVM module, which are only
1615 * available once the module is loaded.
669e846e
SL		 1616 */
1617 kvm_mips_gfn_to_pfn = gfn_to_pfn;
1618 kvm_mips_release_pfn_clean = kvm_release_pfn_clean;
1619 kvm_mips_is_error_pfn = is_error_pfn;
1620
669e846e
SL		 1621 return 0;
1622}
1623
1624void __exit kvm_mips_exit(void)
1625{
1626 kvm_exit();
1627
1628 kvm_mips_gfn_to_pfn = NULL;
1629 kvm_mips_release_pfn_clean = NULL;
1630 kvm_mips_is_error_pfn = NULL;
98e91b84
JH		 1631
1632 unregister_die_notifier(&kvm_mips_csr_die_notifier);
669e846e
SL		 1633}
1634
1635module_init(kvm_mips_init);
1636module_exit(kvm_mips_exit);
1637
1638EXPORT_TRACEPOINT_SYMBOL(kvm_exit);
Linux 6.x block layer and io_uring tree(s)