projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
MIPS: KVM: Use raw_cpu_has_fpu in kvm_mips_guest_can_have_fpu()
[linux-2.6-block.git] / arch / mips / kvm / mips.c
CommitLineData
669e846e
SL		 1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * KVM/MIPS: MIPS specific KVM APIs
7 *
8 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
9 * Authors: Sanjay Lal <sanjayl@kymasys.com>
d116e812 10 */
669e846e
SL		 11
12#include <linux/errno.h>
13#include <linux/err.h>
98e91b84 14#include <linux/kdebug.h>
669e846e
SL		 15#include <linux/module.h>
16#include <linux/vmalloc.h>
17#include <linux/fs.h>
18#include <linux/bootmem.h>
f798217d 19#include <asm/fpu.h>
669e846e
SL		 20#include <asm/page.h>
21#include <asm/cacheflush.h>
22#include <asm/mmu_context.h>
c4c6f2ca 23#include <asm/pgtable.h>
669e846e
SL		 24
25#include <linux/kvm_host.h>
26
d7d5b05f
DCZ		 27#include "interrupt.h"
28#include "commpage.h"
669e846e
SL		 29
30#define CREATE_TRACE_POINTS
31#include "trace.h"
32
33#ifndef VECTORSPACING
34#define VECTORSPACING 0x100 /* for EI/VI mode */
35#endif
36
d116e812 37#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x)
669e846e 38struct kvm_stats_debugfs_item debugfs_entries[] = {
d116e812
DCZ		 39 { "wait", VCPU_STAT(wait_exits), KVM_STAT_VCPU },
40 { "cache", VCPU_STAT(cache_exits), KVM_STAT_VCPU },
41 { "signal", VCPU_STAT(signal_exits), KVM_STAT_VCPU },
42 { "interrupt", VCPU_STAT(int_exits), KVM_STAT_VCPU },
43 { "cop_unsuable", VCPU_STAT(cop_unusable_exits), KVM_STAT_VCPU },
44 { "tlbmod", VCPU_STAT(tlbmod_exits), KVM_STAT_VCPU },
45 { "tlbmiss_ld", VCPU_STAT(tlbmiss_ld_exits), KVM_STAT_VCPU },
46 { "tlbmiss_st", VCPU_STAT(tlbmiss_st_exits), KVM_STAT_VCPU },
47 { "addrerr_st", VCPU_STAT(addrerr_st_exits), KVM_STAT_VCPU },
48 { "addrerr_ld", VCPU_STAT(addrerr_ld_exits), KVM_STAT_VCPU },
49 { "syscall", VCPU_STAT(syscall_exits), KVM_STAT_VCPU },
50 { "resvd_inst", VCPU_STAT(resvd_inst_exits), KVM_STAT_VCPU },
51 { "break_inst", VCPU_STAT(break_inst_exits), KVM_STAT_VCPU },
0a560427 52 { "trap_inst", VCPU_STAT(trap_inst_exits), KVM_STAT_VCPU },
c2537ed9 53 { "msa_fpe", VCPU_STAT(msa_fpe_exits), KVM_STAT_VCPU },
1c0cd66a 54 { "fpe", VCPU_STAT(fpe_exits), KVM_STAT_VCPU },
c2537ed9 55 { "msa_disabled", VCPU_STAT(msa_disabled_exits), KVM_STAT_VCPU },
d116e812 56 { "flush_dcache", VCPU_STAT(flush_dcache_exits), KVM_STAT_VCPU },
f7819512 57 { "halt_successful_poll", VCPU_STAT(halt_successful_poll), KVM_STAT_VCPU },
62bea5bf 58 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll), KVM_STAT_VCPU },
3491caf2 59 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid), KVM_STAT_VCPU },
d116e812 60 { "halt_wakeup", VCPU_STAT(halt_wakeup), KVM_STAT_VCPU },
669e846e
SL		 61 {NULL}
62};
63
64static int kvm_mips_reset_vcpu(struct kvm_vcpu *vcpu)
65{
66 int i;
d116e812 67
669e846e
SL		 68 for_each_possible_cpu(i) {
69 vcpu->arch.guest_kernel_asid[i] = 0;
70 vcpu->arch.guest_user_asid[i] = 0;
71 }
d116e812 72
669e846e
SL		 73 return 0;
74}
75
d116e812
DCZ		 76/*
77 * XXXKYMA: We are simulatoring a processor that has the WII bit set in
78 * Config7, so we are "runnable" if interrupts are pending
669e846e
SL		 79 */
80int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
81{
82 return !!(vcpu->arch.pending_exceptions);
83}
84
85int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
86{
87 return 1;
88}
89
13a34e06 90int kvm_arch_hardware_enable(void)
669e846e
SL		 91{
92 return 0;
93}
94
669e846e
SL		 95int kvm_arch_hardware_setup(void)
96{
97 return 0;
98}
99
669e846e
SL		 100void kvm_arch_check_processor_compat(void *rtn)
101{
d98403a5 102 *(int *)rtn = 0;
669e846e
SL		 103}
104
105static void kvm_mips_init_tlbs(struct kvm *kvm)
106{
107 unsigned long wired;
108
d116e812
DCZ		 109 /*
110 * Add a wired entry to the TLB, it is used to map the commpage to
111 * the Guest kernel
112 */
669e846e
SL		 113 wired = read_c0_wired();
114 write_c0_wired(wired + 1);
115 mtc0_tlbw_hazard();
116 kvm->arch.commpage_tlb = wired;
117
118 kvm_debug("[%d] commpage TLB: %d\n", smp_processor_id(),
119 kvm->arch.commpage_tlb);
120}
121
122static void kvm_mips_init_vm_percpu(void *arg)
123{
124 struct kvm *kvm = (struct kvm *)arg;
125
126 kvm_mips_init_tlbs(kvm);
127 kvm_mips_callbacks->vm_init(kvm);
128
129}
130
131int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
132{
133 if (atomic_inc_return(&kvm_mips_instance) == 1) {
6e95bfd2
JH		 134 kvm_debug("%s: 1st KVM instance, setup host TLB parameters\n",
135 __func__);
669e846e
SL		 136 on_each_cpu(kvm_mips_init_vm_percpu, kvm, 1);
137 }
138
669e846e
SL		 139 return 0;
140}
141
142void kvm_mips_free_vcpus(struct kvm *kvm)
143{
144 unsigned int i;
145 struct kvm_vcpu *vcpu;
146
147 /* Put the pages we reserved for the guest pmap */
148 for (i = 0; i < kvm->arch.guest_pmap_npages; i++) {
149 if (kvm->arch.guest_pmap[i] != KVM_INVALID_PAGE)
9befad23 150 kvm_release_pfn_clean(kvm->arch.guest_pmap[i]);
669e846e 151 }
c6c0a663 152 kfree(kvm->arch.guest_pmap);
669e846e
SL		 153
154 kvm_for_each_vcpu(i, vcpu, kvm) {
155 kvm_arch_vcpu_free(vcpu);
156 }
157
158 mutex_lock(&kvm->lock);
159
160 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
161 kvm->vcpus[i] = NULL;
162
163 atomic_set(&kvm->online_vcpus, 0);
164
165 mutex_unlock(&kvm->lock);
166}
167
669e846e
SL		 168static void kvm_mips_uninit_tlbs(void *arg)
169{
170 /* Restore wired count */
171 write_c0_wired(0);
172 mtc0_tlbw_hazard();
173 /* Clear out all the TLBs */
174 kvm_local_flush_tlb_all();
175}
176
177void kvm_arch_destroy_vm(struct kvm *kvm)
178{
179 kvm_mips_free_vcpus(kvm);
180
181 /* If this is the last instance, restore wired count */
182 if (atomic_dec_return(&kvm_mips_instance) == 0) {
6e95bfd2
JH		 183 kvm_debug("%s: last KVM instance, restoring TLB parameters\n",
184 __func__);
669e846e
SL		 185 on_each_cpu(kvm_mips_uninit_tlbs, NULL, 1);
186 }
187}
188
d116e812
DCZ		 189long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl,
190 unsigned long arg)
669e846e 191{
ed829857 192 return -ENOIOCTLCMD;
669e846e
SL		 193}
194
5587027c
AK		 195int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
196 unsigned long npages)
669e846e
SL		 197{
198 return 0;
199}
200
201int kvm_arch_prepare_memory_region(struct kvm *kvm,
d116e812 202 struct kvm_memory_slot *memslot,
09170a49 203 const struct kvm_userspace_memory_region *mem,
d116e812 204 enum kvm_mr_change change)
669e846e
SL		 205{
206 return 0;
207}
208
209void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 210 const struct kvm_userspace_memory_region *mem,
d116e812 211 const struct kvm_memory_slot *old,
f36f3f28 212 const struct kvm_memory_slot *new,
d116e812 213 enum kvm_mr_change change)
669e846e
SL		 214{
215 unsigned long npages = 0;
d98403a5 216 int i;
669e846e
SL		 217
218 kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n",
219 __func__, kvm, mem->slot, mem->guest_phys_addr,
220 mem->memory_size, mem->userspace_addr);
221
222 /* Setup Guest PMAP table */
223 if (!kvm->arch.guest_pmap) {
224 if (mem->slot == 0)
225 npages = mem->memory_size >> PAGE_SHIFT;
226
227 if (npages) {
228 kvm->arch.guest_pmap_npages = npages;
229 kvm->arch.guest_pmap =
230 kzalloc(npages * sizeof(unsigned long), GFP_KERNEL);
231
232 if (!kvm->arch.guest_pmap) {
f7fdcb60 233 kvm_err("Failed to allocate guest PMAP\n");
d98403a5 234 return;
669e846e
SL		 235 }
236
6e95bfd2
JH		 237 kvm_debug("Allocated space for Guest PMAP Table (%ld pages) @ %p\n",
238 npages, kvm->arch.guest_pmap);
669e846e
SL		 239
240 /* Now setup the page table */
d116e812 241 for (i = 0; i < npages; i++)
669e846e 242 kvm->arch.guest_pmap[i] = KVM_INVALID_PAGE;
669e846e
SL		 243 }
244 }
669e846e
SL		 245}
246
669e846e
SL		 247struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id)
248{
669e846e
SL		 249 int err, size, offset;
250 void *gebase;
251 int i;
252
253 struct kvm_vcpu *vcpu = kzalloc(sizeof(struct kvm_vcpu), GFP_KERNEL);
254
255 if (!vcpu) {
256 err = -ENOMEM;
257 goto out;
258 }
259
260 err = kvm_vcpu_init(vcpu, kvm, id);
261
262 if (err)
263 goto out_free_cpu;
264
6e95bfd2 265 kvm_debug("kvm @ %p: create cpu %d at %p\n", kvm, id, vcpu);
669e846e 266
d116e812
DCZ		 267 /*
268 * Allocate space for host mode exception handlers that handle
669e846e
SL		 269 * guest mode exits
270 */
d116e812 271 if (cpu_has_veic || cpu_has_vint)
669e846e 272 size = 0x200 + VECTORSPACING * 64;
d116e812 273 else
7006e2df 274 size = 0x4000;
669e846e 275
669e846e
SL		 276 gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL);
277
278 if (!gebase) {
279 err = -ENOMEM;
585bb8f9 280 goto out_uninit_cpu;
669e846e 281 }
6e95bfd2
JH		 282 kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n",
283 ALIGN(size, PAGE_SIZE), gebase);
669e846e
SL		 284
285 /* Save new ebase */
286 vcpu->arch.guest_ebase = gebase;
287
288 /* Copy L1 Guest Exception handler to correct offset */
289
290 /* TLB Refill, EXL = 0 */
291 memcpy(gebase, mips32_exception,
292 mips32_exceptionEnd - mips32_exception);
293
294 /* General Exception Entry point */
295 memcpy(gebase + 0x180, mips32_exception,
296 mips32_exceptionEnd - mips32_exception);
297
298 /* For vectored interrupts poke the exception code @ all offsets 0-7 */
299 for (i = 0; i < 8; i++) {
300 kvm_debug("L1 Vectored handler @ %p\n",
301 gebase + 0x200 + (i * VECTORSPACING));
302 memcpy(gebase + 0x200 + (i * VECTORSPACING), mips32_exception,
303 mips32_exceptionEnd - mips32_exception);
304 }
305
306 /* General handler, relocate to unmapped space for sanity's sake */
307 offset = 0x2000;
6e95bfd2
JH		 308 kvm_debug("Installing KVM Exception handlers @ %p, %#x bytes\n",
309 gebase + offset,
310 mips32_GuestExceptionEnd - mips32_GuestException);
669e846e
SL		 311
312 memcpy(gebase + offset, mips32_GuestException,
313 mips32_GuestExceptionEnd - mips32_GuestException);
314
797179bc
JH		 315#ifdef MODULE
316 offset += mips32_GuestExceptionEnd - mips32_GuestException;
317 memcpy(gebase + offset, (char *)__kvm_mips_vcpu_run,
318 __kvm_mips_vcpu_run_end - (char *)__kvm_mips_vcpu_run);
319 vcpu->arch.vcpu_run = gebase + offset;
320#else
321 vcpu->arch.vcpu_run = __kvm_mips_vcpu_run;
322#endif
323
669e846e 324 /* Invalidate the icache for these ranges */
facaaec1
JH		 325 local_flush_icache_range((unsigned long)gebase,
326 (unsigned long)gebase + ALIGN(size, PAGE_SIZE));
669e846e 327
d116e812
DCZ		 328 /*
329 * Allocate comm page for guest kernel, a TLB will be reserved for
330 * mapping GVA @ 0xFFFF8000 to this page
331 */
669e846e
SL		 332 vcpu->arch.kseg0_commpage = kzalloc(PAGE_SIZE << 1, GFP_KERNEL);
333
334 if (!vcpu->arch.kseg0_commpage) {
335 err = -ENOMEM;
336 goto out_free_gebase;
337 }
338
6e95bfd2 339 kvm_debug("Allocated COMM page @ %p\n", vcpu->arch.kseg0_commpage);
669e846e
SL		 340 kvm_mips_commpage_init(vcpu);
341
342 /* Init */
343 vcpu->arch.last_sched_cpu = -1;
344
345 /* Start off the timer */
e30492bb 346 kvm_mips_init_count(vcpu);
669e846e
SL		 347
348 return vcpu;
349
350out_free_gebase:
351 kfree(gebase);
352
585bb8f9
JH		 353out_uninit_cpu:
354 kvm_vcpu_uninit(vcpu);
355
669e846e
SL		 356out_free_cpu:
357 kfree(vcpu);
358
359out:
360 return ERR_PTR(err);
361}
362
363void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
364{
365 hrtimer_cancel(&vcpu->arch.comparecount_timer);
366
367 kvm_vcpu_uninit(vcpu);
368
369 kvm_mips_dump_stats(vcpu);
370
c6c0a663
JH		 371 kfree(vcpu->arch.guest_ebase);
372 kfree(vcpu->arch.kseg0_commpage);
8c9eb041 373 kfree(vcpu);
669e846e
SL		 374}
375
376void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
377{
378 kvm_arch_vcpu_free(vcpu);
379}
380
d116e812
DCZ		 381int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
382 struct kvm_guest_debug *dbg)
669e846e 383{
ed829857 384 return -ENOIOCTLCMD;
669e846e
SL		 385}
386
387int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
388{
389 int r = 0;
390 sigset_t sigsaved;
391
392 if (vcpu->sigset_active)
393 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
394
395 if (vcpu->mmio_needed) {
396 if (!vcpu->mmio_is_write)
397 kvm_mips_complete_mmio_load(vcpu, run);
398 vcpu->mmio_needed = 0;
399 }
400
f798217d
JH		 401 lose_fpu(1);
402
044f0f03 403 local_irq_disable();
669e846e
SL		 404 /* Check if we have any exceptions/interrupts pending */
405 kvm_mips_deliver_interrupts(vcpu,
406 kvm_read_c0_guest_cause(vcpu->arch.cop0));
407
ccf73aaf 408 __kvm_guest_enter();
669e846e 409
c4c6f2ca
JH		 410 /* Disable hardware page table walking while in guest */
411 htw_stop();
412
93258604 413 trace_kvm_enter(vcpu);
797179bc 414 r = vcpu->arch.vcpu_run(run, vcpu);
93258604 415 trace_kvm_out(vcpu);
669e846e 416
c4c6f2ca
JH		 417 /* Re-enable HTW before enabling interrupts */
418 htw_start();
419
ccf73aaf 420 __kvm_guest_exit();
669e846e
SL		 421 local_irq_enable();
422
423 if (vcpu->sigset_active)
424 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
425
426 return r;
427}
428
d116e812
DCZ		 429int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
430 struct kvm_mips_interrupt *irq)
669e846e
SL		 431{
432 int intr = (int)irq->irq;
433 struct kvm_vcpu *dvcpu = NULL;
434
435 if (intr == 3 || intr == -3 || intr == 4 || intr == -4)
436 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu,
437 (int)intr);
438
439 if (irq->cpu == -1)
440 dvcpu = vcpu;
441 else
442 dvcpu = vcpu->kvm->vcpus[irq->cpu];
443
444 if (intr == 2 || intr == 3 || intr == 4) {
445 kvm_mips_callbacks->queue_io_int(dvcpu, irq);
446
447 } else if (intr == -2 || intr == -3 || intr == -4) {
448 kvm_mips_callbacks->dequeue_io_int(dvcpu, irq);
449 } else {
450 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__,
451 irq->cpu, irq->irq);
452 return -EINVAL;
453 }
454
455 dvcpu->arch.wait = 0;
456
8577370f
MT		 457 if (swait_active(&dvcpu->wq))
458 swake_up(&dvcpu->wq);
669e846e
SL		 459
460 return 0;
461}
462
d116e812
DCZ		 463int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
464 struct kvm_mp_state *mp_state)
669e846e 465{
ed829857 466 return -ENOIOCTLCMD;
669e846e
SL		 467}
468
d116e812
DCZ		 469int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
470 struct kvm_mp_state *mp_state)
669e846e 471{
ed829857 472 return -ENOIOCTLCMD;
669e846e
SL		 473}
474
4c73fb2b
DD		 475static u64 kvm_mips_get_one_regs[] = {
476 KVM_REG_MIPS_R0,
477 KVM_REG_MIPS_R1,
478 KVM_REG_MIPS_R2,
479 KVM_REG_MIPS_R3,
480 KVM_REG_MIPS_R4,
481 KVM_REG_MIPS_R5,
482 KVM_REG_MIPS_R6,
483 KVM_REG_MIPS_R7,
484 KVM_REG_MIPS_R8,
485 KVM_REG_MIPS_R9,
486 KVM_REG_MIPS_R10,
487 KVM_REG_MIPS_R11,
488 KVM_REG_MIPS_R12,
489 KVM_REG_MIPS_R13,
490 KVM_REG_MIPS_R14,
491 KVM_REG_MIPS_R15,
492 KVM_REG_MIPS_R16,
493 KVM_REG_MIPS_R17,
494 KVM_REG_MIPS_R18,
495 KVM_REG_MIPS_R19,
496 KVM_REG_MIPS_R20,
497 KVM_REG_MIPS_R21,
498 KVM_REG_MIPS_R22,
499 KVM_REG_MIPS_R23,
500 KVM_REG_MIPS_R24,
501 KVM_REG_MIPS_R25,
502 KVM_REG_MIPS_R26,
503 KVM_REG_MIPS_R27,
504 KVM_REG_MIPS_R28,
505 KVM_REG_MIPS_R29,
506 KVM_REG_MIPS_R30,
507 KVM_REG_MIPS_R31,
508
509 KVM_REG_MIPS_HI,
510 KVM_REG_MIPS_LO,
511 KVM_REG_MIPS_PC,
512
513 KVM_REG_MIPS_CP0_INDEX,
514 KVM_REG_MIPS_CP0_CONTEXT,
7767b7d2 515 KVM_REG_MIPS_CP0_USERLOCAL,
4c73fb2b
DD		 516 KVM_REG_MIPS_CP0_PAGEMASK,
517 KVM_REG_MIPS_CP0_WIRED,
16fd5c1d 518 KVM_REG_MIPS_CP0_HWRENA,
4c73fb2b 519 KVM_REG_MIPS_CP0_BADVADDR,
f8be02da 520 KVM_REG_MIPS_CP0_COUNT,
4c73fb2b 521 KVM_REG_MIPS_CP0_ENTRYHI,
f8be02da 522 KVM_REG_MIPS_CP0_COMPARE,
4c73fb2b
DD		 523 KVM_REG_MIPS_CP0_STATUS,
524 KVM_REG_MIPS_CP0_CAUSE,
fb6df0cd 525 KVM_REG_MIPS_CP0_EPC,
1068eaaf 526 KVM_REG_MIPS_CP0_PRID,
4c73fb2b
DD		 527 KVM_REG_MIPS_CP0_CONFIG,
528 KVM_REG_MIPS_CP0_CONFIG1,
529 KVM_REG_MIPS_CP0_CONFIG2,
530 KVM_REG_MIPS_CP0_CONFIG3,
c771607a
JH		 531 KVM_REG_MIPS_CP0_CONFIG4,
532 KVM_REG_MIPS_CP0_CONFIG5,
4c73fb2b 533 KVM_REG_MIPS_CP0_CONFIG7,
f8239342
JH		 534 KVM_REG_MIPS_CP0_ERROREPC,
535
536 KVM_REG_MIPS_COUNT_CTL,
537 KVM_REG_MIPS_COUNT_RESUME,
f74a8e22 538 KVM_REG_MIPS_COUNT_HZ,
4c73fb2b
DD		 539};
540
f5c43bd4
JH		 541static unsigned long kvm_mips_num_regs(struct kvm_vcpu *vcpu)
542{
543 unsigned long ret;
544
545 ret = ARRAY_SIZE(kvm_mips_get_one_regs);
546 ret += kvm_mips_callbacks->num_regs(vcpu);
547
548 return ret;
549}
550
551static int kvm_mips_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices)
552{
553 if (copy_to_user(indices, kvm_mips_get_one_regs,
554 sizeof(kvm_mips_get_one_regs)))
555 return -EFAULT;
556 indices += ARRAY_SIZE(kvm_mips_get_one_regs);
557
558 return kvm_mips_callbacks->copy_reg_indices(vcpu, indices);
559}
560
4c73fb2b
DD		 561static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
562 const struct kvm_one_reg *reg)
563{
4c73fb2b 564 struct mips_coproc *cop0 = vcpu->arch.cop0;
379245cd 565 struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
f8be02da 566 int ret;
4c73fb2b 567 s64 v;
ab86bd60 568 s64 vs[2];
379245cd 569 unsigned int idx;
4c73fb2b
DD		 570
571 switch (reg->id) {
379245cd 572 /* General purpose registers */
4c73fb2b
DD		 573 case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31:
574 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0];
575 break;
576 case KVM_REG_MIPS_HI:
577 v = (long)vcpu->arch.hi;
578 break;
579 case KVM_REG_MIPS_LO:
580 v = (long)vcpu->arch.lo;
581 break;
582 case KVM_REG_MIPS_PC:
583 v = (long)vcpu->arch.pc;
584 break;
585
379245cd
JH		 586 /* Floating point registers */
587 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
588 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
589 return -EINVAL;
590 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
591 /* Odd singles in top of even double when FR=0 */
592 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
593 v = get_fpr32(&fpu->fpr[idx], 0);
594 else
595 v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1);
596 break;
597 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
598 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
599 return -EINVAL;
600 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
601 /* Can't access odd doubles in FR=0 mode */
602 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
603 return -EINVAL;
604 v = get_fpr64(&fpu->fpr[idx], 0);
605 break;
606 case KVM_REG_MIPS_FCR_IR:
607 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
608 return -EINVAL;
609 v = boot_cpu_data.fpu_id;
610 break;
611 case KVM_REG_MIPS_FCR_CSR:
612 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
613 return -EINVAL;
614 v = fpu->fcr31;
615 break;
616
ab86bd60
JH		 617 /* MIPS SIMD Architecture (MSA) registers */
618 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
619 if (!kvm_mips_guest_has_msa(&vcpu->arch))
620 return -EINVAL;
621 /* Can't access MSA registers in FR=0 mode */
622 if (!(kvm_read_c0_guest_status(cop0) & ST0_FR))
623 return -EINVAL;
624 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
625#ifdef CONFIG_CPU_LITTLE_ENDIAN
626 /* least significant byte first */
627 vs[0] = get_fpr64(&fpu->fpr[idx], 0);
628 vs[1] = get_fpr64(&fpu->fpr[idx], 1);
629#else
630 /* most significant byte first */
631 vs[0] = get_fpr64(&fpu->fpr[idx], 1);
632 vs[1] = get_fpr64(&fpu->fpr[idx], 0);
633#endif
634 break;
635 case KVM_REG_MIPS_MSA_IR:
636 if (!kvm_mips_guest_has_msa(&vcpu->arch))
637 return -EINVAL;
638 v = boot_cpu_data.msa_id;
639 break;
640 case KVM_REG_MIPS_MSA_CSR:
641 if (!kvm_mips_guest_has_msa(&vcpu->arch))
642 return -EINVAL;
643 v = fpu->msacsr;
644 break;
645
379245cd 646 /* Co-processor 0 registers */
4c73fb2b
DD		 647 case KVM_REG_MIPS_CP0_INDEX:
648 v = (long)kvm_read_c0_guest_index(cop0);
649 break;
650 case KVM_REG_MIPS_CP0_CONTEXT:
651 v = (long)kvm_read_c0_guest_context(cop0);
652 break;
7767b7d2
JH		 653 case KVM_REG_MIPS_CP0_USERLOCAL:
654 v = (long)kvm_read_c0_guest_userlocal(cop0);
655 break;
4c73fb2b
DD		 656 case KVM_REG_MIPS_CP0_PAGEMASK:
657 v = (long)kvm_read_c0_guest_pagemask(cop0);
658 break;
659 case KVM_REG_MIPS_CP0_WIRED:
660 v = (long)kvm_read_c0_guest_wired(cop0);
661 break;
16fd5c1d
JH		 662 case KVM_REG_MIPS_CP0_HWRENA:
663 v = (long)kvm_read_c0_guest_hwrena(cop0);
664 break;
4c73fb2b
DD		 665 case KVM_REG_MIPS_CP0_BADVADDR:
666 v = (long)kvm_read_c0_guest_badvaddr(cop0);
667 break;
668 case KVM_REG_MIPS_CP0_ENTRYHI:
669 v = (long)kvm_read_c0_guest_entryhi(cop0);
670 break;
f8be02da
JH		 671 case KVM_REG_MIPS_CP0_COMPARE:
672 v = (long)kvm_read_c0_guest_compare(cop0);
673 break;
4c73fb2b
DD		 674 case KVM_REG_MIPS_CP0_STATUS:
675 v = (long)kvm_read_c0_guest_status(cop0);
676 break;
677 case KVM_REG_MIPS_CP0_CAUSE:
678 v = (long)kvm_read_c0_guest_cause(cop0);
679 break;
fb6df0cd
JH		 680 case KVM_REG_MIPS_CP0_EPC:
681 v = (long)kvm_read_c0_guest_epc(cop0);
682 break;
1068eaaf
JH		 683 case KVM_REG_MIPS_CP0_PRID:
684 v = (long)kvm_read_c0_guest_prid(cop0);
685 break;
4c73fb2b
DD		 686 case KVM_REG_MIPS_CP0_CONFIG:
687 v = (long)kvm_read_c0_guest_config(cop0);
688 break;
689 case KVM_REG_MIPS_CP0_CONFIG1:
690 v = (long)kvm_read_c0_guest_config1(cop0);
691 break;
692 case KVM_REG_MIPS_CP0_CONFIG2:
693 v = (long)kvm_read_c0_guest_config2(cop0);
694 break;
695 case KVM_REG_MIPS_CP0_CONFIG3:
696 v = (long)kvm_read_c0_guest_config3(cop0);
697 break;
c771607a
JH		 698 case KVM_REG_MIPS_CP0_CONFIG4:
699 v = (long)kvm_read_c0_guest_config4(cop0);
700 break;
701 case KVM_REG_MIPS_CP0_CONFIG5:
702 v = (long)kvm_read_c0_guest_config5(cop0);
703 break;
4c73fb2b
DD		 704 case KVM_REG_MIPS_CP0_CONFIG7:
705 v = (long)kvm_read_c0_guest_config7(cop0);
706 break;
e93d4c15
JH		 707 case KVM_REG_MIPS_CP0_ERROREPC:
708 v = (long)kvm_read_c0_guest_errorepc(cop0);
709 break;
f8be02da 710 /* registers to be handled specially */
cc68d22f 711 default:
f8be02da
JH		 712 ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v);
713 if (ret)
714 return ret;
715 break;
4c73fb2b 716 }
681865d4
DD		 717 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
718 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
d116e812 719
681865d4
DD		 720 return put_user(v, uaddr64);
721 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
722 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
723 u32 v32 = (u32)v;
d116e812 724
681865d4 725 return put_user(v32, uaddr32);
ab86bd60
JH		 726 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
727 void __user *uaddr = (void __user *)(long)reg->addr;
728
0178fd7d 729 return copy_to_user(uaddr, vs, 16) ? -EFAULT : 0;
681865d4
DD		 730 } else {
731 return -EINVAL;
732 }
4c73fb2b
DD		 733}
734
735static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
736 const struct kvm_one_reg *reg)
737{
4c73fb2b 738 struct mips_coproc *cop0 = vcpu->arch.cop0;
379245cd
JH		 739 struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
740 s64 v;
ab86bd60 741 s64 vs[2];
379245cd 742 unsigned int idx;
4c73fb2b 743
681865d4
DD		 744 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
745 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
746
747 if (get_user(v, uaddr64) != 0)
748 return -EFAULT;
749 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
750 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
751 s32 v32;
752
753 if (get_user(v32, uaddr32) != 0)
754 return -EFAULT;
755 v = (s64)v32;
ab86bd60
JH		 756 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
757 void __user *uaddr = (void __user *)(long)reg->addr;
758
0178fd7d 759 return copy_from_user(vs, uaddr, 16) ? -EFAULT : 0;
681865d4
DD		 760 } else {
761 return -EINVAL;
762 }
4c73fb2b
DD		 763
764 switch (reg->id) {
379245cd 765 /* General purpose registers */
4c73fb2b
DD		 766 case KVM_REG_MIPS_R0:
767 /* Silently ignore requests to set $0 */
768 break;
769 case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31:
770 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v;
771 break;
772 case KVM_REG_MIPS_HI:
773 vcpu->arch.hi = v;
774 break;
775 case KVM_REG_MIPS_LO:
776 vcpu->arch.lo = v;
777 break;
778 case KVM_REG_MIPS_PC:
779 vcpu->arch.pc = v;
780 break;
781
379245cd
JH		 782 /* Floating point registers */
783 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
784 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
785 return -EINVAL;
786 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
787 /* Odd singles in top of even double when FR=0 */
788 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
789 set_fpr32(&fpu->fpr[idx], 0, v);
790 else
791 set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v);
792 break;
793 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
794 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
795 return -EINVAL;
796 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
797 /* Can't access odd doubles in FR=0 mode */
798 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
799 return -EINVAL;
800 set_fpr64(&fpu->fpr[idx], 0, v);
801 break;
802 case KVM_REG_MIPS_FCR_IR:
803 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
804 return -EINVAL;
805 /* Read-only */
806 break;
807 case KVM_REG_MIPS_FCR_CSR:
808 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
809 return -EINVAL;
810 fpu->fcr31 = v;
811 break;
812
ab86bd60
JH		 813 /* MIPS SIMD Architecture (MSA) registers */
814 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
815 if (!kvm_mips_guest_has_msa(&vcpu->arch))
816 return -EINVAL;
817 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
818#ifdef CONFIG_CPU_LITTLE_ENDIAN
819 /* least significant byte first */
820 set_fpr64(&fpu->fpr[idx], 0, vs[0]);
821 set_fpr64(&fpu->fpr[idx], 1, vs[1]);
822#else
823 /* most significant byte first */
824 set_fpr64(&fpu->fpr[idx], 1, vs[0]);
825 set_fpr64(&fpu->fpr[idx], 0, vs[1]);
826#endif
827 break;
828 case KVM_REG_MIPS_MSA_IR:
829 if (!kvm_mips_guest_has_msa(&vcpu->arch))
830 return -EINVAL;
831 /* Read-only */
832 break;
833 case KVM_REG_MIPS_MSA_CSR:
834 if (!kvm_mips_guest_has_msa(&vcpu->arch))
835 return -EINVAL;
836 fpu->msacsr = v;
837 break;
838
379245cd 839 /* Co-processor 0 registers */
4c73fb2b
DD		 840 case KVM_REG_MIPS_CP0_INDEX:
841 kvm_write_c0_guest_index(cop0, v);
842 break;
843 case KVM_REG_MIPS_CP0_CONTEXT:
844 kvm_write_c0_guest_context(cop0, v);
845 break;
7767b7d2
JH		 846 case KVM_REG_MIPS_CP0_USERLOCAL:
847 kvm_write_c0_guest_userlocal(cop0, v);
848 break;
4c73fb2b
DD		 849 case KVM_REG_MIPS_CP0_PAGEMASK:
850 kvm_write_c0_guest_pagemask(cop0, v);
851 break;
852 case KVM_REG_MIPS_CP0_WIRED:
853 kvm_write_c0_guest_wired(cop0, v);
854 break;
16fd5c1d
JH		 855 case KVM_REG_MIPS_CP0_HWRENA:
856 kvm_write_c0_guest_hwrena(cop0, v);
857 break;
4c73fb2b
DD		 858 case KVM_REG_MIPS_CP0_BADVADDR:
859 kvm_write_c0_guest_badvaddr(cop0, v);
860 break;
861 case KVM_REG_MIPS_CP0_ENTRYHI:
862 kvm_write_c0_guest_entryhi(cop0, v);
863 break;
864 case KVM_REG_MIPS_CP0_STATUS:
865 kvm_write_c0_guest_status(cop0, v);
866 break;
fb6df0cd
JH		 867 case KVM_REG_MIPS_CP0_EPC:
868 kvm_write_c0_guest_epc(cop0, v);
869 break;
1068eaaf
JH		 870 case KVM_REG_MIPS_CP0_PRID:
871 kvm_write_c0_guest_prid(cop0, v);
872 break;
4c73fb2b
DD		 873 case KVM_REG_MIPS_CP0_ERROREPC:
874 kvm_write_c0_guest_errorepc(cop0, v);
875 break;
f8be02da 876 /* registers to be handled specially */
4c73fb2b 877 default:
cc68d22f 878 return kvm_mips_callbacks->set_one_reg(vcpu, reg, v);
4c73fb2b
DD		 879 }
880 return 0;
881}
882
5fafd874
JH		 883static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
884 struct kvm_enable_cap *cap)
885{
886 int r = 0;
887
888 if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap))
889 return -EINVAL;
890 if (cap->flags)
891 return -EINVAL;
892 if (cap->args[0])
893 return -EINVAL;
894
895 switch (cap->cap) {
896 case KVM_CAP_MIPS_FPU:
897 vcpu->arch.fpu_enabled = true;
898 break;
d952bd07
JH		 899 case KVM_CAP_MIPS_MSA:
900 vcpu->arch.msa_enabled = true;
901 break;
5fafd874
JH		 902 default:
903 r = -EINVAL;
904 break;
905 }
906
907 return r;
908}
909
d116e812
DCZ		 910long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl,
911 unsigned long arg)
669e846e
SL		 912{
913 struct kvm_vcpu *vcpu = filp->private_data;
914 void __user *argp = (void __user *)arg;
915 long r;
669e846e
SL		 916
917 switch (ioctl) {
4c73fb2b
DD		 918 case KVM_SET_ONE_REG:
919 case KVM_GET_ONE_REG: {
920 struct kvm_one_reg reg;
d116e812 921
4c73fb2b
DD		 922 if (copy_from_user(&reg, argp, sizeof(reg)))
923 return -EFAULT;
924 if (ioctl == KVM_SET_ONE_REG)
925 return kvm_mips_set_reg(vcpu, &reg);
926 else
927 return kvm_mips_get_reg(vcpu, &reg);
928 }
929 case KVM_GET_REG_LIST: {
930 struct kvm_reg_list __user *user_list = argp;
4c73fb2b
DD		 931 struct kvm_reg_list reg_list;
932 unsigned n;
933
934 if (copy_from_user(&reg_list, user_list, sizeof(reg_list)))
935 return -EFAULT;
936 n = reg_list.n;
f5c43bd4 937 reg_list.n = kvm_mips_num_regs(vcpu);
4c73fb2b
DD		 938 if (copy_to_user(user_list, &reg_list, sizeof(reg_list)))
939 return -EFAULT;
940 if (n < reg_list.n)
941 return -E2BIG;
f5c43bd4 942 return kvm_mips_copy_reg_indices(vcpu, user_list->reg);
4c73fb2b 943 }
669e846e
SL		 944 case KVM_NMI:
945 /* Treat the NMI as a CPU reset */
946 r = kvm_mips_reset_vcpu(vcpu);
947 break;
948 case KVM_INTERRUPT:
949 {
950 struct kvm_mips_interrupt irq;
d116e812 951
669e846e
SL		 952 r = -EFAULT;
953 if (copy_from_user(&irq, argp, sizeof(irq)))
954 goto out;
955
669e846e
SL		 956 kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__,
957 irq.irq);
958
959 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
960 break;
961 }
5fafd874
JH		 962 case KVM_ENABLE_CAP: {
963 struct kvm_enable_cap cap;
964
965 r = -EFAULT;
966 if (copy_from_user(&cap, argp, sizeof(cap)))
967 goto out;
968 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
969 break;
970 }
669e846e 971 default:
4c73fb2b 972 r = -ENOIOCTLCMD;
669e846e
SL		 973 }
974
975out:
976 return r;
977}
978
d116e812 979/* Get (and clear) the dirty memory log for a memory slot. */
669e846e
SL		 980int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
981{
9f6b8029 982 struct kvm_memslots *slots;
669e846e
SL		 983 struct kvm_memory_slot *memslot;
984 unsigned long ga, ga_end;
985 int is_dirty = 0;
986 int r;
987 unsigned long n;
988
989 mutex_lock(&kvm->slots_lock);
990
991 r = kvm_get_dirty_log(kvm, log, &is_dirty);
992 if (r)
993 goto out;
994
995 /* If nothing is dirty, don't bother messing with page tables. */
996 if (is_dirty) {
9f6b8029
PB		 997 slots = kvm_memslots(kvm);
998 memslot = id_to_memslot(slots, log->slot);
669e846e
SL		 999
1000 ga = memslot->base_gfn << PAGE_SHIFT;
1001 ga_end = ga + (memslot->npages << PAGE_SHIFT);
1002
6ad78a5c
DCZ		 1003 kvm_info("%s: dirty, ga: %#lx, ga_end %#lx\n", __func__, ga,
1004 ga_end);
669e846e
SL		 1005
1006 n = kvm_dirty_bitmap_bytes(memslot);
1007 memset(memslot->dirty_bitmap, 0, n);
1008 }
1009
1010 r = 0;
1011out:
1012 mutex_unlock(&kvm->slots_lock);
1013 return r;
1014
1015}
1016
1017long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
1018{
1019 long r;
1020
1021 switch (ioctl) {
1022 default:
ed829857 1023 r = -ENOIOCTLCMD;
669e846e
SL		 1024 }
1025
1026 return r;
1027}
1028
1029int kvm_arch_init(void *opaque)
1030{
669e846e
SL		 1031 if (kvm_mips_callbacks) {
1032 kvm_err("kvm: module already exists\n");
1033 return -EEXIST;
1034 }
1035
d98403a5 1036 return kvm_mips_emulation_init(&kvm_mips_callbacks);
669e846e
SL		 1037}
1038
1039void kvm_arch_exit(void)
1040{
1041 kvm_mips_callbacks = NULL;
1042}
1043
d116e812
DCZ		 1044int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
1045 struct kvm_sregs *sregs)
669e846e 1046{
ed829857 1047 return -ENOIOCTLCMD;
669e846e
SL		 1048}
1049
d116e812
DCZ		 1050int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
1051 struct kvm_sregs *sregs)
669e846e 1052{
ed829857 1053 return -ENOIOCTLCMD;
669e846e
SL		 1054}
1055
31928aa5 1056void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
669e846e 1057{
669e846e
SL		 1058}
1059
1060int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1061{
ed829857 1062 return -ENOIOCTLCMD;
669e846e
SL		 1063}
1064
1065int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1066{
ed829857 1067 return -ENOIOCTLCMD;
669e846e
SL		 1068}
1069
1070int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
1071{
1072 return VM_FAULT_SIGBUS;
1073}
1074
784aa3d7 1075int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
669e846e
SL		 1076{
1077 int r;
1078
1079 switch (ext) {
4c73fb2b 1080 case KVM_CAP_ONE_REG:
5fafd874 1081 case KVM_CAP_ENABLE_CAP:
4c73fb2b
DD		 1082 r = 1;
1083 break;
669e846e
SL		 1084 case KVM_CAP_COALESCED_MMIO:
1085 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1086 break;
5fafd874 1087 case KVM_CAP_MIPS_FPU:
556f2a52
JH		 1088 /* We don't handle systems with inconsistent cpu_has_fpu */
1089 r = !!raw_cpu_has_fpu;
5fafd874 1090 break;
d952bd07
JH		 1091 case KVM_CAP_MIPS_MSA:
1092 /*
1093 * We don't support MSA vector partitioning yet:
1094 * 1) It would require explicit support which can't be tested
1095 * yet due to lack of support in current hardware.
1096 * 2) It extends the state that would need to be saved/restored
1097 * by e.g. QEMU for migration.
1098 *
1099 * When vector partitioning hardware becomes available, support
1100 * could be added by requiring a flag when enabling
1101 * KVM_CAP_MIPS_MSA capability to indicate that userland knows
1102 * to save/restore the appropriate extra state.
1103 */
1104 r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF);
1105 break;
669e846e
SL		 1106 default:
1107 r = 0;
1108 break;
1109 }
1110 return r;
669e846e
SL		 1111}
1112
1113int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
1114{
1115 return kvm_mips_pending_timer(vcpu);
1116}
1117
1118int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu)
1119{
1120 int i;
1121 struct mips_coproc *cop0;
1122
1123 if (!vcpu)
1124 return -1;
1125
6ad78a5c
DCZ		 1126 kvm_debug("VCPU Register Dump:\n");
1127 kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc);
1128 kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions);
669e846e
SL		 1129
1130 for (i = 0; i < 32; i += 4) {
6ad78a5c 1131 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i,
669e846e
SL		 1132 vcpu->arch.gprs[i],
1133 vcpu->arch.gprs[i + 1],
1134 vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]);
1135 }
6ad78a5c
DCZ		 1136 kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi);
1137 kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo);
669e846e
SL		 1138
1139 cop0 = vcpu->arch.cop0;
6ad78a5c
DCZ		 1140 kvm_debug("\tStatus: 0x%08lx, Cause: 0x%08lx\n",
1141 kvm_read_c0_guest_status(cop0),
1142 kvm_read_c0_guest_cause(cop0));
669e846e 1143
6ad78a5c 1144 kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0));
669e846e
SL		 1145
1146 return 0;
1147}
1148
1149int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1150{
1151 int i;
1152
8d17dd04 1153 for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
bf32ebf6 1154 vcpu->arch.gprs[i] = regs->gpr[i];
8d17dd04 1155 vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */
669e846e
SL		 1156 vcpu->arch.hi = regs->hi;
1157 vcpu->arch.lo = regs->lo;
1158 vcpu->arch.pc = regs->pc;
1159
4c73fb2b 1160 return 0;
669e846e
SL		 1161}
1162
1163int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1164{
1165 int i;
1166
8d17dd04 1167 for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
bf32ebf6 1168 regs->gpr[i] = vcpu->arch.gprs[i];
669e846e
SL		 1169
1170 regs->hi = vcpu->arch.hi;
1171 regs->lo = vcpu->arch.lo;
1172 regs->pc = vcpu->arch.pc;
1173
4c73fb2b 1174 return 0;
669e846e
SL		 1175}
1176
0fae34f4 1177static void kvm_mips_comparecount_func(unsigned long data)
669e846e
SL		 1178{
1179 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
1180
1181 kvm_mips_callbacks->queue_timer_int(vcpu);
1182
1183 vcpu->arch.wait = 0;
8577370f
MT		 1184 if (swait_active(&vcpu->wq))
1185 swake_up(&vcpu->wq);
669e846e
SL		 1186}
1187
d116e812 1188/* low level hrtimer wake routine */
0fae34f4 1189static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer)
669e846e
SL		 1190{
1191 struct kvm_vcpu *vcpu;
1192
1193 vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer);
1194 kvm_mips_comparecount_func((unsigned long) vcpu);
e30492bb 1195 return kvm_mips_count_timeout(vcpu);
669e846e
SL		 1196}
1197
1198int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
1199{
1200 kvm_mips_callbacks->vcpu_init(vcpu);
1201 hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC,
1202 HRTIMER_MODE_REL);
1203 vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup;
669e846e
SL		 1204 return 0;
1205}
1206
d116e812
DCZ		 1207int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
1208 struct kvm_translation *tr)
669e846e
SL		 1209{
1210 return 0;
1211}
1212
1213/* Initial guest state */
1214int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
1215{
1216 return kvm_mips_callbacks->vcpu_setup(vcpu);
1217}
1218
d116e812 1219static void kvm_mips_set_c0_status(void)
669e846e 1220{
8cffd197 1221 u32 status = read_c0_status();
669e846e 1222
669e846e
SL		 1223 if (cpu_has_dsp)
1224 status |= (ST0_MX);
1225
1226 write_c0_status(status);
1227 ehb();
1228}
1229
1230/*
1231 * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
1232 */
1233int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu)
1234{
8cffd197
JH		 1235 u32 cause = vcpu->arch.host_cp0_cause;
1236 u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
1237 u32 __user *opc = (u32 __user *) vcpu->arch.pc;
669e846e
SL		 1238 unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
1239 enum emulation_result er = EMULATE_DONE;
1240 int ret = RESUME_GUEST;
1241
c4c6f2ca
JH		 1242 /* re-enable HTW before enabling interrupts */
1243 htw_start();
1244
669e846e
SL		 1245 /* Set a default exit reason */
1246 run->exit_reason = KVM_EXIT_UNKNOWN;
1247 run->ready_for_interrupt_injection = 1;
1248
d116e812
DCZ		 1249 /*
1250 * Set the appropriate status bits based on host CPU features,
1251 * before we hit the scheduler
1252 */
669e846e
SL		 1253 kvm_mips_set_c0_status();
1254
1255 local_irq_enable();
1256
1257 kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n",
1258 cause, opc, run, vcpu);
1e09e86a 1259 trace_kvm_exit(vcpu, exccode);
669e846e 1260
d116e812
DCZ		 1261 /*
1262 * Do a privilege check, if in UM most of these exit conditions end up
669e846e
SL		 1263 * causing an exception to be delivered to the Guest Kernel
1264 */
1265 er = kvm_mips_check_privilege(cause, opc, run, vcpu);
1266 if (er == EMULATE_PRIV_FAIL) {
1267 goto skip_emul;
1268 } else if (er == EMULATE_FAIL) {
1269 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1270 ret = RESUME_HOST;
1271 goto skip_emul;
1272 }
1273
1274 switch (exccode) {
16d100db
JH		 1275 case EXCCODE_INT:
1276 kvm_debug("[%d]EXCCODE_INT @ %p\n", vcpu->vcpu_id, opc);
669e846e
SL		 1277
1278 ++vcpu->stat.int_exits;
669e846e 1279
d116e812 1280 if (need_resched())
669e846e 1281 cond_resched();
669e846e
SL		 1282
1283 ret = RESUME_GUEST;
1284 break;
1285
16d100db
JH		 1286 case EXCCODE_CPU:
1287 kvm_debug("EXCCODE_CPU: @ PC: %p\n", opc);
669e846e
SL		 1288
1289 ++vcpu->stat.cop_unusable_exits;
669e846e
SL		 1290 ret = kvm_mips_callbacks->handle_cop_unusable(vcpu);
1291 /* XXXKYMA: Might need to return to user space */
d116e812 1292 if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN)
669e846e 1293 ret = RESUME_HOST;
669e846e
SL		 1294 break;
1295
16d100db 1296 case EXCCODE_MOD:
669e846e 1297 ++vcpu->stat.tlbmod_exits;
669e846e
SL		 1298 ret = kvm_mips_callbacks->handle_tlb_mod(vcpu);
1299 break;
1300
16d100db 1301 case EXCCODE_TLBS:
d116e812
DCZ		 1302 kvm_debug("TLB ST fault: cause %#x, status %#lx, PC: %p, BadVaddr: %#lx\n",
1303 cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc,
1304 badvaddr);
669e846e
SL		 1305
1306 ++vcpu->stat.tlbmiss_st_exits;
669e846e
SL		 1307 ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu);
1308 break;
1309
16d100db 1310 case EXCCODE_TLBL:
669e846e
SL		 1311 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n",
1312 cause, opc, badvaddr);
1313
1314 ++vcpu->stat.tlbmiss_ld_exits;
669e846e
SL		 1315 ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu);
1316 break;
1317
16d100db 1318 case EXCCODE_ADES:
669e846e 1319 ++vcpu->stat.addrerr_st_exits;
669e846e
SL		 1320 ret = kvm_mips_callbacks->handle_addr_err_st(vcpu);
1321 break;
1322
16d100db 1323 case EXCCODE_ADEL:
669e846e 1324 ++vcpu->stat.addrerr_ld_exits;
669e846e
SL		 1325 ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu);
1326 break;
1327
16d100db 1328 case EXCCODE_SYS:
669e846e 1329 ++vcpu->stat.syscall_exits;
669e846e
SL		 1330 ret = kvm_mips_callbacks->handle_syscall(vcpu);
1331 break;
1332
16d100db 1333 case EXCCODE_RI:
669e846e 1334 ++vcpu->stat.resvd_inst_exits;
669e846e
SL		 1335 ret = kvm_mips_callbacks->handle_res_inst(vcpu);
1336 break;
1337
16d100db 1338 case EXCCODE_BP:
669e846e 1339 ++vcpu->stat.break_inst_exits;
669e846e
SL		 1340 ret = kvm_mips_callbacks->handle_break(vcpu);
1341 break;
1342
16d100db 1343 case EXCCODE_TR:
0a560427 1344 ++vcpu->stat.trap_inst_exits;
0a560427
JH		 1345 ret = kvm_mips_callbacks->handle_trap(vcpu);
1346 break;
1347
16d100db 1348 case EXCCODE_MSAFPE:
c2537ed9 1349 ++vcpu->stat.msa_fpe_exits;
c2537ed9
JH		 1350 ret = kvm_mips_callbacks->handle_msa_fpe(vcpu);
1351 break;
1352
16d100db 1353 case EXCCODE_FPE:
1c0cd66a 1354 ++vcpu->stat.fpe_exits;
1c0cd66a
JH		 1355 ret = kvm_mips_callbacks->handle_fpe(vcpu);
1356 break;
1357
16d100db 1358 case EXCCODE_MSADIS:
c2537ed9 1359 ++vcpu->stat.msa_disabled_exits;
98119ad5
JH		 1360 ret = kvm_mips_callbacks->handle_msa_disabled(vcpu);
1361 break;
1362
669e846e 1363 default:
d116e812
DCZ		 1364 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x BadVaddr: %#lx Status: %#lx\n",
1365 exccode, opc, kvm_get_inst(opc, vcpu), badvaddr,
1366 kvm_read_c0_guest_status(vcpu->arch.cop0));
669e846e
SL		 1367 kvm_arch_vcpu_dump_regs(vcpu);
1368 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1369 ret = RESUME_HOST;
1370 break;
1371
1372 }
1373
1374skip_emul:
1375 local_irq_disable();
1376
1377 if (er == EMULATE_DONE && !(ret & RESUME_HOST))
1378 kvm_mips_deliver_interrupts(vcpu, cause);
1379
1380 if (!(ret & RESUME_HOST)) {
d116e812 1381 /* Only check for signals if not already exiting to userspace */
669e846e
SL		 1382 if (signal_pending(current)) {
1383 run->exit_reason = KVM_EXIT_INTR;
1384 ret = (-EINTR << 2) | RESUME_HOST;
1385 ++vcpu->stat.signal_exits;
1e09e86a 1386 trace_kvm_exit(vcpu, KVM_TRACE_EXIT_SIGNAL);
669e846e
SL		 1387 }
1388 }
1389
98e91b84 1390 if (ret == RESUME_GUEST) {
93258604
JH		 1391 trace_kvm_reenter(vcpu);
1392
98e91b84 1393 /*
539cb89f
JH		 1394 * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context
1395 * is live), restore FCR31 / MSACSR.
98e91b84
JH		 1396 *
1397 * This should be before returning to the guest exception
539cb89f
JH		 1398 * vector, as it may well cause an [MSA] FP exception if there
1399 * are pending exception bits unmasked. (see
98e91b84
JH		 1400 * kvm_mips_csr_die_notifier() for how that is handled).
1401 */
1402 if (kvm_mips_guest_has_fpu(&vcpu->arch) &&
1403 read_c0_status() & ST0_CU1)
1404 __kvm_restore_fcsr(&vcpu->arch);
539cb89f
JH		 1405
1406 if (kvm_mips_guest_has_msa(&vcpu->arch) &&
1407 read_c0_config5() & MIPS_CONF5_MSAEN)
1408 __kvm_restore_msacsr(&vcpu->arch);
98e91b84
JH		 1409 }
1410
c4c6f2ca
JH		 1411 /* Disable HTW before returning to guest or host */
1412 htw_stop();
1413
669e846e
SL		 1414 return ret;
1415}
1416
98e91b84
JH		 1417/* Enable FPU for guest and restore context */
1418void kvm_own_fpu(struct kvm_vcpu *vcpu)
1419{
1420 struct mips_coproc *cop0 = vcpu->arch.cop0;
1421 unsigned int sr, cfg5;
1422
1423 preempt_disable();
1424
539cb89f
JH		 1425 sr = kvm_read_c0_guest_status(cop0);
1426
1427 /*
1428 * If MSA state is already live, it is undefined how it interacts with
1429 * FR=0 FPU state, and we don't want to hit reserved instruction
1430 * exceptions trying to save the MSA state later when CU=1 && FR=1, so
1431 * play it safe and save it first.
1432 *
1433 * In theory we shouldn't ever hit this case since kvm_lose_fpu() should
1434 * get called when guest CU1 is set, however we can't trust the guest
1435 * not to clobber the status register directly via the commpage.
1436 */
1437 if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) &&
f943176a 1438 vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA)
539cb89f
JH		 1439 kvm_lose_fpu(vcpu);
1440
98e91b84
JH		 1441 /*
1442 * Enable FPU for guest
1443 * We set FR and FRE according to guest context
1444 */
98e91b84
JH		 1445 change_c0_status(ST0_CU1 | ST0_FR, sr);
1446 if (cpu_has_fre) {
1447 cfg5 = kvm_read_c0_guest_config5(cop0);
1448 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1449 }
1450 enable_fpu_hazard();
1451
1452 /* If guest FPU state not active, restore it now */
f943176a 1453 if (!(vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)) {
98e91b84 1454 __kvm_restore_fpu(&vcpu->arch);
f943176a 1455 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
04ebebf4
JH		 1456 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_FPU);
1457 } else {
1458 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_FPU);
98e91b84
JH		 1459 }
1460
1461 preempt_enable();
1462}
1463
539cb89f
JH		 1464#ifdef CONFIG_CPU_HAS_MSA
1465/* Enable MSA for guest and restore context */
1466void kvm_own_msa(struct kvm_vcpu *vcpu)
1467{
1468 struct mips_coproc *cop0 = vcpu->arch.cop0;
1469 unsigned int sr, cfg5;
1470
1471 preempt_disable();
1472
1473 /*
1474 * Enable FPU if enabled in guest, since we're restoring FPU context
1475 * anyway. We set FR and FRE according to guest context.
1476 */
1477 if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
1478 sr = kvm_read_c0_guest_status(cop0);
1479
1480 /*
1481 * If FR=0 FPU state is already live, it is undefined how it
1482 * interacts with MSA state, so play it safe and save it first.
1483 */
1484 if (!(sr & ST0_FR) &&
f943176a
JH		 1485 (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU |
1486 KVM_MIPS_AUX_MSA)) == KVM_MIPS_AUX_FPU)
539cb89f
JH		 1487 kvm_lose_fpu(vcpu);
1488
1489 change_c0_status(ST0_CU1 | ST0_FR, sr);
1490 if (sr & ST0_CU1 && cpu_has_fre) {
1491 cfg5 = kvm_read_c0_guest_config5(cop0);
1492 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1493 }
1494 }
1495
1496 /* Enable MSA for guest */
1497 set_c0_config5(MIPS_CONF5_MSAEN);
1498 enable_fpu_hazard();
1499
f943176a
JH		 1500 switch (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA)) {
1501 case KVM_MIPS_AUX_FPU:
539cb89f
JH		 1502 /*
1503 * Guest FPU state already loaded, only restore upper MSA state
1504 */
1505 __kvm_restore_msa_upper(&vcpu->arch);
f943176a 1506 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
04ebebf4 1507 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_MSA);
539cb89f
JH		 1508 break;
1509 case 0:
1510 /* Neither FPU or MSA already active, restore full MSA state */
1511 __kvm_restore_msa(&vcpu->arch);
f943176a 1512 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
539cb89f 1513 if (kvm_mips_guest_has_fpu(&vcpu->arch))
f943176a 1514 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
04ebebf4
JH		 1515 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE,
1516 KVM_TRACE_AUX_FPU_MSA);
539cb89f
JH		 1517 break;
1518 default:
04ebebf4 1519 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_MSA);
539cb89f
JH		 1520 break;
1521 }
1522
1523 preempt_enable();
1524}
1525#endif
1526
1527/* Drop FPU & MSA without saving it */
98e91b84
JH		 1528void kvm_drop_fpu(struct kvm_vcpu *vcpu)
1529{
1530 preempt_disable();
f943176a 1531 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
539cb89f 1532 disable_msa();
04ebebf4 1533 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_MSA);
f943176a 1534 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_MSA;
539cb89f 1535 }
f943176a 1536 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
98e91b84 1537 clear_c0_status(ST0_CU1 | ST0_FR);
04ebebf4 1538 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_FPU);
f943176a 1539 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
98e91b84
JH		 1540 }
1541 preempt_enable();
1542}
1543
539cb89f 1544/* Save and disable FPU & MSA */
98e91b84
JH		 1545void kvm_lose_fpu(struct kvm_vcpu *vcpu)
1546{
1547 /*
539cb89f
JH		 1548 * FPU & MSA get disabled in root context (hardware) when it is disabled
1549 * in guest context (software), but the register state in the hardware
1550 * may still be in use. This is why we explicitly re-enable the hardware
98e91b84
JH		 1551 * before saving.
1552 */
1553
1554 preempt_disable();
f943176a 1555 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
539cb89f
JH		 1556 set_c0_config5(MIPS_CONF5_MSAEN);
1557 enable_fpu_hazard();
1558
1559 __kvm_save_msa(&vcpu->arch);
04ebebf4 1560 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU_MSA);
539cb89f
JH		 1561
1562 /* Disable MSA & FPU */
1563 disable_msa();
f943176a 1564 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
539cb89f 1565 clear_c0_status(ST0_CU1 | ST0_FR);
4ac33429
JH		 1566 disable_fpu_hazard();
1567 }
f943176a
JH		 1568 vcpu->arch.aux_inuse &= ~(KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA);
1569 } else if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
98e91b84
JH		 1570 set_c0_status(ST0_CU1);
1571 enable_fpu_hazard();
1572
1573 __kvm_save_fpu(&vcpu->arch);
f943176a 1574 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
04ebebf4 1575 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU);
98e91b84
JH		 1576
1577 /* Disable FPU */
1578 clear_c0_status(ST0_CU1 | ST0_FR);
4ac33429 1579 disable_fpu_hazard();
98e91b84
JH		 1580 }
1581 preempt_enable();
1582}
1583
1584/*
539cb89f
JH		 1585 * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are
1586 * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP
1587 * exception if cause bits are set in the value being written.
98e91b84
JH		 1588 */
1589static int kvm_mips_csr_die_notify(struct notifier_block *self,
1590 unsigned long cmd, void *ptr)
1591{
1592 struct die_args *args = (struct die_args *)ptr;
1593 struct pt_regs *regs = args->regs;
1594 unsigned long pc;
1595
539cb89f
JH		 1596 /* Only interested in FPE and MSAFPE */
1597 if (cmd != DIE_FP && cmd != DIE_MSAFP)
98e91b84
JH		 1598 return NOTIFY_DONE;
1599
1600 /* Return immediately if guest context isn't active */
1601 if (!(current->flags & PF_VCPU))
1602 return NOTIFY_DONE;
1603
1604 /* Should never get here from user mode */
1605 BUG_ON(user_mode(regs));
1606
1607 pc = instruction_pointer(regs);
1608 switch (cmd) {
1609 case DIE_FP:
1610 /* match 2nd instruction in __kvm_restore_fcsr */
1611 if (pc != (unsigned long)&__kvm_restore_fcsr + 4)
1612 return NOTIFY_DONE;
1613 break;
539cb89f
JH		 1614 case DIE_MSAFP:
1615 /* match 2nd/3rd instruction in __kvm_restore_msacsr */
1616 if (!cpu_has_msa ||
1617 pc < (unsigned long)&__kvm_restore_msacsr + 4 ||
1618 pc > (unsigned long)&__kvm_restore_msacsr + 8)
1619 return NOTIFY_DONE;
1620 break;
98e91b84
JH		 1621 }
1622
1623 /* Move PC forward a little and continue executing */
1624 instruction_pointer(regs) += 4;
1625
1626 return NOTIFY_STOP;
1627}
1628
1629static struct notifier_block kvm_mips_csr_die_notifier = {
1630 .notifier_call = kvm_mips_csr_die_notify,
1631};
1632
2db9d233 1633static int __init kvm_mips_init(void)
669e846e
SL		 1634{
1635 int ret;
1636
1637 ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE);
1638
1639 if (ret)
1640 return ret;
1641
98e91b84
JH		 1642 register_die_notifier(&kvm_mips_csr_die_notifier);
1643
669e846e
SL		 1644 return 0;
1645}
1646
2db9d233 1647static void __exit kvm_mips_exit(void)
669e846e
SL		 1648{
1649 kvm_exit();
1650
98e91b84 1651 unregister_die_notifier(&kvm_mips_csr_die_notifier);
669e846e
SL		 1652}
1653
1654module_init(kvm_mips_init);
1655module_exit(kvm_mips_exit);
1656
1657EXPORT_TRACEPOINT_SYMBOL(kvm_exit);
Linux 6.x block layer and io_uring tree(s)