Commit | Line | Data |
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669e846e SL |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * KVM/MIPS: MIPS specific KVM APIs | |
7 | * | |
8 | * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. | |
9 | * Authors: Sanjay Lal <sanjayl@kymasys.com> | |
d116e812 | 10 | */ |
669e846e | 11 | |
05108709 | 12 | #include <linux/bitops.h> |
669e846e SL |
13 | #include <linux/errno.h> |
14 | #include <linux/err.h> | |
98e91b84 | 15 | #include <linux/kdebug.h> |
669e846e | 16 | #include <linux/module.h> |
d852b5f3 | 17 | #include <linux/uaccess.h> |
669e846e SL |
18 | #include <linux/vmalloc.h> |
19 | #include <linux/fs.h> | |
20 | #include <linux/bootmem.h> | |
f798217d | 21 | #include <asm/fpu.h> |
669e846e SL |
22 | #include <asm/page.h> |
23 | #include <asm/cacheflush.h> | |
24 | #include <asm/mmu_context.h> | |
c4c6f2ca | 25 | #include <asm/pgtable.h> |
669e846e SL |
26 | |
27 | #include <linux/kvm_host.h> | |
28 | ||
d7d5b05f DCZ |
29 | #include "interrupt.h" |
30 | #include "commpage.h" | |
669e846e SL |
31 | |
32 | #define CREATE_TRACE_POINTS | |
33 | #include "trace.h" | |
34 | ||
35 | #ifndef VECTORSPACING | |
36 | #define VECTORSPACING 0x100 /* for EI/VI mode */ | |
37 | #endif | |
38 | ||
d116e812 | 39 | #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x) |
669e846e | 40 | struct kvm_stats_debugfs_item debugfs_entries[] = { |
d116e812 DCZ |
41 | { "wait", VCPU_STAT(wait_exits), KVM_STAT_VCPU }, |
42 | { "cache", VCPU_STAT(cache_exits), KVM_STAT_VCPU }, | |
43 | { "signal", VCPU_STAT(signal_exits), KVM_STAT_VCPU }, | |
44 | { "interrupt", VCPU_STAT(int_exits), KVM_STAT_VCPU }, | |
45 | { "cop_unsuable", VCPU_STAT(cop_unusable_exits), KVM_STAT_VCPU }, | |
46 | { "tlbmod", VCPU_STAT(tlbmod_exits), KVM_STAT_VCPU }, | |
47 | { "tlbmiss_ld", VCPU_STAT(tlbmiss_ld_exits), KVM_STAT_VCPU }, | |
48 | { "tlbmiss_st", VCPU_STAT(tlbmiss_st_exits), KVM_STAT_VCPU }, | |
49 | { "addrerr_st", VCPU_STAT(addrerr_st_exits), KVM_STAT_VCPU }, | |
50 | { "addrerr_ld", VCPU_STAT(addrerr_ld_exits), KVM_STAT_VCPU }, | |
51 | { "syscall", VCPU_STAT(syscall_exits), KVM_STAT_VCPU }, | |
52 | { "resvd_inst", VCPU_STAT(resvd_inst_exits), KVM_STAT_VCPU }, | |
53 | { "break_inst", VCPU_STAT(break_inst_exits), KVM_STAT_VCPU }, | |
0a560427 | 54 | { "trap_inst", VCPU_STAT(trap_inst_exits), KVM_STAT_VCPU }, |
c2537ed9 | 55 | { "msa_fpe", VCPU_STAT(msa_fpe_exits), KVM_STAT_VCPU }, |
1c0cd66a | 56 | { "fpe", VCPU_STAT(fpe_exits), KVM_STAT_VCPU }, |
c2537ed9 | 57 | { "msa_disabled", VCPU_STAT(msa_disabled_exits), KVM_STAT_VCPU }, |
d116e812 | 58 | { "flush_dcache", VCPU_STAT(flush_dcache_exits), KVM_STAT_VCPU }, |
f7819512 | 59 | { "halt_successful_poll", VCPU_STAT(halt_successful_poll), KVM_STAT_VCPU }, |
62bea5bf | 60 | { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll), KVM_STAT_VCPU }, |
3491caf2 | 61 | { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid), KVM_STAT_VCPU }, |
d116e812 | 62 | { "halt_wakeup", VCPU_STAT(halt_wakeup), KVM_STAT_VCPU }, |
669e846e SL |
63 | {NULL} |
64 | }; | |
65 | ||
66 | static int kvm_mips_reset_vcpu(struct kvm_vcpu *vcpu) | |
67 | { | |
68 | int i; | |
d116e812 | 69 | |
669e846e SL |
70 | for_each_possible_cpu(i) { |
71 | vcpu->arch.guest_kernel_asid[i] = 0; | |
72 | vcpu->arch.guest_user_asid[i] = 0; | |
73 | } | |
d116e812 | 74 | |
669e846e SL |
75 | return 0; |
76 | } | |
77 | ||
d116e812 DCZ |
78 | /* |
79 | * XXXKYMA: We are simulatoring a processor that has the WII bit set in | |
80 | * Config7, so we are "runnable" if interrupts are pending | |
669e846e SL |
81 | */ |
82 | int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) | |
83 | { | |
84 | return !!(vcpu->arch.pending_exceptions); | |
85 | } | |
86 | ||
87 | int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) | |
88 | { | |
89 | return 1; | |
90 | } | |
91 | ||
13a34e06 | 92 | int kvm_arch_hardware_enable(void) |
669e846e SL |
93 | { |
94 | return 0; | |
95 | } | |
96 | ||
669e846e SL |
97 | int kvm_arch_hardware_setup(void) |
98 | { | |
99 | return 0; | |
100 | } | |
101 | ||
669e846e SL |
102 | void kvm_arch_check_processor_compat(void *rtn) |
103 | { | |
d98403a5 | 104 | *(int *)rtn = 0; |
669e846e SL |
105 | } |
106 | ||
107 | static void kvm_mips_init_tlbs(struct kvm *kvm) | |
108 | { | |
109 | unsigned long wired; | |
110 | ||
d116e812 DCZ |
111 | /* |
112 | * Add a wired entry to the TLB, it is used to map the commpage to | |
113 | * the Guest kernel | |
114 | */ | |
669e846e SL |
115 | wired = read_c0_wired(); |
116 | write_c0_wired(wired + 1); | |
117 | mtc0_tlbw_hazard(); | |
118 | kvm->arch.commpage_tlb = wired; | |
119 | ||
120 | kvm_debug("[%d] commpage TLB: %d\n", smp_processor_id(), | |
121 | kvm->arch.commpage_tlb); | |
122 | } | |
123 | ||
124 | static void kvm_mips_init_vm_percpu(void *arg) | |
125 | { | |
126 | struct kvm *kvm = (struct kvm *)arg; | |
127 | ||
128 | kvm_mips_init_tlbs(kvm); | |
129 | kvm_mips_callbacks->vm_init(kvm); | |
130 | ||
131 | } | |
132 | ||
133 | int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) | |
134 | { | |
135 | if (atomic_inc_return(&kvm_mips_instance) == 1) { | |
6e95bfd2 JH |
136 | kvm_debug("%s: 1st KVM instance, setup host TLB parameters\n", |
137 | __func__); | |
669e846e SL |
138 | on_each_cpu(kvm_mips_init_vm_percpu, kvm, 1); |
139 | } | |
140 | ||
669e846e SL |
141 | return 0; |
142 | } | |
143 | ||
235539b4 LC |
144 | bool kvm_arch_has_vcpu_debugfs(void) |
145 | { | |
146 | return false; | |
147 | } | |
148 | ||
149 | int kvm_arch_create_vcpu_debugfs(struct kvm_vcpu *vcpu) | |
150 | { | |
151 | return 0; | |
152 | } | |
153 | ||
669e846e SL |
154 | void kvm_mips_free_vcpus(struct kvm *kvm) |
155 | { | |
156 | unsigned int i; | |
157 | struct kvm_vcpu *vcpu; | |
158 | ||
159 | /* Put the pages we reserved for the guest pmap */ | |
160 | for (i = 0; i < kvm->arch.guest_pmap_npages; i++) { | |
161 | if (kvm->arch.guest_pmap[i] != KVM_INVALID_PAGE) | |
9befad23 | 162 | kvm_release_pfn_clean(kvm->arch.guest_pmap[i]); |
669e846e | 163 | } |
c6c0a663 | 164 | kfree(kvm->arch.guest_pmap); |
669e846e SL |
165 | |
166 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
167 | kvm_arch_vcpu_free(vcpu); | |
168 | } | |
169 | ||
170 | mutex_lock(&kvm->lock); | |
171 | ||
172 | for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) | |
173 | kvm->vcpus[i] = NULL; | |
174 | ||
175 | atomic_set(&kvm->online_vcpus, 0); | |
176 | ||
177 | mutex_unlock(&kvm->lock); | |
178 | } | |
179 | ||
669e846e SL |
180 | static void kvm_mips_uninit_tlbs(void *arg) |
181 | { | |
182 | /* Restore wired count */ | |
183 | write_c0_wired(0); | |
184 | mtc0_tlbw_hazard(); | |
185 | /* Clear out all the TLBs */ | |
186 | kvm_local_flush_tlb_all(); | |
187 | } | |
188 | ||
189 | void kvm_arch_destroy_vm(struct kvm *kvm) | |
190 | { | |
191 | kvm_mips_free_vcpus(kvm); | |
192 | ||
193 | /* If this is the last instance, restore wired count */ | |
194 | if (atomic_dec_return(&kvm_mips_instance) == 0) { | |
6e95bfd2 JH |
195 | kvm_debug("%s: last KVM instance, restoring TLB parameters\n", |
196 | __func__); | |
669e846e SL |
197 | on_each_cpu(kvm_mips_uninit_tlbs, NULL, 1); |
198 | } | |
199 | } | |
200 | ||
d116e812 DCZ |
201 | long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl, |
202 | unsigned long arg) | |
669e846e | 203 | { |
ed829857 | 204 | return -ENOIOCTLCMD; |
669e846e SL |
205 | } |
206 | ||
5587027c AK |
207 | int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot, |
208 | unsigned long npages) | |
669e846e SL |
209 | { |
210 | return 0; | |
211 | } | |
212 | ||
213 | int kvm_arch_prepare_memory_region(struct kvm *kvm, | |
d116e812 | 214 | struct kvm_memory_slot *memslot, |
09170a49 | 215 | const struct kvm_userspace_memory_region *mem, |
d116e812 | 216 | enum kvm_mr_change change) |
669e846e SL |
217 | { |
218 | return 0; | |
219 | } | |
220 | ||
221 | void kvm_arch_commit_memory_region(struct kvm *kvm, | |
09170a49 | 222 | const struct kvm_userspace_memory_region *mem, |
d116e812 | 223 | const struct kvm_memory_slot *old, |
f36f3f28 | 224 | const struct kvm_memory_slot *new, |
d116e812 | 225 | enum kvm_mr_change change) |
669e846e SL |
226 | { |
227 | unsigned long npages = 0; | |
d98403a5 | 228 | int i; |
669e846e SL |
229 | |
230 | kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n", | |
231 | __func__, kvm, mem->slot, mem->guest_phys_addr, | |
232 | mem->memory_size, mem->userspace_addr); | |
233 | ||
234 | /* Setup Guest PMAP table */ | |
235 | if (!kvm->arch.guest_pmap) { | |
236 | if (mem->slot == 0) | |
237 | npages = mem->memory_size >> PAGE_SHIFT; | |
238 | ||
239 | if (npages) { | |
240 | kvm->arch.guest_pmap_npages = npages; | |
241 | kvm->arch.guest_pmap = | |
242 | kzalloc(npages * sizeof(unsigned long), GFP_KERNEL); | |
243 | ||
244 | if (!kvm->arch.guest_pmap) { | |
f7fdcb60 | 245 | kvm_err("Failed to allocate guest PMAP\n"); |
d98403a5 | 246 | return; |
669e846e SL |
247 | } |
248 | ||
6e95bfd2 JH |
249 | kvm_debug("Allocated space for Guest PMAP Table (%ld pages) @ %p\n", |
250 | npages, kvm->arch.guest_pmap); | |
669e846e SL |
251 | |
252 | /* Now setup the page table */ | |
d116e812 | 253 | for (i = 0; i < npages; i++) |
669e846e | 254 | kvm->arch.guest_pmap[i] = KVM_INVALID_PAGE; |
669e846e SL |
255 | } |
256 | } | |
669e846e SL |
257 | } |
258 | ||
d7b8f890 JH |
259 | static inline void dump_handler(const char *symbol, void *start, void *end) |
260 | { | |
261 | u32 *p; | |
262 | ||
263 | pr_debug("LEAF(%s)\n", symbol); | |
264 | ||
265 | pr_debug("\t.set push\n"); | |
266 | pr_debug("\t.set noreorder\n"); | |
267 | ||
268 | for (p = start; p < (u32 *)end; ++p) | |
269 | pr_debug("\t.word\t0x%08x\t\t# %p\n", *p, p); | |
270 | ||
271 | pr_debug("\t.set\tpop\n"); | |
272 | ||
273 | pr_debug("\tEND(%s)\n", symbol); | |
274 | } | |
275 | ||
669e846e SL |
276 | struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id) |
277 | { | |
90e9311a | 278 | int err, size; |
1f9ca62c | 279 | void *gebase, *p, *handler; |
669e846e SL |
280 | int i; |
281 | ||
282 | struct kvm_vcpu *vcpu = kzalloc(sizeof(struct kvm_vcpu), GFP_KERNEL); | |
283 | ||
284 | if (!vcpu) { | |
285 | err = -ENOMEM; | |
286 | goto out; | |
287 | } | |
288 | ||
289 | err = kvm_vcpu_init(vcpu, kvm, id); | |
290 | ||
291 | if (err) | |
292 | goto out_free_cpu; | |
293 | ||
6e95bfd2 | 294 | kvm_debug("kvm @ %p: create cpu %d at %p\n", kvm, id, vcpu); |
669e846e | 295 | |
d116e812 DCZ |
296 | /* |
297 | * Allocate space for host mode exception handlers that handle | |
669e846e SL |
298 | * guest mode exits |
299 | */ | |
d116e812 | 300 | if (cpu_has_veic || cpu_has_vint) |
669e846e | 301 | size = 0x200 + VECTORSPACING * 64; |
d116e812 | 302 | else |
7006e2df | 303 | size = 0x4000; |
669e846e | 304 | |
669e846e SL |
305 | gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL); |
306 | ||
307 | if (!gebase) { | |
308 | err = -ENOMEM; | |
585bb8f9 | 309 | goto out_uninit_cpu; |
669e846e | 310 | } |
6e95bfd2 JH |
311 | kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n", |
312 | ALIGN(size, PAGE_SIZE), gebase); | |
669e846e | 313 | |
2a06dab8 JH |
314 | /* |
315 | * Check new ebase actually fits in CP0_EBase. The lack of a write gate | |
316 | * limits us to the low 512MB of physical address space. If the memory | |
317 | * we allocate is out of range, just give up now. | |
318 | */ | |
319 | if (!cpu_has_ebase_wg && virt_to_phys(gebase) >= 0x20000000) { | |
320 | kvm_err("CP0_EBase.WG required for guest exception base %pK\n", | |
321 | gebase); | |
322 | err = -ENOMEM; | |
323 | goto out_free_gebase; | |
324 | } | |
325 | ||
669e846e SL |
326 | /* Save new ebase */ |
327 | vcpu->arch.guest_ebase = gebase; | |
328 | ||
90e9311a | 329 | /* Build guest exception vectors dynamically in unmapped memory */ |
1f9ca62c | 330 | handler = gebase + 0x2000; |
669e846e SL |
331 | |
332 | /* TLB Refill, EXL = 0 */ | |
1f9ca62c | 333 | kvm_mips_build_exception(gebase, handler); |
669e846e SL |
334 | |
335 | /* General Exception Entry point */ | |
1f9ca62c | 336 | kvm_mips_build_exception(gebase + 0x180, handler); |
669e846e SL |
337 | |
338 | /* For vectored interrupts poke the exception code @ all offsets 0-7 */ | |
339 | for (i = 0; i < 8; i++) { | |
340 | kvm_debug("L1 Vectored handler @ %p\n", | |
341 | gebase + 0x200 + (i * VECTORSPACING)); | |
1f9ca62c JH |
342 | kvm_mips_build_exception(gebase + 0x200 + i * VECTORSPACING, |
343 | handler); | |
669e846e SL |
344 | } |
345 | ||
90e9311a | 346 | /* General exit handler */ |
1f9ca62c | 347 | p = handler; |
90e9311a JH |
348 | p = kvm_mips_build_exit(p); |
349 | ||
350 | /* Guest entry routine */ | |
351 | vcpu->arch.vcpu_run = p; | |
352 | p = kvm_mips_build_vcpu_run(p); | |
797179bc | 353 | |
d7b8f890 JH |
354 | /* Dump the generated code */ |
355 | pr_debug("#include <asm/asm.h>\n"); | |
356 | pr_debug("#include <asm/regdef.h>\n"); | |
357 | pr_debug("\n"); | |
358 | dump_handler("kvm_vcpu_run", vcpu->arch.vcpu_run, p); | |
359 | dump_handler("kvm_gen_exc", gebase + 0x180, gebase + 0x200); | |
360 | dump_handler("kvm_exit", gebase + 0x2000, vcpu->arch.vcpu_run); | |
361 | ||
669e846e | 362 | /* Invalidate the icache for these ranges */ |
facaaec1 JH |
363 | local_flush_icache_range((unsigned long)gebase, |
364 | (unsigned long)gebase + ALIGN(size, PAGE_SIZE)); | |
669e846e | 365 | |
d116e812 DCZ |
366 | /* |
367 | * Allocate comm page for guest kernel, a TLB will be reserved for | |
368 | * mapping GVA @ 0xFFFF8000 to this page | |
369 | */ | |
669e846e SL |
370 | vcpu->arch.kseg0_commpage = kzalloc(PAGE_SIZE << 1, GFP_KERNEL); |
371 | ||
372 | if (!vcpu->arch.kseg0_commpage) { | |
373 | err = -ENOMEM; | |
374 | goto out_free_gebase; | |
375 | } | |
376 | ||
6e95bfd2 | 377 | kvm_debug("Allocated COMM page @ %p\n", vcpu->arch.kseg0_commpage); |
669e846e SL |
378 | kvm_mips_commpage_init(vcpu); |
379 | ||
380 | /* Init */ | |
381 | vcpu->arch.last_sched_cpu = -1; | |
382 | ||
383 | /* Start off the timer */ | |
e30492bb | 384 | kvm_mips_init_count(vcpu); |
669e846e SL |
385 | |
386 | return vcpu; | |
387 | ||
388 | out_free_gebase: | |
389 | kfree(gebase); | |
390 | ||
585bb8f9 JH |
391 | out_uninit_cpu: |
392 | kvm_vcpu_uninit(vcpu); | |
393 | ||
669e846e SL |
394 | out_free_cpu: |
395 | kfree(vcpu); | |
396 | ||
397 | out: | |
398 | return ERR_PTR(err); | |
399 | } | |
400 | ||
401 | void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu) | |
402 | { | |
403 | hrtimer_cancel(&vcpu->arch.comparecount_timer); | |
404 | ||
405 | kvm_vcpu_uninit(vcpu); | |
406 | ||
407 | kvm_mips_dump_stats(vcpu); | |
408 | ||
c6c0a663 JH |
409 | kfree(vcpu->arch.guest_ebase); |
410 | kfree(vcpu->arch.kseg0_commpage); | |
8c9eb041 | 411 | kfree(vcpu); |
669e846e SL |
412 | } |
413 | ||
414 | void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) | |
415 | { | |
416 | kvm_arch_vcpu_free(vcpu); | |
417 | } | |
418 | ||
d116e812 DCZ |
419 | int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, |
420 | struct kvm_guest_debug *dbg) | |
669e846e | 421 | { |
ed829857 | 422 | return -ENOIOCTLCMD; |
669e846e SL |
423 | } |
424 | ||
25b08c7f JH |
425 | /* Must be called with preemption disabled, just before entering guest */ |
426 | static void kvm_mips_check_asids(struct kvm_vcpu *vcpu) | |
427 | { | |
428 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
9078210e | 429 | int i, cpu = smp_processor_id(); |
25b08c7f JH |
430 | unsigned int gasid; |
431 | ||
432 | /* | |
433 | * Lazy host ASID regeneration for guest user mode. | |
434 | * If the guest ASID has changed since the last guest usermode | |
435 | * execution, regenerate the host ASID so as to invalidate stale TLB | |
436 | * entries. | |
437 | */ | |
438 | if (!KVM_GUEST_KERNEL_MODE(vcpu)) { | |
439 | gasid = kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID; | |
440 | if (gasid != vcpu->arch.last_user_gasid) { | |
441 | kvm_get_new_mmu_context(&vcpu->arch.guest_user_mm, cpu, | |
442 | vcpu); | |
443 | vcpu->arch.guest_user_asid[cpu] = | |
444 | vcpu->arch.guest_user_mm.context.asid[cpu]; | |
9078210e JH |
445 | for_each_possible_cpu(i) |
446 | if (i != cpu) | |
447 | vcpu->arch.guest_user_asid[cpu] = 0; | |
25b08c7f JH |
448 | vcpu->arch.last_user_gasid = gasid; |
449 | } | |
450 | } | |
451 | } | |
452 | ||
669e846e SL |
453 | int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run) |
454 | { | |
455 | int r = 0; | |
456 | sigset_t sigsaved; | |
457 | ||
458 | if (vcpu->sigset_active) | |
459 | sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved); | |
460 | ||
461 | if (vcpu->mmio_needed) { | |
462 | if (!vcpu->mmio_is_write) | |
463 | kvm_mips_complete_mmio_load(vcpu, run); | |
464 | vcpu->mmio_needed = 0; | |
465 | } | |
466 | ||
f798217d JH |
467 | lose_fpu(1); |
468 | ||
044f0f03 | 469 | local_irq_disable(); |
669e846e SL |
470 | /* Check if we have any exceptions/interrupts pending */ |
471 | kvm_mips_deliver_interrupts(vcpu, | |
472 | kvm_read_c0_guest_cause(vcpu->arch.cop0)); | |
473 | ||
6edaa530 | 474 | guest_enter_irqoff(); |
669e846e | 475 | |
c4c6f2ca JH |
476 | /* Disable hardware page table walking while in guest */ |
477 | htw_stop(); | |
478 | ||
93258604 | 479 | trace_kvm_enter(vcpu); |
25b08c7f JH |
480 | |
481 | kvm_mips_check_asids(vcpu); | |
482 | ||
797179bc | 483 | r = vcpu->arch.vcpu_run(run, vcpu); |
93258604 | 484 | trace_kvm_out(vcpu); |
669e846e | 485 | |
c4c6f2ca JH |
486 | /* Re-enable HTW before enabling interrupts */ |
487 | htw_start(); | |
488 | ||
6edaa530 | 489 | guest_exit_irqoff(); |
669e846e SL |
490 | local_irq_enable(); |
491 | ||
492 | if (vcpu->sigset_active) | |
493 | sigprocmask(SIG_SETMASK, &sigsaved, NULL); | |
494 | ||
495 | return r; | |
496 | } | |
497 | ||
d116e812 DCZ |
498 | int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, |
499 | struct kvm_mips_interrupt *irq) | |
669e846e SL |
500 | { |
501 | int intr = (int)irq->irq; | |
502 | struct kvm_vcpu *dvcpu = NULL; | |
503 | ||
504 | if (intr == 3 || intr == -3 || intr == 4 || intr == -4) | |
505 | kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu, | |
506 | (int)intr); | |
507 | ||
508 | if (irq->cpu == -1) | |
509 | dvcpu = vcpu; | |
510 | else | |
511 | dvcpu = vcpu->kvm->vcpus[irq->cpu]; | |
512 | ||
513 | if (intr == 2 || intr == 3 || intr == 4) { | |
514 | kvm_mips_callbacks->queue_io_int(dvcpu, irq); | |
515 | ||
516 | } else if (intr == -2 || intr == -3 || intr == -4) { | |
517 | kvm_mips_callbacks->dequeue_io_int(dvcpu, irq); | |
518 | } else { | |
519 | kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__, | |
520 | irq->cpu, irq->irq); | |
521 | return -EINVAL; | |
522 | } | |
523 | ||
524 | dvcpu->arch.wait = 0; | |
525 | ||
8577370f MT |
526 | if (swait_active(&dvcpu->wq)) |
527 | swake_up(&dvcpu->wq); | |
669e846e SL |
528 | |
529 | return 0; | |
530 | } | |
531 | ||
d116e812 DCZ |
532 | int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, |
533 | struct kvm_mp_state *mp_state) | |
669e846e | 534 | { |
ed829857 | 535 | return -ENOIOCTLCMD; |
669e846e SL |
536 | } |
537 | ||
d116e812 DCZ |
538 | int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, |
539 | struct kvm_mp_state *mp_state) | |
669e846e | 540 | { |
ed829857 | 541 | return -ENOIOCTLCMD; |
669e846e SL |
542 | } |
543 | ||
4c73fb2b DD |
544 | static u64 kvm_mips_get_one_regs[] = { |
545 | KVM_REG_MIPS_R0, | |
546 | KVM_REG_MIPS_R1, | |
547 | KVM_REG_MIPS_R2, | |
548 | KVM_REG_MIPS_R3, | |
549 | KVM_REG_MIPS_R4, | |
550 | KVM_REG_MIPS_R5, | |
551 | KVM_REG_MIPS_R6, | |
552 | KVM_REG_MIPS_R7, | |
553 | KVM_REG_MIPS_R8, | |
554 | KVM_REG_MIPS_R9, | |
555 | KVM_REG_MIPS_R10, | |
556 | KVM_REG_MIPS_R11, | |
557 | KVM_REG_MIPS_R12, | |
558 | KVM_REG_MIPS_R13, | |
559 | KVM_REG_MIPS_R14, | |
560 | KVM_REG_MIPS_R15, | |
561 | KVM_REG_MIPS_R16, | |
562 | KVM_REG_MIPS_R17, | |
563 | KVM_REG_MIPS_R18, | |
564 | KVM_REG_MIPS_R19, | |
565 | KVM_REG_MIPS_R20, | |
566 | KVM_REG_MIPS_R21, | |
567 | KVM_REG_MIPS_R22, | |
568 | KVM_REG_MIPS_R23, | |
569 | KVM_REG_MIPS_R24, | |
570 | KVM_REG_MIPS_R25, | |
571 | KVM_REG_MIPS_R26, | |
572 | KVM_REG_MIPS_R27, | |
573 | KVM_REG_MIPS_R28, | |
574 | KVM_REG_MIPS_R29, | |
575 | KVM_REG_MIPS_R30, | |
576 | KVM_REG_MIPS_R31, | |
577 | ||
70e92c7e | 578 | #ifndef CONFIG_CPU_MIPSR6 |
4c73fb2b DD |
579 | KVM_REG_MIPS_HI, |
580 | KVM_REG_MIPS_LO, | |
70e92c7e | 581 | #endif |
4c73fb2b DD |
582 | KVM_REG_MIPS_PC, |
583 | ||
584 | KVM_REG_MIPS_CP0_INDEX, | |
585 | KVM_REG_MIPS_CP0_CONTEXT, | |
7767b7d2 | 586 | KVM_REG_MIPS_CP0_USERLOCAL, |
4c73fb2b DD |
587 | KVM_REG_MIPS_CP0_PAGEMASK, |
588 | KVM_REG_MIPS_CP0_WIRED, | |
16fd5c1d | 589 | KVM_REG_MIPS_CP0_HWRENA, |
4c73fb2b | 590 | KVM_REG_MIPS_CP0_BADVADDR, |
f8be02da | 591 | KVM_REG_MIPS_CP0_COUNT, |
4c73fb2b | 592 | KVM_REG_MIPS_CP0_ENTRYHI, |
f8be02da | 593 | KVM_REG_MIPS_CP0_COMPARE, |
4c73fb2b DD |
594 | KVM_REG_MIPS_CP0_STATUS, |
595 | KVM_REG_MIPS_CP0_CAUSE, | |
fb6df0cd | 596 | KVM_REG_MIPS_CP0_EPC, |
1068eaaf | 597 | KVM_REG_MIPS_CP0_PRID, |
4c73fb2b DD |
598 | KVM_REG_MIPS_CP0_CONFIG, |
599 | KVM_REG_MIPS_CP0_CONFIG1, | |
600 | KVM_REG_MIPS_CP0_CONFIG2, | |
601 | KVM_REG_MIPS_CP0_CONFIG3, | |
c771607a JH |
602 | KVM_REG_MIPS_CP0_CONFIG4, |
603 | KVM_REG_MIPS_CP0_CONFIG5, | |
4c73fb2b | 604 | KVM_REG_MIPS_CP0_CONFIG7, |
f8239342 JH |
605 | KVM_REG_MIPS_CP0_ERROREPC, |
606 | ||
607 | KVM_REG_MIPS_COUNT_CTL, | |
608 | KVM_REG_MIPS_COUNT_RESUME, | |
f74a8e22 | 609 | KVM_REG_MIPS_COUNT_HZ, |
4c73fb2b DD |
610 | }; |
611 | ||
e5775930 JH |
612 | static u64 kvm_mips_get_one_regs_fpu[] = { |
613 | KVM_REG_MIPS_FCR_IR, | |
614 | KVM_REG_MIPS_FCR_CSR, | |
615 | }; | |
616 | ||
617 | static u64 kvm_mips_get_one_regs_msa[] = { | |
618 | KVM_REG_MIPS_MSA_IR, | |
619 | KVM_REG_MIPS_MSA_CSR, | |
620 | }; | |
621 | ||
05108709 JH |
622 | static u64 kvm_mips_get_one_regs_kscratch[] = { |
623 | KVM_REG_MIPS_CP0_KSCRATCH1, | |
624 | KVM_REG_MIPS_CP0_KSCRATCH2, | |
625 | KVM_REG_MIPS_CP0_KSCRATCH3, | |
626 | KVM_REG_MIPS_CP0_KSCRATCH4, | |
627 | KVM_REG_MIPS_CP0_KSCRATCH5, | |
628 | KVM_REG_MIPS_CP0_KSCRATCH6, | |
629 | }; | |
630 | ||
f5c43bd4 JH |
631 | static unsigned long kvm_mips_num_regs(struct kvm_vcpu *vcpu) |
632 | { | |
633 | unsigned long ret; | |
634 | ||
635 | ret = ARRAY_SIZE(kvm_mips_get_one_regs); | |
e5775930 JH |
636 | if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) { |
637 | ret += ARRAY_SIZE(kvm_mips_get_one_regs_fpu) + 48; | |
638 | /* odd doubles */ | |
639 | if (boot_cpu_data.fpu_id & MIPS_FPIR_F64) | |
640 | ret += 16; | |
641 | } | |
642 | if (kvm_mips_guest_can_have_msa(&vcpu->arch)) | |
643 | ret += ARRAY_SIZE(kvm_mips_get_one_regs_msa) + 32; | |
05108709 | 644 | ret += __arch_hweight8(vcpu->arch.kscratch_enabled); |
f5c43bd4 JH |
645 | ret += kvm_mips_callbacks->num_regs(vcpu); |
646 | ||
647 | return ret; | |
648 | } | |
649 | ||
650 | static int kvm_mips_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices) | |
651 | { | |
e5775930 JH |
652 | u64 index; |
653 | unsigned int i; | |
654 | ||
f5c43bd4 JH |
655 | if (copy_to_user(indices, kvm_mips_get_one_regs, |
656 | sizeof(kvm_mips_get_one_regs))) | |
657 | return -EFAULT; | |
658 | indices += ARRAY_SIZE(kvm_mips_get_one_regs); | |
659 | ||
e5775930 JH |
660 | if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) { |
661 | if (copy_to_user(indices, kvm_mips_get_one_regs_fpu, | |
662 | sizeof(kvm_mips_get_one_regs_fpu))) | |
663 | return -EFAULT; | |
664 | indices += ARRAY_SIZE(kvm_mips_get_one_regs_fpu); | |
665 | ||
666 | for (i = 0; i < 32; ++i) { | |
667 | index = KVM_REG_MIPS_FPR_32(i); | |
668 | if (copy_to_user(indices, &index, sizeof(index))) | |
669 | return -EFAULT; | |
670 | ++indices; | |
671 | ||
672 | /* skip odd doubles if no F64 */ | |
673 | if (i & 1 && !(boot_cpu_data.fpu_id & MIPS_FPIR_F64)) | |
674 | continue; | |
675 | ||
676 | index = KVM_REG_MIPS_FPR_64(i); | |
677 | if (copy_to_user(indices, &index, sizeof(index))) | |
678 | return -EFAULT; | |
679 | ++indices; | |
680 | } | |
681 | } | |
682 | ||
683 | if (kvm_mips_guest_can_have_msa(&vcpu->arch)) { | |
684 | if (copy_to_user(indices, kvm_mips_get_one_regs_msa, | |
685 | sizeof(kvm_mips_get_one_regs_msa))) | |
686 | return -EFAULT; | |
687 | indices += ARRAY_SIZE(kvm_mips_get_one_regs_msa); | |
688 | ||
689 | for (i = 0; i < 32; ++i) { | |
690 | index = KVM_REG_MIPS_VEC_128(i); | |
691 | if (copy_to_user(indices, &index, sizeof(index))) | |
692 | return -EFAULT; | |
693 | ++indices; | |
694 | } | |
695 | } | |
696 | ||
05108709 JH |
697 | for (i = 0; i < 6; ++i) { |
698 | if (!(vcpu->arch.kscratch_enabled & BIT(i + 2))) | |
699 | continue; | |
700 | ||
701 | if (copy_to_user(indices, &kvm_mips_get_one_regs_kscratch[i], | |
702 | sizeof(kvm_mips_get_one_regs_kscratch[i]))) | |
703 | return -EFAULT; | |
704 | ++indices; | |
705 | } | |
706 | ||
f5c43bd4 JH |
707 | return kvm_mips_callbacks->copy_reg_indices(vcpu, indices); |
708 | } | |
709 | ||
4c73fb2b DD |
710 | static int kvm_mips_get_reg(struct kvm_vcpu *vcpu, |
711 | const struct kvm_one_reg *reg) | |
712 | { | |
4c73fb2b | 713 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
379245cd | 714 | struct mips_fpu_struct *fpu = &vcpu->arch.fpu; |
f8be02da | 715 | int ret; |
4c73fb2b | 716 | s64 v; |
ab86bd60 | 717 | s64 vs[2]; |
379245cd | 718 | unsigned int idx; |
4c73fb2b DD |
719 | |
720 | switch (reg->id) { | |
379245cd | 721 | /* General purpose registers */ |
4c73fb2b DD |
722 | case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31: |
723 | v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0]; | |
724 | break; | |
70e92c7e | 725 | #ifndef CONFIG_CPU_MIPSR6 |
4c73fb2b DD |
726 | case KVM_REG_MIPS_HI: |
727 | v = (long)vcpu->arch.hi; | |
728 | break; | |
729 | case KVM_REG_MIPS_LO: | |
730 | v = (long)vcpu->arch.lo; | |
731 | break; | |
70e92c7e | 732 | #endif |
4c73fb2b DD |
733 | case KVM_REG_MIPS_PC: |
734 | v = (long)vcpu->arch.pc; | |
735 | break; | |
736 | ||
379245cd JH |
737 | /* Floating point registers */ |
738 | case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31): | |
739 | if (!kvm_mips_guest_has_fpu(&vcpu->arch)) | |
740 | return -EINVAL; | |
741 | idx = reg->id - KVM_REG_MIPS_FPR_32(0); | |
742 | /* Odd singles in top of even double when FR=0 */ | |
743 | if (kvm_read_c0_guest_status(cop0) & ST0_FR) | |
744 | v = get_fpr32(&fpu->fpr[idx], 0); | |
745 | else | |
746 | v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1); | |
747 | break; | |
748 | case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31): | |
749 | if (!kvm_mips_guest_has_fpu(&vcpu->arch)) | |
750 | return -EINVAL; | |
751 | idx = reg->id - KVM_REG_MIPS_FPR_64(0); | |
752 | /* Can't access odd doubles in FR=0 mode */ | |
753 | if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR)) | |
754 | return -EINVAL; | |
755 | v = get_fpr64(&fpu->fpr[idx], 0); | |
756 | break; | |
757 | case KVM_REG_MIPS_FCR_IR: | |
758 | if (!kvm_mips_guest_has_fpu(&vcpu->arch)) | |
759 | return -EINVAL; | |
760 | v = boot_cpu_data.fpu_id; | |
761 | break; | |
762 | case KVM_REG_MIPS_FCR_CSR: | |
763 | if (!kvm_mips_guest_has_fpu(&vcpu->arch)) | |
764 | return -EINVAL; | |
765 | v = fpu->fcr31; | |
766 | break; | |
767 | ||
ab86bd60 JH |
768 | /* MIPS SIMD Architecture (MSA) registers */ |
769 | case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31): | |
770 | if (!kvm_mips_guest_has_msa(&vcpu->arch)) | |
771 | return -EINVAL; | |
772 | /* Can't access MSA registers in FR=0 mode */ | |
773 | if (!(kvm_read_c0_guest_status(cop0) & ST0_FR)) | |
774 | return -EINVAL; | |
775 | idx = reg->id - KVM_REG_MIPS_VEC_128(0); | |
776 | #ifdef CONFIG_CPU_LITTLE_ENDIAN | |
777 | /* least significant byte first */ | |
778 | vs[0] = get_fpr64(&fpu->fpr[idx], 0); | |
779 | vs[1] = get_fpr64(&fpu->fpr[idx], 1); | |
780 | #else | |
781 | /* most significant byte first */ | |
782 | vs[0] = get_fpr64(&fpu->fpr[idx], 1); | |
783 | vs[1] = get_fpr64(&fpu->fpr[idx], 0); | |
784 | #endif | |
785 | break; | |
786 | case KVM_REG_MIPS_MSA_IR: | |
787 | if (!kvm_mips_guest_has_msa(&vcpu->arch)) | |
788 | return -EINVAL; | |
789 | v = boot_cpu_data.msa_id; | |
790 | break; | |
791 | case KVM_REG_MIPS_MSA_CSR: | |
792 | if (!kvm_mips_guest_has_msa(&vcpu->arch)) | |
793 | return -EINVAL; | |
794 | v = fpu->msacsr; | |
795 | break; | |
796 | ||
379245cd | 797 | /* Co-processor 0 registers */ |
4c73fb2b DD |
798 | case KVM_REG_MIPS_CP0_INDEX: |
799 | v = (long)kvm_read_c0_guest_index(cop0); | |
800 | break; | |
801 | case KVM_REG_MIPS_CP0_CONTEXT: | |
802 | v = (long)kvm_read_c0_guest_context(cop0); | |
803 | break; | |
7767b7d2 JH |
804 | case KVM_REG_MIPS_CP0_USERLOCAL: |
805 | v = (long)kvm_read_c0_guest_userlocal(cop0); | |
806 | break; | |
4c73fb2b DD |
807 | case KVM_REG_MIPS_CP0_PAGEMASK: |
808 | v = (long)kvm_read_c0_guest_pagemask(cop0); | |
809 | break; | |
810 | case KVM_REG_MIPS_CP0_WIRED: | |
811 | v = (long)kvm_read_c0_guest_wired(cop0); | |
812 | break; | |
16fd5c1d JH |
813 | case KVM_REG_MIPS_CP0_HWRENA: |
814 | v = (long)kvm_read_c0_guest_hwrena(cop0); | |
815 | break; | |
4c73fb2b DD |
816 | case KVM_REG_MIPS_CP0_BADVADDR: |
817 | v = (long)kvm_read_c0_guest_badvaddr(cop0); | |
818 | break; | |
819 | case KVM_REG_MIPS_CP0_ENTRYHI: | |
820 | v = (long)kvm_read_c0_guest_entryhi(cop0); | |
821 | break; | |
f8be02da JH |
822 | case KVM_REG_MIPS_CP0_COMPARE: |
823 | v = (long)kvm_read_c0_guest_compare(cop0); | |
824 | break; | |
4c73fb2b DD |
825 | case KVM_REG_MIPS_CP0_STATUS: |
826 | v = (long)kvm_read_c0_guest_status(cop0); | |
827 | break; | |
828 | case KVM_REG_MIPS_CP0_CAUSE: | |
829 | v = (long)kvm_read_c0_guest_cause(cop0); | |
830 | break; | |
fb6df0cd JH |
831 | case KVM_REG_MIPS_CP0_EPC: |
832 | v = (long)kvm_read_c0_guest_epc(cop0); | |
833 | break; | |
1068eaaf JH |
834 | case KVM_REG_MIPS_CP0_PRID: |
835 | v = (long)kvm_read_c0_guest_prid(cop0); | |
836 | break; | |
4c73fb2b DD |
837 | case KVM_REG_MIPS_CP0_CONFIG: |
838 | v = (long)kvm_read_c0_guest_config(cop0); | |
839 | break; | |
840 | case KVM_REG_MIPS_CP0_CONFIG1: | |
841 | v = (long)kvm_read_c0_guest_config1(cop0); | |
842 | break; | |
843 | case KVM_REG_MIPS_CP0_CONFIG2: | |
844 | v = (long)kvm_read_c0_guest_config2(cop0); | |
845 | break; | |
846 | case KVM_REG_MIPS_CP0_CONFIG3: | |
847 | v = (long)kvm_read_c0_guest_config3(cop0); | |
848 | break; | |
c771607a JH |
849 | case KVM_REG_MIPS_CP0_CONFIG4: |
850 | v = (long)kvm_read_c0_guest_config4(cop0); | |
851 | break; | |
852 | case KVM_REG_MIPS_CP0_CONFIG5: | |
853 | v = (long)kvm_read_c0_guest_config5(cop0); | |
854 | break; | |
4c73fb2b DD |
855 | case KVM_REG_MIPS_CP0_CONFIG7: |
856 | v = (long)kvm_read_c0_guest_config7(cop0); | |
857 | break; | |
e93d4c15 JH |
858 | case KVM_REG_MIPS_CP0_ERROREPC: |
859 | v = (long)kvm_read_c0_guest_errorepc(cop0); | |
860 | break; | |
05108709 JH |
861 | case KVM_REG_MIPS_CP0_KSCRATCH1 ... KVM_REG_MIPS_CP0_KSCRATCH6: |
862 | idx = reg->id - KVM_REG_MIPS_CP0_KSCRATCH1 + 2; | |
863 | if (!(vcpu->arch.kscratch_enabled & BIT(idx))) | |
864 | return -EINVAL; | |
865 | switch (idx) { | |
866 | case 2: | |
867 | v = (long)kvm_read_c0_guest_kscratch1(cop0); | |
868 | break; | |
869 | case 3: | |
870 | v = (long)kvm_read_c0_guest_kscratch2(cop0); | |
871 | break; | |
872 | case 4: | |
873 | v = (long)kvm_read_c0_guest_kscratch3(cop0); | |
874 | break; | |
875 | case 5: | |
876 | v = (long)kvm_read_c0_guest_kscratch4(cop0); | |
877 | break; | |
878 | case 6: | |
879 | v = (long)kvm_read_c0_guest_kscratch5(cop0); | |
880 | break; | |
881 | case 7: | |
882 | v = (long)kvm_read_c0_guest_kscratch6(cop0); | |
883 | break; | |
884 | } | |
885 | break; | |
f8be02da | 886 | /* registers to be handled specially */ |
cc68d22f | 887 | default: |
f8be02da JH |
888 | ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v); |
889 | if (ret) | |
890 | return ret; | |
891 | break; | |
4c73fb2b | 892 | } |
681865d4 DD |
893 | if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) { |
894 | u64 __user *uaddr64 = (u64 __user *)(long)reg->addr; | |
d116e812 | 895 | |
681865d4 DD |
896 | return put_user(v, uaddr64); |
897 | } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) { | |
898 | u32 __user *uaddr32 = (u32 __user *)(long)reg->addr; | |
899 | u32 v32 = (u32)v; | |
d116e812 | 900 | |
681865d4 | 901 | return put_user(v32, uaddr32); |
ab86bd60 JH |
902 | } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) { |
903 | void __user *uaddr = (void __user *)(long)reg->addr; | |
904 | ||
0178fd7d | 905 | return copy_to_user(uaddr, vs, 16) ? -EFAULT : 0; |
681865d4 DD |
906 | } else { |
907 | return -EINVAL; | |
908 | } | |
4c73fb2b DD |
909 | } |
910 | ||
911 | static int kvm_mips_set_reg(struct kvm_vcpu *vcpu, | |
912 | const struct kvm_one_reg *reg) | |
913 | { | |
4c73fb2b | 914 | struct mips_coproc *cop0 = vcpu->arch.cop0; |
379245cd JH |
915 | struct mips_fpu_struct *fpu = &vcpu->arch.fpu; |
916 | s64 v; | |
ab86bd60 | 917 | s64 vs[2]; |
379245cd | 918 | unsigned int idx; |
4c73fb2b | 919 | |
681865d4 DD |
920 | if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) { |
921 | u64 __user *uaddr64 = (u64 __user *)(long)reg->addr; | |
922 | ||
923 | if (get_user(v, uaddr64) != 0) | |
924 | return -EFAULT; | |
925 | } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) { | |
926 | u32 __user *uaddr32 = (u32 __user *)(long)reg->addr; | |
927 | s32 v32; | |
928 | ||
929 | if (get_user(v32, uaddr32) != 0) | |
930 | return -EFAULT; | |
931 | v = (s64)v32; | |
ab86bd60 JH |
932 | } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) { |
933 | void __user *uaddr = (void __user *)(long)reg->addr; | |
934 | ||
0178fd7d | 935 | return copy_from_user(vs, uaddr, 16) ? -EFAULT : 0; |
681865d4 DD |
936 | } else { |
937 | return -EINVAL; | |
938 | } | |
4c73fb2b DD |
939 | |
940 | switch (reg->id) { | |
379245cd | 941 | /* General purpose registers */ |
4c73fb2b DD |
942 | case KVM_REG_MIPS_R0: |
943 | /* Silently ignore requests to set $0 */ | |
944 | break; | |
945 | case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31: | |
946 | vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v; | |
947 | break; | |
70e92c7e | 948 | #ifndef CONFIG_CPU_MIPSR6 |
4c73fb2b DD |
949 | case KVM_REG_MIPS_HI: |
950 | vcpu->arch.hi = v; | |
951 | break; | |
952 | case KVM_REG_MIPS_LO: | |
953 | vcpu->arch.lo = v; | |
954 | break; | |
70e92c7e | 955 | #endif |
4c73fb2b DD |
956 | case KVM_REG_MIPS_PC: |
957 | vcpu->arch.pc = v; | |
958 | break; | |
959 | ||
379245cd JH |
960 | /* Floating point registers */ |
961 | case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31): | |
962 | if (!kvm_mips_guest_has_fpu(&vcpu->arch)) | |
963 | return -EINVAL; | |
964 | idx = reg->id - KVM_REG_MIPS_FPR_32(0); | |
965 | /* Odd singles in top of even double when FR=0 */ | |
966 | if (kvm_read_c0_guest_status(cop0) & ST0_FR) | |
967 | set_fpr32(&fpu->fpr[idx], 0, v); | |
968 | else | |
969 | set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v); | |
970 | break; | |
971 | case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31): | |
972 | if (!kvm_mips_guest_has_fpu(&vcpu->arch)) | |
973 | return -EINVAL; | |
974 | idx = reg->id - KVM_REG_MIPS_FPR_64(0); | |
975 | /* Can't access odd doubles in FR=0 mode */ | |
976 | if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR)) | |
977 | return -EINVAL; | |
978 | set_fpr64(&fpu->fpr[idx], 0, v); | |
979 | break; | |
980 | case KVM_REG_MIPS_FCR_IR: | |
981 | if (!kvm_mips_guest_has_fpu(&vcpu->arch)) | |
982 | return -EINVAL; | |
983 | /* Read-only */ | |
984 | break; | |
985 | case KVM_REG_MIPS_FCR_CSR: | |
986 | if (!kvm_mips_guest_has_fpu(&vcpu->arch)) | |
987 | return -EINVAL; | |
988 | fpu->fcr31 = v; | |
989 | break; | |
990 | ||
ab86bd60 JH |
991 | /* MIPS SIMD Architecture (MSA) registers */ |
992 | case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31): | |
993 | if (!kvm_mips_guest_has_msa(&vcpu->arch)) | |
994 | return -EINVAL; | |
995 | idx = reg->id - KVM_REG_MIPS_VEC_128(0); | |
996 | #ifdef CONFIG_CPU_LITTLE_ENDIAN | |
997 | /* least significant byte first */ | |
998 | set_fpr64(&fpu->fpr[idx], 0, vs[0]); | |
999 | set_fpr64(&fpu->fpr[idx], 1, vs[1]); | |
1000 | #else | |
1001 | /* most significant byte first */ | |
1002 | set_fpr64(&fpu->fpr[idx], 1, vs[0]); | |
1003 | set_fpr64(&fpu->fpr[idx], 0, vs[1]); | |
1004 | #endif | |
1005 | break; | |
1006 | case KVM_REG_MIPS_MSA_IR: | |
1007 | if (!kvm_mips_guest_has_msa(&vcpu->arch)) | |
1008 | return -EINVAL; | |
1009 | /* Read-only */ | |
1010 | break; | |
1011 | case KVM_REG_MIPS_MSA_CSR: | |
1012 | if (!kvm_mips_guest_has_msa(&vcpu->arch)) | |
1013 | return -EINVAL; | |
1014 | fpu->msacsr = v; | |
1015 | break; | |
1016 | ||
379245cd | 1017 | /* Co-processor 0 registers */ |
4c73fb2b DD |
1018 | case KVM_REG_MIPS_CP0_INDEX: |
1019 | kvm_write_c0_guest_index(cop0, v); | |
1020 | break; | |
1021 | case KVM_REG_MIPS_CP0_CONTEXT: | |
1022 | kvm_write_c0_guest_context(cop0, v); | |
1023 | break; | |
7767b7d2 JH |
1024 | case KVM_REG_MIPS_CP0_USERLOCAL: |
1025 | kvm_write_c0_guest_userlocal(cop0, v); | |
1026 | break; | |
4c73fb2b DD |
1027 | case KVM_REG_MIPS_CP0_PAGEMASK: |
1028 | kvm_write_c0_guest_pagemask(cop0, v); | |
1029 | break; | |
1030 | case KVM_REG_MIPS_CP0_WIRED: | |
1031 | kvm_write_c0_guest_wired(cop0, v); | |
1032 | break; | |
16fd5c1d JH |
1033 | case KVM_REG_MIPS_CP0_HWRENA: |
1034 | kvm_write_c0_guest_hwrena(cop0, v); | |
1035 | break; | |
4c73fb2b DD |
1036 | case KVM_REG_MIPS_CP0_BADVADDR: |
1037 | kvm_write_c0_guest_badvaddr(cop0, v); | |
1038 | break; | |
1039 | case KVM_REG_MIPS_CP0_ENTRYHI: | |
1040 | kvm_write_c0_guest_entryhi(cop0, v); | |
1041 | break; | |
1042 | case KVM_REG_MIPS_CP0_STATUS: | |
1043 | kvm_write_c0_guest_status(cop0, v); | |
1044 | break; | |
fb6df0cd JH |
1045 | case KVM_REG_MIPS_CP0_EPC: |
1046 | kvm_write_c0_guest_epc(cop0, v); | |
1047 | break; | |
1068eaaf JH |
1048 | case KVM_REG_MIPS_CP0_PRID: |
1049 | kvm_write_c0_guest_prid(cop0, v); | |
1050 | break; | |
4c73fb2b DD |
1051 | case KVM_REG_MIPS_CP0_ERROREPC: |
1052 | kvm_write_c0_guest_errorepc(cop0, v); | |
1053 | break; | |
05108709 JH |
1054 | case KVM_REG_MIPS_CP0_KSCRATCH1 ... KVM_REG_MIPS_CP0_KSCRATCH6: |
1055 | idx = reg->id - KVM_REG_MIPS_CP0_KSCRATCH1 + 2; | |
1056 | if (!(vcpu->arch.kscratch_enabled & BIT(idx))) | |
1057 | return -EINVAL; | |
1058 | switch (idx) { | |
1059 | case 2: | |
1060 | kvm_write_c0_guest_kscratch1(cop0, v); | |
1061 | break; | |
1062 | case 3: | |
1063 | kvm_write_c0_guest_kscratch2(cop0, v); | |
1064 | break; | |
1065 | case 4: | |
1066 | kvm_write_c0_guest_kscratch3(cop0, v); | |
1067 | break; | |
1068 | case 5: | |
1069 | kvm_write_c0_guest_kscratch4(cop0, v); | |
1070 | break; | |
1071 | case 6: | |
1072 | kvm_write_c0_guest_kscratch5(cop0, v); | |
1073 | break; | |
1074 | case 7: | |
1075 | kvm_write_c0_guest_kscratch6(cop0, v); | |
1076 | break; | |
1077 | } | |
1078 | break; | |
f8be02da | 1079 | /* registers to be handled specially */ |
4c73fb2b | 1080 | default: |
cc68d22f | 1081 | return kvm_mips_callbacks->set_one_reg(vcpu, reg, v); |
4c73fb2b DD |
1082 | } |
1083 | return 0; | |
1084 | } | |
1085 | ||
5fafd874 JH |
1086 | static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, |
1087 | struct kvm_enable_cap *cap) | |
1088 | { | |
1089 | int r = 0; | |
1090 | ||
1091 | if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap)) | |
1092 | return -EINVAL; | |
1093 | if (cap->flags) | |
1094 | return -EINVAL; | |
1095 | if (cap->args[0]) | |
1096 | return -EINVAL; | |
1097 | ||
1098 | switch (cap->cap) { | |
1099 | case KVM_CAP_MIPS_FPU: | |
1100 | vcpu->arch.fpu_enabled = true; | |
1101 | break; | |
d952bd07 JH |
1102 | case KVM_CAP_MIPS_MSA: |
1103 | vcpu->arch.msa_enabled = true; | |
1104 | break; | |
5fafd874 JH |
1105 | default: |
1106 | r = -EINVAL; | |
1107 | break; | |
1108 | } | |
1109 | ||
1110 | return r; | |
1111 | } | |
1112 | ||
d116e812 DCZ |
1113 | long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl, |
1114 | unsigned long arg) | |
669e846e SL |
1115 | { |
1116 | struct kvm_vcpu *vcpu = filp->private_data; | |
1117 | void __user *argp = (void __user *)arg; | |
1118 | long r; | |
669e846e SL |
1119 | |
1120 | switch (ioctl) { | |
4c73fb2b DD |
1121 | case KVM_SET_ONE_REG: |
1122 | case KVM_GET_ONE_REG: { | |
1123 | struct kvm_one_reg reg; | |
d116e812 | 1124 | |
4c73fb2b DD |
1125 | if (copy_from_user(®, argp, sizeof(reg))) |
1126 | return -EFAULT; | |
1127 | if (ioctl == KVM_SET_ONE_REG) | |
1128 | return kvm_mips_set_reg(vcpu, ®); | |
1129 | else | |
1130 | return kvm_mips_get_reg(vcpu, ®); | |
1131 | } | |
1132 | case KVM_GET_REG_LIST: { | |
1133 | struct kvm_reg_list __user *user_list = argp; | |
4c73fb2b DD |
1134 | struct kvm_reg_list reg_list; |
1135 | unsigned n; | |
1136 | ||
1137 | if (copy_from_user(®_list, user_list, sizeof(reg_list))) | |
1138 | return -EFAULT; | |
1139 | n = reg_list.n; | |
f5c43bd4 | 1140 | reg_list.n = kvm_mips_num_regs(vcpu); |
4c73fb2b DD |
1141 | if (copy_to_user(user_list, ®_list, sizeof(reg_list))) |
1142 | return -EFAULT; | |
1143 | if (n < reg_list.n) | |
1144 | return -E2BIG; | |
f5c43bd4 | 1145 | return kvm_mips_copy_reg_indices(vcpu, user_list->reg); |
4c73fb2b | 1146 | } |
669e846e SL |
1147 | case KVM_NMI: |
1148 | /* Treat the NMI as a CPU reset */ | |
1149 | r = kvm_mips_reset_vcpu(vcpu); | |
1150 | break; | |
1151 | case KVM_INTERRUPT: | |
1152 | { | |
1153 | struct kvm_mips_interrupt irq; | |
d116e812 | 1154 | |
669e846e SL |
1155 | r = -EFAULT; |
1156 | if (copy_from_user(&irq, argp, sizeof(irq))) | |
1157 | goto out; | |
1158 | ||
669e846e SL |
1159 | kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__, |
1160 | irq.irq); | |
1161 | ||
1162 | r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); | |
1163 | break; | |
1164 | } | |
5fafd874 JH |
1165 | case KVM_ENABLE_CAP: { |
1166 | struct kvm_enable_cap cap; | |
1167 | ||
1168 | r = -EFAULT; | |
1169 | if (copy_from_user(&cap, argp, sizeof(cap))) | |
1170 | goto out; | |
1171 | r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); | |
1172 | break; | |
1173 | } | |
669e846e | 1174 | default: |
4c73fb2b | 1175 | r = -ENOIOCTLCMD; |
669e846e SL |
1176 | } |
1177 | ||
1178 | out: | |
1179 | return r; | |
1180 | } | |
1181 | ||
d116e812 | 1182 | /* Get (and clear) the dirty memory log for a memory slot. */ |
669e846e SL |
1183 | int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log) |
1184 | { | |
9f6b8029 | 1185 | struct kvm_memslots *slots; |
669e846e SL |
1186 | struct kvm_memory_slot *memslot; |
1187 | unsigned long ga, ga_end; | |
1188 | int is_dirty = 0; | |
1189 | int r; | |
1190 | unsigned long n; | |
1191 | ||
1192 | mutex_lock(&kvm->slots_lock); | |
1193 | ||
1194 | r = kvm_get_dirty_log(kvm, log, &is_dirty); | |
1195 | if (r) | |
1196 | goto out; | |
1197 | ||
1198 | /* If nothing is dirty, don't bother messing with page tables. */ | |
1199 | if (is_dirty) { | |
9f6b8029 PB |
1200 | slots = kvm_memslots(kvm); |
1201 | memslot = id_to_memslot(slots, log->slot); | |
669e846e SL |
1202 | |
1203 | ga = memslot->base_gfn << PAGE_SHIFT; | |
1204 | ga_end = ga + (memslot->npages << PAGE_SHIFT); | |
1205 | ||
6ad78a5c DCZ |
1206 | kvm_info("%s: dirty, ga: %#lx, ga_end %#lx\n", __func__, ga, |
1207 | ga_end); | |
669e846e SL |
1208 | |
1209 | n = kvm_dirty_bitmap_bytes(memslot); | |
1210 | memset(memslot->dirty_bitmap, 0, n); | |
1211 | } | |
1212 | ||
1213 | r = 0; | |
1214 | out: | |
1215 | mutex_unlock(&kvm->slots_lock); | |
1216 | return r; | |
1217 | ||
1218 | } | |
1219 | ||
1220 | long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg) | |
1221 | { | |
1222 | long r; | |
1223 | ||
1224 | switch (ioctl) { | |
1225 | default: | |
ed829857 | 1226 | r = -ENOIOCTLCMD; |
669e846e SL |
1227 | } |
1228 | ||
1229 | return r; | |
1230 | } | |
1231 | ||
1232 | int kvm_arch_init(void *opaque) | |
1233 | { | |
669e846e SL |
1234 | if (kvm_mips_callbacks) { |
1235 | kvm_err("kvm: module already exists\n"); | |
1236 | return -EEXIST; | |
1237 | } | |
1238 | ||
d98403a5 | 1239 | return kvm_mips_emulation_init(&kvm_mips_callbacks); |
669e846e SL |
1240 | } |
1241 | ||
1242 | void kvm_arch_exit(void) | |
1243 | { | |
1244 | kvm_mips_callbacks = NULL; | |
1245 | } | |
1246 | ||
d116e812 DCZ |
1247 | int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, |
1248 | struct kvm_sregs *sregs) | |
669e846e | 1249 | { |
ed829857 | 1250 | return -ENOIOCTLCMD; |
669e846e SL |
1251 | } |
1252 | ||
d116e812 DCZ |
1253 | int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, |
1254 | struct kvm_sregs *sregs) | |
669e846e | 1255 | { |
ed829857 | 1256 | return -ENOIOCTLCMD; |
669e846e SL |
1257 | } |
1258 | ||
31928aa5 | 1259 | void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) |
669e846e | 1260 | { |
669e846e SL |
1261 | } |
1262 | ||
1263 | int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
1264 | { | |
ed829857 | 1265 | return -ENOIOCTLCMD; |
669e846e SL |
1266 | } |
1267 | ||
1268 | int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
1269 | { | |
ed829857 | 1270 | return -ENOIOCTLCMD; |
669e846e SL |
1271 | } |
1272 | ||
1273 | int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) | |
1274 | { | |
1275 | return VM_FAULT_SIGBUS; | |
1276 | } | |
1277 | ||
784aa3d7 | 1278 | int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) |
669e846e SL |
1279 | { |
1280 | int r; | |
1281 | ||
1282 | switch (ext) { | |
4c73fb2b | 1283 | case KVM_CAP_ONE_REG: |
5fafd874 | 1284 | case KVM_CAP_ENABLE_CAP: |
4c73fb2b DD |
1285 | r = 1; |
1286 | break; | |
669e846e SL |
1287 | case KVM_CAP_COALESCED_MMIO: |
1288 | r = KVM_COALESCED_MMIO_PAGE_OFFSET; | |
1289 | break; | |
5fafd874 | 1290 | case KVM_CAP_MIPS_FPU: |
556f2a52 JH |
1291 | /* We don't handle systems with inconsistent cpu_has_fpu */ |
1292 | r = !!raw_cpu_has_fpu; | |
5fafd874 | 1293 | break; |
d952bd07 JH |
1294 | case KVM_CAP_MIPS_MSA: |
1295 | /* | |
1296 | * We don't support MSA vector partitioning yet: | |
1297 | * 1) It would require explicit support which can't be tested | |
1298 | * yet due to lack of support in current hardware. | |
1299 | * 2) It extends the state that would need to be saved/restored | |
1300 | * by e.g. QEMU for migration. | |
1301 | * | |
1302 | * When vector partitioning hardware becomes available, support | |
1303 | * could be added by requiring a flag when enabling | |
1304 | * KVM_CAP_MIPS_MSA capability to indicate that userland knows | |
1305 | * to save/restore the appropriate extra state. | |
1306 | */ | |
1307 | r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF); | |
1308 | break; | |
669e846e SL |
1309 | default: |
1310 | r = 0; | |
1311 | break; | |
1312 | } | |
1313 | return r; | |
669e846e SL |
1314 | } |
1315 | ||
1316 | int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu) | |
1317 | { | |
1318 | return kvm_mips_pending_timer(vcpu); | |
1319 | } | |
1320 | ||
1321 | int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu) | |
1322 | { | |
1323 | int i; | |
1324 | struct mips_coproc *cop0; | |
1325 | ||
1326 | if (!vcpu) | |
1327 | return -1; | |
1328 | ||
6ad78a5c DCZ |
1329 | kvm_debug("VCPU Register Dump:\n"); |
1330 | kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc); | |
1331 | kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions); | |
669e846e SL |
1332 | |
1333 | for (i = 0; i < 32; i += 4) { | |
6ad78a5c | 1334 | kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i, |
669e846e SL |
1335 | vcpu->arch.gprs[i], |
1336 | vcpu->arch.gprs[i + 1], | |
1337 | vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]); | |
1338 | } | |
6ad78a5c DCZ |
1339 | kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi); |
1340 | kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo); | |
669e846e SL |
1341 | |
1342 | cop0 = vcpu->arch.cop0; | |
6ad78a5c DCZ |
1343 | kvm_debug("\tStatus: 0x%08lx, Cause: 0x%08lx\n", |
1344 | kvm_read_c0_guest_status(cop0), | |
1345 | kvm_read_c0_guest_cause(cop0)); | |
669e846e | 1346 | |
6ad78a5c | 1347 | kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0)); |
669e846e SL |
1348 | |
1349 | return 0; | |
1350 | } | |
1351 | ||
1352 | int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
1353 | { | |
1354 | int i; | |
1355 | ||
8d17dd04 | 1356 | for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++) |
bf32ebf6 | 1357 | vcpu->arch.gprs[i] = regs->gpr[i]; |
8d17dd04 | 1358 | vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */ |
669e846e SL |
1359 | vcpu->arch.hi = regs->hi; |
1360 | vcpu->arch.lo = regs->lo; | |
1361 | vcpu->arch.pc = regs->pc; | |
1362 | ||
4c73fb2b | 1363 | return 0; |
669e846e SL |
1364 | } |
1365 | ||
1366 | int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) | |
1367 | { | |
1368 | int i; | |
1369 | ||
8d17dd04 | 1370 | for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++) |
bf32ebf6 | 1371 | regs->gpr[i] = vcpu->arch.gprs[i]; |
669e846e SL |
1372 | |
1373 | regs->hi = vcpu->arch.hi; | |
1374 | regs->lo = vcpu->arch.lo; | |
1375 | regs->pc = vcpu->arch.pc; | |
1376 | ||
4c73fb2b | 1377 | return 0; |
669e846e SL |
1378 | } |
1379 | ||
0fae34f4 | 1380 | static void kvm_mips_comparecount_func(unsigned long data) |
669e846e SL |
1381 | { |
1382 | struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data; | |
1383 | ||
1384 | kvm_mips_callbacks->queue_timer_int(vcpu); | |
1385 | ||
1386 | vcpu->arch.wait = 0; | |
8577370f MT |
1387 | if (swait_active(&vcpu->wq)) |
1388 | swake_up(&vcpu->wq); | |
669e846e SL |
1389 | } |
1390 | ||
d116e812 | 1391 | /* low level hrtimer wake routine */ |
0fae34f4 | 1392 | static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer) |
669e846e SL |
1393 | { |
1394 | struct kvm_vcpu *vcpu; | |
1395 | ||
1396 | vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer); | |
1397 | kvm_mips_comparecount_func((unsigned long) vcpu); | |
e30492bb | 1398 | return kvm_mips_count_timeout(vcpu); |
669e846e SL |
1399 | } |
1400 | ||
1401 | int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu) | |
1402 | { | |
1403 | kvm_mips_callbacks->vcpu_init(vcpu); | |
1404 | hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC, | |
1405 | HRTIMER_MODE_REL); | |
1406 | vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup; | |
669e846e SL |
1407 | return 0; |
1408 | } | |
1409 | ||
d116e812 DCZ |
1410 | int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, |
1411 | struct kvm_translation *tr) | |
669e846e SL |
1412 | { |
1413 | return 0; | |
1414 | } | |
1415 | ||
1416 | /* Initial guest state */ | |
1417 | int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu) | |
1418 | { | |
1419 | return kvm_mips_callbacks->vcpu_setup(vcpu); | |
1420 | } | |
1421 | ||
d116e812 | 1422 | static void kvm_mips_set_c0_status(void) |
669e846e | 1423 | { |
8cffd197 | 1424 | u32 status = read_c0_status(); |
669e846e | 1425 | |
669e846e SL |
1426 | if (cpu_has_dsp) |
1427 | status |= (ST0_MX); | |
1428 | ||
1429 | write_c0_status(status); | |
1430 | ehb(); | |
1431 | } | |
1432 | ||
1433 | /* | |
1434 | * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV) | |
1435 | */ | |
1436 | int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu) | |
1437 | { | |
8cffd197 JH |
1438 | u32 cause = vcpu->arch.host_cp0_cause; |
1439 | u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f; | |
1440 | u32 __user *opc = (u32 __user *) vcpu->arch.pc; | |
669e846e SL |
1441 | unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr; |
1442 | enum emulation_result er = EMULATE_DONE; | |
1443 | int ret = RESUME_GUEST; | |
1444 | ||
c4c6f2ca JH |
1445 | /* re-enable HTW before enabling interrupts */ |
1446 | htw_start(); | |
1447 | ||
669e846e SL |
1448 | /* Set a default exit reason */ |
1449 | run->exit_reason = KVM_EXIT_UNKNOWN; | |
1450 | run->ready_for_interrupt_injection = 1; | |
1451 | ||
d116e812 DCZ |
1452 | /* |
1453 | * Set the appropriate status bits based on host CPU features, | |
1454 | * before we hit the scheduler | |
1455 | */ | |
669e846e SL |
1456 | kvm_mips_set_c0_status(); |
1457 | ||
1458 | local_irq_enable(); | |
1459 | ||
1460 | kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n", | |
1461 | cause, opc, run, vcpu); | |
1e09e86a | 1462 | trace_kvm_exit(vcpu, exccode); |
669e846e | 1463 | |
d116e812 DCZ |
1464 | /* |
1465 | * Do a privilege check, if in UM most of these exit conditions end up | |
669e846e SL |
1466 | * causing an exception to be delivered to the Guest Kernel |
1467 | */ | |
1468 | er = kvm_mips_check_privilege(cause, opc, run, vcpu); | |
1469 | if (er == EMULATE_PRIV_FAIL) { | |
1470 | goto skip_emul; | |
1471 | } else if (er == EMULATE_FAIL) { | |
1472 | run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
1473 | ret = RESUME_HOST; | |
1474 | goto skip_emul; | |
1475 | } | |
1476 | ||
1477 | switch (exccode) { | |
16d100db JH |
1478 | case EXCCODE_INT: |
1479 | kvm_debug("[%d]EXCCODE_INT @ %p\n", vcpu->vcpu_id, opc); | |
669e846e SL |
1480 | |
1481 | ++vcpu->stat.int_exits; | |
669e846e | 1482 | |
d116e812 | 1483 | if (need_resched()) |
669e846e | 1484 | cond_resched(); |
669e846e SL |
1485 | |
1486 | ret = RESUME_GUEST; | |
1487 | break; | |
1488 | ||
16d100db JH |
1489 | case EXCCODE_CPU: |
1490 | kvm_debug("EXCCODE_CPU: @ PC: %p\n", opc); | |
669e846e SL |
1491 | |
1492 | ++vcpu->stat.cop_unusable_exits; | |
669e846e SL |
1493 | ret = kvm_mips_callbacks->handle_cop_unusable(vcpu); |
1494 | /* XXXKYMA: Might need to return to user space */ | |
d116e812 | 1495 | if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN) |
669e846e | 1496 | ret = RESUME_HOST; |
669e846e SL |
1497 | break; |
1498 | ||
16d100db | 1499 | case EXCCODE_MOD: |
669e846e | 1500 | ++vcpu->stat.tlbmod_exits; |
669e846e SL |
1501 | ret = kvm_mips_callbacks->handle_tlb_mod(vcpu); |
1502 | break; | |
1503 | ||
16d100db | 1504 | case EXCCODE_TLBS: |
d116e812 DCZ |
1505 | kvm_debug("TLB ST fault: cause %#x, status %#lx, PC: %p, BadVaddr: %#lx\n", |
1506 | cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc, | |
1507 | badvaddr); | |
669e846e SL |
1508 | |
1509 | ++vcpu->stat.tlbmiss_st_exits; | |
669e846e SL |
1510 | ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu); |
1511 | break; | |
1512 | ||
16d100db | 1513 | case EXCCODE_TLBL: |
669e846e SL |
1514 | kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n", |
1515 | cause, opc, badvaddr); | |
1516 | ||
1517 | ++vcpu->stat.tlbmiss_ld_exits; | |
669e846e SL |
1518 | ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu); |
1519 | break; | |
1520 | ||
16d100db | 1521 | case EXCCODE_ADES: |
669e846e | 1522 | ++vcpu->stat.addrerr_st_exits; |
669e846e SL |
1523 | ret = kvm_mips_callbacks->handle_addr_err_st(vcpu); |
1524 | break; | |
1525 | ||
16d100db | 1526 | case EXCCODE_ADEL: |
669e846e | 1527 | ++vcpu->stat.addrerr_ld_exits; |
669e846e SL |
1528 | ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu); |
1529 | break; | |
1530 | ||
16d100db | 1531 | case EXCCODE_SYS: |
669e846e | 1532 | ++vcpu->stat.syscall_exits; |
669e846e SL |
1533 | ret = kvm_mips_callbacks->handle_syscall(vcpu); |
1534 | break; | |
1535 | ||
16d100db | 1536 | case EXCCODE_RI: |
669e846e | 1537 | ++vcpu->stat.resvd_inst_exits; |
669e846e SL |
1538 | ret = kvm_mips_callbacks->handle_res_inst(vcpu); |
1539 | break; | |
1540 | ||
16d100db | 1541 | case EXCCODE_BP: |
669e846e | 1542 | ++vcpu->stat.break_inst_exits; |
669e846e SL |
1543 | ret = kvm_mips_callbacks->handle_break(vcpu); |
1544 | break; | |
1545 | ||
16d100db | 1546 | case EXCCODE_TR: |
0a560427 | 1547 | ++vcpu->stat.trap_inst_exits; |
0a560427 JH |
1548 | ret = kvm_mips_callbacks->handle_trap(vcpu); |
1549 | break; | |
1550 | ||
16d100db | 1551 | case EXCCODE_MSAFPE: |
c2537ed9 | 1552 | ++vcpu->stat.msa_fpe_exits; |
c2537ed9 JH |
1553 | ret = kvm_mips_callbacks->handle_msa_fpe(vcpu); |
1554 | break; | |
1555 | ||
16d100db | 1556 | case EXCCODE_FPE: |
1c0cd66a | 1557 | ++vcpu->stat.fpe_exits; |
1c0cd66a JH |
1558 | ret = kvm_mips_callbacks->handle_fpe(vcpu); |
1559 | break; | |
1560 | ||
16d100db | 1561 | case EXCCODE_MSADIS: |
c2537ed9 | 1562 | ++vcpu->stat.msa_disabled_exits; |
98119ad5 JH |
1563 | ret = kvm_mips_callbacks->handle_msa_disabled(vcpu); |
1564 | break; | |
1565 | ||
669e846e | 1566 | default: |
d116e812 DCZ |
1567 | kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x BadVaddr: %#lx Status: %#lx\n", |
1568 | exccode, opc, kvm_get_inst(opc, vcpu), badvaddr, | |
1569 | kvm_read_c0_guest_status(vcpu->arch.cop0)); | |
669e846e SL |
1570 | kvm_arch_vcpu_dump_regs(vcpu); |
1571 | run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
1572 | ret = RESUME_HOST; | |
1573 | break; | |
1574 | ||
1575 | } | |
1576 | ||
1577 | skip_emul: | |
1578 | local_irq_disable(); | |
1579 | ||
1580 | if (er == EMULATE_DONE && !(ret & RESUME_HOST)) | |
1581 | kvm_mips_deliver_interrupts(vcpu, cause); | |
1582 | ||
1583 | if (!(ret & RESUME_HOST)) { | |
d116e812 | 1584 | /* Only check for signals if not already exiting to userspace */ |
669e846e SL |
1585 | if (signal_pending(current)) { |
1586 | run->exit_reason = KVM_EXIT_INTR; | |
1587 | ret = (-EINTR << 2) | RESUME_HOST; | |
1588 | ++vcpu->stat.signal_exits; | |
1e09e86a | 1589 | trace_kvm_exit(vcpu, KVM_TRACE_EXIT_SIGNAL); |
669e846e SL |
1590 | } |
1591 | } | |
1592 | ||
98e91b84 | 1593 | if (ret == RESUME_GUEST) { |
93258604 JH |
1594 | trace_kvm_reenter(vcpu); |
1595 | ||
25b08c7f JH |
1596 | kvm_mips_check_asids(vcpu); |
1597 | ||
98e91b84 | 1598 | /* |
539cb89f JH |
1599 | * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context |
1600 | * is live), restore FCR31 / MSACSR. | |
98e91b84 JH |
1601 | * |
1602 | * This should be before returning to the guest exception | |
539cb89f JH |
1603 | * vector, as it may well cause an [MSA] FP exception if there |
1604 | * are pending exception bits unmasked. (see | |
98e91b84 JH |
1605 | * kvm_mips_csr_die_notifier() for how that is handled). |
1606 | */ | |
1607 | if (kvm_mips_guest_has_fpu(&vcpu->arch) && | |
1608 | read_c0_status() & ST0_CU1) | |
1609 | __kvm_restore_fcsr(&vcpu->arch); | |
539cb89f JH |
1610 | |
1611 | if (kvm_mips_guest_has_msa(&vcpu->arch) && | |
1612 | read_c0_config5() & MIPS_CONF5_MSAEN) | |
1613 | __kvm_restore_msacsr(&vcpu->arch); | |
98e91b84 JH |
1614 | } |
1615 | ||
c4c6f2ca JH |
1616 | /* Disable HTW before returning to guest or host */ |
1617 | htw_stop(); | |
1618 | ||
669e846e SL |
1619 | return ret; |
1620 | } | |
1621 | ||
98e91b84 JH |
1622 | /* Enable FPU for guest and restore context */ |
1623 | void kvm_own_fpu(struct kvm_vcpu *vcpu) | |
1624 | { | |
1625 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
1626 | unsigned int sr, cfg5; | |
1627 | ||
1628 | preempt_disable(); | |
1629 | ||
539cb89f JH |
1630 | sr = kvm_read_c0_guest_status(cop0); |
1631 | ||
1632 | /* | |
1633 | * If MSA state is already live, it is undefined how it interacts with | |
1634 | * FR=0 FPU state, and we don't want to hit reserved instruction | |
1635 | * exceptions trying to save the MSA state later when CU=1 && FR=1, so | |
1636 | * play it safe and save it first. | |
1637 | * | |
1638 | * In theory we shouldn't ever hit this case since kvm_lose_fpu() should | |
1639 | * get called when guest CU1 is set, however we can't trust the guest | |
1640 | * not to clobber the status register directly via the commpage. | |
1641 | */ | |
1642 | if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) && | |
f943176a | 1643 | vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) |
539cb89f JH |
1644 | kvm_lose_fpu(vcpu); |
1645 | ||
98e91b84 JH |
1646 | /* |
1647 | * Enable FPU for guest | |
1648 | * We set FR and FRE according to guest context | |
1649 | */ | |
98e91b84 JH |
1650 | change_c0_status(ST0_CU1 | ST0_FR, sr); |
1651 | if (cpu_has_fre) { | |
1652 | cfg5 = kvm_read_c0_guest_config5(cop0); | |
1653 | change_c0_config5(MIPS_CONF5_FRE, cfg5); | |
1654 | } | |
1655 | enable_fpu_hazard(); | |
1656 | ||
1657 | /* If guest FPU state not active, restore it now */ | |
f943176a | 1658 | if (!(vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)) { |
98e91b84 | 1659 | __kvm_restore_fpu(&vcpu->arch); |
f943176a | 1660 | vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU; |
04ebebf4 JH |
1661 | trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_FPU); |
1662 | } else { | |
1663 | trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_FPU); | |
98e91b84 JH |
1664 | } |
1665 | ||
1666 | preempt_enable(); | |
1667 | } | |
1668 | ||
539cb89f JH |
1669 | #ifdef CONFIG_CPU_HAS_MSA |
1670 | /* Enable MSA for guest and restore context */ | |
1671 | void kvm_own_msa(struct kvm_vcpu *vcpu) | |
1672 | { | |
1673 | struct mips_coproc *cop0 = vcpu->arch.cop0; | |
1674 | unsigned int sr, cfg5; | |
1675 | ||
1676 | preempt_disable(); | |
1677 | ||
1678 | /* | |
1679 | * Enable FPU if enabled in guest, since we're restoring FPU context | |
1680 | * anyway. We set FR and FRE according to guest context. | |
1681 | */ | |
1682 | if (kvm_mips_guest_has_fpu(&vcpu->arch)) { | |
1683 | sr = kvm_read_c0_guest_status(cop0); | |
1684 | ||
1685 | /* | |
1686 | * If FR=0 FPU state is already live, it is undefined how it | |
1687 | * interacts with MSA state, so play it safe and save it first. | |
1688 | */ | |
1689 | if (!(sr & ST0_FR) && | |
f943176a JH |
1690 | (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | |
1691 | KVM_MIPS_AUX_MSA)) == KVM_MIPS_AUX_FPU) | |
539cb89f JH |
1692 | kvm_lose_fpu(vcpu); |
1693 | ||
1694 | change_c0_status(ST0_CU1 | ST0_FR, sr); | |
1695 | if (sr & ST0_CU1 && cpu_has_fre) { | |
1696 | cfg5 = kvm_read_c0_guest_config5(cop0); | |
1697 | change_c0_config5(MIPS_CONF5_FRE, cfg5); | |
1698 | } | |
1699 | } | |
1700 | ||
1701 | /* Enable MSA for guest */ | |
1702 | set_c0_config5(MIPS_CONF5_MSAEN); | |
1703 | enable_fpu_hazard(); | |
1704 | ||
f943176a JH |
1705 | switch (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA)) { |
1706 | case KVM_MIPS_AUX_FPU: | |
539cb89f JH |
1707 | /* |
1708 | * Guest FPU state already loaded, only restore upper MSA state | |
1709 | */ | |
1710 | __kvm_restore_msa_upper(&vcpu->arch); | |
f943176a | 1711 | vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA; |
04ebebf4 | 1712 | trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_MSA); |
539cb89f JH |
1713 | break; |
1714 | case 0: | |
1715 | /* Neither FPU or MSA already active, restore full MSA state */ | |
1716 | __kvm_restore_msa(&vcpu->arch); | |
f943176a | 1717 | vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA; |
539cb89f | 1718 | if (kvm_mips_guest_has_fpu(&vcpu->arch)) |
f943176a | 1719 | vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU; |
04ebebf4 JH |
1720 | trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, |
1721 | KVM_TRACE_AUX_FPU_MSA); | |
539cb89f JH |
1722 | break; |
1723 | default: | |
04ebebf4 | 1724 | trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_MSA); |
539cb89f JH |
1725 | break; |
1726 | } | |
1727 | ||
1728 | preempt_enable(); | |
1729 | } | |
1730 | #endif | |
1731 | ||
1732 | /* Drop FPU & MSA without saving it */ | |
98e91b84 JH |
1733 | void kvm_drop_fpu(struct kvm_vcpu *vcpu) |
1734 | { | |
1735 | preempt_disable(); | |
f943176a | 1736 | if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) { |
539cb89f | 1737 | disable_msa(); |
04ebebf4 | 1738 | trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_MSA); |
f943176a | 1739 | vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_MSA; |
539cb89f | 1740 | } |
f943176a | 1741 | if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) { |
98e91b84 | 1742 | clear_c0_status(ST0_CU1 | ST0_FR); |
04ebebf4 | 1743 | trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_FPU); |
f943176a | 1744 | vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU; |
98e91b84 JH |
1745 | } |
1746 | preempt_enable(); | |
1747 | } | |
1748 | ||
539cb89f | 1749 | /* Save and disable FPU & MSA */ |
98e91b84 JH |
1750 | void kvm_lose_fpu(struct kvm_vcpu *vcpu) |
1751 | { | |
1752 | /* | |
539cb89f JH |
1753 | * FPU & MSA get disabled in root context (hardware) when it is disabled |
1754 | * in guest context (software), but the register state in the hardware | |
1755 | * may still be in use. This is why we explicitly re-enable the hardware | |
98e91b84 JH |
1756 | * before saving. |
1757 | */ | |
1758 | ||
1759 | preempt_disable(); | |
f943176a | 1760 | if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) { |
539cb89f JH |
1761 | set_c0_config5(MIPS_CONF5_MSAEN); |
1762 | enable_fpu_hazard(); | |
1763 | ||
1764 | __kvm_save_msa(&vcpu->arch); | |
04ebebf4 | 1765 | trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU_MSA); |
539cb89f JH |
1766 | |
1767 | /* Disable MSA & FPU */ | |
1768 | disable_msa(); | |
f943176a | 1769 | if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) { |
539cb89f | 1770 | clear_c0_status(ST0_CU1 | ST0_FR); |
4ac33429 JH |
1771 | disable_fpu_hazard(); |
1772 | } | |
f943176a JH |
1773 | vcpu->arch.aux_inuse &= ~(KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA); |
1774 | } else if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) { | |
98e91b84 JH |
1775 | set_c0_status(ST0_CU1); |
1776 | enable_fpu_hazard(); | |
1777 | ||
1778 | __kvm_save_fpu(&vcpu->arch); | |
f943176a | 1779 | vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU; |
04ebebf4 | 1780 | trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU); |
98e91b84 JH |
1781 | |
1782 | /* Disable FPU */ | |
1783 | clear_c0_status(ST0_CU1 | ST0_FR); | |
4ac33429 | 1784 | disable_fpu_hazard(); |
98e91b84 JH |
1785 | } |
1786 | preempt_enable(); | |
1787 | } | |
1788 | ||
1789 | /* | |
539cb89f JH |
1790 | * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are |
1791 | * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP | |
1792 | * exception if cause bits are set in the value being written. | |
98e91b84 JH |
1793 | */ |
1794 | static int kvm_mips_csr_die_notify(struct notifier_block *self, | |
1795 | unsigned long cmd, void *ptr) | |
1796 | { | |
1797 | struct die_args *args = (struct die_args *)ptr; | |
1798 | struct pt_regs *regs = args->regs; | |
1799 | unsigned long pc; | |
1800 | ||
539cb89f JH |
1801 | /* Only interested in FPE and MSAFPE */ |
1802 | if (cmd != DIE_FP && cmd != DIE_MSAFP) | |
98e91b84 JH |
1803 | return NOTIFY_DONE; |
1804 | ||
1805 | /* Return immediately if guest context isn't active */ | |
1806 | if (!(current->flags & PF_VCPU)) | |
1807 | return NOTIFY_DONE; | |
1808 | ||
1809 | /* Should never get here from user mode */ | |
1810 | BUG_ON(user_mode(regs)); | |
1811 | ||
1812 | pc = instruction_pointer(regs); | |
1813 | switch (cmd) { | |
1814 | case DIE_FP: | |
1815 | /* match 2nd instruction in __kvm_restore_fcsr */ | |
1816 | if (pc != (unsigned long)&__kvm_restore_fcsr + 4) | |
1817 | return NOTIFY_DONE; | |
1818 | break; | |
539cb89f JH |
1819 | case DIE_MSAFP: |
1820 | /* match 2nd/3rd instruction in __kvm_restore_msacsr */ | |
1821 | if (!cpu_has_msa || | |
1822 | pc < (unsigned long)&__kvm_restore_msacsr + 4 || | |
1823 | pc > (unsigned long)&__kvm_restore_msacsr + 8) | |
1824 | return NOTIFY_DONE; | |
1825 | break; | |
98e91b84 JH |
1826 | } |
1827 | ||
1828 | /* Move PC forward a little and continue executing */ | |
1829 | instruction_pointer(regs) += 4; | |
1830 | ||
1831 | return NOTIFY_STOP; | |
1832 | } | |
1833 | ||
1834 | static struct notifier_block kvm_mips_csr_die_notifier = { | |
1835 | .notifier_call = kvm_mips_csr_die_notify, | |
1836 | }; | |
1837 | ||
2db9d233 | 1838 | static int __init kvm_mips_init(void) |
669e846e SL |
1839 | { |
1840 | int ret; | |
1841 | ||
1e5217f5 JH |
1842 | ret = kvm_mips_entry_setup(); |
1843 | if (ret) | |
1844 | return ret; | |
1845 | ||
669e846e SL |
1846 | ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE); |
1847 | ||
1848 | if (ret) | |
1849 | return ret; | |
1850 | ||
98e91b84 JH |
1851 | register_die_notifier(&kvm_mips_csr_die_notifier); |
1852 | ||
669e846e SL |
1853 | return 0; |
1854 | } | |
1855 | ||
2db9d233 | 1856 | static void __exit kvm_mips_exit(void) |
669e846e SL |
1857 | { |
1858 | kvm_exit(); | |
1859 | ||
98e91b84 | 1860 | unregister_die_notifier(&kvm_mips_csr_die_notifier); |
669e846e SL |
1861 | } |
1862 | ||
1863 | module_init(kvm_mips_init); | |
1864 | module_exit(kvm_mips_exit); | |
1865 | ||
1866 | EXPORT_TRACEPOINT_SYMBOL(kvm_exit); |