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Document the meaning of the CPU_MIPS32, CPU_MIPS64, CPU_MIPSR1 and
[linux-2.6-block.git] / arch / mips / kernel / traps.c
CommitLineData
1da177e4
LT		 1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 - 1999, 2000, 01 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2000, 01 MIPS Technologies, Inc.
3b2396d9 12 * Copyright (C) 2002, 2003, 2004, 2005 Maciej W. Rozycki
1da177e4
LT		 13 */
14#include <linux/config.h>
15#include <linux/init.h>
16#include <linux/mm.h>
17#include <linux/module.h>
18#include <linux/sched.h>
19#include <linux/smp.h>
20#include <linux/smp_lock.h>
21#include <linux/spinlock.h>
22#include <linux/kallsyms.h>
e01402b1 23#include <linux/bootmem.h>
1da177e4
LT		 24
25#include <asm/bootinfo.h>
26#include <asm/branch.h>
27#include <asm/break.h>
28#include <asm/cpu.h>
e50c0a8f 29#include <asm/dsp.h>
1da177e4 30#include <asm/fpu.h>
340ee4b9
RB		 31#include <asm/mipsregs.h>
32#include <asm/mipsmtregs.h>
1da177e4
LT		 33#include <asm/module.h>
34#include <asm/pgtable.h>
35#include <asm/ptrace.h>
36#include <asm/sections.h>
37#include <asm/system.h>
38#include <asm/tlbdebug.h>
39#include <asm/traps.h>
40#include <asm/uaccess.h>
41#include <asm/mmu_context.h>
42#include <asm/watch.h>
43#include <asm/types.h>
44
45extern asmlinkage void handle_tlbm(void);
46extern asmlinkage void handle_tlbl(void);
47extern asmlinkage void handle_tlbs(void);
48extern asmlinkage void handle_adel(void);
49extern asmlinkage void handle_ades(void);
50extern asmlinkage void handle_ibe(void);
51extern asmlinkage void handle_dbe(void);
52extern asmlinkage void handle_sys(void);
53extern asmlinkage void handle_bp(void);
54extern asmlinkage void handle_ri(void);
55extern asmlinkage void handle_cpu(void);
56extern asmlinkage void handle_ov(void);
57extern asmlinkage void handle_tr(void);
58extern asmlinkage void handle_fpe(void);
59extern asmlinkage void handle_mdmx(void);
60extern asmlinkage void handle_watch(void);
340ee4b9 61extern asmlinkage void handle_mt(void);
e50c0a8f 62extern asmlinkage void handle_dsp(void);
1da177e4
LT		 63extern asmlinkage void handle_mcheck(void);
64extern asmlinkage void handle_reserved(void);
65
66extern int fpu_emulator_cop1Handler(int xcptno, struct pt_regs *xcp,
67 struct mips_fpu_soft_struct *ctx);
68
69void (*board_be_init)(void);
70int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
e01402b1
RB		 71void (*board_nmi_handler_setup)(void);
72void (*board_ejtag_handler_setup)(void);
73void (*board_bind_eic_interrupt)(int irq, int regset);
1da177e4
LT		 74
75/*
76 * These constant is for searching for possible module text segments.
77 * MODULE_RANGE is a guess of how much space is likely to be vmalloced.
78 */
79#define MODULE_RANGE (8*1024*1024)
80
81/*
82 * This routine abuses get_user()/put_user() to reference pointers
83 * with at least a bit of error checking ...
84 */
85void show_stack(struct task_struct *task, unsigned long *sp)
86{
87 const int field = 2 * sizeof(unsigned long);
88 long stackdata;
89 int i;
90
91 if (!sp) {
92 if (task && task != current)
93 sp = (unsigned long *) task->thread.reg29;
94 else
95 sp = (unsigned long *) &sp;
96 }
97
98 printk("Stack :");
99 i = 0;
100 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
101 if (i && ((i % (64 / field)) == 0))
102 printk("\n ");
103 if (i > 39) {
104 printk(" ...");
105 break;
106 }
107
108 if (__get_user(stackdata, sp++)) {
109 printk(" (Bad stack address)");
110 break;
111 }
112
113 printk(" %0*lx", field, stackdata);
114 i++;
115 }
116 printk("\n");
117}
118
119void show_trace(struct task_struct *task, unsigned long *stack)
120{
121 const int field = 2 * sizeof(unsigned long);
122 unsigned long addr;
123
124 if (!stack) {
125 if (task && task != current)
126 stack = (unsigned long *) task->thread.reg29;
127 else
128 stack = (unsigned long *) &stack;
129 }
130
131 printk("Call Trace:");
132#ifdef CONFIG_KALLSYMS
133 printk("\n");
134#endif
135 while (!kstack_end(stack)) {
136 addr = *stack++;
137 if (__kernel_text_address(addr)) {
138 printk(" [<%0*lx>] ", field, addr);
139 print_symbol("%s\n", addr);
140 }
141 }
142 printk("\n");
143}
144
145/*
146 * The architecture-independent dump_stack generator
147 */
148void dump_stack(void)
149{
150 unsigned long stack;
151
152 show_trace(current, &stack);
153}
154
155EXPORT_SYMBOL(dump_stack);
156
157void show_code(unsigned int *pc)
158{
159 long i;
160
161 printk("\nCode:");
162
163 for(i = -3 ; i < 6 ; i++) {
164 unsigned int insn;
165 if (__get_user(insn, pc + i)) {
166 printk(" (Bad address in epc)\n");
167 break;
168 }
169 printk("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>'));
170 }
171}
172
173void show_regs(struct pt_regs *regs)
174{
175 const int field = 2 * sizeof(unsigned long);
176 unsigned int cause = regs->cp0_cause;
177 int i;
178
179 printk("Cpu %d\n", smp_processor_id());
180
181 /*
182 * Saved main processor registers
183 */
184 for (i = 0; i < 32; ) {
185 if ((i % 4) == 0)
186 printk("$%2d :", i);
187 if (i == 0)
188 printk(" %0*lx", field, 0UL);
189 else if (i == 26 || i == 27)
190 printk(" %*s", field, "");
191 else
192 printk(" %0*lx", field, regs->regs[i]);
193
194 i++;
195 if ((i % 4) == 0)
196 printk("\n");
197 }
198
199 printk("Hi : %0*lx\n", field, regs->hi);
200 printk("Lo : %0*lx\n", field, regs->lo);
201
202 /*
203 * Saved cp0 registers
204 */
205 printk("epc : %0*lx ", field, regs->cp0_epc);
206 print_symbol("%s ", regs->cp0_epc);
207 printk(" %s\n", print_tainted());
208 printk("ra : %0*lx ", field, regs->regs[31]);
209 print_symbol("%s\n", regs->regs[31]);
210
211 printk("Status: %08x ", (uint32_t) regs->cp0_status);
212
3b2396d9
MR		 213 if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) {
214 if (regs->cp0_status & ST0_KUO)
215 printk("KUo ");
216 if (regs->cp0_status & ST0_IEO)
217 printk("IEo ");
218 if (regs->cp0_status & ST0_KUP)
219 printk("KUp ");
220 if (regs->cp0_status & ST0_IEP)
221 printk("IEp ");
222 if (regs->cp0_status & ST0_KUC)
223 printk("KUc ");
224 if (regs->cp0_status & ST0_IEC)
225 printk("IEc ");
226 } else {
227 if (regs->cp0_status & ST0_KX)
228 printk("KX ");
229 if (regs->cp0_status & ST0_SX)
230 printk("SX ");
231 if (regs->cp0_status & ST0_UX)
232 printk("UX ");
233 switch (regs->cp0_status & ST0_KSU) {
234 case KSU_USER:
235 printk("USER ");
236 break;
237 case KSU_SUPERVISOR:
238 printk("SUPERVISOR ");
239 break;
240 case KSU_KERNEL:
241 printk("KERNEL ");
242 break;
243 default:
244 printk("BAD_MODE ");
245 break;
246 }
247 if (regs->cp0_status & ST0_ERL)
248 printk("ERL ");
249 if (regs->cp0_status & ST0_EXL)
250 printk("EXL ");
251 if (regs->cp0_status & ST0_IE)
252 printk("IE ");
1da177e4 253 }
1da177e4
LT		 254 printk("\n");
255
256 printk("Cause : %08x\n", cause);
257
258 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
259 if (1 <= cause && cause <= 5)
260 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
261
262 printk("PrId : %08x\n", read_c0_prid());
263}
264
265void show_registers(struct pt_regs *regs)
266{
267 show_regs(regs);
268 print_modules();
269 printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n",
270 current->comm, current->pid, current_thread_info(), current);
271 show_stack(current, (long *) regs->regs[29]);
272 show_trace(current, (long *) regs->regs[29]);
273 show_code((unsigned int *) regs->cp0_epc);
274 printk("\n");
275}
276
277static DEFINE_SPINLOCK(die_lock);
278
260c9673
MR		 279NORET_TYPE void ATTRIB_NORET __die(const char * str, struct pt_regs * regs,
280 const char * file, const char * func,
281 unsigned long line)
1da177e4
LT		 282{
283 static int die_counter;
284
285 console_verbose();
286 spin_lock_irq(&die_lock);
287 printk("%s", str);
288 if (file && func)
289 printk(" in %s:%s, line %ld", file, func, line);
290 printk("[#%d]:\n", ++die_counter);
291 show_registers(regs);
292 spin_unlock_irq(&die_lock);
293 do_exit(SIGSEGV);
294}
295
296void __die_if_kernel(const char * str, struct pt_regs * regs,
297 const char * file, const char * func, unsigned long line)
298{
299 if (!user_mode(regs))
300 __die(str, regs, file, func, line);
301}
302
303extern const struct exception_table_entry __start___dbe_table[];
304extern const struct exception_table_entry __stop___dbe_table[];
305
306void __declare_dbe_table(void)
307{
308 __asm__ __volatile__(
309 ".section\t__dbe_table,\"a\"\n\t"
310 ".previous"
311 );
312}
313
314/* Given an address, look for it in the exception tables. */
315static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
316{
317 const struct exception_table_entry *e;
318
319 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
320 if (!e)
321 e = search_module_dbetables(addr);
322 return e;
323}
324
325asmlinkage void do_be(struct pt_regs *regs)
326{
327 const int field = 2 * sizeof(unsigned long);
328 const struct exception_table_entry *fixup = NULL;
329 int data = regs->cp0_cause & 4;
330 int action = MIPS_BE_FATAL;
331
332 /* XXX For now. Fixme, this searches the wrong table ... */
333 if (data && !user_mode(regs))
334 fixup = search_dbe_tables(exception_epc(regs));
335
336 if (fixup)
337 action = MIPS_BE_FIXUP;
338
339 if (board_be_handler)
340 action = board_be_handler(regs, fixup != 0);
341
342 switch (action) {
343 case MIPS_BE_DISCARD:
344 return;
345 case MIPS_BE_FIXUP:
346 if (fixup) {
347 regs->cp0_epc = fixup->nextinsn;
348 return;
349 }
350 break;
351 default:
352 break;
353 }
354
355 /*
356 * Assume it would be too dangerous to continue ...
357 */
358 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
359 data ? "Data" : "Instruction",
360 field, regs->cp0_epc, field, regs->regs[31]);
361 die_if_kernel("Oops", regs);
362 force_sig(SIGBUS, current);
363}
364
365static inline int get_insn_opcode(struct pt_regs *regs, unsigned int *opcode)
366{
fe00f943 367 unsigned int __user *epc;
1da177e4 368
fe00f943 369 epc = (unsigned int __user *) regs->cp0_epc +
1da177e4
LT		 370 ((regs->cp0_cause & CAUSEF_BD) != 0);
371 if (!get_user(*opcode, epc))
372 return 0;
373
374 force_sig(SIGSEGV, current);
375 return 1;
376}
377
378/*
379 * ll/sc emulation
380 */
381
382#define OPCODE 0xfc000000
383#define BASE 0x03e00000
384#define RT 0x001f0000
385#define OFFSET 0x0000ffff
386#define LL 0xc0000000
387#define SC 0xe0000000
3c37026d
RB		 388#define SPEC3 0x7c000000
389#define RD 0x0000f800
390#define FUNC 0x0000003f
391#define RDHWR 0x0000003b
1da177e4
LT		 392
393/*
394 * The ll_bit is cleared by r*_switch.S
395 */
396
397unsigned long ll_bit;
398
399static struct task_struct *ll_task = NULL;
400
401static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode)
402{
fe00f943 403 unsigned long value, __user *vaddr;
1da177e4
LT		 404 long offset;
405 int signal = 0;
406
407 /*
408 * analyse the ll instruction that just caused a ri exception
409 * and put the referenced address to addr.
410 */
411
412 /* sign extend offset */
413 offset = opcode & OFFSET;
414 offset <<= 16;
415 offset >>= 16;
416
fe00f943
RB		 417 vaddr = (unsigned long __user *)
418 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
1da177e4
LT		 419
420 if ((unsigned long)vaddr & 3) {
421 signal = SIGBUS;
422 goto sig;
423 }
424 if (get_user(value, vaddr)) {
425 signal = SIGSEGV;
426 goto sig;
427 }
428
429 preempt_disable();
430
431 if (ll_task == NULL || ll_task == current) {
432 ll_bit = 1;
433 } else {
434 ll_bit = 0;
435 }
436 ll_task = current;
437
438 preempt_enable();
439
6dd04688
RB		 440 compute_return_epc(regs);
441
1da177e4
LT		 442 regs->regs[(opcode & RT) >> 16] = value;
443
1da177e4
LT		 444 return;
445
446sig:
447 force_sig(signal, current);
448}
449
450static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode)
451{
fe00f943
RB		 452 unsigned long __user *vaddr;
453 unsigned long reg;
1da177e4
LT		 454 long offset;
455 int signal = 0;
456
457 /*
458 * analyse the sc instruction that just caused a ri exception
459 * and put the referenced address to addr.
460 */
461
462 /* sign extend offset */
463 offset = opcode & OFFSET;
464 offset <<= 16;
465 offset >>= 16;
466
fe00f943
RB		 467 vaddr = (unsigned long __user *)
468 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
1da177e4
LT		 469 reg = (opcode & RT) >> 16;
470
471 if ((unsigned long)vaddr & 3) {
472 signal = SIGBUS;
473 goto sig;
474 }
475
476 preempt_disable();
477
478 if (ll_bit == 0 || ll_task != current) {
05b8042a 479 compute_return_epc(regs);
1da177e4
LT		 480 regs->regs[reg] = 0;
481 preempt_enable();
1da177e4
LT		 482 return;
483 }
484
485 preempt_enable();
486
487 if (put_user(regs->regs[reg], vaddr)) {
488 signal = SIGSEGV;
489 goto sig;
490 }
491
6dd04688 492 compute_return_epc(regs);
1da177e4
LT		 493 regs->regs[reg] = 1;
494
1da177e4
LT		 495 return;
496
497sig:
498 force_sig(signal, current);
499}
500
501/*
502 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
503 * opcodes are supposed to result in coprocessor unusable exceptions if
504 * executed on ll/sc-less processors. That's the theory. In practice a
505 * few processors such as NEC's VR4100 throw reserved instruction exceptions
506 * instead, so we're doing the emulation thing in both exception handlers.
507 */
508static inline int simulate_llsc(struct pt_regs *regs)
509{
510 unsigned int opcode;
511
512 if (unlikely(get_insn_opcode(regs, &opcode)))
513 return -EFAULT;
514
515 if ((opcode & OPCODE) == LL) {
516 simulate_ll(regs, opcode);
517 return 0;
518 }
519 if ((opcode & OPCODE) == SC) {
520 simulate_sc(regs, opcode);
521 return 0;
522 }
523
524 return -EFAULT; /* Strange things going on ... */
525}
526
3c37026d
RB		 527/*
528 * Simulate trapping 'rdhwr' instructions to provide user accessible
529 * registers not implemented in hardware. The only current use of this
530 * is the thread area pointer.
531 */
532static inline int simulate_rdhwr(struct pt_regs *regs)
533{
534 struct thread_info *ti = current->thread_info;
535 unsigned int opcode;
536
537 if (unlikely(get_insn_opcode(regs, &opcode)))
538 return -EFAULT;
539
540 if (unlikely(compute_return_epc(regs)))
541 return -EFAULT;
542
543 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
544 int rd = (opcode & RD) >> 11;
545 int rt = (opcode & RT) >> 16;
546 switch (rd) {
547 case 29:
548 regs->regs[rt] = ti->tp_value;
549 break;
550 default:
551 return -EFAULT;
552 }
553 }
554
555 return 0;
556}
557
1da177e4
LT		 558asmlinkage void do_ov(struct pt_regs *regs)
559{
560 siginfo_t info;
561
562 info.si_code = FPE_INTOVF;
563 info.si_signo = SIGFPE;
564 info.si_errno = 0;
fe00f943 565 info.si_addr = (void __user *) regs->cp0_epc;
1da177e4
LT		 566 force_sig_info(SIGFPE, &info, current);
567}
568
569/*
570 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
571 */
572asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
573{
574 if (fcr31 & FPU_CSR_UNI_X) {
575 int sig;
576
577 preempt_disable();
578
cd21dfcf
RB		 579#ifdef CONFIG_PREEMPT
580 if (!is_fpu_owner()) {
581 /* We might lose fpu before disabling preempt... */
582 own_fpu();
583 BUG_ON(!used_math());
584 restore_fp(current);
585 }
586#endif
1da177e4
LT		 587 /*
588 * Unimplemented operation exception. If we've got the full
589 * software emulator on-board, let's use it...
590 *
591 * Force FPU to dump state into task/thread context. We're
592 * moving a lot of data here for what is probably a single
593 * instruction, but the alternative is to pre-decode the FP
594 * register operands before invoking the emulator, which seems
595 * a bit extreme for what should be an infrequent event.
596 */
597 save_fp(current);
cd21dfcf
RB		 598 /* Ensure 'resume' not overwrite saved fp context again. */
599 lose_fpu();
600
601 preempt_enable();
1da177e4
LT		 602
603 /* Run the emulator */
604 sig = fpu_emulator_cop1Handler (0, regs,
605 &current->thread.fpu.soft);
606
cd21dfcf
RB		 607 preempt_disable();
608
609 own_fpu(); /* Using the FPU again. */
1da177e4
LT		 610 /*
611 * We can't allow the emulated instruction to leave any of
612 * the cause bit set in $fcr31.
613 */
614 current->thread.fpu.soft.fcr31 &= ~FPU_CSR_ALL_X;
615
616 /* Restore the hardware register state */
617 restore_fp(current);
618
619 preempt_enable();
620
621 /* If something went wrong, signal */
622 if (sig)
623 force_sig(sig, current);
624
625 return;
626 }
627
628 force_sig(SIGFPE, current);
629}
630
631asmlinkage void do_bp(struct pt_regs *regs)
632{
633 unsigned int opcode, bcode;
634 siginfo_t info;
635
636 die_if_kernel("Break instruction in kernel code", regs);
637
638 if (get_insn_opcode(regs, &opcode))
639 return;
640
641 /*
642 * There is the ancient bug in the MIPS assemblers that the break
643 * code starts left to bit 16 instead to bit 6 in the opcode.
644 * Gas is bug-compatible, but not always, grrr...
645 * We handle both cases with a simple heuristics. --macro
646 */
647 bcode = ((opcode >> 6) & ((1 << 20) - 1));
648 if (bcode < (1 << 10))
649 bcode <<= 10;
650
651 /*
652 * (A short test says that IRIX 5.3 sends SIGTRAP for all break
653 * insns, even for break codes that indicate arithmetic failures.
654 * Weird ...)
655 * But should we continue the brokenness??? --macro
656 */
657 switch (bcode) {
658 case BRK_OVERFLOW << 10:
659 case BRK_DIVZERO << 10:
660 if (bcode == (BRK_DIVZERO << 10))
661 info.si_code = FPE_INTDIV;
662 else
663 info.si_code = FPE_INTOVF;
664 info.si_signo = SIGFPE;
665 info.si_errno = 0;
fe00f943 666 info.si_addr = (void __user *) regs->cp0_epc;
1da177e4
LT		 667 force_sig_info(SIGFPE, &info, current);
668 break;
669 default:
670 force_sig(SIGTRAP, current);
671 }
672}
673
674asmlinkage void do_tr(struct pt_regs *regs)
675{
676 unsigned int opcode, tcode = 0;
677 siginfo_t info;
678
679 die_if_kernel("Trap instruction in kernel code", regs);
680
681 if (get_insn_opcode(regs, &opcode))
682 return;
683
684 /* Immediate versions don't provide a code. */
685 if (!(opcode & OPCODE))
686 tcode = ((opcode >> 6) & ((1 << 10) - 1));
687
688 /*
689 * (A short test says that IRIX 5.3 sends SIGTRAP for all trap
690 * insns, even for trap codes that indicate arithmetic failures.
691 * Weird ...)
692 * But should we continue the brokenness??? --macro
693 */
694 switch (tcode) {
695 case BRK_OVERFLOW:
696 case BRK_DIVZERO:
697 if (tcode == BRK_DIVZERO)
698 info.si_code = FPE_INTDIV;
699 else
700 info.si_code = FPE_INTOVF;
701 info.si_signo = SIGFPE;
702 info.si_errno = 0;
fe00f943 703 info.si_addr = (void __user *) regs->cp0_epc;
1da177e4
LT		 704 force_sig_info(SIGFPE, &info, current);
705 break;
706 default:
707 force_sig(SIGTRAP, current);
708 }
709}
710
711asmlinkage void do_ri(struct pt_regs *regs)
712{
713 die_if_kernel("Reserved instruction in kernel code", regs);
714
715 if (!cpu_has_llsc)
716 if (!simulate_llsc(regs))
717 return;
718
3c37026d
RB		 719 if (!simulate_rdhwr(regs))
720 return;
721
1da177e4
LT		 722 force_sig(SIGILL, current);
723}
724
725asmlinkage void do_cpu(struct pt_regs *regs)
726{
727 unsigned int cpid;
728
729 die_if_kernel("do_cpu invoked from kernel context!", regs);
730
731 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
732
733 switch (cpid) {
734 case 0:
3c37026d
RB		 735 if (!cpu_has_llsc)
736 if (!simulate_llsc(regs))
737 return;
1da177e4 738
3c37026d 739 if (!simulate_rdhwr(regs))
1da177e4 740 return;
3c37026d 741
1da177e4
LT		 742 break;
743
744 case 1:
745 preempt_disable();
746
747 own_fpu();
748 if (used_math()) { /* Using the FPU again. */
749 restore_fp(current);
750 } else { /* First time FPU user. */
751 init_fpu();
752 set_used_math();
753 }
754
cd21dfcf
RB		 755 preempt_enable();
756
1da177e4
LT		 757 if (!cpu_has_fpu) {
758 int sig = fpu_emulator_cop1Handler(0, regs,
759 &current->thread.fpu.soft);
760 if (sig)
761 force_sig(sig, current);
762 }
763
1da177e4
LT		 764 return;
765
766 case 2:
767 case 3:
768 break;
769 }
770
771 force_sig(SIGILL, current);
772}
773
774asmlinkage void do_mdmx(struct pt_regs *regs)
775{
776 force_sig(SIGILL, current);
777}
778
779asmlinkage void do_watch(struct pt_regs *regs)
780{
781 /*
782 * We use the watch exception where available to detect stack
783 * overflows.
784 */
785 dump_tlb_all();
786 show_regs(regs);
787 panic("Caught WATCH exception - probably caused by stack overflow.");
788}
789
790asmlinkage void do_mcheck(struct pt_regs *regs)
791{
792 show_regs(regs);
793 dump_tlb_all();
794 /*
795 * Some chips may have other causes of machine check (e.g. SB1
796 * graduation timer)
797 */
798 panic("Caught Machine Check exception - %scaused by multiple "
799 "matching entries in the TLB.",
800 (regs->cp0_status & ST0_TS) ? "" : "not ");
801}
802
340ee4b9
RB		 803asmlinkage void do_mt(struct pt_regs *regs)
804{
805 die_if_kernel("MIPS MT Thread exception in kernel", regs);
806
807 force_sig(SIGILL, current);
808}
809
810
e50c0a8f
RB		 811asmlinkage void do_dsp(struct pt_regs *regs)
812{
813 if (cpu_has_dsp)
814 panic("Unexpected DSP exception\n");
815
816 force_sig(SIGILL, current);
817}
818
1da177e4
LT		 819asmlinkage void do_reserved(struct pt_regs *regs)
820{
821 /*
822 * Game over - no way to handle this if it ever occurs. Most probably
823 * caused by a new unknown cpu type or after another deadly
824 * hard/software error.
825 */
826 show_regs(regs);
827 panic("Caught reserved exception %ld - should not happen.",
828 (regs->cp0_cause & 0x7f) >> 2);
829}
830
e01402b1
RB		 831asmlinkage void do_default_vi(struct pt_regs *regs)
832{
833 show_regs(regs);
834 panic("Caught unexpected vectored interrupt.");
835}
836
1da177e4
LT		 837/*
838 * Some MIPS CPUs can enable/disable for cache parity detection, but do
839 * it different ways.
840 */
841static inline void parity_protection_init(void)
842{
843 switch (current_cpu_data.cputype) {
844 case CPU_24K:
1da177e4 845 case CPU_5KC:
14f18b7f
RB		 846 write_c0_ecc(0x80000000);
847 back_to_back_c0_hazard();
848 /* Set the PE bit (bit 31) in the c0_errctl register. */
849 printk(KERN_INFO "Cache parity protection %sabled\n",
850 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
1da177e4
LT		 851 break;
852 case CPU_20KC:
853 case CPU_25KF:
854 /* Clear the DE bit (bit 16) in the c0_status register. */
855 printk(KERN_INFO "Enable cache parity protection for "
856 "MIPS 20KC/25KF CPUs.\n");
857 clear_c0_status(ST0_DE);
858 break;
859 default:
860 break;
861 }
862}
863
864asmlinkage void cache_parity_error(void)
865{
866 const int field = 2 * sizeof(unsigned long);
867 unsigned int reg_val;
868
869 /* For the moment, report the problem and hang. */
870 printk("Cache error exception:\n");
871 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
872 reg_val = read_c0_cacheerr();
873 printk("c0_cacheerr == %08x\n", reg_val);
874
875 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
876 reg_val & (1<<30) ? "secondary" : "primary",
877 reg_val & (1<<31) ? "data" : "insn");
878 printk("Error bits: %s%s%s%s%s%s%s\n",
879 reg_val & (1<<29) ? "ED " : "",
880 reg_val & (1<<28) ? "ET " : "",
881 reg_val & (1<<26) ? "EE " : "",
882 reg_val & (1<<25) ? "EB " : "",
883 reg_val & (1<<24) ? "EI " : "",
884 reg_val & (1<<23) ? "E1 " : "",
885 reg_val & (1<<22) ? "E0 " : "");
886 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
887
6e760c8d 888#if defined(CONFIG_CPU_MIPS32_R1) || defined(CONFIG_CPU_MIPS64_R1)
1da177e4
LT		 889 if (reg_val & (1<<22))
890 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
891
892 if (reg_val & (1<<23))
893 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
894#endif
895
896 panic("Can't handle the cache error!");
897}
898
899/*
900 * SDBBP EJTAG debug exception handler.
901 * We skip the instruction and return to the next instruction.
902 */
903void ejtag_exception_handler(struct pt_regs *regs)
904{
905 const int field = 2 * sizeof(unsigned long);
906 unsigned long depc, old_epc;
907 unsigned int debug;
908
909 printk("SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
910 depc = read_c0_depc();
911 debug = read_c0_debug();
912 printk("c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
913 if (debug & 0x80000000) {
914 /*
915 * In branch delay slot.
916 * We cheat a little bit here and use EPC to calculate the
917 * debug return address (DEPC). EPC is restored after the
918 * calculation.
919 */
920 old_epc = regs->cp0_epc;
921 regs->cp0_epc = depc;
922 __compute_return_epc(regs);
923 depc = regs->cp0_epc;
924 regs->cp0_epc = old_epc;
925 } else
926 depc += 4;
927 write_c0_depc(depc);
928
929#if 0
930 printk("\n\n----- Enable EJTAG single stepping ----\n\n");
931 write_c0_debug(debug | 0x100);
932#endif
933}
934
935/*
936 * NMI exception handler.
937 */
938void nmi_exception_handler(struct pt_regs *regs)
939{
940 printk("NMI taken!!!!\n");
941 die("NMI", regs);
942 while(1) ;
943}
944
e01402b1
RB		 945#define VECTORSPACING 0x100 /* for EI/VI mode */
946
947unsigned long ebase;
1da177e4 948unsigned long exception_handlers[32];
e01402b1 949unsigned long vi_handlers[64];
1da177e4
LT		 950
951/*
952 * As a side effect of the way this is implemented we're limited
953 * to interrupt handlers in the address range from
954 * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ...
955 */
956void *set_except_vector(int n, void *addr)
957{
958 unsigned long handler = (unsigned long) addr;
959 unsigned long old_handler = exception_handlers[n];
960
961 exception_handlers[n] = handler;
962 if (n == 0 && cpu_has_divec) {
e01402b1 963 *(volatile u32 *)(ebase + 0x200) = 0x08000000 |
1da177e4 964 (0x03ffffff & (handler >> 2));
e01402b1
RB		 965 flush_icache_range(ebase + 0x200, ebase + 0x204);
966 }
967 return (void *)old_handler;
968}
969
970#ifdef CONFIG_CPU_MIPSR2
971/*
972 * Shadow register allocation
973 * FIXME: SMP...
974 */
975
976/* MIPSR2 shadow register sets */
977struct shadow_registers {
978 spinlock_t sr_lock; /* */
979 int sr_supported; /* Number of shadow register sets supported */
980 int sr_allocated; /* Bitmap of allocated shadow registers */
981} shadow_registers;
982
983void mips_srs_init(void)
984{
985#ifdef CONFIG_CPU_MIPSR2_SRS
986 shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
987 printk ("%d MIPSR2 register sets available\n", shadow_registers.sr_supported);
988#else
989 shadow_registers.sr_supported = 1;
990#endif
991 shadow_registers.sr_allocated = 1; /* Set 0 used by kernel */
992 spin_lock_init(&shadow_registers.sr_lock);
993}
994
995int mips_srs_max(void)
996{
997 return shadow_registers.sr_supported;
998}
999
1000int mips_srs_alloc (void)
1001{
1002 struct shadow_registers *sr = &shadow_registers;
1003 unsigned long flags;
1004 int set;
1005
1006 spin_lock_irqsave(&sr->sr_lock, flags);
1007
1008 for (set = 0; set < sr->sr_supported; set++) {
1009 if ((sr->sr_allocated & (1 << set)) == 0) {
1010 sr->sr_allocated |= 1 << set;
1011 spin_unlock_irqrestore(&sr->sr_lock, flags);
1012 return set;
1013 }
1014 }
1015
1016 /* None available */
1017 spin_unlock_irqrestore(&sr->sr_lock, flags);
1018 return -1;
1019}
1020
1021void mips_srs_free (int set)
1022{
1023 struct shadow_registers *sr = &shadow_registers;
1024 unsigned long flags;
1025
1026 spin_lock_irqsave(&sr->sr_lock, flags);
1027 sr->sr_allocated &= ~(1 << set);
1028 spin_unlock_irqrestore(&sr->sr_lock, flags);
1029}
1030
1031void *set_vi_srs_handler (int n, void *addr, int srs)
1032{
1033 unsigned long handler;
1034 unsigned long old_handler = vi_handlers[n];
1035 u32 *w;
1036 unsigned char *b;
1037
1038 if (!cpu_has_veic && !cpu_has_vint)
1039 BUG();
1040
1041 if (addr == NULL) {
1042 handler = (unsigned long) do_default_vi;
1043 srs = 0;
1044 }
1045 else
1046 handler = (unsigned long) addr;
1047 vi_handlers[n] = (unsigned long) addr;
1048
1049 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1050
1051 if (srs >= mips_srs_max())
1052 panic("Shadow register set %d not supported", srs);
1053
1054 if (cpu_has_veic) {
1055 if (board_bind_eic_interrupt)
1056 board_bind_eic_interrupt (n, srs);
1057 }
1058 else if (cpu_has_vint) {
1059 /* SRSMap is only defined if shadow sets are implemented */
1060 if (mips_srs_max() > 1)
1061 change_c0_srsmap (0xf << n*4, srs << n*4);
1062 }
1063
1064 if (srs == 0) {
1065 /*
1066 * If no shadow set is selected then use the default handler
1067 * that does normal register saving and a standard interrupt exit
1068 */
1069
1070 extern char except_vec_vi, except_vec_vi_lui;
1071 extern char except_vec_vi_ori, except_vec_vi_end;
1072 const int handler_len = &except_vec_vi_end - &except_vec_vi;
1073 const int lui_offset = &except_vec_vi_lui - &except_vec_vi;
1074 const int ori_offset = &except_vec_vi_ori - &except_vec_vi;
1075
1076 if (handler_len > VECTORSPACING) {
1077 /*
1078 * Sigh... panicing won't help as the console
1079 * is probably not configured :(
1080 */
1081 panic ("VECTORSPACING too small");
1082 }
1083
1084 memcpy (b, &except_vec_vi, handler_len);
1085 w = (u32 *)(b + lui_offset);
1086 *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff);
1087 w = (u32 *)(b + ori_offset);
1088 *w = (*w & 0xffff0000) | ((u32)handler & 0xffff);
1089 flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len));
1090 }
1091 else {
1092 /*
1093 * In other cases jump directly to the interrupt handler
1094 *
1095 * It is the handlers responsibility to save registers if required
1096 * (eg hi/lo) and return from the exception using "eret"
1097 */
1098 w = (u32 *)b;
1099 *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */
1100 *w = 0;
1101 flush_icache_range((unsigned long)b, (unsigned long)(b+8));
1da177e4 1102 }
e01402b1 1103
1da177e4
LT		 1104 return (void *)old_handler;
1105}
1106
e01402b1
RB		 1107void *set_vi_handler (int n, void *addr)
1108{
1109 return set_vi_srs_handler (n, addr, 0);
1110}
1111#endif
1112
1da177e4
LT		 1113/*
1114 * This is used by native signal handling
1115 */
1116asmlinkage int (*save_fp_context)(struct sigcontext *sc);
1117asmlinkage int (*restore_fp_context)(struct sigcontext *sc);
1118
1119extern asmlinkage int _save_fp_context(struct sigcontext *sc);
1120extern asmlinkage int _restore_fp_context(struct sigcontext *sc);
1121
1122extern asmlinkage int fpu_emulator_save_context(struct sigcontext *sc);
1123extern asmlinkage int fpu_emulator_restore_context(struct sigcontext *sc);
1124
1125static inline void signal_init(void)
1126{
1127 if (cpu_has_fpu) {
1128 save_fp_context = _save_fp_context;
1129 restore_fp_context = _restore_fp_context;
1130 } else {
1131 save_fp_context = fpu_emulator_save_context;
1132 restore_fp_context = fpu_emulator_restore_context;
1133 }
1134}
1135
1136#ifdef CONFIG_MIPS32_COMPAT
1137
1138/*
1139 * This is used by 32-bit signal stuff on the 64-bit kernel
1140 */
1141asmlinkage int (*save_fp_context32)(struct sigcontext32 *sc);
1142asmlinkage int (*restore_fp_context32)(struct sigcontext32 *sc);
1143
1144extern asmlinkage int _save_fp_context32(struct sigcontext32 *sc);
1145extern asmlinkage int _restore_fp_context32(struct sigcontext32 *sc);
1146
1147extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 *sc);
1148extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 *sc);
1149
1150static inline void signal32_init(void)
1151{
1152 if (cpu_has_fpu) {
1153 save_fp_context32 = _save_fp_context32;
1154 restore_fp_context32 = _restore_fp_context32;
1155 } else {
1156 save_fp_context32 = fpu_emulator_save_context32;
1157 restore_fp_context32 = fpu_emulator_restore_context32;
1158 }
1159}
1160#endif
1161
1162extern void cpu_cache_init(void);
1163extern void tlb_init(void);
1d40cfcd 1164extern void flush_tlb_handlers(void);
1da177e4
LT		 1165
1166void __init per_cpu_trap_init(void)
1167{
1168 unsigned int cpu = smp_processor_id();
1169 unsigned int status_set = ST0_CU0;
1170
1171 /*
1172 * Disable coprocessors and select 32-bit or 64-bit addressing
1173 * and the 16/32 or 32/32 FPR register model. Reset the BEV
1174 * flag that some firmware may have left set and the TS bit (for
1175 * IP27). Set XX for ISA IV code to work.
1176 */
875d43e7 1177#ifdef CONFIG_64BIT
1da177e4
LT		 1178 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
1179#endif
1180 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
1181 status_set |= ST0_XX;
e50c0a8f 1182 change_c0_status(ST0_CU|ST0_MX|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
1da177e4
LT		 1183 status_set);
1184
e50c0a8f
RB		 1185 if (cpu_has_dsp)
1186 set_c0_status(ST0_MX);
1187
e01402b1
RB		 1188#ifdef CONFIG_CPU_MIPSR2
1189 write_c0_hwrena (0x0000000f); /* Allow rdhwr to all registers */
1190#endif
1191
1da177e4 1192 /*
e01402b1 1193 * Interrupt handling.
1da177e4 1194 */
e01402b1
RB		 1195 if (cpu_has_veic || cpu_has_vint) {
1196 write_c0_ebase (ebase);
1197 /* Setting vector spacing enables EI/VI mode */
1198 change_c0_intctl (0x3e0, VECTORSPACING);
1199 }
d03d0a57
RB		 1200 if (cpu_has_divec) {
1201 if (cpu_has_mipsmt) {
1202 unsigned int vpflags = dvpe();
1203 set_c0_cause(CAUSEF_IV);
1204 evpe(vpflags);
1205 } else
1206 set_c0_cause(CAUSEF_IV);
1207 }
1da177e4
LT		 1208
1209 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
1210 TLBMISS_HANDLER_SETUP();
1211
1212 atomic_inc(&init_mm.mm_count);
1213 current->active_mm = &init_mm;
1214 BUG_ON(current->mm);
1215 enter_lazy_tlb(&init_mm, current);
1216
1217 cpu_cache_init();
1218 tlb_init();
1219}
1220
e01402b1
RB		 1221/* Install CPU exception handler */
1222void __init set_handler (unsigned long offset, void *addr, unsigned long size)
1223{
1224 memcpy((void *)(ebase + offset), addr, size);
1225 flush_icache_range(ebase + offset, ebase + offset + size);
1226}
1227
1228/* Install uncached CPU exception handler */
1229void __init set_uncached_handler (unsigned long offset, void *addr, unsigned long size)
1230{
1231#ifdef CONFIG_32BIT
1232 unsigned long uncached_ebase = KSEG1ADDR(ebase);
1233#endif
1234#ifdef CONFIG_64BIT
1235 unsigned long uncached_ebase = TO_UNCAC(ebase);
1236#endif
1237
1238 memcpy((void *)(uncached_ebase + offset), addr, size);
1239}
1240
1da177e4
LT		 1241void __init trap_init(void)
1242{
1243 extern char except_vec3_generic, except_vec3_r4000;
1da177e4
LT		 1244 extern char except_vec4;
1245 unsigned long i;
1246
e01402b1
RB		 1247 if (cpu_has_veic || cpu_has_vint)
1248 ebase = (unsigned long) alloc_bootmem_low_pages (0x200 + VECTORSPACING*64);
1249 else
1250 ebase = CAC_BASE;
1251
1252#ifdef CONFIG_CPU_MIPSR2
1253 mips_srs_init();
1254#endif
1255
1da177e4
LT		 1256 per_cpu_trap_init();
1257
1258 /*
1259 * Copy the generic exception handlers to their final destination.
1260 * This will be overriden later as suitable for a particular
1261 * configuration.
1262 */
e01402b1 1263 set_handler(0x180, &except_vec3_generic, 0x80);
1da177e4
LT		 1264
1265 /*
1266 * Setup default vectors
1267 */
1268 for (i = 0; i <= 31; i++)
1269 set_except_vector(i, handle_reserved);
1270
1271 /*
1272 * Copy the EJTAG debug exception vector handler code to it's final
1273 * destination.
1274 */
e01402b1
RB		 1275 if (cpu_has_ejtag && board_ejtag_handler_setup)
1276 board_ejtag_handler_setup ();
1da177e4
LT		 1277
1278 /*
1279 * Only some CPUs have the watch exceptions.
1280 */
1281 if (cpu_has_watch)
1282 set_except_vector(23, handle_watch);
1283
1284 /*
e01402b1 1285 * Initialise interrupt handlers
1da177e4 1286 */
e01402b1
RB		 1287 if (cpu_has_veic || cpu_has_vint) {
1288 int nvec = cpu_has_veic ? 64 : 8;
1289 for (i = 0; i < nvec; i++)
1290 set_vi_handler (i, NULL);
1291 }
1292 else if (cpu_has_divec)
1293 set_handler(0x200, &except_vec4, 0x8);
1da177e4
LT		 1294
1295 /*
1296 * Some CPUs can enable/disable for cache parity detection, but does
1297 * it different ways.
1298 */
1299 parity_protection_init();
1300
1301 /*
1302 * The Data Bus Errors / Instruction Bus Errors are signaled
1303 * by external hardware. Therefore these two exceptions
1304 * may have board specific handlers.
1305 */
1306 if (board_be_init)
1307 board_be_init();
1308
1309 set_except_vector(1, handle_tlbm);
1310 set_except_vector(2, handle_tlbl);
1311 set_except_vector(3, handle_tlbs);
1312
1313 set_except_vector(4, handle_adel);
1314 set_except_vector(5, handle_ades);
1315
1316 set_except_vector(6, handle_ibe);
1317 set_except_vector(7, handle_dbe);
1318
1319 set_except_vector(8, handle_sys);
1320 set_except_vector(9, handle_bp);
1321 set_except_vector(10, handle_ri);
1322 set_except_vector(11, handle_cpu);
1323 set_except_vector(12, handle_ov);
1324 set_except_vector(13, handle_tr);
1da177e4
LT		 1325
1326 if (current_cpu_data.cputype == CPU_R6000 ||
1327 current_cpu_data.cputype == CPU_R6000A) {
1328 /*
1329 * The R6000 is the only R-series CPU that features a machine
1330 * check exception (similar to the R4000 cache error) and
1331 * unaligned ldc1/sdc1 exception. The handlers have not been
1332 * written yet. Well, anyway there is no R6000 machine on the
1333 * current list of targets for Linux/MIPS.
1334 * (Duh, crap, there is someone with a triple R6k machine)
1335 */
1336 //set_except_vector(14, handle_mc);
1337 //set_except_vector(15, handle_ndc);
1338 }
1339
e01402b1
RB		 1340
1341 if (board_nmi_handler_setup)
1342 board_nmi_handler_setup();
1343
e50c0a8f
RB		 1344 if (cpu_has_fpu && !cpu_has_nofpuex)
1345 set_except_vector(15, handle_fpe);
1346
1347 set_except_vector(22, handle_mdmx);
1348
1349 if (cpu_has_mcheck)
1350 set_except_vector(24, handle_mcheck);
1351
340ee4b9
RB		 1352 if (cpu_has_mipsmt)
1353 set_except_vector(25, handle_mt);
1354
e50c0a8f
RB		 1355 if (cpu_has_dsp)
1356 set_except_vector(26, handle_dsp);
1357
1358 if (cpu_has_vce)
1359 /* Special exception: R4[04]00 uses also the divec space. */
1360 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100);
1361 else if (cpu_has_4kex)
1362 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80);
1363 else
1364 memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80);
1365
1da177e4
LT		 1366 signal_init();
1367#ifdef CONFIG_MIPS32_COMPAT
1368 signal32_init();
1369#endif
1370
e01402b1 1371 flush_icache_range(ebase, ebase + 0x400);
1d40cfcd 1372 flush_tlb_handlers();
1da177e4 1373}
Linux 6.x block layer and io_uring tree(s)