Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 1994 - 1999, 2000, 01 Ralf Baechle | |
7 | * Copyright (C) 1995, 1996 Paul M. Antoine | |
8 | * Copyright (C) 1998 Ulf Carlsson | |
9 | * Copyright (C) 1999 Silicon Graphics, Inc. | |
10 | * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com | |
11 | * Copyright (C) 2000, 01 MIPS Technologies, Inc. | |
3b2396d9 | 12 | * Copyright (C) 2002, 2003, 2004, 2005 Maciej W. Rozycki |
1da177e4 LT |
13 | */ |
14 | #include <linux/config.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/mm.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/sched.h> | |
19 | #include <linux/smp.h> | |
20 | #include <linux/smp_lock.h> | |
21 | #include <linux/spinlock.h> | |
22 | #include <linux/kallsyms.h> | |
e01402b1 | 23 | #include <linux/bootmem.h> |
1da177e4 LT |
24 | |
25 | #include <asm/bootinfo.h> | |
26 | #include <asm/branch.h> | |
27 | #include <asm/break.h> | |
28 | #include <asm/cpu.h> | |
e50c0a8f | 29 | #include <asm/dsp.h> |
1da177e4 | 30 | #include <asm/fpu.h> |
340ee4b9 RB |
31 | #include <asm/mipsregs.h> |
32 | #include <asm/mipsmtregs.h> | |
1da177e4 LT |
33 | #include <asm/module.h> |
34 | #include <asm/pgtable.h> | |
35 | #include <asm/ptrace.h> | |
36 | #include <asm/sections.h> | |
37 | #include <asm/system.h> | |
38 | #include <asm/tlbdebug.h> | |
39 | #include <asm/traps.h> | |
40 | #include <asm/uaccess.h> | |
41 | #include <asm/mmu_context.h> | |
42 | #include <asm/watch.h> | |
43 | #include <asm/types.h> | |
44 | ||
45 | extern asmlinkage void handle_tlbm(void); | |
46 | extern asmlinkage void handle_tlbl(void); | |
47 | extern asmlinkage void handle_tlbs(void); | |
48 | extern asmlinkage void handle_adel(void); | |
49 | extern asmlinkage void handle_ades(void); | |
50 | extern asmlinkage void handle_ibe(void); | |
51 | extern asmlinkage void handle_dbe(void); | |
52 | extern asmlinkage void handle_sys(void); | |
53 | extern asmlinkage void handle_bp(void); | |
54 | extern asmlinkage void handle_ri(void); | |
55 | extern asmlinkage void handle_cpu(void); | |
56 | extern asmlinkage void handle_ov(void); | |
57 | extern asmlinkage void handle_tr(void); | |
58 | extern asmlinkage void handle_fpe(void); | |
59 | extern asmlinkage void handle_mdmx(void); | |
60 | extern asmlinkage void handle_watch(void); | |
340ee4b9 | 61 | extern asmlinkage void handle_mt(void); |
e50c0a8f | 62 | extern asmlinkage void handle_dsp(void); |
1da177e4 LT |
63 | extern asmlinkage void handle_mcheck(void); |
64 | extern asmlinkage void handle_reserved(void); | |
65 | ||
12616ed2 | 66 | extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, |
1da177e4 LT |
67 | struct mips_fpu_soft_struct *ctx); |
68 | ||
69 | void (*board_be_init)(void); | |
70 | int (*board_be_handler)(struct pt_regs *regs, int is_fixup); | |
e01402b1 RB |
71 | void (*board_nmi_handler_setup)(void); |
72 | void (*board_ejtag_handler_setup)(void); | |
73 | void (*board_bind_eic_interrupt)(int irq, int regset); | |
1da177e4 LT |
74 | |
75 | /* | |
76 | * These constant is for searching for possible module text segments. | |
77 | * MODULE_RANGE is a guess of how much space is likely to be vmalloced. | |
78 | */ | |
79 | #define MODULE_RANGE (8*1024*1024) | |
80 | ||
81 | /* | |
82 | * This routine abuses get_user()/put_user() to reference pointers | |
83 | * with at least a bit of error checking ... | |
84 | */ | |
85 | void show_stack(struct task_struct *task, unsigned long *sp) | |
86 | { | |
87 | const int field = 2 * sizeof(unsigned long); | |
88 | long stackdata; | |
89 | int i; | |
90 | ||
91 | if (!sp) { | |
92 | if (task && task != current) | |
93 | sp = (unsigned long *) task->thread.reg29; | |
94 | else | |
95 | sp = (unsigned long *) &sp; | |
96 | } | |
97 | ||
98 | printk("Stack :"); | |
99 | i = 0; | |
100 | while ((unsigned long) sp & (PAGE_SIZE - 1)) { | |
101 | if (i && ((i % (64 / field)) == 0)) | |
102 | printk("\n "); | |
103 | if (i > 39) { | |
104 | printk(" ..."); | |
105 | break; | |
106 | } | |
107 | ||
108 | if (__get_user(stackdata, sp++)) { | |
109 | printk(" (Bad stack address)"); | |
110 | break; | |
111 | } | |
112 | ||
113 | printk(" %0*lx", field, stackdata); | |
114 | i++; | |
115 | } | |
116 | printk("\n"); | |
117 | } | |
118 | ||
119 | void show_trace(struct task_struct *task, unsigned long *stack) | |
120 | { | |
121 | const int field = 2 * sizeof(unsigned long); | |
122 | unsigned long addr; | |
123 | ||
124 | if (!stack) { | |
125 | if (task && task != current) | |
126 | stack = (unsigned long *) task->thread.reg29; | |
127 | else | |
128 | stack = (unsigned long *) &stack; | |
129 | } | |
130 | ||
131 | printk("Call Trace:"); | |
132 | #ifdef CONFIG_KALLSYMS | |
133 | printk("\n"); | |
134 | #endif | |
135 | while (!kstack_end(stack)) { | |
136 | addr = *stack++; | |
137 | if (__kernel_text_address(addr)) { | |
138 | printk(" [<%0*lx>] ", field, addr); | |
139 | print_symbol("%s\n", addr); | |
140 | } | |
141 | } | |
142 | printk("\n"); | |
143 | } | |
144 | ||
145 | /* | |
146 | * The architecture-independent dump_stack generator | |
147 | */ | |
148 | void dump_stack(void) | |
149 | { | |
150 | unsigned long stack; | |
151 | ||
152 | show_trace(current, &stack); | |
153 | } | |
154 | ||
155 | EXPORT_SYMBOL(dump_stack); | |
156 | ||
157 | void show_code(unsigned int *pc) | |
158 | { | |
159 | long i; | |
160 | ||
161 | printk("\nCode:"); | |
162 | ||
163 | for(i = -3 ; i < 6 ; i++) { | |
164 | unsigned int insn; | |
165 | if (__get_user(insn, pc + i)) { | |
166 | printk(" (Bad address in epc)\n"); | |
167 | break; | |
168 | } | |
169 | printk("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>')); | |
170 | } | |
171 | } | |
172 | ||
173 | void show_regs(struct pt_regs *regs) | |
174 | { | |
175 | const int field = 2 * sizeof(unsigned long); | |
176 | unsigned int cause = regs->cp0_cause; | |
177 | int i; | |
178 | ||
179 | printk("Cpu %d\n", smp_processor_id()); | |
180 | ||
181 | /* | |
182 | * Saved main processor registers | |
183 | */ | |
184 | for (i = 0; i < 32; ) { | |
185 | if ((i % 4) == 0) | |
186 | printk("$%2d :", i); | |
187 | if (i == 0) | |
188 | printk(" %0*lx", field, 0UL); | |
189 | else if (i == 26 || i == 27) | |
190 | printk(" %*s", field, ""); | |
191 | else | |
192 | printk(" %0*lx", field, regs->regs[i]); | |
193 | ||
194 | i++; | |
195 | if ((i % 4) == 0) | |
196 | printk("\n"); | |
197 | } | |
198 | ||
199 | printk("Hi : %0*lx\n", field, regs->hi); | |
200 | printk("Lo : %0*lx\n", field, regs->lo); | |
201 | ||
202 | /* | |
203 | * Saved cp0 registers | |
204 | */ | |
205 | printk("epc : %0*lx ", field, regs->cp0_epc); | |
206 | print_symbol("%s ", regs->cp0_epc); | |
207 | printk(" %s\n", print_tainted()); | |
208 | printk("ra : %0*lx ", field, regs->regs[31]); | |
209 | print_symbol("%s\n", regs->regs[31]); | |
210 | ||
211 | printk("Status: %08x ", (uint32_t) regs->cp0_status); | |
212 | ||
3b2396d9 MR |
213 | if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) { |
214 | if (regs->cp0_status & ST0_KUO) | |
215 | printk("KUo "); | |
216 | if (regs->cp0_status & ST0_IEO) | |
217 | printk("IEo "); | |
218 | if (regs->cp0_status & ST0_KUP) | |
219 | printk("KUp "); | |
220 | if (regs->cp0_status & ST0_IEP) | |
221 | printk("IEp "); | |
222 | if (regs->cp0_status & ST0_KUC) | |
223 | printk("KUc "); | |
224 | if (regs->cp0_status & ST0_IEC) | |
225 | printk("IEc "); | |
226 | } else { | |
227 | if (regs->cp0_status & ST0_KX) | |
228 | printk("KX "); | |
229 | if (regs->cp0_status & ST0_SX) | |
230 | printk("SX "); | |
231 | if (regs->cp0_status & ST0_UX) | |
232 | printk("UX "); | |
233 | switch (regs->cp0_status & ST0_KSU) { | |
234 | case KSU_USER: | |
235 | printk("USER "); | |
236 | break; | |
237 | case KSU_SUPERVISOR: | |
238 | printk("SUPERVISOR "); | |
239 | break; | |
240 | case KSU_KERNEL: | |
241 | printk("KERNEL "); | |
242 | break; | |
243 | default: | |
244 | printk("BAD_MODE "); | |
245 | break; | |
246 | } | |
247 | if (regs->cp0_status & ST0_ERL) | |
248 | printk("ERL "); | |
249 | if (regs->cp0_status & ST0_EXL) | |
250 | printk("EXL "); | |
251 | if (regs->cp0_status & ST0_IE) | |
252 | printk("IE "); | |
1da177e4 | 253 | } |
1da177e4 LT |
254 | printk("\n"); |
255 | ||
256 | printk("Cause : %08x\n", cause); | |
257 | ||
258 | cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; | |
259 | if (1 <= cause && cause <= 5) | |
260 | printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr); | |
261 | ||
262 | printk("PrId : %08x\n", read_c0_prid()); | |
263 | } | |
264 | ||
265 | void show_registers(struct pt_regs *regs) | |
266 | { | |
267 | show_regs(regs); | |
268 | print_modules(); | |
269 | printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n", | |
270 | current->comm, current->pid, current_thread_info(), current); | |
271 | show_stack(current, (long *) regs->regs[29]); | |
272 | show_trace(current, (long *) regs->regs[29]); | |
273 | show_code((unsigned int *) regs->cp0_epc); | |
274 | printk("\n"); | |
275 | } | |
276 | ||
277 | static DEFINE_SPINLOCK(die_lock); | |
278 | ||
178086c8 | 279 | NORET_TYPE void ATTRIB_NORET die(const char * str, struct pt_regs * regs) |
1da177e4 LT |
280 | { |
281 | static int die_counter; | |
282 | ||
283 | console_verbose(); | |
284 | spin_lock_irq(&die_lock); | |
178086c8 | 285 | printk("%s[#%d]:\n", str, ++die_counter); |
1da177e4 LT |
286 | show_registers(regs); |
287 | spin_unlock_irq(&die_lock); | |
288 | do_exit(SIGSEGV); | |
289 | } | |
290 | ||
1da177e4 LT |
291 | extern const struct exception_table_entry __start___dbe_table[]; |
292 | extern const struct exception_table_entry __stop___dbe_table[]; | |
293 | ||
294 | void __declare_dbe_table(void) | |
295 | { | |
296 | __asm__ __volatile__( | |
297 | ".section\t__dbe_table,\"a\"\n\t" | |
298 | ".previous" | |
299 | ); | |
300 | } | |
301 | ||
302 | /* Given an address, look for it in the exception tables. */ | |
303 | static const struct exception_table_entry *search_dbe_tables(unsigned long addr) | |
304 | { | |
305 | const struct exception_table_entry *e; | |
306 | ||
307 | e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr); | |
308 | if (!e) | |
309 | e = search_module_dbetables(addr); | |
310 | return e; | |
311 | } | |
312 | ||
313 | asmlinkage void do_be(struct pt_regs *regs) | |
314 | { | |
315 | const int field = 2 * sizeof(unsigned long); | |
316 | const struct exception_table_entry *fixup = NULL; | |
317 | int data = regs->cp0_cause & 4; | |
318 | int action = MIPS_BE_FATAL; | |
319 | ||
320 | /* XXX For now. Fixme, this searches the wrong table ... */ | |
321 | if (data && !user_mode(regs)) | |
322 | fixup = search_dbe_tables(exception_epc(regs)); | |
323 | ||
324 | if (fixup) | |
325 | action = MIPS_BE_FIXUP; | |
326 | ||
327 | if (board_be_handler) | |
328 | action = board_be_handler(regs, fixup != 0); | |
329 | ||
330 | switch (action) { | |
331 | case MIPS_BE_DISCARD: | |
332 | return; | |
333 | case MIPS_BE_FIXUP: | |
334 | if (fixup) { | |
335 | regs->cp0_epc = fixup->nextinsn; | |
336 | return; | |
337 | } | |
338 | break; | |
339 | default: | |
340 | break; | |
341 | } | |
342 | ||
343 | /* | |
344 | * Assume it would be too dangerous to continue ... | |
345 | */ | |
346 | printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", | |
347 | data ? "Data" : "Instruction", | |
348 | field, regs->cp0_epc, field, regs->regs[31]); | |
349 | die_if_kernel("Oops", regs); | |
350 | force_sig(SIGBUS, current); | |
351 | } | |
352 | ||
353 | static inline int get_insn_opcode(struct pt_regs *regs, unsigned int *opcode) | |
354 | { | |
fe00f943 | 355 | unsigned int __user *epc; |
1da177e4 | 356 | |
fe00f943 | 357 | epc = (unsigned int __user *) regs->cp0_epc + |
1da177e4 LT |
358 | ((regs->cp0_cause & CAUSEF_BD) != 0); |
359 | if (!get_user(*opcode, epc)) | |
360 | return 0; | |
361 | ||
362 | force_sig(SIGSEGV, current); | |
363 | return 1; | |
364 | } | |
365 | ||
366 | /* | |
367 | * ll/sc emulation | |
368 | */ | |
369 | ||
370 | #define OPCODE 0xfc000000 | |
371 | #define BASE 0x03e00000 | |
372 | #define RT 0x001f0000 | |
373 | #define OFFSET 0x0000ffff | |
374 | #define LL 0xc0000000 | |
375 | #define SC 0xe0000000 | |
3c37026d RB |
376 | #define SPEC3 0x7c000000 |
377 | #define RD 0x0000f800 | |
378 | #define FUNC 0x0000003f | |
379 | #define RDHWR 0x0000003b | |
1da177e4 LT |
380 | |
381 | /* | |
382 | * The ll_bit is cleared by r*_switch.S | |
383 | */ | |
384 | ||
385 | unsigned long ll_bit; | |
386 | ||
387 | static struct task_struct *ll_task = NULL; | |
388 | ||
389 | static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode) | |
390 | { | |
fe00f943 | 391 | unsigned long value, __user *vaddr; |
1da177e4 LT |
392 | long offset; |
393 | int signal = 0; | |
394 | ||
395 | /* | |
396 | * analyse the ll instruction that just caused a ri exception | |
397 | * and put the referenced address to addr. | |
398 | */ | |
399 | ||
400 | /* sign extend offset */ | |
401 | offset = opcode & OFFSET; | |
402 | offset <<= 16; | |
403 | offset >>= 16; | |
404 | ||
fe00f943 RB |
405 | vaddr = (unsigned long __user *) |
406 | ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); | |
1da177e4 LT |
407 | |
408 | if ((unsigned long)vaddr & 3) { | |
409 | signal = SIGBUS; | |
410 | goto sig; | |
411 | } | |
412 | if (get_user(value, vaddr)) { | |
413 | signal = SIGSEGV; | |
414 | goto sig; | |
415 | } | |
416 | ||
417 | preempt_disable(); | |
418 | ||
419 | if (ll_task == NULL || ll_task == current) { | |
420 | ll_bit = 1; | |
421 | } else { | |
422 | ll_bit = 0; | |
423 | } | |
424 | ll_task = current; | |
425 | ||
426 | preempt_enable(); | |
427 | ||
6dd04688 RB |
428 | compute_return_epc(regs); |
429 | ||
1da177e4 LT |
430 | regs->regs[(opcode & RT) >> 16] = value; |
431 | ||
1da177e4 LT |
432 | return; |
433 | ||
434 | sig: | |
435 | force_sig(signal, current); | |
436 | } | |
437 | ||
438 | static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode) | |
439 | { | |
fe00f943 RB |
440 | unsigned long __user *vaddr; |
441 | unsigned long reg; | |
1da177e4 LT |
442 | long offset; |
443 | int signal = 0; | |
444 | ||
445 | /* | |
446 | * analyse the sc instruction that just caused a ri exception | |
447 | * and put the referenced address to addr. | |
448 | */ | |
449 | ||
450 | /* sign extend offset */ | |
451 | offset = opcode & OFFSET; | |
452 | offset <<= 16; | |
453 | offset >>= 16; | |
454 | ||
fe00f943 RB |
455 | vaddr = (unsigned long __user *) |
456 | ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); | |
1da177e4 LT |
457 | reg = (opcode & RT) >> 16; |
458 | ||
459 | if ((unsigned long)vaddr & 3) { | |
460 | signal = SIGBUS; | |
461 | goto sig; | |
462 | } | |
463 | ||
464 | preempt_disable(); | |
465 | ||
466 | if (ll_bit == 0 || ll_task != current) { | |
05b8042a | 467 | compute_return_epc(regs); |
1da177e4 LT |
468 | regs->regs[reg] = 0; |
469 | preempt_enable(); | |
1da177e4 LT |
470 | return; |
471 | } | |
472 | ||
473 | preempt_enable(); | |
474 | ||
475 | if (put_user(regs->regs[reg], vaddr)) { | |
476 | signal = SIGSEGV; | |
477 | goto sig; | |
478 | } | |
479 | ||
6dd04688 | 480 | compute_return_epc(regs); |
1da177e4 LT |
481 | regs->regs[reg] = 1; |
482 | ||
1da177e4 LT |
483 | return; |
484 | ||
485 | sig: | |
486 | force_sig(signal, current); | |
487 | } | |
488 | ||
489 | /* | |
490 | * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both | |
491 | * opcodes are supposed to result in coprocessor unusable exceptions if | |
492 | * executed on ll/sc-less processors. That's the theory. In practice a | |
493 | * few processors such as NEC's VR4100 throw reserved instruction exceptions | |
494 | * instead, so we're doing the emulation thing in both exception handlers. | |
495 | */ | |
496 | static inline int simulate_llsc(struct pt_regs *regs) | |
497 | { | |
498 | unsigned int opcode; | |
499 | ||
500 | if (unlikely(get_insn_opcode(regs, &opcode))) | |
501 | return -EFAULT; | |
502 | ||
503 | if ((opcode & OPCODE) == LL) { | |
504 | simulate_ll(regs, opcode); | |
505 | return 0; | |
506 | } | |
507 | if ((opcode & OPCODE) == SC) { | |
508 | simulate_sc(regs, opcode); | |
509 | return 0; | |
510 | } | |
511 | ||
512 | return -EFAULT; /* Strange things going on ... */ | |
513 | } | |
514 | ||
3c37026d RB |
515 | /* |
516 | * Simulate trapping 'rdhwr' instructions to provide user accessible | |
517 | * registers not implemented in hardware. The only current use of this | |
518 | * is the thread area pointer. | |
519 | */ | |
520 | static inline int simulate_rdhwr(struct pt_regs *regs) | |
521 | { | |
dc8f6029 | 522 | struct thread_info *ti = task_thread_info(current); |
3c37026d RB |
523 | unsigned int opcode; |
524 | ||
525 | if (unlikely(get_insn_opcode(regs, &opcode))) | |
526 | return -EFAULT; | |
527 | ||
528 | if (unlikely(compute_return_epc(regs))) | |
529 | return -EFAULT; | |
530 | ||
531 | if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { | |
532 | int rd = (opcode & RD) >> 11; | |
533 | int rt = (opcode & RT) >> 16; | |
534 | switch (rd) { | |
535 | case 29: | |
536 | regs->regs[rt] = ti->tp_value; | |
56ebd51b | 537 | return 0; |
3c37026d RB |
538 | default: |
539 | return -EFAULT; | |
540 | } | |
541 | } | |
542 | ||
56ebd51b DJ |
543 | /* Not ours. */ |
544 | return -EFAULT; | |
3c37026d RB |
545 | } |
546 | ||
1da177e4 LT |
547 | asmlinkage void do_ov(struct pt_regs *regs) |
548 | { | |
549 | siginfo_t info; | |
550 | ||
551 | info.si_code = FPE_INTOVF; | |
552 | info.si_signo = SIGFPE; | |
553 | info.si_errno = 0; | |
fe00f943 | 554 | info.si_addr = (void __user *) regs->cp0_epc; |
1da177e4 LT |
555 | force_sig_info(SIGFPE, &info, current); |
556 | } | |
557 | ||
558 | /* | |
559 | * XXX Delayed fp exceptions when doing a lazy ctx switch XXX | |
560 | */ | |
561 | asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) | |
562 | { | |
563 | if (fcr31 & FPU_CSR_UNI_X) { | |
564 | int sig; | |
565 | ||
566 | preempt_disable(); | |
567 | ||
cd21dfcf RB |
568 | #ifdef CONFIG_PREEMPT |
569 | if (!is_fpu_owner()) { | |
570 | /* We might lose fpu before disabling preempt... */ | |
571 | own_fpu(); | |
572 | BUG_ON(!used_math()); | |
573 | restore_fp(current); | |
574 | } | |
575 | #endif | |
1da177e4 LT |
576 | /* |
577 | * Unimplemented operation exception. If we've got the full | |
578 | * software emulator on-board, let's use it... | |
579 | * | |
580 | * Force FPU to dump state into task/thread context. We're | |
581 | * moving a lot of data here for what is probably a single | |
582 | * instruction, but the alternative is to pre-decode the FP | |
583 | * register operands before invoking the emulator, which seems | |
584 | * a bit extreme for what should be an infrequent event. | |
585 | */ | |
586 | save_fp(current); | |
cd21dfcf RB |
587 | /* Ensure 'resume' not overwrite saved fp context again. */ |
588 | lose_fpu(); | |
589 | ||
590 | preempt_enable(); | |
1da177e4 LT |
591 | |
592 | /* Run the emulator */ | |
12616ed2 | 593 | sig = fpu_emulator_cop1Handler (regs, |
1da177e4 LT |
594 | ¤t->thread.fpu.soft); |
595 | ||
cd21dfcf RB |
596 | preempt_disable(); |
597 | ||
598 | own_fpu(); /* Using the FPU again. */ | |
1da177e4 LT |
599 | /* |
600 | * We can't allow the emulated instruction to leave any of | |
601 | * the cause bit set in $fcr31. | |
602 | */ | |
603 | current->thread.fpu.soft.fcr31 &= ~FPU_CSR_ALL_X; | |
604 | ||
605 | /* Restore the hardware register state */ | |
606 | restore_fp(current); | |
607 | ||
608 | preempt_enable(); | |
609 | ||
610 | /* If something went wrong, signal */ | |
611 | if (sig) | |
612 | force_sig(sig, current); | |
613 | ||
614 | return; | |
615 | } | |
616 | ||
617 | force_sig(SIGFPE, current); | |
618 | } | |
619 | ||
620 | asmlinkage void do_bp(struct pt_regs *regs) | |
621 | { | |
622 | unsigned int opcode, bcode; | |
623 | siginfo_t info; | |
624 | ||
625 | die_if_kernel("Break instruction in kernel code", regs); | |
626 | ||
627 | if (get_insn_opcode(regs, &opcode)) | |
628 | return; | |
629 | ||
630 | /* | |
631 | * There is the ancient bug in the MIPS assemblers that the break | |
632 | * code starts left to bit 16 instead to bit 6 in the opcode. | |
633 | * Gas is bug-compatible, but not always, grrr... | |
634 | * We handle both cases with a simple heuristics. --macro | |
635 | */ | |
636 | bcode = ((opcode >> 6) & ((1 << 20) - 1)); | |
637 | if (bcode < (1 << 10)) | |
638 | bcode <<= 10; | |
639 | ||
640 | /* | |
641 | * (A short test says that IRIX 5.3 sends SIGTRAP for all break | |
642 | * insns, even for break codes that indicate arithmetic failures. | |
643 | * Weird ...) | |
644 | * But should we continue the brokenness??? --macro | |
645 | */ | |
646 | switch (bcode) { | |
647 | case BRK_OVERFLOW << 10: | |
648 | case BRK_DIVZERO << 10: | |
649 | if (bcode == (BRK_DIVZERO << 10)) | |
650 | info.si_code = FPE_INTDIV; | |
651 | else | |
652 | info.si_code = FPE_INTOVF; | |
653 | info.si_signo = SIGFPE; | |
654 | info.si_errno = 0; | |
fe00f943 | 655 | info.si_addr = (void __user *) regs->cp0_epc; |
1da177e4 LT |
656 | force_sig_info(SIGFPE, &info, current); |
657 | break; | |
658 | default: | |
659 | force_sig(SIGTRAP, current); | |
660 | } | |
661 | } | |
662 | ||
663 | asmlinkage void do_tr(struct pt_regs *regs) | |
664 | { | |
665 | unsigned int opcode, tcode = 0; | |
666 | siginfo_t info; | |
667 | ||
668 | die_if_kernel("Trap instruction in kernel code", regs); | |
669 | ||
670 | if (get_insn_opcode(regs, &opcode)) | |
671 | return; | |
672 | ||
673 | /* Immediate versions don't provide a code. */ | |
674 | if (!(opcode & OPCODE)) | |
675 | tcode = ((opcode >> 6) & ((1 << 10) - 1)); | |
676 | ||
677 | /* | |
678 | * (A short test says that IRIX 5.3 sends SIGTRAP for all trap | |
679 | * insns, even for trap codes that indicate arithmetic failures. | |
680 | * Weird ...) | |
681 | * But should we continue the brokenness??? --macro | |
682 | */ | |
683 | switch (tcode) { | |
684 | case BRK_OVERFLOW: | |
685 | case BRK_DIVZERO: | |
686 | if (tcode == BRK_DIVZERO) | |
687 | info.si_code = FPE_INTDIV; | |
688 | else | |
689 | info.si_code = FPE_INTOVF; | |
690 | info.si_signo = SIGFPE; | |
691 | info.si_errno = 0; | |
fe00f943 | 692 | info.si_addr = (void __user *) regs->cp0_epc; |
1da177e4 LT |
693 | force_sig_info(SIGFPE, &info, current); |
694 | break; | |
695 | default: | |
696 | force_sig(SIGTRAP, current); | |
697 | } | |
698 | } | |
699 | ||
700 | asmlinkage void do_ri(struct pt_regs *regs) | |
701 | { | |
702 | die_if_kernel("Reserved instruction in kernel code", regs); | |
703 | ||
704 | if (!cpu_has_llsc) | |
705 | if (!simulate_llsc(regs)) | |
706 | return; | |
707 | ||
3c37026d RB |
708 | if (!simulate_rdhwr(regs)) |
709 | return; | |
710 | ||
1da177e4 LT |
711 | force_sig(SIGILL, current); |
712 | } | |
713 | ||
714 | asmlinkage void do_cpu(struct pt_regs *regs) | |
715 | { | |
716 | unsigned int cpid; | |
717 | ||
718 | die_if_kernel("do_cpu invoked from kernel context!", regs); | |
719 | ||
720 | cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; | |
721 | ||
722 | switch (cpid) { | |
723 | case 0: | |
3c37026d RB |
724 | if (!cpu_has_llsc) |
725 | if (!simulate_llsc(regs)) | |
726 | return; | |
1da177e4 | 727 | |
3c37026d | 728 | if (!simulate_rdhwr(regs)) |
1da177e4 | 729 | return; |
3c37026d | 730 | |
1da177e4 LT |
731 | break; |
732 | ||
733 | case 1: | |
734 | preempt_disable(); | |
735 | ||
736 | own_fpu(); | |
737 | if (used_math()) { /* Using the FPU again. */ | |
738 | restore_fp(current); | |
739 | } else { /* First time FPU user. */ | |
740 | init_fpu(); | |
741 | set_used_math(); | |
742 | } | |
743 | ||
cd21dfcf RB |
744 | preempt_enable(); |
745 | ||
1da177e4 | 746 | if (!cpu_has_fpu) { |
12616ed2 | 747 | int sig = fpu_emulator_cop1Handler(regs, |
1da177e4 LT |
748 | ¤t->thread.fpu.soft); |
749 | if (sig) | |
750 | force_sig(sig, current); | |
751 | } | |
752 | ||
1da177e4 LT |
753 | return; |
754 | ||
755 | case 2: | |
756 | case 3: | |
757 | break; | |
758 | } | |
759 | ||
760 | force_sig(SIGILL, current); | |
761 | } | |
762 | ||
763 | asmlinkage void do_mdmx(struct pt_regs *regs) | |
764 | { | |
765 | force_sig(SIGILL, current); | |
766 | } | |
767 | ||
768 | asmlinkage void do_watch(struct pt_regs *regs) | |
769 | { | |
770 | /* | |
771 | * We use the watch exception where available to detect stack | |
772 | * overflows. | |
773 | */ | |
774 | dump_tlb_all(); | |
775 | show_regs(regs); | |
776 | panic("Caught WATCH exception - probably caused by stack overflow."); | |
777 | } | |
778 | ||
779 | asmlinkage void do_mcheck(struct pt_regs *regs) | |
780 | { | |
781 | show_regs(regs); | |
782 | dump_tlb_all(); | |
783 | /* | |
784 | * Some chips may have other causes of machine check (e.g. SB1 | |
785 | * graduation timer) | |
786 | */ | |
787 | panic("Caught Machine Check exception - %scaused by multiple " | |
788 | "matching entries in the TLB.", | |
789 | (regs->cp0_status & ST0_TS) ? "" : "not "); | |
790 | } | |
791 | ||
340ee4b9 RB |
792 | asmlinkage void do_mt(struct pt_regs *regs) |
793 | { | |
794 | die_if_kernel("MIPS MT Thread exception in kernel", regs); | |
795 | ||
796 | force_sig(SIGILL, current); | |
797 | } | |
798 | ||
799 | ||
e50c0a8f RB |
800 | asmlinkage void do_dsp(struct pt_regs *regs) |
801 | { | |
802 | if (cpu_has_dsp) | |
803 | panic("Unexpected DSP exception\n"); | |
804 | ||
805 | force_sig(SIGILL, current); | |
806 | } | |
807 | ||
1da177e4 LT |
808 | asmlinkage void do_reserved(struct pt_regs *regs) |
809 | { | |
810 | /* | |
811 | * Game over - no way to handle this if it ever occurs. Most probably | |
812 | * caused by a new unknown cpu type or after another deadly | |
813 | * hard/software error. | |
814 | */ | |
815 | show_regs(regs); | |
816 | panic("Caught reserved exception %ld - should not happen.", | |
817 | (regs->cp0_cause & 0x7f) >> 2); | |
818 | } | |
819 | ||
e01402b1 RB |
820 | asmlinkage void do_default_vi(struct pt_regs *regs) |
821 | { | |
822 | show_regs(regs); | |
823 | panic("Caught unexpected vectored interrupt."); | |
824 | } | |
825 | ||
1da177e4 LT |
826 | /* |
827 | * Some MIPS CPUs can enable/disable for cache parity detection, but do | |
828 | * it different ways. | |
829 | */ | |
830 | static inline void parity_protection_init(void) | |
831 | { | |
832 | switch (current_cpu_data.cputype) { | |
833 | case CPU_24K: | |
1da177e4 | 834 | case CPU_5KC: |
14f18b7f RB |
835 | write_c0_ecc(0x80000000); |
836 | back_to_back_c0_hazard(); | |
837 | /* Set the PE bit (bit 31) in the c0_errctl register. */ | |
838 | printk(KERN_INFO "Cache parity protection %sabled\n", | |
839 | (read_c0_ecc() & 0x80000000) ? "en" : "dis"); | |
1da177e4 LT |
840 | break; |
841 | case CPU_20KC: | |
842 | case CPU_25KF: | |
843 | /* Clear the DE bit (bit 16) in the c0_status register. */ | |
844 | printk(KERN_INFO "Enable cache parity protection for " | |
845 | "MIPS 20KC/25KF CPUs.\n"); | |
846 | clear_c0_status(ST0_DE); | |
847 | break; | |
848 | default: | |
849 | break; | |
850 | } | |
851 | } | |
852 | ||
853 | asmlinkage void cache_parity_error(void) | |
854 | { | |
855 | const int field = 2 * sizeof(unsigned long); | |
856 | unsigned int reg_val; | |
857 | ||
858 | /* For the moment, report the problem and hang. */ | |
859 | printk("Cache error exception:\n"); | |
860 | printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); | |
861 | reg_val = read_c0_cacheerr(); | |
862 | printk("c0_cacheerr == %08x\n", reg_val); | |
863 | ||
864 | printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", | |
865 | reg_val & (1<<30) ? "secondary" : "primary", | |
866 | reg_val & (1<<31) ? "data" : "insn"); | |
867 | printk("Error bits: %s%s%s%s%s%s%s\n", | |
868 | reg_val & (1<<29) ? "ED " : "", | |
869 | reg_val & (1<<28) ? "ET " : "", | |
870 | reg_val & (1<<26) ? "EE " : "", | |
871 | reg_val & (1<<25) ? "EB " : "", | |
872 | reg_val & (1<<24) ? "EI " : "", | |
873 | reg_val & (1<<23) ? "E1 " : "", | |
874 | reg_val & (1<<22) ? "E0 " : ""); | |
875 | printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); | |
876 | ||
ec917c2c | 877 | #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) |
1da177e4 LT |
878 | if (reg_val & (1<<22)) |
879 | printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); | |
880 | ||
881 | if (reg_val & (1<<23)) | |
882 | printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1()); | |
883 | #endif | |
884 | ||
885 | panic("Can't handle the cache error!"); | |
886 | } | |
887 | ||
888 | /* | |
889 | * SDBBP EJTAG debug exception handler. | |
890 | * We skip the instruction and return to the next instruction. | |
891 | */ | |
892 | void ejtag_exception_handler(struct pt_regs *regs) | |
893 | { | |
894 | const int field = 2 * sizeof(unsigned long); | |
895 | unsigned long depc, old_epc; | |
896 | unsigned int debug; | |
897 | ||
898 | printk("SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); | |
899 | depc = read_c0_depc(); | |
900 | debug = read_c0_debug(); | |
901 | printk("c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug); | |
902 | if (debug & 0x80000000) { | |
903 | /* | |
904 | * In branch delay slot. | |
905 | * We cheat a little bit here and use EPC to calculate the | |
906 | * debug return address (DEPC). EPC is restored after the | |
907 | * calculation. | |
908 | */ | |
909 | old_epc = regs->cp0_epc; | |
910 | regs->cp0_epc = depc; | |
911 | __compute_return_epc(regs); | |
912 | depc = regs->cp0_epc; | |
913 | regs->cp0_epc = old_epc; | |
914 | } else | |
915 | depc += 4; | |
916 | write_c0_depc(depc); | |
917 | ||
918 | #if 0 | |
919 | printk("\n\n----- Enable EJTAG single stepping ----\n\n"); | |
920 | write_c0_debug(debug | 0x100); | |
921 | #endif | |
922 | } | |
923 | ||
924 | /* | |
925 | * NMI exception handler. | |
926 | */ | |
927 | void nmi_exception_handler(struct pt_regs *regs) | |
928 | { | |
929 | printk("NMI taken!!!!\n"); | |
930 | die("NMI", regs); | |
931 | while(1) ; | |
932 | } | |
933 | ||
e01402b1 RB |
934 | #define VECTORSPACING 0x100 /* for EI/VI mode */ |
935 | ||
936 | unsigned long ebase; | |
1da177e4 | 937 | unsigned long exception_handlers[32]; |
e01402b1 | 938 | unsigned long vi_handlers[64]; |
1da177e4 LT |
939 | |
940 | /* | |
941 | * As a side effect of the way this is implemented we're limited | |
942 | * to interrupt handlers in the address range from | |
943 | * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ... | |
944 | */ | |
945 | void *set_except_vector(int n, void *addr) | |
946 | { | |
947 | unsigned long handler = (unsigned long) addr; | |
948 | unsigned long old_handler = exception_handlers[n]; | |
949 | ||
950 | exception_handlers[n] = handler; | |
951 | if (n == 0 && cpu_has_divec) { | |
e01402b1 | 952 | *(volatile u32 *)(ebase + 0x200) = 0x08000000 | |
1da177e4 | 953 | (0x03ffffff & (handler >> 2)); |
e01402b1 RB |
954 | flush_icache_range(ebase + 0x200, ebase + 0x204); |
955 | } | |
956 | return (void *)old_handler; | |
957 | } | |
958 | ||
959 | #ifdef CONFIG_CPU_MIPSR2 | |
960 | /* | |
961 | * Shadow register allocation | |
962 | * FIXME: SMP... | |
963 | */ | |
964 | ||
965 | /* MIPSR2 shadow register sets */ | |
966 | struct shadow_registers { | |
967 | spinlock_t sr_lock; /* */ | |
968 | int sr_supported; /* Number of shadow register sets supported */ | |
969 | int sr_allocated; /* Bitmap of allocated shadow registers */ | |
970 | } shadow_registers; | |
971 | ||
972 | void mips_srs_init(void) | |
973 | { | |
974 | #ifdef CONFIG_CPU_MIPSR2_SRS | |
975 | shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1; | |
976 | printk ("%d MIPSR2 register sets available\n", shadow_registers.sr_supported); | |
977 | #else | |
978 | shadow_registers.sr_supported = 1; | |
979 | #endif | |
980 | shadow_registers.sr_allocated = 1; /* Set 0 used by kernel */ | |
981 | spin_lock_init(&shadow_registers.sr_lock); | |
982 | } | |
983 | ||
984 | int mips_srs_max(void) | |
985 | { | |
986 | return shadow_registers.sr_supported; | |
987 | } | |
988 | ||
989 | int mips_srs_alloc (void) | |
990 | { | |
991 | struct shadow_registers *sr = &shadow_registers; | |
992 | unsigned long flags; | |
993 | int set; | |
994 | ||
995 | spin_lock_irqsave(&sr->sr_lock, flags); | |
996 | ||
997 | for (set = 0; set < sr->sr_supported; set++) { | |
998 | if ((sr->sr_allocated & (1 << set)) == 0) { | |
999 | sr->sr_allocated |= 1 << set; | |
1000 | spin_unlock_irqrestore(&sr->sr_lock, flags); | |
1001 | return set; | |
1002 | } | |
1003 | } | |
1004 | ||
1005 | /* None available */ | |
1006 | spin_unlock_irqrestore(&sr->sr_lock, flags); | |
1007 | return -1; | |
1008 | } | |
1009 | ||
1010 | void mips_srs_free (int set) | |
1011 | { | |
1012 | struct shadow_registers *sr = &shadow_registers; | |
1013 | unsigned long flags; | |
1014 | ||
1015 | spin_lock_irqsave(&sr->sr_lock, flags); | |
1016 | sr->sr_allocated &= ~(1 << set); | |
1017 | spin_unlock_irqrestore(&sr->sr_lock, flags); | |
1018 | } | |
1019 | ||
1020 | void *set_vi_srs_handler (int n, void *addr, int srs) | |
1021 | { | |
1022 | unsigned long handler; | |
1023 | unsigned long old_handler = vi_handlers[n]; | |
1024 | u32 *w; | |
1025 | unsigned char *b; | |
1026 | ||
1027 | if (!cpu_has_veic && !cpu_has_vint) | |
1028 | BUG(); | |
1029 | ||
1030 | if (addr == NULL) { | |
1031 | handler = (unsigned long) do_default_vi; | |
1032 | srs = 0; | |
1033 | } | |
1034 | else | |
1035 | handler = (unsigned long) addr; | |
1036 | vi_handlers[n] = (unsigned long) addr; | |
1037 | ||
1038 | b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); | |
1039 | ||
1040 | if (srs >= mips_srs_max()) | |
1041 | panic("Shadow register set %d not supported", srs); | |
1042 | ||
1043 | if (cpu_has_veic) { | |
1044 | if (board_bind_eic_interrupt) | |
1045 | board_bind_eic_interrupt (n, srs); | |
1046 | } | |
1047 | else if (cpu_has_vint) { | |
1048 | /* SRSMap is only defined if shadow sets are implemented */ | |
1049 | if (mips_srs_max() > 1) | |
1050 | change_c0_srsmap (0xf << n*4, srs << n*4); | |
1051 | } | |
1052 | ||
1053 | if (srs == 0) { | |
1054 | /* | |
1055 | * If no shadow set is selected then use the default handler | |
1056 | * that does normal register saving and a standard interrupt exit | |
1057 | */ | |
1058 | ||
1059 | extern char except_vec_vi, except_vec_vi_lui; | |
1060 | extern char except_vec_vi_ori, except_vec_vi_end; | |
1061 | const int handler_len = &except_vec_vi_end - &except_vec_vi; | |
1062 | const int lui_offset = &except_vec_vi_lui - &except_vec_vi; | |
1063 | const int ori_offset = &except_vec_vi_ori - &except_vec_vi; | |
1064 | ||
1065 | if (handler_len > VECTORSPACING) { | |
1066 | /* | |
1067 | * Sigh... panicing won't help as the console | |
1068 | * is probably not configured :( | |
1069 | */ | |
1070 | panic ("VECTORSPACING too small"); | |
1071 | } | |
1072 | ||
1073 | memcpy (b, &except_vec_vi, handler_len); | |
1074 | w = (u32 *)(b + lui_offset); | |
1075 | *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff); | |
1076 | w = (u32 *)(b + ori_offset); | |
1077 | *w = (*w & 0xffff0000) | ((u32)handler & 0xffff); | |
1078 | flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len)); | |
1079 | } | |
1080 | else { | |
1081 | /* | |
1082 | * In other cases jump directly to the interrupt handler | |
1083 | * | |
1084 | * It is the handlers responsibility to save registers if required | |
1085 | * (eg hi/lo) and return from the exception using "eret" | |
1086 | */ | |
1087 | w = (u32 *)b; | |
1088 | *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */ | |
1089 | *w = 0; | |
1090 | flush_icache_range((unsigned long)b, (unsigned long)(b+8)); | |
1da177e4 | 1091 | } |
e01402b1 | 1092 | |
1da177e4 LT |
1093 | return (void *)old_handler; |
1094 | } | |
1095 | ||
e01402b1 RB |
1096 | void *set_vi_handler (int n, void *addr) |
1097 | { | |
1098 | return set_vi_srs_handler (n, addr, 0); | |
1099 | } | |
1100 | #endif | |
1101 | ||
1da177e4 LT |
1102 | /* |
1103 | * This is used by native signal handling | |
1104 | */ | |
1105 | asmlinkage int (*save_fp_context)(struct sigcontext *sc); | |
1106 | asmlinkage int (*restore_fp_context)(struct sigcontext *sc); | |
1107 | ||
1108 | extern asmlinkage int _save_fp_context(struct sigcontext *sc); | |
1109 | extern asmlinkage int _restore_fp_context(struct sigcontext *sc); | |
1110 | ||
1111 | extern asmlinkage int fpu_emulator_save_context(struct sigcontext *sc); | |
1112 | extern asmlinkage int fpu_emulator_restore_context(struct sigcontext *sc); | |
1113 | ||
1114 | static inline void signal_init(void) | |
1115 | { | |
1116 | if (cpu_has_fpu) { | |
1117 | save_fp_context = _save_fp_context; | |
1118 | restore_fp_context = _restore_fp_context; | |
1119 | } else { | |
1120 | save_fp_context = fpu_emulator_save_context; | |
1121 | restore_fp_context = fpu_emulator_restore_context; | |
1122 | } | |
1123 | } | |
1124 | ||
1125 | #ifdef CONFIG_MIPS32_COMPAT | |
1126 | ||
1127 | /* | |
1128 | * This is used by 32-bit signal stuff on the 64-bit kernel | |
1129 | */ | |
1130 | asmlinkage int (*save_fp_context32)(struct sigcontext32 *sc); | |
1131 | asmlinkage int (*restore_fp_context32)(struct sigcontext32 *sc); | |
1132 | ||
1133 | extern asmlinkage int _save_fp_context32(struct sigcontext32 *sc); | |
1134 | extern asmlinkage int _restore_fp_context32(struct sigcontext32 *sc); | |
1135 | ||
1136 | extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 *sc); | |
1137 | extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 *sc); | |
1138 | ||
1139 | static inline void signal32_init(void) | |
1140 | { | |
1141 | if (cpu_has_fpu) { | |
1142 | save_fp_context32 = _save_fp_context32; | |
1143 | restore_fp_context32 = _restore_fp_context32; | |
1144 | } else { | |
1145 | save_fp_context32 = fpu_emulator_save_context32; | |
1146 | restore_fp_context32 = fpu_emulator_restore_context32; | |
1147 | } | |
1148 | } | |
1149 | #endif | |
1150 | ||
1151 | extern void cpu_cache_init(void); | |
1152 | extern void tlb_init(void); | |
1d40cfcd | 1153 | extern void flush_tlb_handlers(void); |
1da177e4 LT |
1154 | |
1155 | void __init per_cpu_trap_init(void) | |
1156 | { | |
1157 | unsigned int cpu = smp_processor_id(); | |
1158 | unsigned int status_set = ST0_CU0; | |
1159 | ||
1160 | /* | |
1161 | * Disable coprocessors and select 32-bit or 64-bit addressing | |
1162 | * and the 16/32 or 32/32 FPR register model. Reset the BEV | |
1163 | * flag that some firmware may have left set and the TS bit (for | |
1164 | * IP27). Set XX for ISA IV code to work. | |
1165 | */ | |
875d43e7 | 1166 | #ifdef CONFIG_64BIT |
1da177e4 LT |
1167 | status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; |
1168 | #endif | |
1169 | if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV) | |
1170 | status_set |= ST0_XX; | |
e50c0a8f | 1171 | change_c0_status(ST0_CU|ST0_MX|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, |
1da177e4 LT |
1172 | status_set); |
1173 | ||
e50c0a8f RB |
1174 | if (cpu_has_dsp) |
1175 | set_c0_status(ST0_MX); | |
1176 | ||
e01402b1 RB |
1177 | #ifdef CONFIG_CPU_MIPSR2 |
1178 | write_c0_hwrena (0x0000000f); /* Allow rdhwr to all registers */ | |
1179 | #endif | |
1180 | ||
1da177e4 | 1181 | /* |
e01402b1 | 1182 | * Interrupt handling. |
1da177e4 | 1183 | */ |
e01402b1 RB |
1184 | if (cpu_has_veic || cpu_has_vint) { |
1185 | write_c0_ebase (ebase); | |
1186 | /* Setting vector spacing enables EI/VI mode */ | |
1187 | change_c0_intctl (0x3e0, VECTORSPACING); | |
1188 | } | |
d03d0a57 RB |
1189 | if (cpu_has_divec) { |
1190 | if (cpu_has_mipsmt) { | |
1191 | unsigned int vpflags = dvpe(); | |
1192 | set_c0_cause(CAUSEF_IV); | |
1193 | evpe(vpflags); | |
1194 | } else | |
1195 | set_c0_cause(CAUSEF_IV); | |
1196 | } | |
1da177e4 LT |
1197 | |
1198 | cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; | |
1199 | TLBMISS_HANDLER_SETUP(); | |
1200 | ||
1201 | atomic_inc(&init_mm.mm_count); | |
1202 | current->active_mm = &init_mm; | |
1203 | BUG_ON(current->mm); | |
1204 | enter_lazy_tlb(&init_mm, current); | |
1205 | ||
1206 | cpu_cache_init(); | |
1207 | tlb_init(); | |
1208 | } | |
1209 | ||
e01402b1 RB |
1210 | /* Install CPU exception handler */ |
1211 | void __init set_handler (unsigned long offset, void *addr, unsigned long size) | |
1212 | { | |
1213 | memcpy((void *)(ebase + offset), addr, size); | |
1214 | flush_icache_range(ebase + offset, ebase + offset + size); | |
1215 | } | |
1216 | ||
1217 | /* Install uncached CPU exception handler */ | |
1218 | void __init set_uncached_handler (unsigned long offset, void *addr, unsigned long size) | |
1219 | { | |
1220 | #ifdef CONFIG_32BIT | |
1221 | unsigned long uncached_ebase = KSEG1ADDR(ebase); | |
1222 | #endif | |
1223 | #ifdef CONFIG_64BIT | |
1224 | unsigned long uncached_ebase = TO_UNCAC(ebase); | |
1225 | #endif | |
1226 | ||
1227 | memcpy((void *)(uncached_ebase + offset), addr, size); | |
1228 | } | |
1229 | ||
1da177e4 LT |
1230 | void __init trap_init(void) |
1231 | { | |
1232 | extern char except_vec3_generic, except_vec3_r4000; | |
1da177e4 LT |
1233 | extern char except_vec4; |
1234 | unsigned long i; | |
1235 | ||
e01402b1 RB |
1236 | if (cpu_has_veic || cpu_has_vint) |
1237 | ebase = (unsigned long) alloc_bootmem_low_pages (0x200 + VECTORSPACING*64); | |
1238 | else | |
1239 | ebase = CAC_BASE; | |
1240 | ||
1241 | #ifdef CONFIG_CPU_MIPSR2 | |
1242 | mips_srs_init(); | |
1243 | #endif | |
1244 | ||
1da177e4 LT |
1245 | per_cpu_trap_init(); |
1246 | ||
1247 | /* | |
1248 | * Copy the generic exception handlers to their final destination. | |
1249 | * This will be overriden later as suitable for a particular | |
1250 | * configuration. | |
1251 | */ | |
e01402b1 | 1252 | set_handler(0x180, &except_vec3_generic, 0x80); |
1da177e4 LT |
1253 | |
1254 | /* | |
1255 | * Setup default vectors | |
1256 | */ | |
1257 | for (i = 0; i <= 31; i++) | |
1258 | set_except_vector(i, handle_reserved); | |
1259 | ||
1260 | /* | |
1261 | * Copy the EJTAG debug exception vector handler code to it's final | |
1262 | * destination. | |
1263 | */ | |
e01402b1 RB |
1264 | if (cpu_has_ejtag && board_ejtag_handler_setup) |
1265 | board_ejtag_handler_setup (); | |
1da177e4 LT |
1266 | |
1267 | /* | |
1268 | * Only some CPUs have the watch exceptions. | |
1269 | */ | |
1270 | if (cpu_has_watch) | |
1271 | set_except_vector(23, handle_watch); | |
1272 | ||
1273 | /* | |
e01402b1 | 1274 | * Initialise interrupt handlers |
1da177e4 | 1275 | */ |
e01402b1 RB |
1276 | if (cpu_has_veic || cpu_has_vint) { |
1277 | int nvec = cpu_has_veic ? 64 : 8; | |
1278 | for (i = 0; i < nvec; i++) | |
1279 | set_vi_handler (i, NULL); | |
1280 | } | |
1281 | else if (cpu_has_divec) | |
1282 | set_handler(0x200, &except_vec4, 0x8); | |
1da177e4 LT |
1283 | |
1284 | /* | |
1285 | * Some CPUs can enable/disable for cache parity detection, but does | |
1286 | * it different ways. | |
1287 | */ | |
1288 | parity_protection_init(); | |
1289 | ||
1290 | /* | |
1291 | * The Data Bus Errors / Instruction Bus Errors are signaled | |
1292 | * by external hardware. Therefore these two exceptions | |
1293 | * may have board specific handlers. | |
1294 | */ | |
1295 | if (board_be_init) | |
1296 | board_be_init(); | |
1297 | ||
1298 | set_except_vector(1, handle_tlbm); | |
1299 | set_except_vector(2, handle_tlbl); | |
1300 | set_except_vector(3, handle_tlbs); | |
1301 | ||
1302 | set_except_vector(4, handle_adel); | |
1303 | set_except_vector(5, handle_ades); | |
1304 | ||
1305 | set_except_vector(6, handle_ibe); | |
1306 | set_except_vector(7, handle_dbe); | |
1307 | ||
1308 | set_except_vector(8, handle_sys); | |
1309 | set_except_vector(9, handle_bp); | |
1310 | set_except_vector(10, handle_ri); | |
1311 | set_except_vector(11, handle_cpu); | |
1312 | set_except_vector(12, handle_ov); | |
1313 | set_except_vector(13, handle_tr); | |
1da177e4 LT |
1314 | |
1315 | if (current_cpu_data.cputype == CPU_R6000 || | |
1316 | current_cpu_data.cputype == CPU_R6000A) { | |
1317 | /* | |
1318 | * The R6000 is the only R-series CPU that features a machine | |
1319 | * check exception (similar to the R4000 cache error) and | |
1320 | * unaligned ldc1/sdc1 exception. The handlers have not been | |
1321 | * written yet. Well, anyway there is no R6000 machine on the | |
1322 | * current list of targets for Linux/MIPS. | |
1323 | * (Duh, crap, there is someone with a triple R6k machine) | |
1324 | */ | |
1325 | //set_except_vector(14, handle_mc); | |
1326 | //set_except_vector(15, handle_ndc); | |
1327 | } | |
1328 | ||
e01402b1 RB |
1329 | |
1330 | if (board_nmi_handler_setup) | |
1331 | board_nmi_handler_setup(); | |
1332 | ||
e50c0a8f RB |
1333 | if (cpu_has_fpu && !cpu_has_nofpuex) |
1334 | set_except_vector(15, handle_fpe); | |
1335 | ||
1336 | set_except_vector(22, handle_mdmx); | |
1337 | ||
1338 | if (cpu_has_mcheck) | |
1339 | set_except_vector(24, handle_mcheck); | |
1340 | ||
340ee4b9 RB |
1341 | if (cpu_has_mipsmt) |
1342 | set_except_vector(25, handle_mt); | |
1343 | ||
e50c0a8f RB |
1344 | if (cpu_has_dsp) |
1345 | set_except_vector(26, handle_dsp); | |
1346 | ||
1347 | if (cpu_has_vce) | |
1348 | /* Special exception: R4[04]00 uses also the divec space. */ | |
1349 | memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100); | |
1350 | else if (cpu_has_4kex) | |
1351 | memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80); | |
1352 | else | |
1353 | memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80); | |
1354 | ||
1da177e4 LT |
1355 | signal_init(); |
1356 | #ifdef CONFIG_MIPS32_COMPAT | |
1357 | signal32_init(); | |
1358 | #endif | |
1359 | ||
e01402b1 | 1360 | flush_icache_range(ebase, ebase + 0x400); |
1d40cfcd | 1361 | flush_tlb_handlers(); |
1da177e4 | 1362 | } |