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[MIPS] Remove unused MODULE_RANGE macro.
[linux-block.git] / arch / mips / kernel / traps.c
CommitLineData
1da177e4
LT		 1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
36ccf1c0 6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
1da177e4
LT		 7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2000, 01 MIPS Technologies, Inc.
3b2396d9 12 * Copyright (C) 2002, 2003, 2004, 2005 Maciej W. Rozycki
1da177e4 13 */
1da177e4
LT		 14#include <linux/init.h>
15#include <linux/mm.h>
16#include <linux/module.h>
17#include <linux/sched.h>
18#include <linux/smp.h>
19#include <linux/smp_lock.h>
20#include <linux/spinlock.h>
21#include <linux/kallsyms.h>
e01402b1 22#include <linux/bootmem.h>
d4fd1989 23#include <linux/interrupt.h>
1da177e4
LT		 24
25#include <asm/bootinfo.h>
26#include <asm/branch.h>
27#include <asm/break.h>
28#include <asm/cpu.h>
e50c0a8f 29#include <asm/dsp.h>
1da177e4 30#include <asm/fpu.h>
340ee4b9
RB		 31#include <asm/mipsregs.h>
32#include <asm/mipsmtregs.h>
1da177e4
LT		 33#include <asm/module.h>
34#include <asm/pgtable.h>
35#include <asm/ptrace.h>
36#include <asm/sections.h>
37#include <asm/system.h>
38#include <asm/tlbdebug.h>
39#include <asm/traps.h>
40#include <asm/uaccess.h>
41#include <asm/mmu_context.h>
42#include <asm/watch.h>
43#include <asm/types.h>
44
e4ac58af 45extern asmlinkage void handle_int(void);
1da177e4
LT		 46extern asmlinkage void handle_tlbm(void);
47extern asmlinkage void handle_tlbl(void);
48extern asmlinkage void handle_tlbs(void);
49extern asmlinkage void handle_adel(void);
50extern asmlinkage void handle_ades(void);
51extern asmlinkage void handle_ibe(void);
52extern asmlinkage void handle_dbe(void);
53extern asmlinkage void handle_sys(void);
54extern asmlinkage void handle_bp(void);
55extern asmlinkage void handle_ri(void);
56extern asmlinkage void handle_cpu(void);
57extern asmlinkage void handle_ov(void);
58extern asmlinkage void handle_tr(void);
59extern asmlinkage void handle_fpe(void);
60extern asmlinkage void handle_mdmx(void);
61extern asmlinkage void handle_watch(void);
340ee4b9 62extern asmlinkage void handle_mt(void);
e50c0a8f 63extern asmlinkage void handle_dsp(void);
1da177e4
LT		 64extern asmlinkage void handle_mcheck(void);
65extern asmlinkage void handle_reserved(void);
66
12616ed2 67extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
eae89076 68 struct mips_fpu_struct *ctx);
1da177e4
LT		 69
70void (*board_be_init)(void);
71int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
e01402b1
RB		 72void (*board_nmi_handler_setup)(void);
73void (*board_ejtag_handler_setup)(void);
74void (*board_bind_eic_interrupt)(int irq, int regset);
1da177e4 75
1da177e4 76
e889d78f
AN		 77static void show_trace(unsigned long *stack)
78{
79 const int field = 2 * sizeof(unsigned long);
80 unsigned long addr;
81
82 printk("Call Trace:");
83#ifdef CONFIG_KALLSYMS
84 printk("\n");
85#endif
86 while (!kstack_end(stack)) {
87 addr = *stack++;
88 if (__kernel_text_address(addr)) {
89 printk(" [<%0*lx>] ", field, addr);
90 print_symbol("%s\n", addr);
91 }
92 }
93 printk("\n");
94}
95
f66686f7
AN		 96#ifdef CONFIG_KALLSYMS
97static int raw_show_trace;
98static int __init set_raw_show_trace(char *str)
99{
100 raw_show_trace = 1;
101 return 1;
102}
103__setup("raw_show_trace", set_raw_show_trace);
104
105extern unsigned long unwind_stack(struct task_struct *task,
106 unsigned long **sp, unsigned long pc);
107static void show_frametrace(struct task_struct *task, struct pt_regs *regs)
108{
109 const int field = 2 * sizeof(unsigned long);
110 unsigned long *stack = (long *)regs->regs[29];
111 unsigned long pc = regs->cp0_epc;
112 int top = 1;
113
114 if (raw_show_trace || !__kernel_text_address(pc)) {
115 show_trace(stack);
116 return;
117 }
118 printk("Call Trace:\n");
119 while (__kernel_text_address(pc)) {
120 printk(" [<%0*lx>] ", field, pc);
121 print_symbol("%s\n", pc);
122 pc = unwind_stack(task, &stack, pc);
123 if (top && pc == 0)
124 pc = regs->regs[31]; /* leaf? */
125 top = 0;
126 }
127 printk("\n");
128}
129#else
130#define show_frametrace(task, r) show_trace((long *)(r)->regs[29]);
131#endif
132
1da177e4
LT		 133/*
134 * This routine abuses get_user()/put_user() to reference pointers
135 * with at least a bit of error checking ...
136 */
f66686f7 137static void show_stacktrace(struct task_struct *task, struct pt_regs *regs)
1da177e4
LT		 138{
139 const int field = 2 * sizeof(unsigned long);
140 long stackdata;
141 int i;
f66686f7 142 unsigned long *sp = (unsigned long *)regs->regs[29];
1da177e4
LT		 143
144 printk("Stack :");
145 i = 0;
146 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
147 if (i && ((i % (64 / field)) == 0))
148 printk("\n ");
149 if (i > 39) {
150 printk(" ...");
151 break;
152 }
153
154 if (__get_user(stackdata, sp++)) {
155 printk(" (Bad stack address)");
156 break;
157 }
158
159 printk(" %0*lx", field, stackdata);
160 i++;
161 }
162 printk("\n");
f66686f7
AN		 163 show_frametrace(task, regs);
164}
165
166static noinline void prepare_frametrace(struct pt_regs *regs)
167{
168 __asm__ __volatile__(
169 "1: la $2, 1b\n\t"
170#ifdef CONFIG_64BIT
171 "sd $2, %0\n\t"
172 "sd $29, %1\n\t"
173 "sd $31, %2\n\t"
174#else
175 "sw $2, %0\n\t"
176 "sw $29, %1\n\t"
177 "sw $31, %2\n\t"
178#endif
179 : "=m" (regs->cp0_epc),
180 "=m" (regs->regs[29]), "=m" (regs->regs[31])
181 : : "memory");
182}
183
184void show_stack(struct task_struct *task, unsigned long *sp)
185{
186 struct pt_regs regs;
187 if (sp) {
188 regs.regs[29] = (unsigned long)sp;
189 regs.regs[31] = 0;
190 regs.cp0_epc = 0;
191 } else {
192 if (task && task != current) {
193 regs.regs[29] = task->thread.reg29;
194 regs.regs[31] = 0;
195 regs.cp0_epc = task->thread.reg31;
196 } else {
197 prepare_frametrace(&regs);
198 }
199 }
200 show_stacktrace(task, &regs);
1da177e4
LT		 201}
202
203/*
204 * The architecture-independent dump_stack generator
205 */
206void dump_stack(void)
207{
208 unsigned long stack;
209
f66686f7
AN		 210#ifdef CONFIG_KALLSYMS
211 if (!raw_show_trace) {
212 struct pt_regs regs;
213 prepare_frametrace(&regs);
214 show_frametrace(current, &regs);
215 return;
216 }
217#endif
e889d78f 218 show_trace(&stack);
1da177e4
LT		 219}
220
221EXPORT_SYMBOL(dump_stack);
222
223void show_code(unsigned int *pc)
224{
225 long i;
226
227 printk("\nCode:");
228
229 for(i = -3 ; i < 6 ; i++) {
230 unsigned int insn;
231 if (__get_user(insn, pc + i)) {
232 printk(" (Bad address in epc)\n");
233 break;
234 }
235 printk("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>'));
236 }
237}
238
239void show_regs(struct pt_regs *regs)
240{
241 const int field = 2 * sizeof(unsigned long);
242 unsigned int cause = regs->cp0_cause;
243 int i;
244
245 printk("Cpu %d\n", smp_processor_id());
246
247 /*
248 * Saved main processor registers
249 */
250 for (i = 0; i < 32; ) {
251 if ((i % 4) == 0)
252 printk("$%2d :", i);
253 if (i == 0)
254 printk(" %0*lx", field, 0UL);
255 else if (i == 26 || i == 27)
256 printk(" %*s", field, "");
257 else
258 printk(" %0*lx", field, regs->regs[i]);
259
260 i++;
261 if ((i % 4) == 0)
262 printk("\n");
263 }
264
265 printk("Hi : %0*lx\n", field, regs->hi);
266 printk("Lo : %0*lx\n", field, regs->lo);
267
268 /*
269 * Saved cp0 registers
270 */
271 printk("epc : %0*lx ", field, regs->cp0_epc);
272 print_symbol("%s ", regs->cp0_epc);
273 printk(" %s\n", print_tainted());
274 printk("ra : %0*lx ", field, regs->regs[31]);
275 print_symbol("%s\n", regs->regs[31]);
276
277 printk("Status: %08x ", (uint32_t) regs->cp0_status);
278
3b2396d9
MR		 279 if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) {
280 if (regs->cp0_status & ST0_KUO)
281 printk("KUo ");
282 if (regs->cp0_status & ST0_IEO)
283 printk("IEo ");
284 if (regs->cp0_status & ST0_KUP)
285 printk("KUp ");
286 if (regs->cp0_status & ST0_IEP)
287 printk("IEp ");
288 if (regs->cp0_status & ST0_KUC)
289 printk("KUc ");
290 if (regs->cp0_status & ST0_IEC)
291 printk("IEc ");
292 } else {
293 if (regs->cp0_status & ST0_KX)
294 printk("KX ");
295 if (regs->cp0_status & ST0_SX)
296 printk("SX ");
297 if (regs->cp0_status & ST0_UX)
298 printk("UX ");
299 switch (regs->cp0_status & ST0_KSU) {
300 case KSU_USER:
301 printk("USER ");
302 break;
303 case KSU_SUPERVISOR:
304 printk("SUPERVISOR ");
305 break;
306 case KSU_KERNEL:
307 printk("KERNEL ");
308 break;
309 default:
310 printk("BAD_MODE ");
311 break;
312 }
313 if (regs->cp0_status & ST0_ERL)
314 printk("ERL ");
315 if (regs->cp0_status & ST0_EXL)
316 printk("EXL ");
317 if (regs->cp0_status & ST0_IE)
318 printk("IE ");
1da177e4 319 }
1da177e4
LT		 320 printk("\n");
321
322 printk("Cause : %08x\n", cause);
323
324 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
325 if (1 <= cause && cause <= 5)
326 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
327
328 printk("PrId : %08x\n", read_c0_prid());
329}
330
331void show_registers(struct pt_regs *regs)
332{
333 show_regs(regs);
334 print_modules();
335 printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n",
336 current->comm, current->pid, current_thread_info(), current);
f66686f7 337 show_stacktrace(current, regs);
1da177e4
LT		 338 show_code((unsigned int *) regs->cp0_epc);
339 printk("\n");
340}
341
342static DEFINE_SPINLOCK(die_lock);
343
178086c8 344NORET_TYPE void ATTRIB_NORET die(const char * str, struct pt_regs * regs)
1da177e4
LT		 345{
346 static int die_counter;
41c594ab
RB		 347#ifdef CONFIG_MIPS_MT_SMTC
348 unsigned long dvpret = dvpe();
349#endif /* CONFIG_MIPS_MT_SMTC */
1da177e4
LT		 350
351 console_verbose();
352 spin_lock_irq(&die_lock);
41c594ab
RB		 353 bust_spinlocks(1);
354#ifdef CONFIG_MIPS_MT_SMTC
355 mips_mt_regdump(dvpret);
356#endif /* CONFIG_MIPS_MT_SMTC */
178086c8 357 printk("%s[#%d]:\n", str, ++die_counter);
1da177e4
LT		 358 show_registers(regs);
359 spin_unlock_irq(&die_lock);
d4fd1989
MB		 360
361 if (in_interrupt())
362 panic("Fatal exception in interrupt");
363
364 if (panic_on_oops) {
365 printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n");
366 ssleep(5);
367 panic("Fatal exception");
368 }
369
1da177e4
LT		 370 do_exit(SIGSEGV);
371}
372
1da177e4
LT		 373extern const struct exception_table_entry __start___dbe_table[];
374extern const struct exception_table_entry __stop___dbe_table[];
375
376void __declare_dbe_table(void)
377{
378 __asm__ __volatile__(
379 ".section\t__dbe_table,\"a\"\n\t"
380 ".previous"
381 );
382}
383
384/* Given an address, look for it in the exception tables. */
385static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
386{
387 const struct exception_table_entry *e;
388
389 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
390 if (!e)
391 e = search_module_dbetables(addr);
392 return e;
393}
394
395asmlinkage void do_be(struct pt_regs *regs)
396{
397 const int field = 2 * sizeof(unsigned long);
398 const struct exception_table_entry *fixup = NULL;
399 int data = regs->cp0_cause & 4;
400 int action = MIPS_BE_FATAL;
401
402 /* XXX For now. Fixme, this searches the wrong table ... */
403 if (data && !user_mode(regs))
404 fixup = search_dbe_tables(exception_epc(regs));
405
406 if (fixup)
407 action = MIPS_BE_FIXUP;
408
409 if (board_be_handler)
410 action = board_be_handler(regs, fixup != 0);
411
412 switch (action) {
413 case MIPS_BE_DISCARD:
414 return;
415 case MIPS_BE_FIXUP:
416 if (fixup) {
417 regs->cp0_epc = fixup->nextinsn;
418 return;
419 }
420 break;
421 default:
422 break;
423 }
424
425 /*
426 * Assume it would be too dangerous to continue ...
427 */
428 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
429 data ? "Data" : "Instruction",
430 field, regs->cp0_epc, field, regs->regs[31]);
431 die_if_kernel("Oops", regs);
432 force_sig(SIGBUS, current);
433}
434
435static inline int get_insn_opcode(struct pt_regs *regs, unsigned int *opcode)
436{
fe00f943 437 unsigned int __user *epc;
1da177e4 438
fe00f943 439 epc = (unsigned int __user *) regs->cp0_epc +
1da177e4
LT		 440 ((regs->cp0_cause & CAUSEF_BD) != 0);
441 if (!get_user(*opcode, epc))
442 return 0;
443
444 force_sig(SIGSEGV, current);
445 return 1;
446}
447
448/*
449 * ll/sc emulation
450 */
451
452#define OPCODE 0xfc000000
453#define BASE 0x03e00000
454#define RT 0x001f0000
455#define OFFSET 0x0000ffff
456#define LL 0xc0000000
457#define SC 0xe0000000
3c37026d
RB		 458#define SPEC3 0x7c000000
459#define RD 0x0000f800
460#define FUNC 0x0000003f
461#define RDHWR 0x0000003b
1da177e4
LT		 462
463/*
464 * The ll_bit is cleared by r*_switch.S
465 */
466
467unsigned long ll_bit;
468
469static struct task_struct *ll_task = NULL;
470
471static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode)
472{
fe00f943 473 unsigned long value, __user *vaddr;
1da177e4
LT		 474 long offset;
475 int signal = 0;
476
477 /*
478 * analyse the ll instruction that just caused a ri exception
479 * and put the referenced address to addr.
480 */
481
482 /* sign extend offset */
483 offset = opcode & OFFSET;
484 offset <<= 16;
485 offset >>= 16;
486
fe00f943
RB		 487 vaddr = (unsigned long __user *)
488 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
1da177e4
LT		 489
490 if ((unsigned long)vaddr & 3) {
491 signal = SIGBUS;
492 goto sig;
493 }
494 if (get_user(value, vaddr)) {
495 signal = SIGSEGV;
496 goto sig;
497 }
498
499 preempt_disable();
500
501 if (ll_task == NULL || ll_task == current) {
502 ll_bit = 1;
503 } else {
504 ll_bit = 0;
505 }
506 ll_task = current;
507
508 preempt_enable();
509
6dd04688
RB		 510 compute_return_epc(regs);
511
1da177e4
LT		 512 regs->regs[(opcode & RT) >> 16] = value;
513
1da177e4
LT		 514 return;
515
516sig:
517 force_sig(signal, current);
518}
519
520static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode)
521{
fe00f943
RB		 522 unsigned long __user *vaddr;
523 unsigned long reg;
1da177e4
LT		 524 long offset;
525 int signal = 0;
526
527 /*
528 * analyse the sc instruction that just caused a ri exception
529 * and put the referenced address to addr.
530 */
531
532 /* sign extend offset */
533 offset = opcode & OFFSET;
534 offset <<= 16;
535 offset >>= 16;
536
fe00f943
RB		 537 vaddr = (unsigned long __user *)
538 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
1da177e4
LT		 539 reg = (opcode & RT) >> 16;
540
541 if ((unsigned long)vaddr & 3) {
542 signal = SIGBUS;
543 goto sig;
544 }
545
546 preempt_disable();
547
548 if (ll_bit == 0 || ll_task != current) {
05b8042a 549 compute_return_epc(regs);
1da177e4
LT		 550 regs->regs[reg] = 0;
551 preempt_enable();
1da177e4
LT		 552 return;
553 }
554
555 preempt_enable();
556
557 if (put_user(regs->regs[reg], vaddr)) {
558 signal = SIGSEGV;
559 goto sig;
560 }
561
6dd04688 562 compute_return_epc(regs);
1da177e4
LT		 563 regs->regs[reg] = 1;
564
1da177e4
LT		 565 return;
566
567sig:
568 force_sig(signal, current);
569}
570
571/*
572 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
573 * opcodes are supposed to result in coprocessor unusable exceptions if
574 * executed on ll/sc-less processors. That's the theory. In practice a
575 * few processors such as NEC's VR4100 throw reserved instruction exceptions
576 * instead, so we're doing the emulation thing in both exception handlers.
577 */
578static inline int simulate_llsc(struct pt_regs *regs)
579{
580 unsigned int opcode;
581
582 if (unlikely(get_insn_opcode(regs, &opcode)))
583 return -EFAULT;
584
585 if ((opcode & OPCODE) == LL) {
586 simulate_ll(regs, opcode);
587 return 0;
588 }
589 if ((opcode & OPCODE) == SC) {
590 simulate_sc(regs, opcode);
591 return 0;
592 }
593
594 return -EFAULT; /* Strange things going on ... */
595}
596
3c37026d
RB		 597/*
598 * Simulate trapping 'rdhwr' instructions to provide user accessible
599 * registers not implemented in hardware. The only current use of this
600 * is the thread area pointer.
601 */
602static inline int simulate_rdhwr(struct pt_regs *regs)
603{
dc8f6029 604 struct thread_info *ti = task_thread_info(current);
3c37026d
RB		 605 unsigned int opcode;
606
607 if (unlikely(get_insn_opcode(regs, &opcode)))
608 return -EFAULT;
609
610 if (unlikely(compute_return_epc(regs)))
611 return -EFAULT;
612
613 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
614 int rd = (opcode & RD) >> 11;
615 int rt = (opcode & RT) >> 16;
616 switch (rd) {
617 case 29:
618 regs->regs[rt] = ti->tp_value;
56ebd51b 619 return 0;
3c37026d
RB		 620 default:
621 return -EFAULT;
622 }
623 }
624
56ebd51b
DJ		 625 /* Not ours. */
626 return -EFAULT;
3c37026d
RB		 627}
628
1da177e4
LT		 629asmlinkage void do_ov(struct pt_regs *regs)
630{
631 siginfo_t info;
632
36ccf1c0
RB		 633 die_if_kernel("Integer overflow", regs);
634
1da177e4
LT		 635 info.si_code = FPE_INTOVF;
636 info.si_signo = SIGFPE;
637 info.si_errno = 0;
fe00f943 638 info.si_addr = (void __user *) regs->cp0_epc;
1da177e4
LT		 639 force_sig_info(SIGFPE, &info, current);
640}
641
642/*
643 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
644 */
645asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
646{
57725f9e
CD		 647 die_if_kernel("FP exception in kernel code", regs);
648
1da177e4
LT		 649 if (fcr31 & FPU_CSR_UNI_X) {
650 int sig;
651
652 preempt_disable();
653
cd21dfcf
RB		 654#ifdef CONFIG_PREEMPT
655 if (!is_fpu_owner()) {
656 /* We might lose fpu before disabling preempt... */
657 own_fpu();
658 BUG_ON(!used_math());
659 restore_fp(current);
660 }
661#endif
1da177e4 662 /*
a3dddd56 663 * Unimplemented operation exception. If we've got the full
1da177e4
LT		 664 * software emulator on-board, let's use it...
665 *
666 * Force FPU to dump state into task/thread context. We're
667 * moving a lot of data here for what is probably a single
668 * instruction, but the alternative is to pre-decode the FP
669 * register operands before invoking the emulator, which seems
670 * a bit extreme for what should be an infrequent event.
671 */
672 save_fp(current);
cd21dfcf
RB		 673 /* Ensure 'resume' not overwrite saved fp context again. */
674 lose_fpu();
675
676 preempt_enable();
1da177e4
LT		 677
678 /* Run the emulator */
eae89076 679 sig = fpu_emulator_cop1Handler (regs, &current->thread.fpu);
1da177e4 680
cd21dfcf
RB		 681 preempt_disable();
682
683 own_fpu(); /* Using the FPU again. */
1da177e4
LT		 684 /*
685 * We can't allow the emulated instruction to leave any of
686 * the cause bit set in $fcr31.
687 */
eae89076 688 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
1da177e4
LT		 689
690 /* Restore the hardware register state */
691 restore_fp(current);
692
693 preempt_enable();
694
695 /* If something went wrong, signal */
696 if (sig)
697 force_sig(sig, current);
698
699 return;
700 }
701
702 force_sig(SIGFPE, current);
703}
704
705asmlinkage void do_bp(struct pt_regs *regs)
706{
707 unsigned int opcode, bcode;
708 siginfo_t info;
709
710 die_if_kernel("Break instruction in kernel code", regs);
711
712 if (get_insn_opcode(regs, &opcode))
713 return;
714
715 /*
716 * There is the ancient bug in the MIPS assemblers that the break
717 * code starts left to bit 16 instead to bit 6 in the opcode.
718 * Gas is bug-compatible, but not always, grrr...
719 * We handle both cases with a simple heuristics. --macro
720 */
721 bcode = ((opcode >> 6) & ((1 << 20) - 1));
722 if (bcode < (1 << 10))
723 bcode <<= 10;
724
725 /*
726 * (A short test says that IRIX 5.3 sends SIGTRAP for all break
727 * insns, even for break codes that indicate arithmetic failures.
728 * Weird ...)
729 * But should we continue the brokenness??? --macro
730 */
731 switch (bcode) {
732 case BRK_OVERFLOW << 10:
733 case BRK_DIVZERO << 10:
734 if (bcode == (BRK_DIVZERO << 10))
735 info.si_code = FPE_INTDIV;
736 else
737 info.si_code = FPE_INTOVF;
738 info.si_signo = SIGFPE;
739 info.si_errno = 0;
fe00f943 740 info.si_addr = (void __user *) regs->cp0_epc;
1da177e4
LT		 741 force_sig_info(SIGFPE, &info, current);
742 break;
743 default:
744 force_sig(SIGTRAP, current);
745 }
746}
747
748asmlinkage void do_tr(struct pt_regs *regs)
749{
750 unsigned int opcode, tcode = 0;
751 siginfo_t info;
752
753 die_if_kernel("Trap instruction in kernel code", regs);
754
755 if (get_insn_opcode(regs, &opcode))
756 return;
757
758 /* Immediate versions don't provide a code. */
759 if (!(opcode & OPCODE))
760 tcode = ((opcode >> 6) & ((1 << 10) - 1));
761
762 /*
763 * (A short test says that IRIX 5.3 sends SIGTRAP for all trap
764 * insns, even for trap codes that indicate arithmetic failures.
765 * Weird ...)
766 * But should we continue the brokenness??? --macro
767 */
768 switch (tcode) {
769 case BRK_OVERFLOW:
770 case BRK_DIVZERO:
771 if (tcode == BRK_DIVZERO)
772 info.si_code = FPE_INTDIV;
773 else
774 info.si_code = FPE_INTOVF;
775 info.si_signo = SIGFPE;
776 info.si_errno = 0;
fe00f943 777 info.si_addr = (void __user *) regs->cp0_epc;
1da177e4
LT		 778 force_sig_info(SIGFPE, &info, current);
779 break;
780 default:
781 force_sig(SIGTRAP, current);
782 }
783}
784
785asmlinkage void do_ri(struct pt_regs *regs)
786{
787 die_if_kernel("Reserved instruction in kernel code", regs);
788
789 if (!cpu_has_llsc)
790 if (!simulate_llsc(regs))
791 return;
792
3c37026d
RB		 793 if (!simulate_rdhwr(regs))
794 return;
795
1da177e4
LT		 796 force_sig(SIGILL, current);
797}
798
799asmlinkage void do_cpu(struct pt_regs *regs)
800{
801 unsigned int cpid;
802
803 die_if_kernel("do_cpu invoked from kernel context!", regs);
804
805 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
806
807 switch (cpid) {
808 case 0:
3c37026d
RB		 809 if (!cpu_has_llsc)
810 if (!simulate_llsc(regs))
811 return;
1da177e4 812
3c37026d 813 if (!simulate_rdhwr(regs))
1da177e4 814 return;
3c37026d 815
1da177e4
LT		 816 break;
817
818 case 1:
819 preempt_disable();
820
821 own_fpu();
822 if (used_math()) { /* Using the FPU again. */
823 restore_fp(current);
824 } else { /* First time FPU user. */
825 init_fpu();
826 set_used_math();
827 }
828
cd21dfcf
RB		 829 preempt_enable();
830
1da177e4 831 if (!cpu_has_fpu) {
12616ed2 832 int sig = fpu_emulator_cop1Handler(regs,
eae89076 833 &current->thread.fpu);
1da177e4
LT		 834 if (sig)
835 force_sig(sig, current);
f088fc84
RB		 836#ifdef CONFIG_MIPS_MT_FPAFF
837 else {
838 /*
839 * MIPS MT processors may have fewer FPU contexts
840 * than CPU threads. If we've emulated more than
841 * some threshold number of instructions, force
842 * migration to a "CPU" that has FP support.
843 */
844 if(mt_fpemul_threshold > 0
845 && ((current->thread.emulated_fp++
846 > mt_fpemul_threshold))) {
847 /*
848 * If there's no FPU present, or if the
849 * application has already restricted
850 * the allowed set to exclude any CPUs
851 * with FPUs, we'll skip the procedure.
852 */
853 if (cpus_intersects(current->cpus_allowed,
854 mt_fpu_cpumask)) {
855 cpumask_t tmask;
856
857 cpus_and(tmask,
858 current->thread.user_cpus_allowed,
859 mt_fpu_cpumask);
860 set_cpus_allowed(current, tmask);
861 current->thread.mflags |= MF_FPUBOUND;
862 }
863 }
864 }
865#endif /* CONFIG_MIPS_MT_FPAFF */
1da177e4
LT		 866 }
867
1da177e4
LT		 868 return;
869
870 case 2:
871 case 3:
41c594ab 872 die_if_kernel("do_cpu invoked from kernel context!", regs);
1da177e4
LT		 873 break;
874 }
875
876 force_sig(SIGILL, current);
877}
878
879asmlinkage void do_mdmx(struct pt_regs *regs)
880{
881 force_sig(SIGILL, current);
882}
883
884asmlinkage void do_watch(struct pt_regs *regs)
885{
886 /*
887 * We use the watch exception where available to detect stack
888 * overflows.
889 */
890 dump_tlb_all();
891 show_regs(regs);
892 panic("Caught WATCH exception - probably caused by stack overflow.");
893}
894
895asmlinkage void do_mcheck(struct pt_regs *regs)
896{
cac4bcbc
RB		 897 const int field = 2 * sizeof(unsigned long);
898 int multi_match = regs->cp0_status & ST0_TS;
899
1da177e4 900 show_regs(regs);
cac4bcbc
RB		 901
902 if (multi_match) {
903 printk("Index : %0x\n", read_c0_index());
904 printk("Pagemask: %0x\n", read_c0_pagemask());
905 printk("EntryHi : %0*lx\n", field, read_c0_entryhi());
906 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
907 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
908 printk("\n");
909 dump_tlb_all();
910 }
911
912 show_code((unsigned int *) regs->cp0_epc);
913
1da177e4
LT		 914 /*
915 * Some chips may have other causes of machine check (e.g. SB1
916 * graduation timer)
917 */
918 panic("Caught Machine Check exception - %scaused by multiple "
919 "matching entries in the TLB.",
cac4bcbc 920 (multi_match) ? "" : "not ");
1da177e4
LT		 921}
922
340ee4b9
RB		 923asmlinkage void do_mt(struct pt_regs *regs)
924{
41c594ab
RB		 925 int subcode;
926
41c594ab
RB		 927 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
928 >> VPECONTROL_EXCPT_SHIFT;
929 switch (subcode) {
930 case 0:
e35a5e35 931 printk(KERN_DEBUG "Thread Underflow\n");
41c594ab
RB		 932 break;
933 case 1:
e35a5e35 934 printk(KERN_DEBUG "Thread Overflow\n");
41c594ab
RB		 935 break;
936 case 2:
e35a5e35 937 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
41c594ab
RB		 938 break;
939 case 3:
e35a5e35 940 printk(KERN_DEBUG "Gating Storage Exception\n");
41c594ab
RB		 941 break;
942 case 4:
e35a5e35 943 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
41c594ab
RB		 944 break;
945 case 5:
e35a5e35 946 printk(KERN_DEBUG "Gating Storage Schedulier Exception\n");
41c594ab
RB		 947 break;
948 default:
e35a5e35 949 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
41c594ab
RB		 950 subcode);
951 break;
952 }
340ee4b9
RB		 953 die_if_kernel("MIPS MT Thread exception in kernel", regs);
954
955 force_sig(SIGILL, current);
956}
957
958
e50c0a8f
RB		 959asmlinkage void do_dsp(struct pt_regs *regs)
960{
961 if (cpu_has_dsp)
962 panic("Unexpected DSP exception\n");
963
964 force_sig(SIGILL, current);
965}
966
1da177e4
LT		 967asmlinkage void do_reserved(struct pt_regs *regs)
968{
969 /*
970 * Game over - no way to handle this if it ever occurs. Most probably
971 * caused by a new unknown cpu type or after another deadly
972 * hard/software error.
973 */
974 show_regs(regs);
975 panic("Caught reserved exception %ld - should not happen.",
976 (regs->cp0_cause & 0x7f) >> 2);
977}
978
e01402b1
RB		 979asmlinkage void do_default_vi(struct pt_regs *regs)
980{
981 show_regs(regs);
982 panic("Caught unexpected vectored interrupt.");
983}
984
1da177e4
LT		 985/*
986 * Some MIPS CPUs can enable/disable for cache parity detection, but do
987 * it different ways.
988 */
989static inline void parity_protection_init(void)
990{
991 switch (current_cpu_data.cputype) {
992 case CPU_24K:
98a41de9 993 case CPU_34K:
1da177e4 994 case CPU_5KC:
14f18b7f
RB		 995 write_c0_ecc(0x80000000);
996 back_to_back_c0_hazard();
997 /* Set the PE bit (bit 31) in the c0_errctl register. */
998 printk(KERN_INFO "Cache parity protection %sabled\n",
999 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
1da177e4
LT		 1000 break;
1001 case CPU_20KC:
1002 case CPU_25KF:
1003 /* Clear the DE bit (bit 16) in the c0_status register. */
1004 printk(KERN_INFO "Enable cache parity protection for "
1005 "MIPS 20KC/25KF CPUs.\n");
1006 clear_c0_status(ST0_DE);
1007 break;
1008 default:
1009 break;
1010 }
1011}
1012
1013asmlinkage void cache_parity_error(void)
1014{
1015 const int field = 2 * sizeof(unsigned long);
1016 unsigned int reg_val;
1017
1018 /* For the moment, report the problem and hang. */
1019 printk("Cache error exception:\n");
1020 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1021 reg_val = read_c0_cacheerr();
1022 printk("c0_cacheerr == %08x\n", reg_val);
1023
1024 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1025 reg_val & (1<<30) ? "secondary" : "primary",
1026 reg_val & (1<<31) ? "data" : "insn");
1027 printk("Error bits: %s%s%s%s%s%s%s\n",
1028 reg_val & (1<<29) ? "ED " : "",
1029 reg_val & (1<<28) ? "ET " : "",
1030 reg_val & (1<<26) ? "EE " : "",
1031 reg_val & (1<<25) ? "EB " : "",
1032 reg_val & (1<<24) ? "EI " : "",
1033 reg_val & (1<<23) ? "E1 " : "",
1034 reg_val & (1<<22) ? "E0 " : "");
1035 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1036
ec917c2c 1037#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1da177e4
LT		 1038 if (reg_val & (1<<22))
1039 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
1040
1041 if (reg_val & (1<<23))
1042 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
1043#endif
1044
1045 panic("Can't handle the cache error!");
1046}
1047
1048/*
1049 * SDBBP EJTAG debug exception handler.
1050 * We skip the instruction and return to the next instruction.
1051 */
1052void ejtag_exception_handler(struct pt_regs *regs)
1053{
1054 const int field = 2 * sizeof(unsigned long);
1055 unsigned long depc, old_epc;
1056 unsigned int debug;
1057
70ae6126 1058 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1da177e4
LT		 1059 depc = read_c0_depc();
1060 debug = read_c0_debug();
70ae6126 1061 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
1da177e4
LT		 1062 if (debug & 0x80000000) {
1063 /*
1064 * In branch delay slot.
1065 * We cheat a little bit here and use EPC to calculate the
1066 * debug return address (DEPC). EPC is restored after the
1067 * calculation.
1068 */
1069 old_epc = regs->cp0_epc;
1070 regs->cp0_epc = depc;
1071 __compute_return_epc(regs);
1072 depc = regs->cp0_epc;
1073 regs->cp0_epc = old_epc;
1074 } else
1075 depc += 4;
1076 write_c0_depc(depc);
1077
1078#if 0
70ae6126 1079 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1da177e4
LT		 1080 write_c0_debug(debug | 0x100);
1081#endif
1082}
1083
1084/*
1085 * NMI exception handler.
1086 */
1087void nmi_exception_handler(struct pt_regs *regs)
1088{
41c594ab
RB		 1089#ifdef CONFIG_MIPS_MT_SMTC
1090 unsigned long dvpret = dvpe();
1091 bust_spinlocks(1);
1092 printk("NMI taken!!!!\n");
1093 mips_mt_regdump(dvpret);
1094#else
1095 bust_spinlocks(1);
1da177e4 1096 printk("NMI taken!!!!\n");
41c594ab 1097#endif /* CONFIG_MIPS_MT_SMTC */
1da177e4
LT		 1098 die("NMI", regs);
1099 while(1) ;
1100}
1101
e01402b1
RB		 1102#define VECTORSPACING 0x100 /* for EI/VI mode */
1103
1104unsigned long ebase;
1da177e4 1105unsigned long exception_handlers[32];
e01402b1 1106unsigned long vi_handlers[64];
1da177e4
LT		 1107
1108/*
1109 * As a side effect of the way this is implemented we're limited
1110 * to interrupt handlers in the address range from
1111 * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ...
1112 */
1113void *set_except_vector(int n, void *addr)
1114{
1115 unsigned long handler = (unsigned long) addr;
1116 unsigned long old_handler = exception_handlers[n];
1117
1118 exception_handlers[n] = handler;
1119 if (n == 0 && cpu_has_divec) {
e01402b1 1120 *(volatile u32 *)(ebase + 0x200) = 0x08000000 |
1da177e4 1121 (0x03ffffff & (handler >> 2));
e01402b1
RB		 1122 flush_icache_range(ebase + 0x200, ebase + 0x204);
1123 }
1124 return (void *)old_handler;
1125}
1126
f41ae0b2 1127#ifdef CONFIG_CPU_MIPSR2_SRS
e01402b1 1128/*
193dd2ce 1129 * MIPSR2 shadow register set allocation
e01402b1
RB		 1130 * FIXME: SMP...
1131 */
1132
193dd2ce
RB		 1133static struct shadow_registers {
1134 /*
1135 * Number of shadow register sets supported
1136 */
1137 unsigned long sr_supported;
1138 /*
1139 * Bitmap of allocated shadow registers
1140 */
1141 unsigned long sr_allocated;
e01402b1
RB		 1142} shadow_registers;
1143
bb12d612 1144static void mips_srs_init(void)
e01402b1 1145{
e01402b1 1146 shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
7acb783e
RB		 1147 printk(KERN_INFO "%d MIPSR2 register sets available\n",
1148 shadow_registers.sr_supported);
e01402b1 1149 shadow_registers.sr_allocated = 1; /* Set 0 used by kernel */
e01402b1
RB		 1150}
1151
1152int mips_srs_max(void)
1153{
1154 return shadow_registers.sr_supported;
1155}
1156
ff3eab2a 1157int mips_srs_alloc(void)
e01402b1
RB		 1158{
1159 struct shadow_registers *sr = &shadow_registers;
e01402b1
RB		 1160 int set;
1161
193dd2ce
RB		 1162again:
1163 set = find_first_zero_bit(&sr->sr_allocated, sr->sr_supported);
1164 if (set >= sr->sr_supported)
1165 return -1;
e01402b1 1166
193dd2ce
RB		 1167 if (test_and_set_bit(set, &sr->sr_allocated))
1168 goto again;
e01402b1 1169
193dd2ce 1170 return set;
e01402b1
RB		 1171}
1172
41c594ab 1173void mips_srs_free(int set)
e01402b1
RB		 1174{
1175 struct shadow_registers *sr = &shadow_registers;
e01402b1 1176
193dd2ce 1177 clear_bit(set, &sr->sr_allocated);
e01402b1
RB		 1178}
1179
b4d05cb9 1180static void *set_vi_srs_handler(int n, void *addr, int srs)
e01402b1
RB		 1181{
1182 unsigned long handler;
1183 unsigned long old_handler = vi_handlers[n];
1184 u32 *w;
1185 unsigned char *b;
1186
1187 if (!cpu_has_veic && !cpu_has_vint)
1188 BUG();
1189
1190 if (addr == NULL) {
1191 handler = (unsigned long) do_default_vi;
1192 srs = 0;
41c594ab 1193 } else
e01402b1
RB		 1194 handler = (unsigned long) addr;
1195 vi_handlers[n] = (unsigned long) addr;
1196
1197 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1198
1199 if (srs >= mips_srs_max())
1200 panic("Shadow register set %d not supported", srs);
1201
1202 if (cpu_has_veic) {
1203 if (board_bind_eic_interrupt)
1204 board_bind_eic_interrupt (n, srs);
41c594ab 1205 } else if (cpu_has_vint) {
e01402b1
RB		 1206 /* SRSMap is only defined if shadow sets are implemented */
1207 if (mips_srs_max() > 1)
1208 change_c0_srsmap (0xf << n*4, srs << n*4);
1209 }
1210
1211 if (srs == 0) {
1212 /*
1213 * If no shadow set is selected then use the default handler
1214 * that does normal register saving and a standard interrupt exit
1215 */
1216
1217 extern char except_vec_vi, except_vec_vi_lui;
1218 extern char except_vec_vi_ori, except_vec_vi_end;
41c594ab
RB		 1219#ifdef CONFIG_MIPS_MT_SMTC
1220 /*
1221 * We need to provide the SMTC vectored interrupt handler
1222 * not only with the address of the handler, but with the
1223 * Status.IM bit to be masked before going there.
1224 */
1225 extern char except_vec_vi_mori;
1226 const int mori_offset = &except_vec_vi_mori - &except_vec_vi;
1227#endif /* CONFIG_MIPS_MT_SMTC */
e01402b1
RB		 1228 const int handler_len = &except_vec_vi_end - &except_vec_vi;
1229 const int lui_offset = &except_vec_vi_lui - &except_vec_vi;
1230 const int ori_offset = &except_vec_vi_ori - &except_vec_vi;
1231
1232 if (handler_len > VECTORSPACING) {
1233 /*
1234 * Sigh... panicing won't help as the console
1235 * is probably not configured :(
1236 */
1237 panic ("VECTORSPACING too small");
1238 }
1239
1240 memcpy (b, &except_vec_vi, handler_len);
41c594ab
RB		 1241#ifdef CONFIG_MIPS_MT_SMTC
1242 if (n > 7)
1243 printk("Vector index %d exceeds SMTC maximum\n", n);
1244 w = (u32 *)(b + mori_offset);
1245 *w = (*w & 0xffff0000) | (0x100 << n);
1246#endif /* CONFIG_MIPS_MT_SMTC */
e01402b1
RB		 1247 w = (u32 *)(b + lui_offset);
1248 *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff);
1249 w = (u32 *)(b + ori_offset);
1250 *w = (*w & 0xffff0000) | ((u32)handler & 0xffff);
1251 flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len));
1252 }
1253 else {
1254 /*
1255 * In other cases jump directly to the interrupt handler
1256 *
1257 * It is the handlers responsibility to save registers if required
1258 * (eg hi/lo) and return from the exception using "eret"
1259 */
1260 w = (u32 *)b;
1261 *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */
1262 *w = 0;
1263 flush_icache_range((unsigned long)b, (unsigned long)(b+8));
1da177e4 1264 }
e01402b1 1265
1da177e4
LT		 1266 return (void *)old_handler;
1267}
1268
41c594ab 1269void *set_vi_handler(int n, void *addr)
e01402b1 1270{
ff3eab2a 1271 return set_vi_srs_handler(n, addr, 0);
e01402b1 1272}
f41ae0b2
RB		 1273
1274#else
1275
1276static inline void mips_srs_init(void)
1277{
1278}
1279
1280#endif /* CONFIG_CPU_MIPSR2_SRS */
e01402b1 1281
1da177e4
LT		 1282/*
1283 * This is used by native signal handling
1284 */
1285asmlinkage int (*save_fp_context)(struct sigcontext *sc);
1286asmlinkage int (*restore_fp_context)(struct sigcontext *sc);
1287
1288extern asmlinkage int _save_fp_context(struct sigcontext *sc);
1289extern asmlinkage int _restore_fp_context(struct sigcontext *sc);
1290
1291extern asmlinkage int fpu_emulator_save_context(struct sigcontext *sc);
1292extern asmlinkage int fpu_emulator_restore_context(struct sigcontext *sc);
1293
41c594ab
RB		 1294#ifdef CONFIG_SMP
1295static int smp_save_fp_context(struct sigcontext *sc)
1296{
1297 return cpu_has_fpu
1298 ? _save_fp_context(sc)
1299 : fpu_emulator_save_context(sc);
1300}
1301
1302static int smp_restore_fp_context(struct sigcontext *sc)
1303{
1304 return cpu_has_fpu
1305 ? _restore_fp_context(sc)
1306 : fpu_emulator_restore_context(sc);
1307}
1308#endif
1309
1da177e4
LT		 1310static inline void signal_init(void)
1311{
41c594ab
RB		 1312#ifdef CONFIG_SMP
1313 /* For now just do the cpu_has_fpu check when the functions are invoked */
1314 save_fp_context = smp_save_fp_context;
1315 restore_fp_context = smp_restore_fp_context;
1316#else
1da177e4
LT		 1317 if (cpu_has_fpu) {
1318 save_fp_context = _save_fp_context;
1319 restore_fp_context = _restore_fp_context;
1320 } else {
1321 save_fp_context = fpu_emulator_save_context;
1322 restore_fp_context = fpu_emulator_restore_context;
1323 }
41c594ab 1324#endif
1da177e4
LT		 1325}
1326
1327#ifdef CONFIG_MIPS32_COMPAT
1328
1329/*
1330 * This is used by 32-bit signal stuff on the 64-bit kernel
1331 */
1332asmlinkage int (*save_fp_context32)(struct sigcontext32 *sc);
1333asmlinkage int (*restore_fp_context32)(struct sigcontext32 *sc);
1334
1335extern asmlinkage int _save_fp_context32(struct sigcontext32 *sc);
1336extern asmlinkage int _restore_fp_context32(struct sigcontext32 *sc);
1337
1338extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 *sc);
1339extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 *sc);
1340
1341static inline void signal32_init(void)
1342{
1343 if (cpu_has_fpu) {
1344 save_fp_context32 = _save_fp_context32;
1345 restore_fp_context32 = _restore_fp_context32;
1346 } else {
1347 save_fp_context32 = fpu_emulator_save_context32;
1348 restore_fp_context32 = fpu_emulator_restore_context32;
1349 }
1350}
1351#endif
1352
1353extern void cpu_cache_init(void);
1354extern void tlb_init(void);
1d40cfcd 1355extern void flush_tlb_handlers(void);
1da177e4
LT		 1356
1357void __init per_cpu_trap_init(void)
1358{
1359 unsigned int cpu = smp_processor_id();
1360 unsigned int status_set = ST0_CU0;
41c594ab
RB		 1361#ifdef CONFIG_MIPS_MT_SMTC
1362 int secondaryTC = 0;
1363 int bootTC = (cpu == 0);
1364
1365 /*
1366 * Only do per_cpu_trap_init() for first TC of Each VPE.
1367 * Note that this hack assumes that the SMTC init code
1368 * assigns TCs consecutively and in ascending order.
1369 */
1370
1371 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) &&
1372 ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id))
1373 secondaryTC = 1;
1374#endif /* CONFIG_MIPS_MT_SMTC */
1da177e4
LT		 1375
1376 /*
1377 * Disable coprocessors and select 32-bit or 64-bit addressing
1378 * and the 16/32 or 32/32 FPR register model. Reset the BEV
1379 * flag that some firmware may have left set and the TS bit (for
1380 * IP27). Set XX for ISA IV code to work.
1381 */
875d43e7 1382#ifdef CONFIG_64BIT
1da177e4
LT		 1383 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
1384#endif
1385 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
1386 status_set |= ST0_XX;
b38c7399 1387 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
1da177e4
LT		 1388 status_set);
1389
e50c0a8f
RB		 1390 if (cpu_has_dsp)
1391 set_c0_status(ST0_MX);
1392
e01402b1
RB		 1393#ifdef CONFIG_CPU_MIPSR2
1394 write_c0_hwrena (0x0000000f); /* Allow rdhwr to all registers */
1395#endif
1396
41c594ab
RB		 1397#ifdef CONFIG_MIPS_MT_SMTC
1398 if (!secondaryTC) {
1399#endif /* CONFIG_MIPS_MT_SMTC */
1400
1da177e4 1401 /*
e01402b1 1402 * Interrupt handling.
1da177e4 1403 */
e01402b1
RB		 1404 if (cpu_has_veic || cpu_has_vint) {
1405 write_c0_ebase (ebase);
1406 /* Setting vector spacing enables EI/VI mode */
1407 change_c0_intctl (0x3e0, VECTORSPACING);
1408 }
d03d0a57
RB		 1409 if (cpu_has_divec) {
1410 if (cpu_has_mipsmt) {
1411 unsigned int vpflags = dvpe();
1412 set_c0_cause(CAUSEF_IV);
1413 evpe(vpflags);
1414 } else
1415 set_c0_cause(CAUSEF_IV);
1416 }
41c594ab
RB		 1417#ifdef CONFIG_MIPS_MT_SMTC
1418 }
1419#endif /* CONFIG_MIPS_MT_SMTC */
1da177e4
LT		 1420
1421 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
1422 TLBMISS_HANDLER_SETUP();
1423
1424 atomic_inc(&init_mm.mm_count);
1425 current->active_mm = &init_mm;
1426 BUG_ON(current->mm);
1427 enter_lazy_tlb(&init_mm, current);
1428
41c594ab
RB		 1429#ifdef CONFIG_MIPS_MT_SMTC
1430 if (bootTC) {
1431#endif /* CONFIG_MIPS_MT_SMTC */
1432 cpu_cache_init();
1433 tlb_init();
1434#ifdef CONFIG_MIPS_MT_SMTC
1435 }
1436#endif /* CONFIG_MIPS_MT_SMTC */
1da177e4
LT		 1437}
1438
e01402b1
RB		 1439/* Install CPU exception handler */
1440void __init set_handler (unsigned long offset, void *addr, unsigned long size)
1441{
1442 memcpy((void *)(ebase + offset), addr, size);
1443 flush_icache_range(ebase + offset, ebase + offset + size);
1444}
1445
1446/* Install uncached CPU exception handler */
1447void __init set_uncached_handler (unsigned long offset, void *addr, unsigned long size)
1448{
1449#ifdef CONFIG_32BIT
1450 unsigned long uncached_ebase = KSEG1ADDR(ebase);
1451#endif
1452#ifdef CONFIG_64BIT
1453 unsigned long uncached_ebase = TO_UNCAC(ebase);
1454#endif
1455
1456 memcpy((void *)(uncached_ebase + offset), addr, size);
1457}
1458
1da177e4
LT		 1459void __init trap_init(void)
1460{
1461 extern char except_vec3_generic, except_vec3_r4000;
1da177e4
LT		 1462 extern char except_vec4;
1463 unsigned long i;
1464
e01402b1
RB		 1465 if (cpu_has_veic || cpu_has_vint)
1466 ebase = (unsigned long) alloc_bootmem_low_pages (0x200 + VECTORSPACING*64);
1467 else
1468 ebase = CAC_BASE;
1469
e01402b1 1470 mips_srs_init();
e01402b1 1471
1da177e4
LT		 1472 per_cpu_trap_init();
1473
1474 /*
1475 * Copy the generic exception handlers to their final destination.
1476 * This will be overriden later as suitable for a particular
1477 * configuration.
1478 */
e01402b1 1479 set_handler(0x180, &except_vec3_generic, 0x80);
1da177e4
LT		 1480
1481 /*
1482 * Setup default vectors
1483 */
1484 for (i = 0; i <= 31; i++)
1485 set_except_vector(i, handle_reserved);
1486
1487 /*
1488 * Copy the EJTAG debug exception vector handler code to it's final
1489 * destination.
1490 */
e01402b1
RB		 1491 if (cpu_has_ejtag && board_ejtag_handler_setup)
1492 board_ejtag_handler_setup ();
1da177e4
LT		 1493
1494 /*
1495 * Only some CPUs have the watch exceptions.
1496 */
1497 if (cpu_has_watch)
1498 set_except_vector(23, handle_watch);
1499
1500 /*
e01402b1 1501 * Initialise interrupt handlers
1da177e4 1502 */
e01402b1
RB		 1503 if (cpu_has_veic || cpu_has_vint) {
1504 int nvec = cpu_has_veic ? 64 : 8;
1505 for (i = 0; i < nvec; i++)
ff3eab2a 1506 set_vi_handler(i, NULL);
e01402b1
RB		 1507 }
1508 else if (cpu_has_divec)
1509 set_handler(0x200, &except_vec4, 0x8);
1da177e4
LT		 1510
1511 /*
1512 * Some CPUs can enable/disable for cache parity detection, but does
1513 * it different ways.
1514 */
1515 parity_protection_init();
1516
1517 /*
1518 * The Data Bus Errors / Instruction Bus Errors are signaled
1519 * by external hardware. Therefore these two exceptions
1520 * may have board specific handlers.
1521 */
1522 if (board_be_init)
1523 board_be_init();
1524
e4ac58af 1525 set_except_vector(0, handle_int);
1da177e4
LT		 1526 set_except_vector(1, handle_tlbm);
1527 set_except_vector(2, handle_tlbl);
1528 set_except_vector(3, handle_tlbs);
1529
1530 set_except_vector(4, handle_adel);
1531 set_except_vector(5, handle_ades);
1532
1533 set_except_vector(6, handle_ibe);
1534 set_except_vector(7, handle_dbe);
1535
1536 set_except_vector(8, handle_sys);
1537 set_except_vector(9, handle_bp);
1538 set_except_vector(10, handle_ri);
1539 set_except_vector(11, handle_cpu);
1540 set_except_vector(12, handle_ov);
1541 set_except_vector(13, handle_tr);
1da177e4
LT		 1542
1543 if (current_cpu_data.cputype == CPU_R6000 ||
1544 current_cpu_data.cputype == CPU_R6000A) {
1545 /*
1546 * The R6000 is the only R-series CPU that features a machine
1547 * check exception (similar to the R4000 cache error) and
1548 * unaligned ldc1/sdc1 exception. The handlers have not been
1549 * written yet. Well, anyway there is no R6000 machine on the
1550 * current list of targets for Linux/MIPS.
1551 * (Duh, crap, there is someone with a triple R6k machine)
1552 */
1553 //set_except_vector(14, handle_mc);
1554 //set_except_vector(15, handle_ndc);
1555 }
1556
e01402b1
RB		 1557
1558 if (board_nmi_handler_setup)
1559 board_nmi_handler_setup();
1560
e50c0a8f
RB		 1561 if (cpu_has_fpu && !cpu_has_nofpuex)
1562 set_except_vector(15, handle_fpe);
1563
1564 set_except_vector(22, handle_mdmx);
1565
1566 if (cpu_has_mcheck)
1567 set_except_vector(24, handle_mcheck);
1568
340ee4b9
RB		 1569 if (cpu_has_mipsmt)
1570 set_except_vector(25, handle_mt);
1571
e50c0a8f
RB		 1572 if (cpu_has_dsp)
1573 set_except_vector(26, handle_dsp);
1574
1575 if (cpu_has_vce)
1576 /* Special exception: R4[04]00 uses also the divec space. */
1577 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100);
1578 else if (cpu_has_4kex)
1579 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80);
1580 else
1581 memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80);
1582
1da177e4
LT		 1583 signal_init();
1584#ifdef CONFIG_MIPS32_COMPAT
1585 signal32_init();
1586#endif
1587
e01402b1 1588 flush_icache_range(ebase, ebase + 0x400);
1d40cfcd 1589 flush_tlb_handlers();
1da177e4 1590}
Linux 6.x block layer and io_uring tree(s)