Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
36ccf1c0 | 6 | * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle |
1da177e4 LT |
7 | * Copyright (C) 1995, 1996 Paul M. Antoine |
8 | * Copyright (C) 1998 Ulf Carlsson | |
9 | * Copyright (C) 1999 Silicon Graphics, Inc. | |
10 | * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com | |
11 | * Copyright (C) 2000, 01 MIPS Technologies, Inc. | |
60b0d655 | 12 | * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki |
1da177e4 | 13 | */ |
8e8a52ed | 14 | #include <linux/bug.h> |
60b0d655 | 15 | #include <linux/compiler.h> |
1da177e4 LT |
16 | #include <linux/init.h> |
17 | #include <linux/mm.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/sched.h> | |
20 | #include <linux/smp.h> | |
1da177e4 LT |
21 | #include <linux/spinlock.h> |
22 | #include <linux/kallsyms.h> | |
e01402b1 | 23 | #include <linux/bootmem.h> |
d4fd1989 | 24 | #include <linux/interrupt.h> |
39b8d525 | 25 | #include <linux/ptrace.h> |
1da177e4 LT |
26 | |
27 | #include <asm/bootinfo.h> | |
28 | #include <asm/branch.h> | |
29 | #include <asm/break.h> | |
30 | #include <asm/cpu.h> | |
e50c0a8f | 31 | #include <asm/dsp.h> |
1da177e4 | 32 | #include <asm/fpu.h> |
340ee4b9 RB |
33 | #include <asm/mipsregs.h> |
34 | #include <asm/mipsmtregs.h> | |
1da177e4 LT |
35 | #include <asm/module.h> |
36 | #include <asm/pgtable.h> | |
37 | #include <asm/ptrace.h> | |
38 | #include <asm/sections.h> | |
39 | #include <asm/system.h> | |
40 | #include <asm/tlbdebug.h> | |
41 | #include <asm/traps.h> | |
42 | #include <asm/uaccess.h> | |
43 | #include <asm/mmu_context.h> | |
1da177e4 | 44 | #include <asm/types.h> |
1df0f0ff | 45 | #include <asm/stacktrace.h> |
1da177e4 | 46 | |
e4ac58af | 47 | extern asmlinkage void handle_int(void); |
1da177e4 LT |
48 | extern asmlinkage void handle_tlbm(void); |
49 | extern asmlinkage void handle_tlbl(void); | |
50 | extern asmlinkage void handle_tlbs(void); | |
51 | extern asmlinkage void handle_adel(void); | |
52 | extern asmlinkage void handle_ades(void); | |
53 | extern asmlinkage void handle_ibe(void); | |
54 | extern asmlinkage void handle_dbe(void); | |
55 | extern asmlinkage void handle_sys(void); | |
56 | extern asmlinkage void handle_bp(void); | |
57 | extern asmlinkage void handle_ri(void); | |
5b10496b AN |
58 | extern asmlinkage void handle_ri_rdhwr_vivt(void); |
59 | extern asmlinkage void handle_ri_rdhwr(void); | |
1da177e4 LT |
60 | extern asmlinkage void handle_cpu(void); |
61 | extern asmlinkage void handle_ov(void); | |
62 | extern asmlinkage void handle_tr(void); | |
63 | extern asmlinkage void handle_fpe(void); | |
64 | extern asmlinkage void handle_mdmx(void); | |
65 | extern asmlinkage void handle_watch(void); | |
340ee4b9 | 66 | extern asmlinkage void handle_mt(void); |
e50c0a8f | 67 | extern asmlinkage void handle_dsp(void); |
1da177e4 LT |
68 | extern asmlinkage void handle_mcheck(void); |
69 | extern asmlinkage void handle_reserved(void); | |
70 | ||
12616ed2 | 71 | extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, |
e04582b7 | 72 | struct mips_fpu_struct *ctx, int has_fpu); |
1da177e4 LT |
73 | |
74 | void (*board_be_init)(void); | |
75 | int (*board_be_handler)(struct pt_regs *regs, int is_fixup); | |
e01402b1 RB |
76 | void (*board_nmi_handler_setup)(void); |
77 | void (*board_ejtag_handler_setup)(void); | |
78 | void (*board_bind_eic_interrupt)(int irq, int regset); | |
1da177e4 | 79 | |
1da177e4 | 80 | |
4d157d5e | 81 | static void show_raw_backtrace(unsigned long reg29) |
e889d78f | 82 | { |
39b8d525 | 83 | unsigned long *sp = (unsigned long *)(reg29 & ~3); |
e889d78f AN |
84 | unsigned long addr; |
85 | ||
86 | printk("Call Trace:"); | |
87 | #ifdef CONFIG_KALLSYMS | |
88 | printk("\n"); | |
89 | #endif | |
10220c88 TB |
90 | while (!kstack_end(sp)) { |
91 | unsigned long __user *p = | |
92 | (unsigned long __user *)(unsigned long)sp++; | |
93 | if (__get_user(addr, p)) { | |
94 | printk(" (Bad stack address)"); | |
95 | break; | |
39b8d525 | 96 | } |
10220c88 TB |
97 | if (__kernel_text_address(addr)) |
98 | print_ip_sym(addr); | |
e889d78f | 99 | } |
10220c88 | 100 | printk("\n"); |
e889d78f AN |
101 | } |
102 | ||
f66686f7 | 103 | #ifdef CONFIG_KALLSYMS |
1df0f0ff | 104 | int raw_show_trace; |
f66686f7 AN |
105 | static int __init set_raw_show_trace(char *str) |
106 | { | |
107 | raw_show_trace = 1; | |
108 | return 1; | |
109 | } | |
110 | __setup("raw_show_trace", set_raw_show_trace); | |
1df0f0ff | 111 | #endif |
4d157d5e | 112 | |
eae23f2c | 113 | static void show_backtrace(struct task_struct *task, const struct pt_regs *regs) |
f66686f7 | 114 | { |
4d157d5e FBH |
115 | unsigned long sp = regs->regs[29]; |
116 | unsigned long ra = regs->regs[31]; | |
f66686f7 | 117 | unsigned long pc = regs->cp0_epc; |
f66686f7 AN |
118 | |
119 | if (raw_show_trace || !__kernel_text_address(pc)) { | |
87151ae3 | 120 | show_raw_backtrace(sp); |
f66686f7 AN |
121 | return; |
122 | } | |
123 | printk("Call Trace:\n"); | |
4d157d5e | 124 | do { |
87151ae3 | 125 | print_ip_sym(pc); |
1924600c | 126 | pc = unwind_stack(task, &sp, pc, &ra); |
4d157d5e | 127 | } while (pc); |
f66686f7 AN |
128 | printk("\n"); |
129 | } | |
f66686f7 | 130 | |
1da177e4 LT |
131 | /* |
132 | * This routine abuses get_user()/put_user() to reference pointers | |
133 | * with at least a bit of error checking ... | |
134 | */ | |
eae23f2c RB |
135 | static void show_stacktrace(struct task_struct *task, |
136 | const struct pt_regs *regs) | |
1da177e4 LT |
137 | { |
138 | const int field = 2 * sizeof(unsigned long); | |
139 | long stackdata; | |
140 | int i; | |
5e0373b8 | 141 | unsigned long __user *sp = (unsigned long __user *)regs->regs[29]; |
1da177e4 LT |
142 | |
143 | printk("Stack :"); | |
144 | i = 0; | |
145 | while ((unsigned long) sp & (PAGE_SIZE - 1)) { | |
146 | if (i && ((i % (64 / field)) == 0)) | |
147 | printk("\n "); | |
148 | if (i > 39) { | |
149 | printk(" ..."); | |
150 | break; | |
151 | } | |
152 | ||
153 | if (__get_user(stackdata, sp++)) { | |
154 | printk(" (Bad stack address)"); | |
155 | break; | |
156 | } | |
157 | ||
158 | printk(" %0*lx", field, stackdata); | |
159 | i++; | |
160 | } | |
161 | printk("\n"); | |
87151ae3 | 162 | show_backtrace(task, regs); |
f66686f7 AN |
163 | } |
164 | ||
f66686f7 AN |
165 | void show_stack(struct task_struct *task, unsigned long *sp) |
166 | { | |
167 | struct pt_regs regs; | |
168 | if (sp) { | |
169 | regs.regs[29] = (unsigned long)sp; | |
170 | regs.regs[31] = 0; | |
171 | regs.cp0_epc = 0; | |
172 | } else { | |
173 | if (task && task != current) { | |
174 | regs.regs[29] = task->thread.reg29; | |
175 | regs.regs[31] = 0; | |
176 | regs.cp0_epc = task->thread.reg31; | |
177 | } else { | |
178 | prepare_frametrace(®s); | |
179 | } | |
180 | } | |
181 | show_stacktrace(task, ®s); | |
1da177e4 LT |
182 | } |
183 | ||
184 | /* | |
185 | * The architecture-independent dump_stack generator | |
186 | */ | |
187 | void dump_stack(void) | |
188 | { | |
1666a6fc | 189 | struct pt_regs regs; |
1da177e4 | 190 | |
1666a6fc FBH |
191 | prepare_frametrace(®s); |
192 | show_backtrace(current, ®s); | |
1da177e4 LT |
193 | } |
194 | ||
195 | EXPORT_SYMBOL(dump_stack); | |
196 | ||
e1bb8289 | 197 | static void show_code(unsigned int __user *pc) |
1da177e4 LT |
198 | { |
199 | long i; | |
39b8d525 | 200 | unsigned short __user *pc16 = NULL; |
1da177e4 LT |
201 | |
202 | printk("\nCode:"); | |
203 | ||
39b8d525 RB |
204 | if ((unsigned long)pc & 1) |
205 | pc16 = (unsigned short __user *)((unsigned long)pc & ~1); | |
1da177e4 LT |
206 | for(i = -3 ; i < 6 ; i++) { |
207 | unsigned int insn; | |
39b8d525 | 208 | if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) { |
1da177e4 LT |
209 | printk(" (Bad address in epc)\n"); |
210 | break; | |
211 | } | |
39b8d525 | 212 | printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>')); |
1da177e4 LT |
213 | } |
214 | } | |
215 | ||
eae23f2c | 216 | static void __show_regs(const struct pt_regs *regs) |
1da177e4 LT |
217 | { |
218 | const int field = 2 * sizeof(unsigned long); | |
219 | unsigned int cause = regs->cp0_cause; | |
220 | int i; | |
221 | ||
222 | printk("Cpu %d\n", smp_processor_id()); | |
223 | ||
224 | /* | |
225 | * Saved main processor registers | |
226 | */ | |
227 | for (i = 0; i < 32; ) { | |
228 | if ((i % 4) == 0) | |
229 | printk("$%2d :", i); | |
230 | if (i == 0) | |
231 | printk(" %0*lx", field, 0UL); | |
232 | else if (i == 26 || i == 27) | |
233 | printk(" %*s", field, ""); | |
234 | else | |
235 | printk(" %0*lx", field, regs->regs[i]); | |
236 | ||
237 | i++; | |
238 | if ((i % 4) == 0) | |
239 | printk("\n"); | |
240 | } | |
241 | ||
9693a853 FBH |
242 | #ifdef CONFIG_CPU_HAS_SMARTMIPS |
243 | printk("Acx : %0*lx\n", field, regs->acx); | |
244 | #endif | |
1da177e4 LT |
245 | printk("Hi : %0*lx\n", field, regs->hi); |
246 | printk("Lo : %0*lx\n", field, regs->lo); | |
247 | ||
248 | /* | |
249 | * Saved cp0 registers | |
250 | */ | |
b012cffe RB |
251 | printk("epc : %0*lx %pS\n", field, regs->cp0_epc, |
252 | (void *) regs->cp0_epc); | |
1da177e4 | 253 | printk(" %s\n", print_tainted()); |
b012cffe RB |
254 | printk("ra : %0*lx %pS\n", field, regs->regs[31], |
255 | (void *) regs->regs[31]); | |
1da177e4 LT |
256 | |
257 | printk("Status: %08x ", (uint32_t) regs->cp0_status); | |
258 | ||
3b2396d9 MR |
259 | if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) { |
260 | if (regs->cp0_status & ST0_KUO) | |
261 | printk("KUo "); | |
262 | if (regs->cp0_status & ST0_IEO) | |
263 | printk("IEo "); | |
264 | if (regs->cp0_status & ST0_KUP) | |
265 | printk("KUp "); | |
266 | if (regs->cp0_status & ST0_IEP) | |
267 | printk("IEp "); | |
268 | if (regs->cp0_status & ST0_KUC) | |
269 | printk("KUc "); | |
270 | if (regs->cp0_status & ST0_IEC) | |
271 | printk("IEc "); | |
272 | } else { | |
273 | if (regs->cp0_status & ST0_KX) | |
274 | printk("KX "); | |
275 | if (regs->cp0_status & ST0_SX) | |
276 | printk("SX "); | |
277 | if (regs->cp0_status & ST0_UX) | |
278 | printk("UX "); | |
279 | switch (regs->cp0_status & ST0_KSU) { | |
280 | case KSU_USER: | |
281 | printk("USER "); | |
282 | break; | |
283 | case KSU_SUPERVISOR: | |
284 | printk("SUPERVISOR "); | |
285 | break; | |
286 | case KSU_KERNEL: | |
287 | printk("KERNEL "); | |
288 | break; | |
289 | default: | |
290 | printk("BAD_MODE "); | |
291 | break; | |
292 | } | |
293 | if (regs->cp0_status & ST0_ERL) | |
294 | printk("ERL "); | |
295 | if (regs->cp0_status & ST0_EXL) | |
296 | printk("EXL "); | |
297 | if (regs->cp0_status & ST0_IE) | |
298 | printk("IE "); | |
1da177e4 | 299 | } |
1da177e4 LT |
300 | printk("\n"); |
301 | ||
302 | printk("Cause : %08x\n", cause); | |
303 | ||
304 | cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; | |
305 | if (1 <= cause && cause <= 5) | |
306 | printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr); | |
307 | ||
9966db25 RB |
308 | printk("PrId : %08x (%s)\n", read_c0_prid(), |
309 | cpu_name_string()); | |
1da177e4 LT |
310 | } |
311 | ||
eae23f2c RB |
312 | /* |
313 | * FIXME: really the generic show_regs should take a const pointer argument. | |
314 | */ | |
315 | void show_regs(struct pt_regs *regs) | |
316 | { | |
317 | __show_regs((struct pt_regs *)regs); | |
318 | } | |
319 | ||
320 | void show_registers(const struct pt_regs *regs) | |
1da177e4 | 321 | { |
39b8d525 RB |
322 | const int field = 2 * sizeof(unsigned long); |
323 | ||
eae23f2c | 324 | __show_regs(regs); |
1da177e4 | 325 | print_modules(); |
39b8d525 RB |
326 | printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n", |
327 | current->comm, current->pid, current_thread_info(), current, | |
328 | field, current_thread_info()->tp_value); | |
329 | if (cpu_has_userlocal) { | |
330 | unsigned long tls; | |
331 | ||
332 | tls = read_c0_userlocal(); | |
333 | if (tls != current_thread_info()->tp_value) | |
334 | printk("*HwTLS: %0*lx\n", field, tls); | |
335 | } | |
336 | ||
f66686f7 | 337 | show_stacktrace(current, regs); |
e1bb8289 | 338 | show_code((unsigned int __user *) regs->cp0_epc); |
1da177e4 LT |
339 | printk("\n"); |
340 | } | |
341 | ||
342 | static DEFINE_SPINLOCK(die_lock); | |
343 | ||
eae23f2c | 344 | void __noreturn die(const char * str, const struct pt_regs * regs) |
1da177e4 LT |
345 | { |
346 | static int die_counter; | |
41c594ab RB |
347 | #ifdef CONFIG_MIPS_MT_SMTC |
348 | unsigned long dvpret = dvpe(); | |
349 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 LT |
350 | |
351 | console_verbose(); | |
352 | spin_lock_irq(&die_lock); | |
41c594ab RB |
353 | bust_spinlocks(1); |
354 | #ifdef CONFIG_MIPS_MT_SMTC | |
355 | mips_mt_regdump(dvpret); | |
356 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
178086c8 | 357 | printk("%s[#%d]:\n", str, ++die_counter); |
1da177e4 | 358 | show_registers(regs); |
bcdcd8e7 | 359 | add_taint(TAINT_DIE); |
1da177e4 | 360 | spin_unlock_irq(&die_lock); |
d4fd1989 MB |
361 | |
362 | if (in_interrupt()) | |
363 | panic("Fatal exception in interrupt"); | |
364 | ||
365 | if (panic_on_oops) { | |
366 | printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n"); | |
367 | ssleep(5); | |
368 | panic("Fatal exception"); | |
369 | } | |
370 | ||
1da177e4 LT |
371 | do_exit(SIGSEGV); |
372 | } | |
373 | ||
1da177e4 LT |
374 | extern const struct exception_table_entry __start___dbe_table[]; |
375 | extern const struct exception_table_entry __stop___dbe_table[]; | |
376 | ||
b6dcec9b RB |
377 | __asm__( |
378 | " .section __dbe_table, \"a\"\n" | |
379 | " .previous \n"); | |
1da177e4 LT |
380 | |
381 | /* Given an address, look for it in the exception tables. */ | |
382 | static const struct exception_table_entry *search_dbe_tables(unsigned long addr) | |
383 | { | |
384 | const struct exception_table_entry *e; | |
385 | ||
386 | e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr); | |
387 | if (!e) | |
388 | e = search_module_dbetables(addr); | |
389 | return e; | |
390 | } | |
391 | ||
392 | asmlinkage void do_be(struct pt_regs *regs) | |
393 | { | |
394 | const int field = 2 * sizeof(unsigned long); | |
395 | const struct exception_table_entry *fixup = NULL; | |
396 | int data = regs->cp0_cause & 4; | |
397 | int action = MIPS_BE_FATAL; | |
398 | ||
399 | /* XXX For now. Fixme, this searches the wrong table ... */ | |
400 | if (data && !user_mode(regs)) | |
401 | fixup = search_dbe_tables(exception_epc(regs)); | |
402 | ||
403 | if (fixup) | |
404 | action = MIPS_BE_FIXUP; | |
405 | ||
406 | if (board_be_handler) | |
28fc582c | 407 | action = board_be_handler(regs, fixup != NULL); |
1da177e4 LT |
408 | |
409 | switch (action) { | |
410 | case MIPS_BE_DISCARD: | |
411 | return; | |
412 | case MIPS_BE_FIXUP: | |
413 | if (fixup) { | |
414 | regs->cp0_epc = fixup->nextinsn; | |
415 | return; | |
416 | } | |
417 | break; | |
418 | default: | |
419 | break; | |
420 | } | |
421 | ||
422 | /* | |
423 | * Assume it would be too dangerous to continue ... | |
424 | */ | |
425 | printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", | |
426 | data ? "Data" : "Instruction", | |
427 | field, regs->cp0_epc, field, regs->regs[31]); | |
428 | die_if_kernel("Oops", regs); | |
429 | force_sig(SIGBUS, current); | |
430 | } | |
431 | ||
1da177e4 | 432 | /* |
60b0d655 | 433 | * ll/sc, rdhwr, sync emulation |
1da177e4 LT |
434 | */ |
435 | ||
436 | #define OPCODE 0xfc000000 | |
437 | #define BASE 0x03e00000 | |
438 | #define RT 0x001f0000 | |
439 | #define OFFSET 0x0000ffff | |
440 | #define LL 0xc0000000 | |
441 | #define SC 0xe0000000 | |
60b0d655 | 442 | #define SPEC0 0x00000000 |
3c37026d RB |
443 | #define SPEC3 0x7c000000 |
444 | #define RD 0x0000f800 | |
445 | #define FUNC 0x0000003f | |
60b0d655 | 446 | #define SYNC 0x0000000f |
3c37026d | 447 | #define RDHWR 0x0000003b |
1da177e4 LT |
448 | |
449 | /* | |
450 | * The ll_bit is cleared by r*_switch.S | |
451 | */ | |
452 | ||
453 | unsigned long ll_bit; | |
454 | ||
455 | static struct task_struct *ll_task = NULL; | |
456 | ||
60b0d655 | 457 | static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode) |
1da177e4 | 458 | { |
fe00f943 | 459 | unsigned long value, __user *vaddr; |
1da177e4 | 460 | long offset; |
1da177e4 LT |
461 | |
462 | /* | |
463 | * analyse the ll instruction that just caused a ri exception | |
464 | * and put the referenced address to addr. | |
465 | */ | |
466 | ||
467 | /* sign extend offset */ | |
468 | offset = opcode & OFFSET; | |
469 | offset <<= 16; | |
470 | offset >>= 16; | |
471 | ||
fe00f943 RB |
472 | vaddr = (unsigned long __user *) |
473 | ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); | |
1da177e4 | 474 | |
60b0d655 MR |
475 | if ((unsigned long)vaddr & 3) |
476 | return SIGBUS; | |
477 | if (get_user(value, vaddr)) | |
478 | return SIGSEGV; | |
1da177e4 LT |
479 | |
480 | preempt_disable(); | |
481 | ||
482 | if (ll_task == NULL || ll_task == current) { | |
483 | ll_bit = 1; | |
484 | } else { | |
485 | ll_bit = 0; | |
486 | } | |
487 | ll_task = current; | |
488 | ||
489 | preempt_enable(); | |
490 | ||
491 | regs->regs[(opcode & RT) >> 16] = value; | |
492 | ||
60b0d655 | 493 | return 0; |
1da177e4 LT |
494 | } |
495 | ||
60b0d655 | 496 | static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode) |
1da177e4 | 497 | { |
fe00f943 RB |
498 | unsigned long __user *vaddr; |
499 | unsigned long reg; | |
1da177e4 | 500 | long offset; |
1da177e4 LT |
501 | |
502 | /* | |
503 | * analyse the sc instruction that just caused a ri exception | |
504 | * and put the referenced address to addr. | |
505 | */ | |
506 | ||
507 | /* sign extend offset */ | |
508 | offset = opcode & OFFSET; | |
509 | offset <<= 16; | |
510 | offset >>= 16; | |
511 | ||
fe00f943 RB |
512 | vaddr = (unsigned long __user *) |
513 | ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); | |
1da177e4 LT |
514 | reg = (opcode & RT) >> 16; |
515 | ||
60b0d655 MR |
516 | if ((unsigned long)vaddr & 3) |
517 | return SIGBUS; | |
1da177e4 LT |
518 | |
519 | preempt_disable(); | |
520 | ||
521 | if (ll_bit == 0 || ll_task != current) { | |
522 | regs->regs[reg] = 0; | |
523 | preempt_enable(); | |
60b0d655 | 524 | return 0; |
1da177e4 LT |
525 | } |
526 | ||
527 | preempt_enable(); | |
528 | ||
60b0d655 MR |
529 | if (put_user(regs->regs[reg], vaddr)) |
530 | return SIGSEGV; | |
1da177e4 LT |
531 | |
532 | regs->regs[reg] = 1; | |
533 | ||
60b0d655 | 534 | return 0; |
1da177e4 LT |
535 | } |
536 | ||
537 | /* | |
538 | * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both | |
539 | * opcodes are supposed to result in coprocessor unusable exceptions if | |
540 | * executed on ll/sc-less processors. That's the theory. In practice a | |
541 | * few processors such as NEC's VR4100 throw reserved instruction exceptions | |
542 | * instead, so we're doing the emulation thing in both exception handlers. | |
543 | */ | |
60b0d655 | 544 | static int simulate_llsc(struct pt_regs *regs, unsigned int opcode) |
1da177e4 | 545 | { |
60b0d655 MR |
546 | if ((opcode & OPCODE) == LL) |
547 | return simulate_ll(regs, opcode); | |
548 | if ((opcode & OPCODE) == SC) | |
549 | return simulate_sc(regs, opcode); | |
1da177e4 | 550 | |
60b0d655 | 551 | return -1; /* Must be something else ... */ |
1da177e4 LT |
552 | } |
553 | ||
3c37026d RB |
554 | /* |
555 | * Simulate trapping 'rdhwr' instructions to provide user accessible | |
1f5826bd | 556 | * registers not implemented in hardware. |
3c37026d | 557 | */ |
60b0d655 | 558 | static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode) |
3c37026d | 559 | { |
dc8f6029 | 560 | struct thread_info *ti = task_thread_info(current); |
3c37026d RB |
561 | |
562 | if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { | |
563 | int rd = (opcode & RD) >> 11; | |
564 | int rt = (opcode & RT) >> 16; | |
565 | switch (rd) { | |
1f5826bd CD |
566 | case 0: /* CPU number */ |
567 | regs->regs[rt] = smp_processor_id(); | |
568 | return 0; | |
569 | case 1: /* SYNCI length */ | |
570 | regs->regs[rt] = min(current_cpu_data.dcache.linesz, | |
571 | current_cpu_data.icache.linesz); | |
572 | return 0; | |
573 | case 2: /* Read count register */ | |
574 | regs->regs[rt] = read_c0_count(); | |
575 | return 0; | |
576 | case 3: /* Count register resolution */ | |
577 | switch (current_cpu_data.cputype) { | |
578 | case CPU_20KC: | |
579 | case CPU_25KF: | |
580 | regs->regs[rt] = 1; | |
581 | break; | |
3c37026d | 582 | default: |
1f5826bd CD |
583 | regs->regs[rt] = 2; |
584 | } | |
585 | return 0; | |
586 | case 29: | |
587 | regs->regs[rt] = ti->tp_value; | |
588 | return 0; | |
589 | default: | |
590 | return -1; | |
3c37026d RB |
591 | } |
592 | } | |
593 | ||
56ebd51b | 594 | /* Not ours. */ |
60b0d655 MR |
595 | return -1; |
596 | } | |
e5679882 | 597 | |
60b0d655 MR |
598 | static int simulate_sync(struct pt_regs *regs, unsigned int opcode) |
599 | { | |
600 | if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) | |
601 | return 0; | |
602 | ||
603 | return -1; /* Must be something else ... */ | |
3c37026d RB |
604 | } |
605 | ||
1da177e4 LT |
606 | asmlinkage void do_ov(struct pt_regs *regs) |
607 | { | |
608 | siginfo_t info; | |
609 | ||
36ccf1c0 RB |
610 | die_if_kernel("Integer overflow", regs); |
611 | ||
1da177e4 LT |
612 | info.si_code = FPE_INTOVF; |
613 | info.si_signo = SIGFPE; | |
614 | info.si_errno = 0; | |
fe00f943 | 615 | info.si_addr = (void __user *) regs->cp0_epc; |
1da177e4 LT |
616 | force_sig_info(SIGFPE, &info, current); |
617 | } | |
618 | ||
619 | /* | |
620 | * XXX Delayed fp exceptions when doing a lazy ctx switch XXX | |
621 | */ | |
622 | asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) | |
623 | { | |
948a34cf TS |
624 | siginfo_t info; |
625 | ||
57725f9e CD |
626 | die_if_kernel("FP exception in kernel code", regs); |
627 | ||
1da177e4 LT |
628 | if (fcr31 & FPU_CSR_UNI_X) { |
629 | int sig; | |
630 | ||
1da177e4 | 631 | /* |
a3dddd56 | 632 | * Unimplemented operation exception. If we've got the full |
1da177e4 LT |
633 | * software emulator on-board, let's use it... |
634 | * | |
635 | * Force FPU to dump state into task/thread context. We're | |
636 | * moving a lot of data here for what is probably a single | |
637 | * instruction, but the alternative is to pre-decode the FP | |
638 | * register operands before invoking the emulator, which seems | |
639 | * a bit extreme for what should be an infrequent event. | |
640 | */ | |
cd21dfcf | 641 | /* Ensure 'resume' not overwrite saved fp context again. */ |
53dc8028 | 642 | lose_fpu(1); |
1da177e4 LT |
643 | |
644 | /* Run the emulator */ | |
49a89efb | 645 | sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1); |
1da177e4 LT |
646 | |
647 | /* | |
648 | * We can't allow the emulated instruction to leave any of | |
649 | * the cause bit set in $fcr31. | |
650 | */ | |
eae89076 | 651 | current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X; |
1da177e4 LT |
652 | |
653 | /* Restore the hardware register state */ | |
53dc8028 | 654 | own_fpu(1); /* Using the FPU again. */ |
1da177e4 LT |
655 | |
656 | /* If something went wrong, signal */ | |
657 | if (sig) | |
658 | force_sig(sig, current); | |
659 | ||
660 | return; | |
948a34cf TS |
661 | } else if (fcr31 & FPU_CSR_INV_X) |
662 | info.si_code = FPE_FLTINV; | |
663 | else if (fcr31 & FPU_CSR_DIV_X) | |
664 | info.si_code = FPE_FLTDIV; | |
665 | else if (fcr31 & FPU_CSR_OVF_X) | |
666 | info.si_code = FPE_FLTOVF; | |
667 | else if (fcr31 & FPU_CSR_UDF_X) | |
668 | info.si_code = FPE_FLTUND; | |
669 | else if (fcr31 & FPU_CSR_INE_X) | |
670 | info.si_code = FPE_FLTRES; | |
671 | else | |
672 | info.si_code = __SI_FAULT; | |
673 | info.si_signo = SIGFPE; | |
674 | info.si_errno = 0; | |
675 | info.si_addr = (void __user *) regs->cp0_epc; | |
676 | force_sig_info(SIGFPE, &info, current); | |
1da177e4 LT |
677 | } |
678 | ||
df270051 RB |
679 | static void do_trap_or_bp(struct pt_regs *regs, unsigned int code, |
680 | const char *str) | |
1da177e4 | 681 | { |
1da177e4 | 682 | siginfo_t info; |
df270051 | 683 | char b[40]; |
1da177e4 LT |
684 | |
685 | /* | |
df270051 RB |
686 | * A short test says that IRIX 5.3 sends SIGTRAP for all trap |
687 | * insns, even for trap and break codes that indicate arithmetic | |
688 | * failures. Weird ... | |
1da177e4 LT |
689 | * But should we continue the brokenness??? --macro |
690 | */ | |
df270051 RB |
691 | switch (code) { |
692 | case BRK_OVERFLOW: | |
693 | case BRK_DIVZERO: | |
694 | scnprintf(b, sizeof(b), "%s instruction in kernel code", str); | |
695 | die_if_kernel(b, regs); | |
696 | if (code == BRK_DIVZERO) | |
1da177e4 LT |
697 | info.si_code = FPE_INTDIV; |
698 | else | |
699 | info.si_code = FPE_INTOVF; | |
700 | info.si_signo = SIGFPE; | |
701 | info.si_errno = 0; | |
fe00f943 | 702 | info.si_addr = (void __user *) regs->cp0_epc; |
1da177e4 LT |
703 | force_sig_info(SIGFPE, &info, current); |
704 | break; | |
63dc68a8 | 705 | case BRK_BUG: |
df270051 RB |
706 | die_if_kernel("Kernel bug detected", regs); |
707 | force_sig(SIGTRAP, current); | |
63dc68a8 | 708 | break; |
1da177e4 | 709 | default: |
df270051 RB |
710 | scnprintf(b, sizeof(b), "%s instruction in kernel code", str); |
711 | die_if_kernel(b, regs); | |
1da177e4 LT |
712 | force_sig(SIGTRAP, current); |
713 | } | |
df270051 RB |
714 | } |
715 | ||
716 | asmlinkage void do_bp(struct pt_regs *regs) | |
717 | { | |
718 | unsigned int opcode, bcode; | |
719 | ||
720 | if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) | |
721 | goto out_sigsegv; | |
722 | ||
723 | /* | |
724 | * There is the ancient bug in the MIPS assemblers that the break | |
725 | * code starts left to bit 16 instead to bit 6 in the opcode. | |
726 | * Gas is bug-compatible, but not always, grrr... | |
727 | * We handle both cases with a simple heuristics. --macro | |
728 | */ | |
729 | bcode = ((opcode >> 6) & ((1 << 20) - 1)); | |
730 | if (bcode >= (1 << 10)) | |
731 | bcode >>= 10; | |
732 | ||
733 | do_trap_or_bp(regs, bcode, "Break"); | |
90fccb13 | 734 | return; |
e5679882 RB |
735 | |
736 | out_sigsegv: | |
737 | force_sig(SIGSEGV, current); | |
1da177e4 LT |
738 | } |
739 | ||
740 | asmlinkage void do_tr(struct pt_regs *regs) | |
741 | { | |
742 | unsigned int opcode, tcode = 0; | |
1da177e4 | 743 | |
ba755f8e | 744 | if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) |
e5679882 | 745 | goto out_sigsegv; |
1da177e4 LT |
746 | |
747 | /* Immediate versions don't provide a code. */ | |
748 | if (!(opcode & OPCODE)) | |
749 | tcode = ((opcode >> 6) & ((1 << 10) - 1)); | |
750 | ||
df270051 | 751 | do_trap_or_bp(regs, tcode, "Trap"); |
90fccb13 | 752 | return; |
e5679882 RB |
753 | |
754 | out_sigsegv: | |
755 | force_sig(SIGSEGV, current); | |
1da177e4 LT |
756 | } |
757 | ||
758 | asmlinkage void do_ri(struct pt_regs *regs) | |
759 | { | |
60b0d655 MR |
760 | unsigned int __user *epc = (unsigned int __user *)exception_epc(regs); |
761 | unsigned long old_epc = regs->cp0_epc; | |
762 | unsigned int opcode = 0; | |
763 | int status = -1; | |
1da177e4 | 764 | |
60b0d655 | 765 | die_if_kernel("Reserved instruction in kernel code", regs); |
1da177e4 | 766 | |
60b0d655 | 767 | if (unlikely(compute_return_epc(regs) < 0)) |
3c37026d RB |
768 | return; |
769 | ||
60b0d655 MR |
770 | if (unlikely(get_user(opcode, epc) < 0)) |
771 | status = SIGSEGV; | |
772 | ||
773 | if (!cpu_has_llsc && status < 0) | |
774 | status = simulate_llsc(regs, opcode); | |
775 | ||
776 | if (status < 0) | |
777 | status = simulate_rdhwr(regs, opcode); | |
778 | ||
779 | if (status < 0) | |
780 | status = simulate_sync(regs, opcode); | |
781 | ||
782 | if (status < 0) | |
783 | status = SIGILL; | |
784 | ||
785 | if (unlikely(status > 0)) { | |
786 | regs->cp0_epc = old_epc; /* Undo skip-over. */ | |
787 | force_sig(status, current); | |
788 | } | |
1da177e4 LT |
789 | } |
790 | ||
d223a861 RB |
791 | /* |
792 | * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've | |
793 | * emulated more than some threshold number of instructions, force migration to | |
794 | * a "CPU" that has FP support. | |
795 | */ | |
796 | static void mt_ase_fp_affinity(void) | |
797 | { | |
798 | #ifdef CONFIG_MIPS_MT_FPAFF | |
799 | if (mt_fpemul_threshold > 0 && | |
800 | ((current->thread.emulated_fp++ > mt_fpemul_threshold))) { | |
801 | /* | |
802 | * If there's no FPU present, or if the application has already | |
803 | * restricted the allowed set to exclude any CPUs with FPUs, | |
804 | * we'll skip the procedure. | |
805 | */ | |
806 | if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) { | |
807 | cpumask_t tmask; | |
808 | ||
809 | cpus_and(tmask, current->thread.user_cpus_allowed, | |
810 | mt_fpu_cpumask); | |
811 | set_cpus_allowed(current, tmask); | |
293c5bd1 | 812 | set_thread_flag(TIF_FPUBOUND); |
d223a861 RB |
813 | } |
814 | } | |
815 | #endif /* CONFIG_MIPS_MT_FPAFF */ | |
816 | } | |
817 | ||
1da177e4 LT |
818 | asmlinkage void do_cpu(struct pt_regs *regs) |
819 | { | |
60b0d655 MR |
820 | unsigned int __user *epc; |
821 | unsigned long old_epc; | |
822 | unsigned int opcode; | |
1da177e4 | 823 | unsigned int cpid; |
60b0d655 | 824 | int status; |
1da177e4 | 825 | |
5323180d AN |
826 | die_if_kernel("do_cpu invoked from kernel context!", regs); |
827 | ||
1da177e4 LT |
828 | cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; |
829 | ||
830 | switch (cpid) { | |
831 | case 0: | |
60b0d655 MR |
832 | epc = (unsigned int __user *)exception_epc(regs); |
833 | old_epc = regs->cp0_epc; | |
834 | opcode = 0; | |
835 | status = -1; | |
1da177e4 | 836 | |
60b0d655 | 837 | if (unlikely(compute_return_epc(regs) < 0)) |
1da177e4 | 838 | return; |
3c37026d | 839 | |
60b0d655 MR |
840 | if (unlikely(get_user(opcode, epc) < 0)) |
841 | status = SIGSEGV; | |
842 | ||
843 | if (!cpu_has_llsc && status < 0) | |
844 | status = simulate_llsc(regs, opcode); | |
845 | ||
846 | if (status < 0) | |
847 | status = simulate_rdhwr(regs, opcode); | |
848 | ||
849 | if (status < 0) | |
850 | status = SIGILL; | |
851 | ||
852 | if (unlikely(status > 0)) { | |
853 | regs->cp0_epc = old_epc; /* Undo skip-over. */ | |
854 | force_sig(status, current); | |
855 | } | |
856 | ||
857 | return; | |
1da177e4 LT |
858 | |
859 | case 1: | |
53dc8028 AN |
860 | if (used_math()) /* Using the FPU again. */ |
861 | own_fpu(1); | |
862 | else { /* First time FPU user. */ | |
1da177e4 LT |
863 | init_fpu(); |
864 | set_used_math(); | |
865 | } | |
866 | ||
5323180d | 867 | if (!raw_cpu_has_fpu) { |
e04582b7 | 868 | int sig; |
e04582b7 AN |
869 | sig = fpu_emulator_cop1Handler(regs, |
870 | ¤t->thread.fpu, 0); | |
1da177e4 LT |
871 | if (sig) |
872 | force_sig(sig, current); | |
d223a861 RB |
873 | else |
874 | mt_ase_fp_affinity(); | |
1da177e4 LT |
875 | } |
876 | ||
1da177e4 LT |
877 | return; |
878 | ||
879 | case 2: | |
880 | case 3: | |
881 | break; | |
882 | } | |
883 | ||
884 | force_sig(SIGILL, current); | |
885 | } | |
886 | ||
887 | asmlinkage void do_mdmx(struct pt_regs *regs) | |
888 | { | |
889 | force_sig(SIGILL, current); | |
890 | } | |
891 | ||
892 | asmlinkage void do_watch(struct pt_regs *regs) | |
893 | { | |
894 | /* | |
895 | * We use the watch exception where available to detect stack | |
896 | * overflows. | |
897 | */ | |
898 | dump_tlb_all(); | |
899 | show_regs(regs); | |
900 | panic("Caught WATCH exception - probably caused by stack overflow."); | |
901 | } | |
902 | ||
903 | asmlinkage void do_mcheck(struct pt_regs *regs) | |
904 | { | |
cac4bcbc RB |
905 | const int field = 2 * sizeof(unsigned long); |
906 | int multi_match = regs->cp0_status & ST0_TS; | |
907 | ||
1da177e4 | 908 | show_regs(regs); |
cac4bcbc RB |
909 | |
910 | if (multi_match) { | |
911 | printk("Index : %0x\n", read_c0_index()); | |
912 | printk("Pagemask: %0x\n", read_c0_pagemask()); | |
913 | printk("EntryHi : %0*lx\n", field, read_c0_entryhi()); | |
914 | printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0()); | |
915 | printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1()); | |
916 | printk("\n"); | |
917 | dump_tlb_all(); | |
918 | } | |
919 | ||
e1bb8289 | 920 | show_code((unsigned int __user *) regs->cp0_epc); |
cac4bcbc | 921 | |
1da177e4 LT |
922 | /* |
923 | * Some chips may have other causes of machine check (e.g. SB1 | |
924 | * graduation timer) | |
925 | */ | |
926 | panic("Caught Machine Check exception - %scaused by multiple " | |
927 | "matching entries in the TLB.", | |
cac4bcbc | 928 | (multi_match) ? "" : "not "); |
1da177e4 LT |
929 | } |
930 | ||
340ee4b9 RB |
931 | asmlinkage void do_mt(struct pt_regs *regs) |
932 | { | |
41c594ab RB |
933 | int subcode; |
934 | ||
41c594ab RB |
935 | subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT) |
936 | >> VPECONTROL_EXCPT_SHIFT; | |
937 | switch (subcode) { | |
938 | case 0: | |
e35a5e35 | 939 | printk(KERN_DEBUG "Thread Underflow\n"); |
41c594ab RB |
940 | break; |
941 | case 1: | |
e35a5e35 | 942 | printk(KERN_DEBUG "Thread Overflow\n"); |
41c594ab RB |
943 | break; |
944 | case 2: | |
e35a5e35 | 945 | printk(KERN_DEBUG "Invalid YIELD Qualifier\n"); |
41c594ab RB |
946 | break; |
947 | case 3: | |
e35a5e35 | 948 | printk(KERN_DEBUG "Gating Storage Exception\n"); |
41c594ab RB |
949 | break; |
950 | case 4: | |
e35a5e35 | 951 | printk(KERN_DEBUG "YIELD Scheduler Exception\n"); |
41c594ab RB |
952 | break; |
953 | case 5: | |
e35a5e35 | 954 | printk(KERN_DEBUG "Gating Storage Schedulier Exception\n"); |
41c594ab RB |
955 | break; |
956 | default: | |
e35a5e35 | 957 | printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n", |
41c594ab RB |
958 | subcode); |
959 | break; | |
960 | } | |
340ee4b9 RB |
961 | die_if_kernel("MIPS MT Thread exception in kernel", regs); |
962 | ||
963 | force_sig(SIGILL, current); | |
964 | } | |
965 | ||
966 | ||
e50c0a8f RB |
967 | asmlinkage void do_dsp(struct pt_regs *regs) |
968 | { | |
969 | if (cpu_has_dsp) | |
970 | panic("Unexpected DSP exception\n"); | |
971 | ||
972 | force_sig(SIGILL, current); | |
973 | } | |
974 | ||
1da177e4 LT |
975 | asmlinkage void do_reserved(struct pt_regs *regs) |
976 | { | |
977 | /* | |
978 | * Game over - no way to handle this if it ever occurs. Most probably | |
979 | * caused by a new unknown cpu type or after another deadly | |
980 | * hard/software error. | |
981 | */ | |
982 | show_regs(regs); | |
983 | panic("Caught reserved exception %ld - should not happen.", | |
984 | (regs->cp0_cause & 0x7f) >> 2); | |
985 | } | |
986 | ||
39b8d525 RB |
987 | static int __initdata l1parity = 1; |
988 | static int __init nol1parity(char *s) | |
989 | { | |
990 | l1parity = 0; | |
991 | return 1; | |
992 | } | |
993 | __setup("nol1par", nol1parity); | |
994 | static int __initdata l2parity = 1; | |
995 | static int __init nol2parity(char *s) | |
996 | { | |
997 | l2parity = 0; | |
998 | return 1; | |
999 | } | |
1000 | __setup("nol2par", nol2parity); | |
1001 | ||
1da177e4 LT |
1002 | /* |
1003 | * Some MIPS CPUs can enable/disable for cache parity detection, but do | |
1004 | * it different ways. | |
1005 | */ | |
1006 | static inline void parity_protection_init(void) | |
1007 | { | |
10cc3529 | 1008 | switch (current_cpu_type()) { |
1da177e4 | 1009 | case CPU_24K: |
98a41de9 | 1010 | case CPU_34K: |
39b8d525 RB |
1011 | case CPU_74K: |
1012 | case CPU_1004K: | |
1013 | { | |
1014 | #define ERRCTL_PE 0x80000000 | |
1015 | #define ERRCTL_L2P 0x00800000 | |
1016 | unsigned long errctl; | |
1017 | unsigned int l1parity_present, l2parity_present; | |
1018 | ||
1019 | errctl = read_c0_ecc(); | |
1020 | errctl &= ~(ERRCTL_PE|ERRCTL_L2P); | |
1021 | ||
1022 | /* probe L1 parity support */ | |
1023 | write_c0_ecc(errctl | ERRCTL_PE); | |
1024 | back_to_back_c0_hazard(); | |
1025 | l1parity_present = (read_c0_ecc() & ERRCTL_PE); | |
1026 | ||
1027 | /* probe L2 parity support */ | |
1028 | write_c0_ecc(errctl|ERRCTL_L2P); | |
1029 | back_to_back_c0_hazard(); | |
1030 | l2parity_present = (read_c0_ecc() & ERRCTL_L2P); | |
1031 | ||
1032 | if (l1parity_present && l2parity_present) { | |
1033 | if (l1parity) | |
1034 | errctl |= ERRCTL_PE; | |
1035 | if (l1parity ^ l2parity) | |
1036 | errctl |= ERRCTL_L2P; | |
1037 | } else if (l1parity_present) { | |
1038 | if (l1parity) | |
1039 | errctl |= ERRCTL_PE; | |
1040 | } else if (l2parity_present) { | |
1041 | if (l2parity) | |
1042 | errctl |= ERRCTL_L2P; | |
1043 | } else { | |
1044 | /* No parity available */ | |
1045 | } | |
1046 | ||
1047 | printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl); | |
1048 | ||
1049 | write_c0_ecc(errctl); | |
1050 | back_to_back_c0_hazard(); | |
1051 | errctl = read_c0_ecc(); | |
1052 | printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl); | |
1053 | ||
1054 | if (l1parity_present) | |
1055 | printk(KERN_INFO "Cache parity protection %sabled\n", | |
1056 | (errctl & ERRCTL_PE) ? "en" : "dis"); | |
1057 | ||
1058 | if (l2parity_present) { | |
1059 | if (l1parity_present && l1parity) | |
1060 | errctl ^= ERRCTL_L2P; | |
1061 | printk(KERN_INFO "L2 cache parity protection %sabled\n", | |
1062 | (errctl & ERRCTL_L2P) ? "en" : "dis"); | |
1063 | } | |
1064 | } | |
1065 | break; | |
1066 | ||
1da177e4 | 1067 | case CPU_5KC: |
14f18b7f RB |
1068 | write_c0_ecc(0x80000000); |
1069 | back_to_back_c0_hazard(); | |
1070 | /* Set the PE bit (bit 31) in the c0_errctl register. */ | |
1071 | printk(KERN_INFO "Cache parity protection %sabled\n", | |
1072 | (read_c0_ecc() & 0x80000000) ? "en" : "dis"); | |
1da177e4 LT |
1073 | break; |
1074 | case CPU_20KC: | |
1075 | case CPU_25KF: | |
1076 | /* Clear the DE bit (bit 16) in the c0_status register. */ | |
1077 | printk(KERN_INFO "Enable cache parity protection for " | |
1078 | "MIPS 20KC/25KF CPUs.\n"); | |
1079 | clear_c0_status(ST0_DE); | |
1080 | break; | |
1081 | default: | |
1082 | break; | |
1083 | } | |
1084 | } | |
1085 | ||
1086 | asmlinkage void cache_parity_error(void) | |
1087 | { | |
1088 | const int field = 2 * sizeof(unsigned long); | |
1089 | unsigned int reg_val; | |
1090 | ||
1091 | /* For the moment, report the problem and hang. */ | |
1092 | printk("Cache error exception:\n"); | |
1093 | printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); | |
1094 | reg_val = read_c0_cacheerr(); | |
1095 | printk("c0_cacheerr == %08x\n", reg_val); | |
1096 | ||
1097 | printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", | |
1098 | reg_val & (1<<30) ? "secondary" : "primary", | |
1099 | reg_val & (1<<31) ? "data" : "insn"); | |
1100 | printk("Error bits: %s%s%s%s%s%s%s\n", | |
1101 | reg_val & (1<<29) ? "ED " : "", | |
1102 | reg_val & (1<<28) ? "ET " : "", | |
1103 | reg_val & (1<<26) ? "EE " : "", | |
1104 | reg_val & (1<<25) ? "EB " : "", | |
1105 | reg_val & (1<<24) ? "EI " : "", | |
1106 | reg_val & (1<<23) ? "E1 " : "", | |
1107 | reg_val & (1<<22) ? "E0 " : ""); | |
1108 | printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); | |
1109 | ||
ec917c2c | 1110 | #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) |
1da177e4 LT |
1111 | if (reg_val & (1<<22)) |
1112 | printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); | |
1113 | ||
1114 | if (reg_val & (1<<23)) | |
1115 | printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1()); | |
1116 | #endif | |
1117 | ||
1118 | panic("Can't handle the cache error!"); | |
1119 | } | |
1120 | ||
1121 | /* | |
1122 | * SDBBP EJTAG debug exception handler. | |
1123 | * We skip the instruction and return to the next instruction. | |
1124 | */ | |
1125 | void ejtag_exception_handler(struct pt_regs *regs) | |
1126 | { | |
1127 | const int field = 2 * sizeof(unsigned long); | |
1128 | unsigned long depc, old_epc; | |
1129 | unsigned int debug; | |
1130 | ||
70ae6126 | 1131 | printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); |
1da177e4 LT |
1132 | depc = read_c0_depc(); |
1133 | debug = read_c0_debug(); | |
70ae6126 | 1134 | printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug); |
1da177e4 LT |
1135 | if (debug & 0x80000000) { |
1136 | /* | |
1137 | * In branch delay slot. | |
1138 | * We cheat a little bit here and use EPC to calculate the | |
1139 | * debug return address (DEPC). EPC is restored after the | |
1140 | * calculation. | |
1141 | */ | |
1142 | old_epc = regs->cp0_epc; | |
1143 | regs->cp0_epc = depc; | |
1144 | __compute_return_epc(regs); | |
1145 | depc = regs->cp0_epc; | |
1146 | regs->cp0_epc = old_epc; | |
1147 | } else | |
1148 | depc += 4; | |
1149 | write_c0_depc(depc); | |
1150 | ||
1151 | #if 0 | |
70ae6126 | 1152 | printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n"); |
1da177e4 LT |
1153 | write_c0_debug(debug | 0x100); |
1154 | #endif | |
1155 | } | |
1156 | ||
1157 | /* | |
1158 | * NMI exception handler. | |
1159 | */ | |
34412c72 | 1160 | NORET_TYPE void ATTRIB_NORET nmi_exception_handler(struct pt_regs *regs) |
1da177e4 | 1161 | { |
41c594ab | 1162 | bust_spinlocks(1); |
1da177e4 LT |
1163 | printk("NMI taken!!!!\n"); |
1164 | die("NMI", regs); | |
1da177e4 LT |
1165 | } |
1166 | ||
e01402b1 RB |
1167 | #define VECTORSPACING 0x100 /* for EI/VI mode */ |
1168 | ||
1169 | unsigned long ebase; | |
1da177e4 | 1170 | unsigned long exception_handlers[32]; |
e01402b1 | 1171 | unsigned long vi_handlers[64]; |
1da177e4 LT |
1172 | |
1173 | /* | |
1174 | * As a side effect of the way this is implemented we're limited | |
1175 | * to interrupt handlers in the address range from | |
1176 | * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ... | |
1177 | */ | |
1178 | void *set_except_vector(int n, void *addr) | |
1179 | { | |
1180 | unsigned long handler = (unsigned long) addr; | |
1181 | unsigned long old_handler = exception_handlers[n]; | |
1182 | ||
1183 | exception_handlers[n] = handler; | |
1184 | if (n == 0 && cpu_has_divec) { | |
ec70f65e RB |
1185 | *(u32 *)(ebase + 0x200) = 0x08000000 | |
1186 | (0x03ffffff & (handler >> 2)); | |
e01402b1 RB |
1187 | flush_icache_range(ebase + 0x200, ebase + 0x204); |
1188 | } | |
1189 | return (void *)old_handler; | |
1190 | } | |
1191 | ||
6ba07e59 AN |
1192 | static asmlinkage void do_default_vi(void) |
1193 | { | |
1194 | show_regs(get_irq_regs()); | |
1195 | panic("Caught unexpected vectored interrupt."); | |
1196 | } | |
1197 | ||
ef300e42 | 1198 | static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) |
e01402b1 RB |
1199 | { |
1200 | unsigned long handler; | |
1201 | unsigned long old_handler = vi_handlers[n]; | |
f6771dbb | 1202 | int srssets = current_cpu_data.srsets; |
e01402b1 RB |
1203 | u32 *w; |
1204 | unsigned char *b; | |
1205 | ||
1206 | if (!cpu_has_veic && !cpu_has_vint) | |
1207 | BUG(); | |
1208 | ||
1209 | if (addr == NULL) { | |
1210 | handler = (unsigned long) do_default_vi; | |
1211 | srs = 0; | |
41c594ab | 1212 | } else |
e01402b1 RB |
1213 | handler = (unsigned long) addr; |
1214 | vi_handlers[n] = (unsigned long) addr; | |
1215 | ||
1216 | b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); | |
1217 | ||
f6771dbb | 1218 | if (srs >= srssets) |
e01402b1 RB |
1219 | panic("Shadow register set %d not supported", srs); |
1220 | ||
1221 | if (cpu_has_veic) { | |
1222 | if (board_bind_eic_interrupt) | |
49a89efb | 1223 | board_bind_eic_interrupt(n, srs); |
41c594ab | 1224 | } else if (cpu_has_vint) { |
e01402b1 | 1225 | /* SRSMap is only defined if shadow sets are implemented */ |
f6771dbb | 1226 | if (srssets > 1) |
49a89efb | 1227 | change_c0_srsmap(0xf << n*4, srs << n*4); |
e01402b1 RB |
1228 | } |
1229 | ||
1230 | if (srs == 0) { | |
1231 | /* | |
1232 | * If no shadow set is selected then use the default handler | |
1233 | * that does normal register saving and a standard interrupt exit | |
1234 | */ | |
1235 | ||
1236 | extern char except_vec_vi, except_vec_vi_lui; | |
1237 | extern char except_vec_vi_ori, except_vec_vi_end; | |
41c594ab RB |
1238 | #ifdef CONFIG_MIPS_MT_SMTC |
1239 | /* | |
1240 | * We need to provide the SMTC vectored interrupt handler | |
1241 | * not only with the address of the handler, but with the | |
1242 | * Status.IM bit to be masked before going there. | |
1243 | */ | |
1244 | extern char except_vec_vi_mori; | |
1245 | const int mori_offset = &except_vec_vi_mori - &except_vec_vi; | |
1246 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
e01402b1 RB |
1247 | const int handler_len = &except_vec_vi_end - &except_vec_vi; |
1248 | const int lui_offset = &except_vec_vi_lui - &except_vec_vi; | |
1249 | const int ori_offset = &except_vec_vi_ori - &except_vec_vi; | |
1250 | ||
1251 | if (handler_len > VECTORSPACING) { | |
1252 | /* | |
1253 | * Sigh... panicing won't help as the console | |
1254 | * is probably not configured :( | |
1255 | */ | |
49a89efb | 1256 | panic("VECTORSPACING too small"); |
e01402b1 RB |
1257 | } |
1258 | ||
49a89efb | 1259 | memcpy(b, &except_vec_vi, handler_len); |
41c594ab | 1260 | #ifdef CONFIG_MIPS_MT_SMTC |
8e8a52ed RB |
1261 | BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */ |
1262 | ||
41c594ab RB |
1263 | w = (u32 *)(b + mori_offset); |
1264 | *w = (*w & 0xffff0000) | (0x100 << n); | |
1265 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
e01402b1 RB |
1266 | w = (u32 *)(b + lui_offset); |
1267 | *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff); | |
1268 | w = (u32 *)(b + ori_offset); | |
1269 | *w = (*w & 0xffff0000) | ((u32)handler & 0xffff); | |
1270 | flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len)); | |
1271 | } | |
1272 | else { | |
1273 | /* | |
1274 | * In other cases jump directly to the interrupt handler | |
1275 | * | |
1276 | * It is the handlers responsibility to save registers if required | |
1277 | * (eg hi/lo) and return from the exception using "eret" | |
1278 | */ | |
1279 | w = (u32 *)b; | |
1280 | *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */ | |
1281 | *w = 0; | |
1282 | flush_icache_range((unsigned long)b, (unsigned long)(b+8)); | |
1da177e4 | 1283 | } |
e01402b1 | 1284 | |
1da177e4 LT |
1285 | return (void *)old_handler; |
1286 | } | |
1287 | ||
ef300e42 | 1288 | void *set_vi_handler(int n, vi_handler_t addr) |
e01402b1 | 1289 | { |
ff3eab2a | 1290 | return set_vi_srs_handler(n, addr, 0); |
e01402b1 | 1291 | } |
f41ae0b2 | 1292 | |
1da177e4 LT |
1293 | /* |
1294 | * This is used by native signal handling | |
1295 | */ | |
53dc8028 AN |
1296 | asmlinkage int (*save_fp_context)(struct sigcontext __user *sc); |
1297 | asmlinkage int (*restore_fp_context)(struct sigcontext __user *sc); | |
1da177e4 | 1298 | |
53dc8028 AN |
1299 | extern asmlinkage int _save_fp_context(struct sigcontext __user *sc); |
1300 | extern asmlinkage int _restore_fp_context(struct sigcontext __user *sc); | |
1da177e4 | 1301 | |
53dc8028 AN |
1302 | extern asmlinkage int fpu_emulator_save_context(struct sigcontext __user *sc); |
1303 | extern asmlinkage int fpu_emulator_restore_context(struct sigcontext __user *sc); | |
1da177e4 | 1304 | |
41c594ab | 1305 | #ifdef CONFIG_SMP |
53dc8028 | 1306 | static int smp_save_fp_context(struct sigcontext __user *sc) |
41c594ab | 1307 | { |
53dc8028 | 1308 | return raw_cpu_has_fpu |
41c594ab RB |
1309 | ? _save_fp_context(sc) |
1310 | : fpu_emulator_save_context(sc); | |
1311 | } | |
1312 | ||
53dc8028 | 1313 | static int smp_restore_fp_context(struct sigcontext __user *sc) |
41c594ab | 1314 | { |
53dc8028 | 1315 | return raw_cpu_has_fpu |
41c594ab RB |
1316 | ? _restore_fp_context(sc) |
1317 | : fpu_emulator_restore_context(sc); | |
1318 | } | |
1319 | #endif | |
1320 | ||
1da177e4 LT |
1321 | static inline void signal_init(void) |
1322 | { | |
41c594ab RB |
1323 | #ifdef CONFIG_SMP |
1324 | /* For now just do the cpu_has_fpu check when the functions are invoked */ | |
1325 | save_fp_context = smp_save_fp_context; | |
1326 | restore_fp_context = smp_restore_fp_context; | |
1327 | #else | |
1da177e4 LT |
1328 | if (cpu_has_fpu) { |
1329 | save_fp_context = _save_fp_context; | |
1330 | restore_fp_context = _restore_fp_context; | |
1331 | } else { | |
1332 | save_fp_context = fpu_emulator_save_context; | |
1333 | restore_fp_context = fpu_emulator_restore_context; | |
1334 | } | |
41c594ab | 1335 | #endif |
1da177e4 LT |
1336 | } |
1337 | ||
1338 | #ifdef CONFIG_MIPS32_COMPAT | |
1339 | ||
1340 | /* | |
1341 | * This is used by 32-bit signal stuff on the 64-bit kernel | |
1342 | */ | |
53dc8028 AN |
1343 | asmlinkage int (*save_fp_context32)(struct sigcontext32 __user *sc); |
1344 | asmlinkage int (*restore_fp_context32)(struct sigcontext32 __user *sc); | |
1da177e4 | 1345 | |
53dc8028 AN |
1346 | extern asmlinkage int _save_fp_context32(struct sigcontext32 __user *sc); |
1347 | extern asmlinkage int _restore_fp_context32(struct sigcontext32 __user *sc); | |
1da177e4 | 1348 | |
53dc8028 AN |
1349 | extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 __user *sc); |
1350 | extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 __user *sc); | |
1da177e4 LT |
1351 | |
1352 | static inline void signal32_init(void) | |
1353 | { | |
1354 | if (cpu_has_fpu) { | |
1355 | save_fp_context32 = _save_fp_context32; | |
1356 | restore_fp_context32 = _restore_fp_context32; | |
1357 | } else { | |
1358 | save_fp_context32 = fpu_emulator_save_context32; | |
1359 | restore_fp_context32 = fpu_emulator_restore_context32; | |
1360 | } | |
1361 | } | |
1362 | #endif | |
1363 | ||
1364 | extern void cpu_cache_init(void); | |
1365 | extern void tlb_init(void); | |
1d40cfcd | 1366 | extern void flush_tlb_handlers(void); |
1da177e4 | 1367 | |
42f77542 RB |
1368 | /* |
1369 | * Timer interrupt | |
1370 | */ | |
1371 | int cp0_compare_irq; | |
1372 | ||
1373 | /* | |
1374 | * Performance counter IRQ or -1 if shared with timer | |
1375 | */ | |
1376 | int cp0_perfcount_irq; | |
1377 | EXPORT_SYMBOL_GPL(cp0_perfcount_irq); | |
1378 | ||
bdc94eb4 CD |
1379 | static int __cpuinitdata noulri; |
1380 | ||
1381 | static int __init ulri_disable(char *s) | |
1382 | { | |
1383 | pr_info("Disabling ulri\n"); | |
1384 | noulri = 1; | |
1385 | ||
1386 | return 1; | |
1387 | } | |
1388 | __setup("noulri", ulri_disable); | |
1389 | ||
234fcd14 | 1390 | void __cpuinit per_cpu_trap_init(void) |
1da177e4 LT |
1391 | { |
1392 | unsigned int cpu = smp_processor_id(); | |
1393 | unsigned int status_set = ST0_CU0; | |
41c594ab RB |
1394 | #ifdef CONFIG_MIPS_MT_SMTC |
1395 | int secondaryTC = 0; | |
1396 | int bootTC = (cpu == 0); | |
1397 | ||
1398 | /* | |
1399 | * Only do per_cpu_trap_init() for first TC of Each VPE. | |
1400 | * Note that this hack assumes that the SMTC init code | |
1401 | * assigns TCs consecutively and in ascending order. | |
1402 | */ | |
1403 | ||
1404 | if (((read_c0_tcbind() & TCBIND_CURTC) != 0) && | |
1405 | ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id)) | |
1406 | secondaryTC = 1; | |
1407 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 LT |
1408 | |
1409 | /* | |
1410 | * Disable coprocessors and select 32-bit or 64-bit addressing | |
1411 | * and the 16/32 or 32/32 FPR register model. Reset the BEV | |
1412 | * flag that some firmware may have left set and the TS bit (for | |
1413 | * IP27). Set XX for ISA IV code to work. | |
1414 | */ | |
875d43e7 | 1415 | #ifdef CONFIG_64BIT |
1da177e4 LT |
1416 | status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; |
1417 | #endif | |
1418 | if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV) | |
1419 | status_set |= ST0_XX; | |
bbaf238b CD |
1420 | if (cpu_has_dsp) |
1421 | status_set |= ST0_MX; | |
1422 | ||
b38c7399 | 1423 | change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, |
1da177e4 LT |
1424 | status_set); |
1425 | ||
a3692020 RB |
1426 | if (cpu_has_mips_r2) { |
1427 | unsigned int enable = 0x0000000f; | |
1428 | ||
bdc94eb4 | 1429 | if (!noulri && cpu_has_userlocal) |
a3692020 RB |
1430 | enable |= (1 << 29); |
1431 | ||
1432 | write_c0_hwrena(enable); | |
1433 | } | |
e01402b1 | 1434 | |
41c594ab RB |
1435 | #ifdef CONFIG_MIPS_MT_SMTC |
1436 | if (!secondaryTC) { | |
1437 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1438 | ||
e01402b1 | 1439 | if (cpu_has_veic || cpu_has_vint) { |
49a89efb | 1440 | write_c0_ebase(ebase); |
e01402b1 | 1441 | /* Setting vector spacing enables EI/VI mode */ |
49a89efb | 1442 | change_c0_intctl(0x3e0, VECTORSPACING); |
e01402b1 | 1443 | } |
d03d0a57 RB |
1444 | if (cpu_has_divec) { |
1445 | if (cpu_has_mipsmt) { | |
1446 | unsigned int vpflags = dvpe(); | |
1447 | set_c0_cause(CAUSEF_IV); | |
1448 | evpe(vpflags); | |
1449 | } else | |
1450 | set_c0_cause(CAUSEF_IV); | |
1451 | } | |
3b1d4ed5 RB |
1452 | |
1453 | /* | |
1454 | * Before R2 both interrupt numbers were fixed to 7, so on R2 only: | |
1455 | * | |
1456 | * o read IntCtl.IPTI to determine the timer interrupt | |
1457 | * o read IntCtl.IPPCI to determine the performance counter interrupt | |
1458 | */ | |
1459 | if (cpu_has_mips_r2) { | |
49a89efb RB |
1460 | cp0_compare_irq = (read_c0_intctl() >> 29) & 7; |
1461 | cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7; | |
c3e838a2 | 1462 | if (cp0_perfcount_irq == cp0_compare_irq) |
3b1d4ed5 | 1463 | cp0_perfcount_irq = -1; |
c3e838a2 CD |
1464 | } else { |
1465 | cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; | |
1466 | cp0_perfcount_irq = -1; | |
3b1d4ed5 RB |
1467 | } |
1468 | ||
41c594ab RB |
1469 | #ifdef CONFIG_MIPS_MT_SMTC |
1470 | } | |
1471 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 LT |
1472 | |
1473 | cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; | |
1474 | TLBMISS_HANDLER_SETUP(); | |
1475 | ||
1476 | atomic_inc(&init_mm.mm_count); | |
1477 | current->active_mm = &init_mm; | |
1478 | BUG_ON(current->mm); | |
1479 | enter_lazy_tlb(&init_mm, current); | |
1480 | ||
41c594ab RB |
1481 | #ifdef CONFIG_MIPS_MT_SMTC |
1482 | if (bootTC) { | |
1483 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1484 | cpu_cache_init(); | |
1485 | tlb_init(); | |
1486 | #ifdef CONFIG_MIPS_MT_SMTC | |
6a05888d RB |
1487 | } else if (!secondaryTC) { |
1488 | /* | |
1489 | * First TC in non-boot VPE must do subset of tlb_init() | |
1490 | * for MMU countrol registers. | |
1491 | */ | |
1492 | write_c0_pagemask(PM_DEFAULT_MASK); | |
1493 | write_c0_wired(0); | |
41c594ab RB |
1494 | } |
1495 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 LT |
1496 | } |
1497 | ||
e01402b1 | 1498 | /* Install CPU exception handler */ |
49a89efb | 1499 | void __init set_handler(unsigned long offset, void *addr, unsigned long size) |
e01402b1 RB |
1500 | { |
1501 | memcpy((void *)(ebase + offset), addr, size); | |
1502 | flush_icache_range(ebase + offset, ebase + offset + size); | |
1503 | } | |
1504 | ||
234fcd14 | 1505 | static char panic_null_cerr[] __cpuinitdata = |
641e97f3 RB |
1506 | "Trying to set NULL cache error exception handler"; |
1507 | ||
e01402b1 | 1508 | /* Install uncached CPU exception handler */ |
234fcd14 RB |
1509 | void __cpuinit set_uncached_handler(unsigned long offset, void *addr, |
1510 | unsigned long size) | |
e01402b1 RB |
1511 | { |
1512 | #ifdef CONFIG_32BIT | |
1513 | unsigned long uncached_ebase = KSEG1ADDR(ebase); | |
1514 | #endif | |
1515 | #ifdef CONFIG_64BIT | |
1516 | unsigned long uncached_ebase = TO_UNCAC(ebase); | |
1517 | #endif | |
1518 | ||
641e97f3 RB |
1519 | if (!addr) |
1520 | panic(panic_null_cerr); | |
1521 | ||
e01402b1 RB |
1522 | memcpy((void *)(uncached_ebase + offset), addr, size); |
1523 | } | |
1524 | ||
5b10496b AN |
1525 | static int __initdata rdhwr_noopt; |
1526 | static int __init set_rdhwr_noopt(char *str) | |
1527 | { | |
1528 | rdhwr_noopt = 1; | |
1529 | return 1; | |
1530 | } | |
1531 | ||
1532 | __setup("rdhwr_noopt", set_rdhwr_noopt); | |
1533 | ||
1da177e4 LT |
1534 | void __init trap_init(void) |
1535 | { | |
1536 | extern char except_vec3_generic, except_vec3_r4000; | |
1da177e4 LT |
1537 | extern char except_vec4; |
1538 | unsigned long i; | |
1539 | ||
e01402b1 | 1540 | if (cpu_has_veic || cpu_has_vint) |
49a89efb | 1541 | ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64); |
e01402b1 RB |
1542 | else |
1543 | ebase = CAC_BASE; | |
1544 | ||
1da177e4 LT |
1545 | per_cpu_trap_init(); |
1546 | ||
1547 | /* | |
1548 | * Copy the generic exception handlers to their final destination. | |
1549 | * This will be overriden later as suitable for a particular | |
1550 | * configuration. | |
1551 | */ | |
e01402b1 | 1552 | set_handler(0x180, &except_vec3_generic, 0x80); |
1da177e4 LT |
1553 | |
1554 | /* | |
1555 | * Setup default vectors | |
1556 | */ | |
1557 | for (i = 0; i <= 31; i++) | |
1558 | set_except_vector(i, handle_reserved); | |
1559 | ||
1560 | /* | |
1561 | * Copy the EJTAG debug exception vector handler code to it's final | |
1562 | * destination. | |
1563 | */ | |
e01402b1 | 1564 | if (cpu_has_ejtag && board_ejtag_handler_setup) |
49a89efb | 1565 | board_ejtag_handler_setup(); |
1da177e4 LT |
1566 | |
1567 | /* | |
1568 | * Only some CPUs have the watch exceptions. | |
1569 | */ | |
1570 | if (cpu_has_watch) | |
1571 | set_except_vector(23, handle_watch); | |
1572 | ||
1573 | /* | |
e01402b1 | 1574 | * Initialise interrupt handlers |
1da177e4 | 1575 | */ |
e01402b1 RB |
1576 | if (cpu_has_veic || cpu_has_vint) { |
1577 | int nvec = cpu_has_veic ? 64 : 8; | |
1578 | for (i = 0; i < nvec; i++) | |
ff3eab2a | 1579 | set_vi_handler(i, NULL); |
e01402b1 RB |
1580 | } |
1581 | else if (cpu_has_divec) | |
1582 | set_handler(0x200, &except_vec4, 0x8); | |
1da177e4 LT |
1583 | |
1584 | /* | |
1585 | * Some CPUs can enable/disable for cache parity detection, but does | |
1586 | * it different ways. | |
1587 | */ | |
1588 | parity_protection_init(); | |
1589 | ||
1590 | /* | |
1591 | * The Data Bus Errors / Instruction Bus Errors are signaled | |
1592 | * by external hardware. Therefore these two exceptions | |
1593 | * may have board specific handlers. | |
1594 | */ | |
1595 | if (board_be_init) | |
1596 | board_be_init(); | |
1597 | ||
e4ac58af | 1598 | set_except_vector(0, handle_int); |
1da177e4 LT |
1599 | set_except_vector(1, handle_tlbm); |
1600 | set_except_vector(2, handle_tlbl); | |
1601 | set_except_vector(3, handle_tlbs); | |
1602 | ||
1603 | set_except_vector(4, handle_adel); | |
1604 | set_except_vector(5, handle_ades); | |
1605 | ||
1606 | set_except_vector(6, handle_ibe); | |
1607 | set_except_vector(7, handle_dbe); | |
1608 | ||
1609 | set_except_vector(8, handle_sys); | |
1610 | set_except_vector(9, handle_bp); | |
5b10496b AN |
1611 | set_except_vector(10, rdhwr_noopt ? handle_ri : |
1612 | (cpu_has_vtag_icache ? | |
1613 | handle_ri_rdhwr_vivt : handle_ri_rdhwr)); | |
1da177e4 LT |
1614 | set_except_vector(11, handle_cpu); |
1615 | set_except_vector(12, handle_ov); | |
1616 | set_except_vector(13, handle_tr); | |
1da177e4 | 1617 | |
10cc3529 RB |
1618 | if (current_cpu_type() == CPU_R6000 || |
1619 | current_cpu_type() == CPU_R6000A) { | |
1da177e4 LT |
1620 | /* |
1621 | * The R6000 is the only R-series CPU that features a machine | |
1622 | * check exception (similar to the R4000 cache error) and | |
1623 | * unaligned ldc1/sdc1 exception. The handlers have not been | |
1624 | * written yet. Well, anyway there is no R6000 machine on the | |
1625 | * current list of targets for Linux/MIPS. | |
1626 | * (Duh, crap, there is someone with a triple R6k machine) | |
1627 | */ | |
1628 | //set_except_vector(14, handle_mc); | |
1629 | //set_except_vector(15, handle_ndc); | |
1630 | } | |
1631 | ||
e01402b1 RB |
1632 | |
1633 | if (board_nmi_handler_setup) | |
1634 | board_nmi_handler_setup(); | |
1635 | ||
e50c0a8f RB |
1636 | if (cpu_has_fpu && !cpu_has_nofpuex) |
1637 | set_except_vector(15, handle_fpe); | |
1638 | ||
1639 | set_except_vector(22, handle_mdmx); | |
1640 | ||
1641 | if (cpu_has_mcheck) | |
1642 | set_except_vector(24, handle_mcheck); | |
1643 | ||
340ee4b9 RB |
1644 | if (cpu_has_mipsmt) |
1645 | set_except_vector(25, handle_mt); | |
1646 | ||
acaec427 | 1647 | set_except_vector(26, handle_dsp); |
e50c0a8f RB |
1648 | |
1649 | if (cpu_has_vce) | |
1650 | /* Special exception: R4[04]00 uses also the divec space. */ | |
1651 | memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100); | |
1652 | else if (cpu_has_4kex) | |
1653 | memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80); | |
1654 | else | |
1655 | memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80); | |
1656 | ||
1da177e4 LT |
1657 | signal_init(); |
1658 | #ifdef CONFIG_MIPS32_COMPAT | |
1659 | signal32_init(); | |
1660 | #endif | |
1661 | ||
e01402b1 | 1662 | flush_icache_range(ebase, ebase + 0x400); |
1d40cfcd | 1663 | flush_tlb_handlers(); |
1da177e4 | 1664 | } |