Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
36ccf1c0 | 6 | * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle |
1da177e4 LT |
7 | * Copyright (C) 1995, 1996 Paul M. Antoine |
8 | * Copyright (C) 1998 Ulf Carlsson | |
9 | * Copyright (C) 1999 Silicon Graphics, Inc. | |
10 | * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com | |
11 | * Copyright (C) 2000, 01 MIPS Technologies, Inc. | |
3b2396d9 | 12 | * Copyright (C) 2002, 2003, 2004, 2005 Maciej W. Rozycki |
1da177e4 | 13 | */ |
1da177e4 LT |
14 | #include <linux/init.h> |
15 | #include <linux/mm.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/sched.h> | |
18 | #include <linux/smp.h> | |
19 | #include <linux/smp_lock.h> | |
20 | #include <linux/spinlock.h> | |
21 | #include <linux/kallsyms.h> | |
e01402b1 | 22 | #include <linux/bootmem.h> |
d4fd1989 | 23 | #include <linux/interrupt.h> |
1da177e4 LT |
24 | |
25 | #include <asm/bootinfo.h> | |
26 | #include <asm/branch.h> | |
27 | #include <asm/break.h> | |
28 | #include <asm/cpu.h> | |
e50c0a8f | 29 | #include <asm/dsp.h> |
1da177e4 | 30 | #include <asm/fpu.h> |
340ee4b9 RB |
31 | #include <asm/mipsregs.h> |
32 | #include <asm/mipsmtregs.h> | |
1da177e4 LT |
33 | #include <asm/module.h> |
34 | #include <asm/pgtable.h> | |
35 | #include <asm/ptrace.h> | |
36 | #include <asm/sections.h> | |
37 | #include <asm/system.h> | |
38 | #include <asm/tlbdebug.h> | |
39 | #include <asm/traps.h> | |
40 | #include <asm/uaccess.h> | |
41 | #include <asm/mmu_context.h> | |
42 | #include <asm/watch.h> | |
43 | #include <asm/types.h> | |
44 | ||
e4ac58af | 45 | extern asmlinkage void handle_int(void); |
1da177e4 LT |
46 | extern asmlinkage void handle_tlbm(void); |
47 | extern asmlinkage void handle_tlbl(void); | |
48 | extern asmlinkage void handle_tlbs(void); | |
49 | extern asmlinkage void handle_adel(void); | |
50 | extern asmlinkage void handle_ades(void); | |
51 | extern asmlinkage void handle_ibe(void); | |
52 | extern asmlinkage void handle_dbe(void); | |
53 | extern asmlinkage void handle_sys(void); | |
54 | extern asmlinkage void handle_bp(void); | |
55 | extern asmlinkage void handle_ri(void); | |
56 | extern asmlinkage void handle_cpu(void); | |
57 | extern asmlinkage void handle_ov(void); | |
58 | extern asmlinkage void handle_tr(void); | |
59 | extern asmlinkage void handle_fpe(void); | |
60 | extern asmlinkage void handle_mdmx(void); | |
61 | extern asmlinkage void handle_watch(void); | |
340ee4b9 | 62 | extern asmlinkage void handle_mt(void); |
e50c0a8f | 63 | extern asmlinkage void handle_dsp(void); |
1da177e4 LT |
64 | extern asmlinkage void handle_mcheck(void); |
65 | extern asmlinkage void handle_reserved(void); | |
66 | ||
12616ed2 | 67 | extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, |
eae89076 | 68 | struct mips_fpu_struct *ctx); |
1da177e4 LT |
69 | |
70 | void (*board_be_init)(void); | |
71 | int (*board_be_handler)(struct pt_regs *regs, int is_fixup); | |
e01402b1 RB |
72 | void (*board_nmi_handler_setup)(void); |
73 | void (*board_ejtag_handler_setup)(void); | |
74 | void (*board_bind_eic_interrupt)(int irq, int regset); | |
1da177e4 | 75 | |
1da177e4 | 76 | |
87151ae3 | 77 | static void show_raw_backtrace(unsigned long *sp) |
e889d78f | 78 | { |
e889d78f AN |
79 | unsigned long addr; |
80 | ||
81 | printk("Call Trace:"); | |
82 | #ifdef CONFIG_KALLSYMS | |
83 | printk("\n"); | |
84 | #endif | |
87151ae3 FBH |
85 | while (!kstack_end(sp)) { |
86 | addr = *sp++; | |
87 | if (__kernel_text_address(addr)) | |
88 | print_ip_sym(addr); | |
e889d78f AN |
89 | } |
90 | printk("\n"); | |
91 | } | |
92 | ||
f66686f7 AN |
93 | #ifdef CONFIG_KALLSYMS |
94 | static int raw_show_trace; | |
95 | static int __init set_raw_show_trace(char *str) | |
96 | { | |
97 | raw_show_trace = 1; | |
98 | return 1; | |
99 | } | |
100 | __setup("raw_show_trace", set_raw_show_trace); | |
101 | ||
102 | extern unsigned long unwind_stack(struct task_struct *task, | |
103 | unsigned long **sp, unsigned long pc); | |
87151ae3 | 104 | static void show_backtrace(struct task_struct *task, struct pt_regs *regs) |
f66686f7 | 105 | { |
87151ae3 | 106 | unsigned long *sp = (long *)regs->regs[29]; |
f66686f7 AN |
107 | unsigned long pc = regs->cp0_epc; |
108 | int top = 1; | |
109 | ||
110 | if (raw_show_trace || !__kernel_text_address(pc)) { | |
87151ae3 | 111 | show_raw_backtrace(sp); |
f66686f7 AN |
112 | return; |
113 | } | |
114 | printk("Call Trace:\n"); | |
115 | while (__kernel_text_address(pc)) { | |
87151ae3 FBH |
116 | print_ip_sym(pc); |
117 | pc = unwind_stack(task, &sp, pc); | |
f66686f7 AN |
118 | if (top && pc == 0) |
119 | pc = regs->regs[31]; /* leaf? */ | |
120 | top = 0; | |
121 | } | |
122 | printk("\n"); | |
123 | } | |
124 | #else | |
87151ae3 | 125 | #define show_backtrace(task, r) show_raw_backtrace((long *)(r)->regs[29]); |
f66686f7 AN |
126 | #endif |
127 | ||
1da177e4 LT |
128 | /* |
129 | * This routine abuses get_user()/put_user() to reference pointers | |
130 | * with at least a bit of error checking ... | |
131 | */ | |
f66686f7 | 132 | static void show_stacktrace(struct task_struct *task, struct pt_regs *regs) |
1da177e4 LT |
133 | { |
134 | const int field = 2 * sizeof(unsigned long); | |
135 | long stackdata; | |
136 | int i; | |
f66686f7 | 137 | unsigned long *sp = (unsigned long *)regs->regs[29]; |
1da177e4 LT |
138 | |
139 | printk("Stack :"); | |
140 | i = 0; | |
141 | while ((unsigned long) sp & (PAGE_SIZE - 1)) { | |
142 | if (i && ((i % (64 / field)) == 0)) | |
143 | printk("\n "); | |
144 | if (i > 39) { | |
145 | printk(" ..."); | |
146 | break; | |
147 | } | |
148 | ||
149 | if (__get_user(stackdata, sp++)) { | |
150 | printk(" (Bad stack address)"); | |
151 | break; | |
152 | } | |
153 | ||
154 | printk(" %0*lx", field, stackdata); | |
155 | i++; | |
156 | } | |
157 | printk("\n"); | |
87151ae3 | 158 | show_backtrace(task, regs); |
f66686f7 AN |
159 | } |
160 | ||
1666a6fc | 161 | static __always_inline void prepare_frametrace(struct pt_regs *regs) |
f66686f7 AN |
162 | { |
163 | __asm__ __volatile__( | |
164 | "1: la $2, 1b\n\t" | |
165 | #ifdef CONFIG_64BIT | |
166 | "sd $2, %0\n\t" | |
167 | "sd $29, %1\n\t" | |
168 | "sd $31, %2\n\t" | |
169 | #else | |
170 | "sw $2, %0\n\t" | |
171 | "sw $29, %1\n\t" | |
172 | "sw $31, %2\n\t" | |
173 | #endif | |
174 | : "=m" (regs->cp0_epc), | |
175 | "=m" (regs->regs[29]), "=m" (regs->regs[31]) | |
176 | : : "memory"); | |
177 | } | |
178 | ||
179 | void show_stack(struct task_struct *task, unsigned long *sp) | |
180 | { | |
181 | struct pt_regs regs; | |
182 | if (sp) { | |
183 | regs.regs[29] = (unsigned long)sp; | |
184 | regs.regs[31] = 0; | |
185 | regs.cp0_epc = 0; | |
186 | } else { | |
187 | if (task && task != current) { | |
188 | regs.regs[29] = task->thread.reg29; | |
189 | regs.regs[31] = 0; | |
190 | regs.cp0_epc = task->thread.reg31; | |
191 | } else { | |
192 | prepare_frametrace(®s); | |
193 | } | |
194 | } | |
195 | show_stacktrace(task, ®s); | |
1da177e4 LT |
196 | } |
197 | ||
198 | /* | |
199 | * The architecture-independent dump_stack generator | |
200 | */ | |
201 | void dump_stack(void) | |
202 | { | |
1666a6fc | 203 | struct pt_regs regs; |
1da177e4 | 204 | |
1666a6fc FBH |
205 | /* |
206 | * Remove any garbage that may be in regs (specially func | |
207 | * addresses) to avoid show_raw_backtrace() to report them | |
208 | */ | |
209 | memset(®s, 0, sizeof(regs)); | |
210 | prepare_frametrace(®s); | |
211 | show_backtrace(current, ®s); | |
1da177e4 LT |
212 | } |
213 | ||
214 | EXPORT_SYMBOL(dump_stack); | |
215 | ||
216 | void show_code(unsigned int *pc) | |
217 | { | |
218 | long i; | |
219 | ||
220 | printk("\nCode:"); | |
221 | ||
222 | for(i = -3 ; i < 6 ; i++) { | |
223 | unsigned int insn; | |
224 | if (__get_user(insn, pc + i)) { | |
225 | printk(" (Bad address in epc)\n"); | |
226 | break; | |
227 | } | |
228 | printk("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>')); | |
229 | } | |
230 | } | |
231 | ||
232 | void show_regs(struct pt_regs *regs) | |
233 | { | |
234 | const int field = 2 * sizeof(unsigned long); | |
235 | unsigned int cause = regs->cp0_cause; | |
236 | int i; | |
237 | ||
238 | printk("Cpu %d\n", smp_processor_id()); | |
239 | ||
240 | /* | |
241 | * Saved main processor registers | |
242 | */ | |
243 | for (i = 0; i < 32; ) { | |
244 | if ((i % 4) == 0) | |
245 | printk("$%2d :", i); | |
246 | if (i == 0) | |
247 | printk(" %0*lx", field, 0UL); | |
248 | else if (i == 26 || i == 27) | |
249 | printk(" %*s", field, ""); | |
250 | else | |
251 | printk(" %0*lx", field, regs->regs[i]); | |
252 | ||
253 | i++; | |
254 | if ((i % 4) == 0) | |
255 | printk("\n"); | |
256 | } | |
257 | ||
258 | printk("Hi : %0*lx\n", field, regs->hi); | |
259 | printk("Lo : %0*lx\n", field, regs->lo); | |
260 | ||
261 | /* | |
262 | * Saved cp0 registers | |
263 | */ | |
264 | printk("epc : %0*lx ", field, regs->cp0_epc); | |
265 | print_symbol("%s ", regs->cp0_epc); | |
266 | printk(" %s\n", print_tainted()); | |
267 | printk("ra : %0*lx ", field, regs->regs[31]); | |
268 | print_symbol("%s\n", regs->regs[31]); | |
269 | ||
270 | printk("Status: %08x ", (uint32_t) regs->cp0_status); | |
271 | ||
3b2396d9 MR |
272 | if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) { |
273 | if (regs->cp0_status & ST0_KUO) | |
274 | printk("KUo "); | |
275 | if (regs->cp0_status & ST0_IEO) | |
276 | printk("IEo "); | |
277 | if (regs->cp0_status & ST0_KUP) | |
278 | printk("KUp "); | |
279 | if (regs->cp0_status & ST0_IEP) | |
280 | printk("IEp "); | |
281 | if (regs->cp0_status & ST0_KUC) | |
282 | printk("KUc "); | |
283 | if (regs->cp0_status & ST0_IEC) | |
284 | printk("IEc "); | |
285 | } else { | |
286 | if (regs->cp0_status & ST0_KX) | |
287 | printk("KX "); | |
288 | if (regs->cp0_status & ST0_SX) | |
289 | printk("SX "); | |
290 | if (regs->cp0_status & ST0_UX) | |
291 | printk("UX "); | |
292 | switch (regs->cp0_status & ST0_KSU) { | |
293 | case KSU_USER: | |
294 | printk("USER "); | |
295 | break; | |
296 | case KSU_SUPERVISOR: | |
297 | printk("SUPERVISOR "); | |
298 | break; | |
299 | case KSU_KERNEL: | |
300 | printk("KERNEL "); | |
301 | break; | |
302 | default: | |
303 | printk("BAD_MODE "); | |
304 | break; | |
305 | } | |
306 | if (regs->cp0_status & ST0_ERL) | |
307 | printk("ERL "); | |
308 | if (regs->cp0_status & ST0_EXL) | |
309 | printk("EXL "); | |
310 | if (regs->cp0_status & ST0_IE) | |
311 | printk("IE "); | |
1da177e4 | 312 | } |
1da177e4 LT |
313 | printk("\n"); |
314 | ||
315 | printk("Cause : %08x\n", cause); | |
316 | ||
317 | cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; | |
318 | if (1 <= cause && cause <= 5) | |
319 | printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr); | |
320 | ||
321 | printk("PrId : %08x\n", read_c0_prid()); | |
322 | } | |
323 | ||
324 | void show_registers(struct pt_regs *regs) | |
325 | { | |
326 | show_regs(regs); | |
327 | print_modules(); | |
328 | printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n", | |
329 | current->comm, current->pid, current_thread_info(), current); | |
f66686f7 | 330 | show_stacktrace(current, regs); |
1da177e4 LT |
331 | show_code((unsigned int *) regs->cp0_epc); |
332 | printk("\n"); | |
333 | } | |
334 | ||
335 | static DEFINE_SPINLOCK(die_lock); | |
336 | ||
178086c8 | 337 | NORET_TYPE void ATTRIB_NORET die(const char * str, struct pt_regs * regs) |
1da177e4 LT |
338 | { |
339 | static int die_counter; | |
41c594ab RB |
340 | #ifdef CONFIG_MIPS_MT_SMTC |
341 | unsigned long dvpret = dvpe(); | |
342 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 LT |
343 | |
344 | console_verbose(); | |
345 | spin_lock_irq(&die_lock); | |
41c594ab RB |
346 | bust_spinlocks(1); |
347 | #ifdef CONFIG_MIPS_MT_SMTC | |
348 | mips_mt_regdump(dvpret); | |
349 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
178086c8 | 350 | printk("%s[#%d]:\n", str, ++die_counter); |
1da177e4 LT |
351 | show_registers(regs); |
352 | spin_unlock_irq(&die_lock); | |
d4fd1989 MB |
353 | |
354 | if (in_interrupt()) | |
355 | panic("Fatal exception in interrupt"); | |
356 | ||
357 | if (panic_on_oops) { | |
358 | printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n"); | |
359 | ssleep(5); | |
360 | panic("Fatal exception"); | |
361 | } | |
362 | ||
1da177e4 LT |
363 | do_exit(SIGSEGV); |
364 | } | |
365 | ||
1da177e4 LT |
366 | extern const struct exception_table_entry __start___dbe_table[]; |
367 | extern const struct exception_table_entry __stop___dbe_table[]; | |
368 | ||
369 | void __declare_dbe_table(void) | |
370 | { | |
371 | __asm__ __volatile__( | |
372 | ".section\t__dbe_table,\"a\"\n\t" | |
373 | ".previous" | |
374 | ); | |
375 | } | |
376 | ||
377 | /* Given an address, look for it in the exception tables. */ | |
378 | static const struct exception_table_entry *search_dbe_tables(unsigned long addr) | |
379 | { | |
380 | const struct exception_table_entry *e; | |
381 | ||
382 | e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr); | |
383 | if (!e) | |
384 | e = search_module_dbetables(addr); | |
385 | return e; | |
386 | } | |
387 | ||
388 | asmlinkage void do_be(struct pt_regs *regs) | |
389 | { | |
390 | const int field = 2 * sizeof(unsigned long); | |
391 | const struct exception_table_entry *fixup = NULL; | |
392 | int data = regs->cp0_cause & 4; | |
393 | int action = MIPS_BE_FATAL; | |
394 | ||
395 | /* XXX For now. Fixme, this searches the wrong table ... */ | |
396 | if (data && !user_mode(regs)) | |
397 | fixup = search_dbe_tables(exception_epc(regs)); | |
398 | ||
399 | if (fixup) | |
400 | action = MIPS_BE_FIXUP; | |
401 | ||
402 | if (board_be_handler) | |
403 | action = board_be_handler(regs, fixup != 0); | |
404 | ||
405 | switch (action) { | |
406 | case MIPS_BE_DISCARD: | |
407 | return; | |
408 | case MIPS_BE_FIXUP: | |
409 | if (fixup) { | |
410 | regs->cp0_epc = fixup->nextinsn; | |
411 | return; | |
412 | } | |
413 | break; | |
414 | default: | |
415 | break; | |
416 | } | |
417 | ||
418 | /* | |
419 | * Assume it would be too dangerous to continue ... | |
420 | */ | |
421 | printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", | |
422 | data ? "Data" : "Instruction", | |
423 | field, regs->cp0_epc, field, regs->regs[31]); | |
424 | die_if_kernel("Oops", regs); | |
425 | force_sig(SIGBUS, current); | |
426 | } | |
427 | ||
428 | static inline int get_insn_opcode(struct pt_regs *regs, unsigned int *opcode) | |
429 | { | |
fe00f943 | 430 | unsigned int __user *epc; |
1da177e4 | 431 | |
fe00f943 | 432 | epc = (unsigned int __user *) regs->cp0_epc + |
1da177e4 LT |
433 | ((regs->cp0_cause & CAUSEF_BD) != 0); |
434 | if (!get_user(*opcode, epc)) | |
435 | return 0; | |
436 | ||
437 | force_sig(SIGSEGV, current); | |
438 | return 1; | |
439 | } | |
440 | ||
441 | /* | |
442 | * ll/sc emulation | |
443 | */ | |
444 | ||
445 | #define OPCODE 0xfc000000 | |
446 | #define BASE 0x03e00000 | |
447 | #define RT 0x001f0000 | |
448 | #define OFFSET 0x0000ffff | |
449 | #define LL 0xc0000000 | |
450 | #define SC 0xe0000000 | |
3c37026d RB |
451 | #define SPEC3 0x7c000000 |
452 | #define RD 0x0000f800 | |
453 | #define FUNC 0x0000003f | |
454 | #define RDHWR 0x0000003b | |
1da177e4 LT |
455 | |
456 | /* | |
457 | * The ll_bit is cleared by r*_switch.S | |
458 | */ | |
459 | ||
460 | unsigned long ll_bit; | |
461 | ||
462 | static struct task_struct *ll_task = NULL; | |
463 | ||
464 | static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode) | |
465 | { | |
fe00f943 | 466 | unsigned long value, __user *vaddr; |
1da177e4 LT |
467 | long offset; |
468 | int signal = 0; | |
469 | ||
470 | /* | |
471 | * analyse the ll instruction that just caused a ri exception | |
472 | * and put the referenced address to addr. | |
473 | */ | |
474 | ||
475 | /* sign extend offset */ | |
476 | offset = opcode & OFFSET; | |
477 | offset <<= 16; | |
478 | offset >>= 16; | |
479 | ||
fe00f943 RB |
480 | vaddr = (unsigned long __user *) |
481 | ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); | |
1da177e4 LT |
482 | |
483 | if ((unsigned long)vaddr & 3) { | |
484 | signal = SIGBUS; | |
485 | goto sig; | |
486 | } | |
487 | if (get_user(value, vaddr)) { | |
488 | signal = SIGSEGV; | |
489 | goto sig; | |
490 | } | |
491 | ||
492 | preempt_disable(); | |
493 | ||
494 | if (ll_task == NULL || ll_task == current) { | |
495 | ll_bit = 1; | |
496 | } else { | |
497 | ll_bit = 0; | |
498 | } | |
499 | ll_task = current; | |
500 | ||
501 | preempt_enable(); | |
502 | ||
6dd04688 RB |
503 | compute_return_epc(regs); |
504 | ||
1da177e4 LT |
505 | regs->regs[(opcode & RT) >> 16] = value; |
506 | ||
1da177e4 LT |
507 | return; |
508 | ||
509 | sig: | |
510 | force_sig(signal, current); | |
511 | } | |
512 | ||
513 | static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode) | |
514 | { | |
fe00f943 RB |
515 | unsigned long __user *vaddr; |
516 | unsigned long reg; | |
1da177e4 LT |
517 | long offset; |
518 | int signal = 0; | |
519 | ||
520 | /* | |
521 | * analyse the sc instruction that just caused a ri exception | |
522 | * and put the referenced address to addr. | |
523 | */ | |
524 | ||
525 | /* sign extend offset */ | |
526 | offset = opcode & OFFSET; | |
527 | offset <<= 16; | |
528 | offset >>= 16; | |
529 | ||
fe00f943 RB |
530 | vaddr = (unsigned long __user *) |
531 | ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); | |
1da177e4 LT |
532 | reg = (opcode & RT) >> 16; |
533 | ||
534 | if ((unsigned long)vaddr & 3) { | |
535 | signal = SIGBUS; | |
536 | goto sig; | |
537 | } | |
538 | ||
539 | preempt_disable(); | |
540 | ||
541 | if (ll_bit == 0 || ll_task != current) { | |
05b8042a | 542 | compute_return_epc(regs); |
1da177e4 LT |
543 | regs->regs[reg] = 0; |
544 | preempt_enable(); | |
1da177e4 LT |
545 | return; |
546 | } | |
547 | ||
548 | preempt_enable(); | |
549 | ||
550 | if (put_user(regs->regs[reg], vaddr)) { | |
551 | signal = SIGSEGV; | |
552 | goto sig; | |
553 | } | |
554 | ||
6dd04688 | 555 | compute_return_epc(regs); |
1da177e4 LT |
556 | regs->regs[reg] = 1; |
557 | ||
1da177e4 LT |
558 | return; |
559 | ||
560 | sig: | |
561 | force_sig(signal, current); | |
562 | } | |
563 | ||
564 | /* | |
565 | * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both | |
566 | * opcodes are supposed to result in coprocessor unusable exceptions if | |
567 | * executed on ll/sc-less processors. That's the theory. In practice a | |
568 | * few processors such as NEC's VR4100 throw reserved instruction exceptions | |
569 | * instead, so we're doing the emulation thing in both exception handlers. | |
570 | */ | |
571 | static inline int simulate_llsc(struct pt_regs *regs) | |
572 | { | |
573 | unsigned int opcode; | |
574 | ||
575 | if (unlikely(get_insn_opcode(regs, &opcode))) | |
576 | return -EFAULT; | |
577 | ||
578 | if ((opcode & OPCODE) == LL) { | |
579 | simulate_ll(regs, opcode); | |
580 | return 0; | |
581 | } | |
582 | if ((opcode & OPCODE) == SC) { | |
583 | simulate_sc(regs, opcode); | |
584 | return 0; | |
585 | } | |
586 | ||
587 | return -EFAULT; /* Strange things going on ... */ | |
588 | } | |
589 | ||
3c37026d RB |
590 | /* |
591 | * Simulate trapping 'rdhwr' instructions to provide user accessible | |
592 | * registers not implemented in hardware. The only current use of this | |
593 | * is the thread area pointer. | |
594 | */ | |
595 | static inline int simulate_rdhwr(struct pt_regs *regs) | |
596 | { | |
dc8f6029 | 597 | struct thread_info *ti = task_thread_info(current); |
3c37026d RB |
598 | unsigned int opcode; |
599 | ||
600 | if (unlikely(get_insn_opcode(regs, &opcode))) | |
601 | return -EFAULT; | |
602 | ||
603 | if (unlikely(compute_return_epc(regs))) | |
604 | return -EFAULT; | |
605 | ||
606 | if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { | |
607 | int rd = (opcode & RD) >> 11; | |
608 | int rt = (opcode & RT) >> 16; | |
609 | switch (rd) { | |
610 | case 29: | |
611 | regs->regs[rt] = ti->tp_value; | |
56ebd51b | 612 | return 0; |
3c37026d RB |
613 | default: |
614 | return -EFAULT; | |
615 | } | |
616 | } | |
617 | ||
56ebd51b DJ |
618 | /* Not ours. */ |
619 | return -EFAULT; | |
3c37026d RB |
620 | } |
621 | ||
1da177e4 LT |
622 | asmlinkage void do_ov(struct pt_regs *regs) |
623 | { | |
624 | siginfo_t info; | |
625 | ||
36ccf1c0 RB |
626 | die_if_kernel("Integer overflow", regs); |
627 | ||
1da177e4 LT |
628 | info.si_code = FPE_INTOVF; |
629 | info.si_signo = SIGFPE; | |
630 | info.si_errno = 0; | |
fe00f943 | 631 | info.si_addr = (void __user *) regs->cp0_epc; |
1da177e4 LT |
632 | force_sig_info(SIGFPE, &info, current); |
633 | } | |
634 | ||
635 | /* | |
636 | * XXX Delayed fp exceptions when doing a lazy ctx switch XXX | |
637 | */ | |
638 | asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) | |
639 | { | |
57725f9e CD |
640 | die_if_kernel("FP exception in kernel code", regs); |
641 | ||
1da177e4 LT |
642 | if (fcr31 & FPU_CSR_UNI_X) { |
643 | int sig; | |
644 | ||
645 | preempt_disable(); | |
646 | ||
cd21dfcf RB |
647 | #ifdef CONFIG_PREEMPT |
648 | if (!is_fpu_owner()) { | |
649 | /* We might lose fpu before disabling preempt... */ | |
650 | own_fpu(); | |
651 | BUG_ON(!used_math()); | |
652 | restore_fp(current); | |
653 | } | |
654 | #endif | |
1da177e4 | 655 | /* |
a3dddd56 | 656 | * Unimplemented operation exception. If we've got the full |
1da177e4 LT |
657 | * software emulator on-board, let's use it... |
658 | * | |
659 | * Force FPU to dump state into task/thread context. We're | |
660 | * moving a lot of data here for what is probably a single | |
661 | * instruction, but the alternative is to pre-decode the FP | |
662 | * register operands before invoking the emulator, which seems | |
663 | * a bit extreme for what should be an infrequent event. | |
664 | */ | |
665 | save_fp(current); | |
cd21dfcf RB |
666 | /* Ensure 'resume' not overwrite saved fp context again. */ |
667 | lose_fpu(); | |
668 | ||
669 | preempt_enable(); | |
1da177e4 LT |
670 | |
671 | /* Run the emulator */ | |
eae89076 | 672 | sig = fpu_emulator_cop1Handler (regs, ¤t->thread.fpu); |
1da177e4 | 673 | |
cd21dfcf RB |
674 | preempt_disable(); |
675 | ||
676 | own_fpu(); /* Using the FPU again. */ | |
1da177e4 LT |
677 | /* |
678 | * We can't allow the emulated instruction to leave any of | |
679 | * the cause bit set in $fcr31. | |
680 | */ | |
eae89076 | 681 | current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X; |
1da177e4 LT |
682 | |
683 | /* Restore the hardware register state */ | |
684 | restore_fp(current); | |
685 | ||
686 | preempt_enable(); | |
687 | ||
688 | /* If something went wrong, signal */ | |
689 | if (sig) | |
690 | force_sig(sig, current); | |
691 | ||
692 | return; | |
693 | } | |
694 | ||
695 | force_sig(SIGFPE, current); | |
696 | } | |
697 | ||
698 | asmlinkage void do_bp(struct pt_regs *regs) | |
699 | { | |
700 | unsigned int opcode, bcode; | |
701 | siginfo_t info; | |
702 | ||
703 | die_if_kernel("Break instruction in kernel code", regs); | |
704 | ||
705 | if (get_insn_opcode(regs, &opcode)) | |
706 | return; | |
707 | ||
708 | /* | |
709 | * There is the ancient bug in the MIPS assemblers that the break | |
710 | * code starts left to bit 16 instead to bit 6 in the opcode. | |
711 | * Gas is bug-compatible, but not always, grrr... | |
712 | * We handle both cases with a simple heuristics. --macro | |
713 | */ | |
714 | bcode = ((opcode >> 6) & ((1 << 20) - 1)); | |
715 | if (bcode < (1 << 10)) | |
716 | bcode <<= 10; | |
717 | ||
718 | /* | |
719 | * (A short test says that IRIX 5.3 sends SIGTRAP for all break | |
720 | * insns, even for break codes that indicate arithmetic failures. | |
721 | * Weird ...) | |
722 | * But should we continue the brokenness??? --macro | |
723 | */ | |
724 | switch (bcode) { | |
725 | case BRK_OVERFLOW << 10: | |
726 | case BRK_DIVZERO << 10: | |
727 | if (bcode == (BRK_DIVZERO << 10)) | |
728 | info.si_code = FPE_INTDIV; | |
729 | else | |
730 | info.si_code = FPE_INTOVF; | |
731 | info.si_signo = SIGFPE; | |
732 | info.si_errno = 0; | |
fe00f943 | 733 | info.si_addr = (void __user *) regs->cp0_epc; |
1da177e4 LT |
734 | force_sig_info(SIGFPE, &info, current); |
735 | break; | |
736 | default: | |
737 | force_sig(SIGTRAP, current); | |
738 | } | |
739 | } | |
740 | ||
741 | asmlinkage void do_tr(struct pt_regs *regs) | |
742 | { | |
743 | unsigned int opcode, tcode = 0; | |
744 | siginfo_t info; | |
745 | ||
746 | die_if_kernel("Trap instruction in kernel code", regs); | |
747 | ||
748 | if (get_insn_opcode(regs, &opcode)) | |
749 | return; | |
750 | ||
751 | /* Immediate versions don't provide a code. */ | |
752 | if (!(opcode & OPCODE)) | |
753 | tcode = ((opcode >> 6) & ((1 << 10) - 1)); | |
754 | ||
755 | /* | |
756 | * (A short test says that IRIX 5.3 sends SIGTRAP for all trap | |
757 | * insns, even for trap codes that indicate arithmetic failures. | |
758 | * Weird ...) | |
759 | * But should we continue the brokenness??? --macro | |
760 | */ | |
761 | switch (tcode) { | |
762 | case BRK_OVERFLOW: | |
763 | case BRK_DIVZERO: | |
764 | if (tcode == BRK_DIVZERO) | |
765 | info.si_code = FPE_INTDIV; | |
766 | else | |
767 | info.si_code = FPE_INTOVF; | |
768 | info.si_signo = SIGFPE; | |
769 | info.si_errno = 0; | |
fe00f943 | 770 | info.si_addr = (void __user *) regs->cp0_epc; |
1da177e4 LT |
771 | force_sig_info(SIGFPE, &info, current); |
772 | break; | |
773 | default: | |
774 | force_sig(SIGTRAP, current); | |
775 | } | |
776 | } | |
777 | ||
778 | asmlinkage void do_ri(struct pt_regs *regs) | |
779 | { | |
780 | die_if_kernel("Reserved instruction in kernel code", regs); | |
781 | ||
782 | if (!cpu_has_llsc) | |
783 | if (!simulate_llsc(regs)) | |
784 | return; | |
785 | ||
3c37026d RB |
786 | if (!simulate_rdhwr(regs)) |
787 | return; | |
788 | ||
1da177e4 LT |
789 | force_sig(SIGILL, current); |
790 | } | |
791 | ||
792 | asmlinkage void do_cpu(struct pt_regs *regs) | |
793 | { | |
794 | unsigned int cpid; | |
795 | ||
796 | die_if_kernel("do_cpu invoked from kernel context!", regs); | |
797 | ||
798 | cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; | |
799 | ||
800 | switch (cpid) { | |
801 | case 0: | |
3c37026d RB |
802 | if (!cpu_has_llsc) |
803 | if (!simulate_llsc(regs)) | |
804 | return; | |
1da177e4 | 805 | |
3c37026d | 806 | if (!simulate_rdhwr(regs)) |
1da177e4 | 807 | return; |
3c37026d | 808 | |
1da177e4 LT |
809 | break; |
810 | ||
811 | case 1: | |
812 | preempt_disable(); | |
813 | ||
814 | own_fpu(); | |
815 | if (used_math()) { /* Using the FPU again. */ | |
816 | restore_fp(current); | |
817 | } else { /* First time FPU user. */ | |
818 | init_fpu(); | |
819 | set_used_math(); | |
820 | } | |
821 | ||
cd21dfcf RB |
822 | preempt_enable(); |
823 | ||
1da177e4 | 824 | if (!cpu_has_fpu) { |
12616ed2 | 825 | int sig = fpu_emulator_cop1Handler(regs, |
eae89076 | 826 | ¤t->thread.fpu); |
1da177e4 LT |
827 | if (sig) |
828 | force_sig(sig, current); | |
f088fc84 RB |
829 | #ifdef CONFIG_MIPS_MT_FPAFF |
830 | else { | |
831 | /* | |
832 | * MIPS MT processors may have fewer FPU contexts | |
833 | * than CPU threads. If we've emulated more than | |
834 | * some threshold number of instructions, force | |
835 | * migration to a "CPU" that has FP support. | |
836 | */ | |
837 | if(mt_fpemul_threshold > 0 | |
838 | && ((current->thread.emulated_fp++ | |
839 | > mt_fpemul_threshold))) { | |
840 | /* | |
841 | * If there's no FPU present, or if the | |
842 | * application has already restricted | |
843 | * the allowed set to exclude any CPUs | |
844 | * with FPUs, we'll skip the procedure. | |
845 | */ | |
846 | if (cpus_intersects(current->cpus_allowed, | |
847 | mt_fpu_cpumask)) { | |
848 | cpumask_t tmask; | |
849 | ||
850 | cpus_and(tmask, | |
851 | current->thread.user_cpus_allowed, | |
852 | mt_fpu_cpumask); | |
853 | set_cpus_allowed(current, tmask); | |
854 | current->thread.mflags |= MF_FPUBOUND; | |
855 | } | |
856 | } | |
857 | } | |
858 | #endif /* CONFIG_MIPS_MT_FPAFF */ | |
1da177e4 LT |
859 | } |
860 | ||
1da177e4 LT |
861 | return; |
862 | ||
863 | case 2: | |
864 | case 3: | |
41c594ab | 865 | die_if_kernel("do_cpu invoked from kernel context!", regs); |
1da177e4 LT |
866 | break; |
867 | } | |
868 | ||
869 | force_sig(SIGILL, current); | |
870 | } | |
871 | ||
872 | asmlinkage void do_mdmx(struct pt_regs *regs) | |
873 | { | |
874 | force_sig(SIGILL, current); | |
875 | } | |
876 | ||
877 | asmlinkage void do_watch(struct pt_regs *regs) | |
878 | { | |
879 | /* | |
880 | * We use the watch exception where available to detect stack | |
881 | * overflows. | |
882 | */ | |
883 | dump_tlb_all(); | |
884 | show_regs(regs); | |
885 | panic("Caught WATCH exception - probably caused by stack overflow."); | |
886 | } | |
887 | ||
888 | asmlinkage void do_mcheck(struct pt_regs *regs) | |
889 | { | |
cac4bcbc RB |
890 | const int field = 2 * sizeof(unsigned long); |
891 | int multi_match = regs->cp0_status & ST0_TS; | |
892 | ||
1da177e4 | 893 | show_regs(regs); |
cac4bcbc RB |
894 | |
895 | if (multi_match) { | |
896 | printk("Index : %0x\n", read_c0_index()); | |
897 | printk("Pagemask: %0x\n", read_c0_pagemask()); | |
898 | printk("EntryHi : %0*lx\n", field, read_c0_entryhi()); | |
899 | printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0()); | |
900 | printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1()); | |
901 | printk("\n"); | |
902 | dump_tlb_all(); | |
903 | } | |
904 | ||
905 | show_code((unsigned int *) regs->cp0_epc); | |
906 | ||
1da177e4 LT |
907 | /* |
908 | * Some chips may have other causes of machine check (e.g. SB1 | |
909 | * graduation timer) | |
910 | */ | |
911 | panic("Caught Machine Check exception - %scaused by multiple " | |
912 | "matching entries in the TLB.", | |
cac4bcbc | 913 | (multi_match) ? "" : "not "); |
1da177e4 LT |
914 | } |
915 | ||
340ee4b9 RB |
916 | asmlinkage void do_mt(struct pt_regs *regs) |
917 | { | |
41c594ab RB |
918 | int subcode; |
919 | ||
41c594ab RB |
920 | subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT) |
921 | >> VPECONTROL_EXCPT_SHIFT; | |
922 | switch (subcode) { | |
923 | case 0: | |
e35a5e35 | 924 | printk(KERN_DEBUG "Thread Underflow\n"); |
41c594ab RB |
925 | break; |
926 | case 1: | |
e35a5e35 | 927 | printk(KERN_DEBUG "Thread Overflow\n"); |
41c594ab RB |
928 | break; |
929 | case 2: | |
e35a5e35 | 930 | printk(KERN_DEBUG "Invalid YIELD Qualifier\n"); |
41c594ab RB |
931 | break; |
932 | case 3: | |
e35a5e35 | 933 | printk(KERN_DEBUG "Gating Storage Exception\n"); |
41c594ab RB |
934 | break; |
935 | case 4: | |
e35a5e35 | 936 | printk(KERN_DEBUG "YIELD Scheduler Exception\n"); |
41c594ab RB |
937 | break; |
938 | case 5: | |
e35a5e35 | 939 | printk(KERN_DEBUG "Gating Storage Schedulier Exception\n"); |
41c594ab RB |
940 | break; |
941 | default: | |
e35a5e35 | 942 | printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n", |
41c594ab RB |
943 | subcode); |
944 | break; | |
945 | } | |
340ee4b9 RB |
946 | die_if_kernel("MIPS MT Thread exception in kernel", regs); |
947 | ||
948 | force_sig(SIGILL, current); | |
949 | } | |
950 | ||
951 | ||
e50c0a8f RB |
952 | asmlinkage void do_dsp(struct pt_regs *regs) |
953 | { | |
954 | if (cpu_has_dsp) | |
955 | panic("Unexpected DSP exception\n"); | |
956 | ||
957 | force_sig(SIGILL, current); | |
958 | } | |
959 | ||
1da177e4 LT |
960 | asmlinkage void do_reserved(struct pt_regs *regs) |
961 | { | |
962 | /* | |
963 | * Game over - no way to handle this if it ever occurs. Most probably | |
964 | * caused by a new unknown cpu type or after another deadly | |
965 | * hard/software error. | |
966 | */ | |
967 | show_regs(regs); | |
968 | panic("Caught reserved exception %ld - should not happen.", | |
969 | (regs->cp0_cause & 0x7f) >> 2); | |
970 | } | |
971 | ||
e01402b1 RB |
972 | asmlinkage void do_default_vi(struct pt_regs *regs) |
973 | { | |
974 | show_regs(regs); | |
975 | panic("Caught unexpected vectored interrupt."); | |
976 | } | |
977 | ||
1da177e4 LT |
978 | /* |
979 | * Some MIPS CPUs can enable/disable for cache parity detection, but do | |
980 | * it different ways. | |
981 | */ | |
982 | static inline void parity_protection_init(void) | |
983 | { | |
984 | switch (current_cpu_data.cputype) { | |
985 | case CPU_24K: | |
98a41de9 | 986 | case CPU_34K: |
1da177e4 | 987 | case CPU_5KC: |
14f18b7f RB |
988 | write_c0_ecc(0x80000000); |
989 | back_to_back_c0_hazard(); | |
990 | /* Set the PE bit (bit 31) in the c0_errctl register. */ | |
991 | printk(KERN_INFO "Cache parity protection %sabled\n", | |
992 | (read_c0_ecc() & 0x80000000) ? "en" : "dis"); | |
1da177e4 LT |
993 | break; |
994 | case CPU_20KC: | |
995 | case CPU_25KF: | |
996 | /* Clear the DE bit (bit 16) in the c0_status register. */ | |
997 | printk(KERN_INFO "Enable cache parity protection for " | |
998 | "MIPS 20KC/25KF CPUs.\n"); | |
999 | clear_c0_status(ST0_DE); | |
1000 | break; | |
1001 | default: | |
1002 | break; | |
1003 | } | |
1004 | } | |
1005 | ||
1006 | asmlinkage void cache_parity_error(void) | |
1007 | { | |
1008 | const int field = 2 * sizeof(unsigned long); | |
1009 | unsigned int reg_val; | |
1010 | ||
1011 | /* For the moment, report the problem and hang. */ | |
1012 | printk("Cache error exception:\n"); | |
1013 | printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); | |
1014 | reg_val = read_c0_cacheerr(); | |
1015 | printk("c0_cacheerr == %08x\n", reg_val); | |
1016 | ||
1017 | printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", | |
1018 | reg_val & (1<<30) ? "secondary" : "primary", | |
1019 | reg_val & (1<<31) ? "data" : "insn"); | |
1020 | printk("Error bits: %s%s%s%s%s%s%s\n", | |
1021 | reg_val & (1<<29) ? "ED " : "", | |
1022 | reg_val & (1<<28) ? "ET " : "", | |
1023 | reg_val & (1<<26) ? "EE " : "", | |
1024 | reg_val & (1<<25) ? "EB " : "", | |
1025 | reg_val & (1<<24) ? "EI " : "", | |
1026 | reg_val & (1<<23) ? "E1 " : "", | |
1027 | reg_val & (1<<22) ? "E0 " : ""); | |
1028 | printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); | |
1029 | ||
ec917c2c | 1030 | #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) |
1da177e4 LT |
1031 | if (reg_val & (1<<22)) |
1032 | printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); | |
1033 | ||
1034 | if (reg_val & (1<<23)) | |
1035 | printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1()); | |
1036 | #endif | |
1037 | ||
1038 | panic("Can't handle the cache error!"); | |
1039 | } | |
1040 | ||
1041 | /* | |
1042 | * SDBBP EJTAG debug exception handler. | |
1043 | * We skip the instruction and return to the next instruction. | |
1044 | */ | |
1045 | void ejtag_exception_handler(struct pt_regs *regs) | |
1046 | { | |
1047 | const int field = 2 * sizeof(unsigned long); | |
1048 | unsigned long depc, old_epc; | |
1049 | unsigned int debug; | |
1050 | ||
70ae6126 | 1051 | printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); |
1da177e4 LT |
1052 | depc = read_c0_depc(); |
1053 | debug = read_c0_debug(); | |
70ae6126 | 1054 | printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug); |
1da177e4 LT |
1055 | if (debug & 0x80000000) { |
1056 | /* | |
1057 | * In branch delay slot. | |
1058 | * We cheat a little bit here and use EPC to calculate the | |
1059 | * debug return address (DEPC). EPC is restored after the | |
1060 | * calculation. | |
1061 | */ | |
1062 | old_epc = regs->cp0_epc; | |
1063 | regs->cp0_epc = depc; | |
1064 | __compute_return_epc(regs); | |
1065 | depc = regs->cp0_epc; | |
1066 | regs->cp0_epc = old_epc; | |
1067 | } else | |
1068 | depc += 4; | |
1069 | write_c0_depc(depc); | |
1070 | ||
1071 | #if 0 | |
70ae6126 | 1072 | printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n"); |
1da177e4 LT |
1073 | write_c0_debug(debug | 0x100); |
1074 | #endif | |
1075 | } | |
1076 | ||
1077 | /* | |
1078 | * NMI exception handler. | |
1079 | */ | |
1080 | void nmi_exception_handler(struct pt_regs *regs) | |
1081 | { | |
41c594ab RB |
1082 | #ifdef CONFIG_MIPS_MT_SMTC |
1083 | unsigned long dvpret = dvpe(); | |
1084 | bust_spinlocks(1); | |
1085 | printk("NMI taken!!!!\n"); | |
1086 | mips_mt_regdump(dvpret); | |
1087 | #else | |
1088 | bust_spinlocks(1); | |
1da177e4 | 1089 | printk("NMI taken!!!!\n"); |
41c594ab | 1090 | #endif /* CONFIG_MIPS_MT_SMTC */ |
1da177e4 LT |
1091 | die("NMI", regs); |
1092 | while(1) ; | |
1093 | } | |
1094 | ||
e01402b1 RB |
1095 | #define VECTORSPACING 0x100 /* for EI/VI mode */ |
1096 | ||
1097 | unsigned long ebase; | |
1da177e4 | 1098 | unsigned long exception_handlers[32]; |
e01402b1 | 1099 | unsigned long vi_handlers[64]; |
1da177e4 LT |
1100 | |
1101 | /* | |
1102 | * As a side effect of the way this is implemented we're limited | |
1103 | * to interrupt handlers in the address range from | |
1104 | * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ... | |
1105 | */ | |
1106 | void *set_except_vector(int n, void *addr) | |
1107 | { | |
1108 | unsigned long handler = (unsigned long) addr; | |
1109 | unsigned long old_handler = exception_handlers[n]; | |
1110 | ||
1111 | exception_handlers[n] = handler; | |
1112 | if (n == 0 && cpu_has_divec) { | |
e01402b1 | 1113 | *(volatile u32 *)(ebase + 0x200) = 0x08000000 | |
1da177e4 | 1114 | (0x03ffffff & (handler >> 2)); |
e01402b1 RB |
1115 | flush_icache_range(ebase + 0x200, ebase + 0x204); |
1116 | } | |
1117 | return (void *)old_handler; | |
1118 | } | |
1119 | ||
f41ae0b2 | 1120 | #ifdef CONFIG_CPU_MIPSR2_SRS |
e01402b1 | 1121 | /* |
193dd2ce | 1122 | * MIPSR2 shadow register set allocation |
e01402b1 RB |
1123 | * FIXME: SMP... |
1124 | */ | |
1125 | ||
193dd2ce RB |
1126 | static struct shadow_registers { |
1127 | /* | |
1128 | * Number of shadow register sets supported | |
1129 | */ | |
1130 | unsigned long sr_supported; | |
1131 | /* | |
1132 | * Bitmap of allocated shadow registers | |
1133 | */ | |
1134 | unsigned long sr_allocated; | |
e01402b1 RB |
1135 | } shadow_registers; |
1136 | ||
bb12d612 | 1137 | static void mips_srs_init(void) |
e01402b1 | 1138 | { |
e01402b1 | 1139 | shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1; |
7acb783e RB |
1140 | printk(KERN_INFO "%d MIPSR2 register sets available\n", |
1141 | shadow_registers.sr_supported); | |
e01402b1 | 1142 | shadow_registers.sr_allocated = 1; /* Set 0 used by kernel */ |
e01402b1 RB |
1143 | } |
1144 | ||
1145 | int mips_srs_max(void) | |
1146 | { | |
1147 | return shadow_registers.sr_supported; | |
1148 | } | |
1149 | ||
ff3eab2a | 1150 | int mips_srs_alloc(void) |
e01402b1 RB |
1151 | { |
1152 | struct shadow_registers *sr = &shadow_registers; | |
e01402b1 RB |
1153 | int set; |
1154 | ||
193dd2ce RB |
1155 | again: |
1156 | set = find_first_zero_bit(&sr->sr_allocated, sr->sr_supported); | |
1157 | if (set >= sr->sr_supported) | |
1158 | return -1; | |
e01402b1 | 1159 | |
193dd2ce RB |
1160 | if (test_and_set_bit(set, &sr->sr_allocated)) |
1161 | goto again; | |
e01402b1 | 1162 | |
193dd2ce | 1163 | return set; |
e01402b1 RB |
1164 | } |
1165 | ||
41c594ab | 1166 | void mips_srs_free(int set) |
e01402b1 RB |
1167 | { |
1168 | struct shadow_registers *sr = &shadow_registers; | |
e01402b1 | 1169 | |
193dd2ce | 1170 | clear_bit(set, &sr->sr_allocated); |
e01402b1 RB |
1171 | } |
1172 | ||
b4d05cb9 | 1173 | static void *set_vi_srs_handler(int n, void *addr, int srs) |
e01402b1 RB |
1174 | { |
1175 | unsigned long handler; | |
1176 | unsigned long old_handler = vi_handlers[n]; | |
1177 | u32 *w; | |
1178 | unsigned char *b; | |
1179 | ||
1180 | if (!cpu_has_veic && !cpu_has_vint) | |
1181 | BUG(); | |
1182 | ||
1183 | if (addr == NULL) { | |
1184 | handler = (unsigned long) do_default_vi; | |
1185 | srs = 0; | |
41c594ab | 1186 | } else |
e01402b1 RB |
1187 | handler = (unsigned long) addr; |
1188 | vi_handlers[n] = (unsigned long) addr; | |
1189 | ||
1190 | b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); | |
1191 | ||
1192 | if (srs >= mips_srs_max()) | |
1193 | panic("Shadow register set %d not supported", srs); | |
1194 | ||
1195 | if (cpu_has_veic) { | |
1196 | if (board_bind_eic_interrupt) | |
1197 | board_bind_eic_interrupt (n, srs); | |
41c594ab | 1198 | } else if (cpu_has_vint) { |
e01402b1 RB |
1199 | /* SRSMap is only defined if shadow sets are implemented */ |
1200 | if (mips_srs_max() > 1) | |
1201 | change_c0_srsmap (0xf << n*4, srs << n*4); | |
1202 | } | |
1203 | ||
1204 | if (srs == 0) { | |
1205 | /* | |
1206 | * If no shadow set is selected then use the default handler | |
1207 | * that does normal register saving and a standard interrupt exit | |
1208 | */ | |
1209 | ||
1210 | extern char except_vec_vi, except_vec_vi_lui; | |
1211 | extern char except_vec_vi_ori, except_vec_vi_end; | |
41c594ab RB |
1212 | #ifdef CONFIG_MIPS_MT_SMTC |
1213 | /* | |
1214 | * We need to provide the SMTC vectored interrupt handler | |
1215 | * not only with the address of the handler, but with the | |
1216 | * Status.IM bit to be masked before going there. | |
1217 | */ | |
1218 | extern char except_vec_vi_mori; | |
1219 | const int mori_offset = &except_vec_vi_mori - &except_vec_vi; | |
1220 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
e01402b1 RB |
1221 | const int handler_len = &except_vec_vi_end - &except_vec_vi; |
1222 | const int lui_offset = &except_vec_vi_lui - &except_vec_vi; | |
1223 | const int ori_offset = &except_vec_vi_ori - &except_vec_vi; | |
1224 | ||
1225 | if (handler_len > VECTORSPACING) { | |
1226 | /* | |
1227 | * Sigh... panicing won't help as the console | |
1228 | * is probably not configured :( | |
1229 | */ | |
1230 | panic ("VECTORSPACING too small"); | |
1231 | } | |
1232 | ||
1233 | memcpy (b, &except_vec_vi, handler_len); | |
41c594ab RB |
1234 | #ifdef CONFIG_MIPS_MT_SMTC |
1235 | if (n > 7) | |
1236 | printk("Vector index %d exceeds SMTC maximum\n", n); | |
1237 | w = (u32 *)(b + mori_offset); | |
1238 | *w = (*w & 0xffff0000) | (0x100 << n); | |
1239 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
e01402b1 RB |
1240 | w = (u32 *)(b + lui_offset); |
1241 | *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff); | |
1242 | w = (u32 *)(b + ori_offset); | |
1243 | *w = (*w & 0xffff0000) | ((u32)handler & 0xffff); | |
1244 | flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len)); | |
1245 | } | |
1246 | else { | |
1247 | /* | |
1248 | * In other cases jump directly to the interrupt handler | |
1249 | * | |
1250 | * It is the handlers responsibility to save registers if required | |
1251 | * (eg hi/lo) and return from the exception using "eret" | |
1252 | */ | |
1253 | w = (u32 *)b; | |
1254 | *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */ | |
1255 | *w = 0; | |
1256 | flush_icache_range((unsigned long)b, (unsigned long)(b+8)); | |
1da177e4 | 1257 | } |
e01402b1 | 1258 | |
1da177e4 LT |
1259 | return (void *)old_handler; |
1260 | } | |
1261 | ||
41c594ab | 1262 | void *set_vi_handler(int n, void *addr) |
e01402b1 | 1263 | { |
ff3eab2a | 1264 | return set_vi_srs_handler(n, addr, 0); |
e01402b1 | 1265 | } |
f41ae0b2 RB |
1266 | |
1267 | #else | |
1268 | ||
1269 | static inline void mips_srs_init(void) | |
1270 | { | |
1271 | } | |
1272 | ||
1273 | #endif /* CONFIG_CPU_MIPSR2_SRS */ | |
e01402b1 | 1274 | |
1da177e4 LT |
1275 | /* |
1276 | * This is used by native signal handling | |
1277 | */ | |
1278 | asmlinkage int (*save_fp_context)(struct sigcontext *sc); | |
1279 | asmlinkage int (*restore_fp_context)(struct sigcontext *sc); | |
1280 | ||
1281 | extern asmlinkage int _save_fp_context(struct sigcontext *sc); | |
1282 | extern asmlinkage int _restore_fp_context(struct sigcontext *sc); | |
1283 | ||
1284 | extern asmlinkage int fpu_emulator_save_context(struct sigcontext *sc); | |
1285 | extern asmlinkage int fpu_emulator_restore_context(struct sigcontext *sc); | |
1286 | ||
41c594ab RB |
1287 | #ifdef CONFIG_SMP |
1288 | static int smp_save_fp_context(struct sigcontext *sc) | |
1289 | { | |
1290 | return cpu_has_fpu | |
1291 | ? _save_fp_context(sc) | |
1292 | : fpu_emulator_save_context(sc); | |
1293 | } | |
1294 | ||
1295 | static int smp_restore_fp_context(struct sigcontext *sc) | |
1296 | { | |
1297 | return cpu_has_fpu | |
1298 | ? _restore_fp_context(sc) | |
1299 | : fpu_emulator_restore_context(sc); | |
1300 | } | |
1301 | #endif | |
1302 | ||
1da177e4 LT |
1303 | static inline void signal_init(void) |
1304 | { | |
41c594ab RB |
1305 | #ifdef CONFIG_SMP |
1306 | /* For now just do the cpu_has_fpu check when the functions are invoked */ | |
1307 | save_fp_context = smp_save_fp_context; | |
1308 | restore_fp_context = smp_restore_fp_context; | |
1309 | #else | |
1da177e4 LT |
1310 | if (cpu_has_fpu) { |
1311 | save_fp_context = _save_fp_context; | |
1312 | restore_fp_context = _restore_fp_context; | |
1313 | } else { | |
1314 | save_fp_context = fpu_emulator_save_context; | |
1315 | restore_fp_context = fpu_emulator_restore_context; | |
1316 | } | |
41c594ab | 1317 | #endif |
1da177e4 LT |
1318 | } |
1319 | ||
1320 | #ifdef CONFIG_MIPS32_COMPAT | |
1321 | ||
1322 | /* | |
1323 | * This is used by 32-bit signal stuff on the 64-bit kernel | |
1324 | */ | |
1325 | asmlinkage int (*save_fp_context32)(struct sigcontext32 *sc); | |
1326 | asmlinkage int (*restore_fp_context32)(struct sigcontext32 *sc); | |
1327 | ||
1328 | extern asmlinkage int _save_fp_context32(struct sigcontext32 *sc); | |
1329 | extern asmlinkage int _restore_fp_context32(struct sigcontext32 *sc); | |
1330 | ||
1331 | extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 *sc); | |
1332 | extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 *sc); | |
1333 | ||
1334 | static inline void signal32_init(void) | |
1335 | { | |
1336 | if (cpu_has_fpu) { | |
1337 | save_fp_context32 = _save_fp_context32; | |
1338 | restore_fp_context32 = _restore_fp_context32; | |
1339 | } else { | |
1340 | save_fp_context32 = fpu_emulator_save_context32; | |
1341 | restore_fp_context32 = fpu_emulator_restore_context32; | |
1342 | } | |
1343 | } | |
1344 | #endif | |
1345 | ||
1346 | extern void cpu_cache_init(void); | |
1347 | extern void tlb_init(void); | |
1d40cfcd | 1348 | extern void flush_tlb_handlers(void); |
1da177e4 LT |
1349 | |
1350 | void __init per_cpu_trap_init(void) | |
1351 | { | |
1352 | unsigned int cpu = smp_processor_id(); | |
1353 | unsigned int status_set = ST0_CU0; | |
41c594ab RB |
1354 | #ifdef CONFIG_MIPS_MT_SMTC |
1355 | int secondaryTC = 0; | |
1356 | int bootTC = (cpu == 0); | |
1357 | ||
1358 | /* | |
1359 | * Only do per_cpu_trap_init() for first TC of Each VPE. | |
1360 | * Note that this hack assumes that the SMTC init code | |
1361 | * assigns TCs consecutively and in ascending order. | |
1362 | */ | |
1363 | ||
1364 | if (((read_c0_tcbind() & TCBIND_CURTC) != 0) && | |
1365 | ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id)) | |
1366 | secondaryTC = 1; | |
1367 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 LT |
1368 | |
1369 | /* | |
1370 | * Disable coprocessors and select 32-bit or 64-bit addressing | |
1371 | * and the 16/32 or 32/32 FPR register model. Reset the BEV | |
1372 | * flag that some firmware may have left set and the TS bit (for | |
1373 | * IP27). Set XX for ISA IV code to work. | |
1374 | */ | |
875d43e7 | 1375 | #ifdef CONFIG_64BIT |
1da177e4 LT |
1376 | status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; |
1377 | #endif | |
1378 | if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV) | |
1379 | status_set |= ST0_XX; | |
b38c7399 | 1380 | change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, |
1da177e4 LT |
1381 | status_set); |
1382 | ||
e50c0a8f RB |
1383 | if (cpu_has_dsp) |
1384 | set_c0_status(ST0_MX); | |
1385 | ||
e01402b1 RB |
1386 | #ifdef CONFIG_CPU_MIPSR2 |
1387 | write_c0_hwrena (0x0000000f); /* Allow rdhwr to all registers */ | |
1388 | #endif | |
1389 | ||
41c594ab RB |
1390 | #ifdef CONFIG_MIPS_MT_SMTC |
1391 | if (!secondaryTC) { | |
1392 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1393 | ||
1da177e4 | 1394 | /* |
e01402b1 | 1395 | * Interrupt handling. |
1da177e4 | 1396 | */ |
e01402b1 RB |
1397 | if (cpu_has_veic || cpu_has_vint) { |
1398 | write_c0_ebase (ebase); | |
1399 | /* Setting vector spacing enables EI/VI mode */ | |
1400 | change_c0_intctl (0x3e0, VECTORSPACING); | |
1401 | } | |
d03d0a57 RB |
1402 | if (cpu_has_divec) { |
1403 | if (cpu_has_mipsmt) { | |
1404 | unsigned int vpflags = dvpe(); | |
1405 | set_c0_cause(CAUSEF_IV); | |
1406 | evpe(vpflags); | |
1407 | } else | |
1408 | set_c0_cause(CAUSEF_IV); | |
1409 | } | |
41c594ab RB |
1410 | #ifdef CONFIG_MIPS_MT_SMTC |
1411 | } | |
1412 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 LT |
1413 | |
1414 | cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; | |
1415 | TLBMISS_HANDLER_SETUP(); | |
1416 | ||
1417 | atomic_inc(&init_mm.mm_count); | |
1418 | current->active_mm = &init_mm; | |
1419 | BUG_ON(current->mm); | |
1420 | enter_lazy_tlb(&init_mm, current); | |
1421 | ||
41c594ab RB |
1422 | #ifdef CONFIG_MIPS_MT_SMTC |
1423 | if (bootTC) { | |
1424 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1425 | cpu_cache_init(); | |
1426 | tlb_init(); | |
1427 | #ifdef CONFIG_MIPS_MT_SMTC | |
1428 | } | |
1429 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 LT |
1430 | } |
1431 | ||
e01402b1 RB |
1432 | /* Install CPU exception handler */ |
1433 | void __init set_handler (unsigned long offset, void *addr, unsigned long size) | |
1434 | { | |
1435 | memcpy((void *)(ebase + offset), addr, size); | |
1436 | flush_icache_range(ebase + offset, ebase + offset + size); | |
1437 | } | |
1438 | ||
1439 | /* Install uncached CPU exception handler */ | |
1440 | void __init set_uncached_handler (unsigned long offset, void *addr, unsigned long size) | |
1441 | { | |
1442 | #ifdef CONFIG_32BIT | |
1443 | unsigned long uncached_ebase = KSEG1ADDR(ebase); | |
1444 | #endif | |
1445 | #ifdef CONFIG_64BIT | |
1446 | unsigned long uncached_ebase = TO_UNCAC(ebase); | |
1447 | #endif | |
1448 | ||
1449 | memcpy((void *)(uncached_ebase + offset), addr, size); | |
1450 | } | |
1451 | ||
1da177e4 LT |
1452 | void __init trap_init(void) |
1453 | { | |
1454 | extern char except_vec3_generic, except_vec3_r4000; | |
1da177e4 LT |
1455 | extern char except_vec4; |
1456 | unsigned long i; | |
1457 | ||
e01402b1 RB |
1458 | if (cpu_has_veic || cpu_has_vint) |
1459 | ebase = (unsigned long) alloc_bootmem_low_pages (0x200 + VECTORSPACING*64); | |
1460 | else | |
1461 | ebase = CAC_BASE; | |
1462 | ||
e01402b1 | 1463 | mips_srs_init(); |
e01402b1 | 1464 | |
1da177e4 LT |
1465 | per_cpu_trap_init(); |
1466 | ||
1467 | /* | |
1468 | * Copy the generic exception handlers to their final destination. | |
1469 | * This will be overriden later as suitable for a particular | |
1470 | * configuration. | |
1471 | */ | |
e01402b1 | 1472 | set_handler(0x180, &except_vec3_generic, 0x80); |
1da177e4 LT |
1473 | |
1474 | /* | |
1475 | * Setup default vectors | |
1476 | */ | |
1477 | for (i = 0; i <= 31; i++) | |
1478 | set_except_vector(i, handle_reserved); | |
1479 | ||
1480 | /* | |
1481 | * Copy the EJTAG debug exception vector handler code to it's final | |
1482 | * destination. | |
1483 | */ | |
e01402b1 RB |
1484 | if (cpu_has_ejtag && board_ejtag_handler_setup) |
1485 | board_ejtag_handler_setup (); | |
1da177e4 LT |
1486 | |
1487 | /* | |
1488 | * Only some CPUs have the watch exceptions. | |
1489 | */ | |
1490 | if (cpu_has_watch) | |
1491 | set_except_vector(23, handle_watch); | |
1492 | ||
1493 | /* | |
e01402b1 | 1494 | * Initialise interrupt handlers |
1da177e4 | 1495 | */ |
e01402b1 RB |
1496 | if (cpu_has_veic || cpu_has_vint) { |
1497 | int nvec = cpu_has_veic ? 64 : 8; | |
1498 | for (i = 0; i < nvec; i++) | |
ff3eab2a | 1499 | set_vi_handler(i, NULL); |
e01402b1 RB |
1500 | } |
1501 | else if (cpu_has_divec) | |
1502 | set_handler(0x200, &except_vec4, 0x8); | |
1da177e4 LT |
1503 | |
1504 | /* | |
1505 | * Some CPUs can enable/disable for cache parity detection, but does | |
1506 | * it different ways. | |
1507 | */ | |
1508 | parity_protection_init(); | |
1509 | ||
1510 | /* | |
1511 | * The Data Bus Errors / Instruction Bus Errors are signaled | |
1512 | * by external hardware. Therefore these two exceptions | |
1513 | * may have board specific handlers. | |
1514 | */ | |
1515 | if (board_be_init) | |
1516 | board_be_init(); | |
1517 | ||
e4ac58af | 1518 | set_except_vector(0, handle_int); |
1da177e4 LT |
1519 | set_except_vector(1, handle_tlbm); |
1520 | set_except_vector(2, handle_tlbl); | |
1521 | set_except_vector(3, handle_tlbs); | |
1522 | ||
1523 | set_except_vector(4, handle_adel); | |
1524 | set_except_vector(5, handle_ades); | |
1525 | ||
1526 | set_except_vector(6, handle_ibe); | |
1527 | set_except_vector(7, handle_dbe); | |
1528 | ||
1529 | set_except_vector(8, handle_sys); | |
1530 | set_except_vector(9, handle_bp); | |
1531 | set_except_vector(10, handle_ri); | |
1532 | set_except_vector(11, handle_cpu); | |
1533 | set_except_vector(12, handle_ov); | |
1534 | set_except_vector(13, handle_tr); | |
1da177e4 LT |
1535 | |
1536 | if (current_cpu_data.cputype == CPU_R6000 || | |
1537 | current_cpu_data.cputype == CPU_R6000A) { | |
1538 | /* | |
1539 | * The R6000 is the only R-series CPU that features a machine | |
1540 | * check exception (similar to the R4000 cache error) and | |
1541 | * unaligned ldc1/sdc1 exception. The handlers have not been | |
1542 | * written yet. Well, anyway there is no R6000 machine on the | |
1543 | * current list of targets for Linux/MIPS. | |
1544 | * (Duh, crap, there is someone with a triple R6k machine) | |
1545 | */ | |
1546 | //set_except_vector(14, handle_mc); | |
1547 | //set_except_vector(15, handle_ndc); | |
1548 | } | |
1549 | ||
e01402b1 RB |
1550 | |
1551 | if (board_nmi_handler_setup) | |
1552 | board_nmi_handler_setup(); | |
1553 | ||
e50c0a8f RB |
1554 | if (cpu_has_fpu && !cpu_has_nofpuex) |
1555 | set_except_vector(15, handle_fpe); | |
1556 | ||
1557 | set_except_vector(22, handle_mdmx); | |
1558 | ||
1559 | if (cpu_has_mcheck) | |
1560 | set_except_vector(24, handle_mcheck); | |
1561 | ||
340ee4b9 RB |
1562 | if (cpu_has_mipsmt) |
1563 | set_except_vector(25, handle_mt); | |
1564 | ||
e50c0a8f RB |
1565 | if (cpu_has_dsp) |
1566 | set_except_vector(26, handle_dsp); | |
1567 | ||
1568 | if (cpu_has_vce) | |
1569 | /* Special exception: R4[04]00 uses also the divec space. */ | |
1570 | memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100); | |
1571 | else if (cpu_has_4kex) | |
1572 | memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80); | |
1573 | else | |
1574 | memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80); | |
1575 | ||
1da177e4 LT |
1576 | signal_init(); |
1577 | #ifdef CONFIG_MIPS32_COMPAT | |
1578 | signal32_init(); | |
1579 | #endif | |
1580 | ||
e01402b1 | 1581 | flush_icache_range(ebase, ebase + 0x400); |
1d40cfcd | 1582 | flush_tlb_handlers(); |
1da177e4 | 1583 | } |