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futex: Add sys_futex_wake()
[linux-2.6-block.git] / arch / mips / kernel / traps.c
CommitLineData
1da177e4
LT		 1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
36ccf1c0 6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
1da177e4
LT		 7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
60b0d655 11 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
2a0b24f5 12 * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved.
b08a9c95 13 * Copyright (C) 2014, Imagination Technologies Ltd.
1da177e4 14 */
ed2d72c1 15#include <linux/bitops.h>
8e8a52ed 16#include <linux/bug.h>
60b0d655 17#include <linux/compiler.h>
c3fc5cd5 18#include <linux/context_tracking.h>
ae4ce454 19#include <linux/cpu_pm.h>
7aa1c8f4 20#include <linux/kexec.h>
1da177e4 21#include <linux/init.h>
8742cd23 22#include <linux/kernel.h>
f9ded569 23#include <linux/module.h>
9f3b8081 24#include <linux/extable.h>
1da177e4 25#include <linux/mm.h>
68e21be2 26#include <linux/sched/mm.h>
b17b0153 27#include <linux/sched/debug.h>
1da177e4 28#include <linux/smp.h>
1da177e4
LT		 29#include <linux/spinlock.h>
30#include <linux/kallsyms.h>
bcec54bf 31#include <linux/memblock.h>
d4fd1989 32#include <linux/interrupt.h>
39b8d525 33#include <linux/ptrace.h>
88547001
JW		 34#include <linux/kgdb.h>
35#include <linux/kdebug.h>
c1bf207d 36#include <linux/kprobes.h>
69f3a7de 37#include <linux/notifier.h>
5dd11d5d 38#include <linux/kdb.h>
ca4d3e67 39#include <linux/irq.h>
7f788d2d 40#include <linux/perf_event.h>
1da177e4 41
a13c9962 42#include <asm/addrspace.h>
1da177e4
LT		 43#include <asm/bootinfo.h>
44#include <asm/branch.h>
45#include <asm/break.h>
69f3a7de 46#include <asm/cop2.h>
1da177e4 47#include <asm/cpu.h>
69f24d17 48#include <asm/cpu-type.h>
e50c0a8f 49#include <asm/dsp.h>
1da177e4 50#include <asm/fpu.h>
ba3049ed 51#include <asm/fpu_emulator.h>
bdc92d74 52#include <asm/idle.h>
b6d18e77 53#include <asm/isa-rev.h>
e83f7e02 54#include <asm/mips-cps.h>
b0a668fb 55#include <asm/mips-r2-to-r6-emul.h>
340ee4b9
RB		 56#include <asm/mipsregs.h>
57#include <asm/mipsmtregs.h>
1da177e4 58#include <asm/module.h>
1db1af84 59#include <asm/msa.h>
1da177e4
LT		 60#include <asm/ptrace.h>
61#include <asm/sections.h>
3b143cca 62#include <asm/siginfo.h>
1da177e4
LT		 63#include <asm/tlbdebug.h>
64#include <asm/traps.h>
7c0f6ba6 65#include <linux/uaccess.h>
b67b2b70 66#include <asm/watch.h>
1da177e4 67#include <asm/mmu_context.h>
1da177e4 68#include <asm/types.h>
1df0f0ff 69#include <asm/stacktrace.h>
4bcb4ad6 70#include <asm/tlbex.h>
92bbe1b9 71#include <asm/uasm.h>
1da177e4 72
ec7a9318
WX		 73#include <asm/mach-loongson64/cpucfg-emul.h>
74
45deb5fa
TB		 75#include "access-helper.h"
76
c65a5480 77extern void check_wait(void);
c65a5480 78extern asmlinkage void rollback_handle_int(void);
e4ac58af 79extern asmlinkage void handle_int(void);
1da177e4
LT		 80extern asmlinkage void handle_adel(void);
81extern asmlinkage void handle_ades(void);
82extern asmlinkage void handle_ibe(void);
83extern asmlinkage void handle_dbe(void);
84extern asmlinkage void handle_sys(void);
85extern asmlinkage void handle_bp(void);
86extern asmlinkage void handle_ri(void);
5a341331 87extern asmlinkage void handle_ri_rdhwr_tlbp(void);
5b10496b 88extern asmlinkage void handle_ri_rdhwr(void);
1da177e4
LT		 89extern asmlinkage void handle_cpu(void);
90extern asmlinkage void handle_ov(void);
91extern asmlinkage void handle_tr(void);
2bcb3fbc 92extern asmlinkage void handle_msa_fpe(void);
1da177e4 93extern asmlinkage void handle_fpe(void);
75b5b5e0 94extern asmlinkage void handle_ftlb(void);
bc6e8dc1 95extern asmlinkage void handle_gsexc(void);
1db1af84 96extern asmlinkage void handle_msa(void);
1da177e4
LT		 97extern asmlinkage void handle_mdmx(void);
98extern asmlinkage void handle_watch(void);
340ee4b9 99extern asmlinkage void handle_mt(void);
e50c0a8f 100extern asmlinkage void handle_dsp(void);
1da177e4
LT		 101extern asmlinkage void handle_mcheck(void);
102extern asmlinkage void handle_reserved(void);
5890f70f 103extern void tlb_do_page_fault_0(void);
1da177e4 104
1da177e4 105void (*board_be_init)(void);
1f761b3e 106static int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
e01402b1
RB		 107void (*board_nmi_handler_setup)(void);
108void (*board_ejtag_handler_setup)(void);
109void (*board_bind_eic_interrupt)(int irq, int regset);
6fb97eff 110void (*board_ebase_setup)(void);
078a55fc 111void(*board_cache_error_setup)(void);
1da177e4 112
1f761b3e
FF		 113void mips_set_be_handler(int (*handler)(struct pt_regs *regs, int is_fixup))
114{
115 board_be_handler = handler;
116}
117EXPORT_SYMBOL_GPL(mips_set_be_handler);
118
45deb5fa
TB		 119static void show_raw_backtrace(unsigned long reg29, const char *loglvl,
120 bool user)
e889d78f 121{
39b8d525 122 unsigned long *sp = (unsigned long *)(reg29 & ~3);
e889d78f
AN		 123 unsigned long addr;
124
96f0458a 125 printk("%sCall Trace:", loglvl);
e889d78f 126#ifdef CONFIG_KALLSYMS
96f0458a 127 printk("%s\n", loglvl);
e889d78f 128#endif
10220c88 129 while (!kstack_end(sp)) {
45deb5fa 130 if (__get_addr(&addr, sp++, user)) {
96f0458a 131 printk("%s (Bad stack address)", loglvl);
10220c88 132 break;
39b8d525 133 }
10220c88 134 if (__kernel_text_address(addr))
96f0458a 135 print_ip_sym(loglvl, addr);
e889d78f 136 }
96f0458a 137 printk("%s\n", loglvl);
e889d78f
AN		 138}
139
f66686f7 140#ifdef CONFIG_KALLSYMS
1df0f0ff 141int raw_show_trace;
f66686f7
AN		 142static int __init set_raw_show_trace(char *str)
143{
144 raw_show_trace = 1;
145 return 1;
146}
147__setup("raw_show_trace", set_raw_show_trace);
1df0f0ff 148#endif
4d157d5e 149
96f0458a 150static void show_backtrace(struct task_struct *task, const struct pt_regs *regs,
45deb5fa 151 const char *loglvl, bool user)
f66686f7 152{
4d157d5e
FBH		 153 unsigned long sp = regs->regs[29];
154 unsigned long ra = regs->regs[31];
f66686f7 155 unsigned long pc = regs->cp0_epc;
f66686f7 156
e909be82
VW		 157 if (!task)
158 task = current;
159
81a76d71 160 if (raw_show_trace || user_mode(regs) || !__kernel_text_address(pc)) {
45deb5fa 161 show_raw_backtrace(sp, loglvl, user);
f66686f7
AN		 162 return;
163 }
96f0458a 164 printk("%sCall Trace:\n", loglvl);
4d157d5e 165 do {
96f0458a 166 print_ip_sym(loglvl, pc);
1924600c 167 pc = unwind_stack(task, &sp, pc, &ra);
4d157d5e 168 } while (pc);
bcf084de 169 pr_cont("\n");
f66686f7 170}
f66686f7 171
1da177e4
LT		 172/*
173 * This routine abuses get_user()/put_user() to reference pointers
174 * with at least a bit of error checking ...
175 */
eae23f2c 176static void show_stacktrace(struct task_struct *task,
45deb5fa 177 const struct pt_regs *regs, const char *loglvl, bool user)
1da177e4
LT		 178{
179 const int field = 2 * sizeof(unsigned long);
45deb5fa 180 unsigned long stackdata;
1da177e4 181 int i;
45deb5fa 182 unsigned long *sp = (unsigned long *)regs->regs[29];
1da177e4 183
96f0458a 184 printk("%sStack :", loglvl);
1da177e4
LT		 185 i = 0;
186 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
fe4e09e7
MR		 187 if (i && ((i % (64 / field)) == 0)) {
188 pr_cont("\n");
96f0458a 189 printk("%s ", loglvl);
fe4e09e7 190 }
1da177e4 191 if (i > 39) {
fe4e09e7 192 pr_cont(" ...");
1da177e4
LT		 193 break;
194 }
195
45deb5fa 196 if (__get_addr(&stackdata, sp++, user)) {
fe4e09e7 197 pr_cont(" (Bad stack address)");
1da177e4
LT		 198 break;
199 }
200
fe4e09e7 201 pr_cont(" %0*lx", field, stackdata);
1da177e4
LT		 202 i++;
203 }
fe4e09e7 204 pr_cont("\n");
45deb5fa 205 show_backtrace(task, regs, loglvl, user);
f66686f7
AN		 206}
207
9cb8f069 208void show_stack(struct task_struct *task, unsigned long *sp, const char *loglvl)
f66686f7
AN		 209{
210 struct pt_regs regs;
85423636
JH		 211
212 regs.cp0_status = KSU_KERNEL;
f66686f7
AN		 213 if (sp) {
214 regs.regs[29] = (unsigned long)sp;
215 regs.regs[31] = 0;
216 regs.cp0_epc = 0;
217 } else {
218 if (task && task != current) {
219 regs.regs[29] = task->thread.reg29;
220 regs.regs[31] = 0;
221 regs.cp0_epc = task->thread.reg31;
222 } else {
223 prepare_frametrace(&regs);
224 }
225 }
45deb5fa 226 show_stacktrace(task, &regs, loglvl, false);
1da177e4
LT		 227}
228
45deb5fa 229static void show_code(void *pc, bool user)
1da177e4
LT		 230{
231 long i;
45deb5fa 232 unsigned short *pc16 = NULL;
1da177e4 233
41000c58 234 printk("Code:");
1da177e4 235
39b8d525 236 if ((unsigned long)pc & 1)
45deb5fa
TB		 237 pc16 = (u16 *)((unsigned long)pc & ~1);
238
1da177e4 239 for(i = -3 ; i < 6 ; i++) {
45deb5fa
TB		 240 if (pc16) {
241 u16 insn16;
242
243 if (__get_inst16(&insn16, pc16 + i, user))
244 goto bad_address;
245
246 pr_cont("%c%04x%c", (i?' ':'<'), insn16, (i?' ':'>'));
247 } else {
248 u32 insn32;
249
250 if (__get_inst32(&insn32, (u32 *)pc + i, user))
251 goto bad_address;
252
253 pr_cont("%c%08x%c", (i?' ':'<'), insn32, (i?' ':'>'));
1da177e4 254 }
1da177e4 255 }
41000c58 256 pr_cont("\n");
45deb5fa
TB		 257 return;
258
259bad_address:
260 pr_cont(" (Bad address in epc)\n\n");
1da177e4
LT		 261}
262
eae23f2c 263static void __show_regs(const struct pt_regs *regs)
1da177e4
LT		 264{
265 const int field = 2 * sizeof(unsigned long);
266 unsigned int cause = regs->cp0_cause;
37dd3818 267 unsigned int exccode;
1da177e4
LT		 268 int i;
269
a43cb95d 270 show_regs_print_info(KERN_DEFAULT);
1da177e4
LT		 271
272 /*
273 * Saved main processor registers
274 */
275 for (i = 0; i < 32; ) {
276 if ((i % 4) == 0)
277 printk("$%2d :", i);
278 if (i == 0)
752f5499 279 pr_cont(" %0*lx", field, 0UL);
1da177e4 280 else if (i == 26 || i == 27)
752f5499 281 pr_cont(" %*s", field, "");
1da177e4 282 else
752f5499 283 pr_cont(" %0*lx", field, regs->regs[i]);
1da177e4
LT		 284
285 i++;
286 if ((i % 4) == 0)
752f5499 287 pr_cont("\n");
1da177e4
LT		 288 }
289
9693a853
FBH		 290#ifdef CONFIG_CPU_HAS_SMARTMIPS
291 printk("Acx : %0*lx\n", field, regs->acx);
292#endif
b6d18e77
PB		 293 if (MIPS_ISA_REV < 6) {
294 printk("Hi : %0*lx\n", field, regs->hi);
295 printk("Lo : %0*lx\n", field, regs->lo);
296 }
1da177e4
LT		 297
298 /*
299 * Saved cp0 registers
300 */
b012cffe
RB		 301 printk("epc : %0*lx %pS\n", field, regs->cp0_epc,
302 (void *) regs->cp0_epc);
b012cffe
RB		 303 printk("ra : %0*lx %pS\n", field, regs->regs[31],
304 (void *) regs->regs[31]);
1da177e4 305
70342287 306 printk("Status: %08x ", (uint32_t) regs->cp0_status);
1da177e4 307
1990e542 308 if (cpu_has_3kex) {
3b2396d9 309 if (regs->cp0_status & ST0_KUO)
752f5499 310 pr_cont("KUo ");
3b2396d9 311 if (regs->cp0_status & ST0_IEO)
752f5499 312 pr_cont("IEo ");
3b2396d9 313 if (regs->cp0_status & ST0_KUP)
752f5499 314 pr_cont("KUp ");
3b2396d9 315 if (regs->cp0_status & ST0_IEP)
752f5499 316 pr_cont("IEp ");
3b2396d9 317 if (regs->cp0_status & ST0_KUC)
752f5499 318 pr_cont("KUc ");
3b2396d9 319 if (regs->cp0_status & ST0_IEC)
752f5499 320 pr_cont("IEc ");
1990e542 321 } else if (cpu_has_4kex) {
3b2396d9 322 if (regs->cp0_status & ST0_KX)
752f5499 323 pr_cont("KX ");
3b2396d9 324 if (regs->cp0_status & ST0_SX)
752f5499 325 pr_cont("SX ");
3b2396d9 326 if (regs->cp0_status & ST0_UX)
752f5499 327 pr_cont("UX ");
3b2396d9
MR		 328 switch (regs->cp0_status & ST0_KSU) {
329 case KSU_USER:
752f5499 330 pr_cont("USER ");
3b2396d9
MR		 331 break;
332 case KSU_SUPERVISOR:
752f5499 333 pr_cont("SUPERVISOR ");
3b2396d9
MR		 334 break;
335 case KSU_KERNEL:
752f5499 336 pr_cont("KERNEL ");
3b2396d9
MR		 337 break;
338 default:
752f5499 339 pr_cont("BAD_MODE ");
3b2396d9
MR		 340 break;
341 }
342 if (regs->cp0_status & ST0_ERL)
752f5499 343 pr_cont("ERL ");
3b2396d9 344 if (regs->cp0_status & ST0_EXL)
752f5499 345 pr_cont("EXL ");
3b2396d9 346 if (regs->cp0_status & ST0_IE)
752f5499 347 pr_cont("IE ");
1da177e4 348 }
752f5499 349 pr_cont("\n");
1da177e4 350
37dd3818
PG		 351 exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
352 printk("Cause : %08x (ExcCode %02x)\n", cause, exccode);
1da177e4 353
37dd3818 354 if (1 <= exccode && exccode <= 5)
1da177e4
LT		 355 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
356
9966db25
RB		 357 printk("PrId : %08x (%s)\n", read_c0_prid(),
358 cpu_name_string());
1da177e4
LT		 359}
360
eae23f2c
RB		 361/*
362 * FIXME: really the generic show_regs should take a const pointer argument.
363 */
364void show_regs(struct pt_regs *regs)
365{
49881542 366 __show_regs(regs);
5a267832 367 dump_stack();
eae23f2c
RB		 368}
369
c1bf207d 370void show_registers(struct pt_regs *regs)
1da177e4 371{
39b8d525
RB		 372 const int field = 2 * sizeof(unsigned long);
373
eae23f2c 374 __show_regs(regs);
1da177e4 375 print_modules();
39b8d525
RB		 376 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n",
377 current->comm, current->pid, current_thread_info(), current,
378 field, current_thread_info()->tp_value);
379 if (cpu_has_userlocal) {
380 unsigned long tls;
381
382 tls = read_c0_userlocal();
383 if (tls != current_thread_info()->tp_value)
384 printk("*HwTLS: %0*lx\n", field, tls);
385 }
386
45deb5fa
TB		 387 show_stacktrace(current, regs, KERN_DEFAULT, user_mode(regs));
388 show_code((void *)regs->cp0_epc, user_mode(regs));
1da177e4
LT		 389 printk("\n");
390}
391
4d85f6af 392static DEFINE_RAW_SPINLOCK(die_lock);
1da177e4 393
70dc6f04 394void __noreturn die(const char *str, struct pt_regs *regs)
1da177e4
LT		 395{
396 static int die_counter;
ce384d83 397 int sig = SIGSEGV;
1da177e4 398
8742cd23
NL		 399 oops_enter();
400
e3b28831 401 if (notify_die(DIE_OOPS, str, regs, 0, current->thread.trap_nr,
dc73e4c1 402 SIGSEGV) == NOTIFY_STOP)
10423c91 403 sig = 0;
5dd11d5d 404
1da177e4 405 console_verbose();
4d85f6af 406 raw_spin_lock_irq(&die_lock);
41c594ab 407 bust_spinlocks(1);
ce384d83 408
178086c8 409 printk("%s[#%d]:\n", str, ++die_counter);
1da177e4 410 show_registers(regs);
373d4d09 411 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
4d85f6af 412 raw_spin_unlock_irq(&die_lock);
d4fd1989 413
8742cd23
NL		 414 oops_exit();
415
d4fd1989
MB		 416 if (in_interrupt())
417 panic("Fatal exception in interrupt");
418
99a7a234 419 if (panic_on_oops)
d4fd1989 420 panic("Fatal exception");
d4fd1989 421
7aa1c8f4
RB		 422 if (regs && kexec_should_crash(current))
423 crash_kexec(regs);
424
0e25498f 425 make_task_dead(sig);
1da177e4
LT		 426}
427
0510617b
TB		 428extern struct exception_table_entry __start___dbe_table[];
429extern struct exception_table_entry __stop___dbe_table[];
1da177e4 430
b6dcec9b
RB		 431__asm__(
432" .section __dbe_table, \"a\"\n"
433" .previous \n");
1da177e4
LT		 434
435/* Given an address, look for it in the exception tables. */
436static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
437{
438 const struct exception_table_entry *e;
439
a94c33dd
TM		 440 e = search_extable(__start___dbe_table,
441 __stop___dbe_table - __start___dbe_table, addr);
1da177e4
LT		 442 if (!e)
443 e = search_module_dbetables(addr);
444 return e;
445}
446
447asmlinkage void do_be(struct pt_regs *regs)
448{
449 const int field = 2 * sizeof(unsigned long);
450 const struct exception_table_entry *fixup = NULL;
451 int data = regs->cp0_cause & 4;
452 int action = MIPS_BE_FATAL;
c3fc5cd5 453 enum ctx_state prev_state;
1da177e4 454
c3fc5cd5 455 prev_state = exception_enter();
70342287 456 /* XXX For now. Fixme, this searches the wrong table ... */
1da177e4
LT		 457 if (data && !user_mode(regs))
458 fixup = search_dbe_tables(exception_epc(regs));
459
460 if (fixup)
461 action = MIPS_BE_FIXUP;
462
463 if (board_be_handler)
28fc582c 464 action = board_be_handler(regs, fixup != NULL);
dabdc185
PB		 465 else
466 mips_cm_error_report();
1da177e4
LT		 467
468 switch (action) {
469 case MIPS_BE_DISCARD:
c3fc5cd5 470 goto out;
1da177e4
LT		 471 case MIPS_BE_FIXUP:
472 if (fixup) {
473 regs->cp0_epc = fixup->nextinsn;
c3fc5cd5 474 goto out;
1da177e4
LT		 475 }
476 break;
477 default:
478 break;
479 }
480
481 /*
482 * Assume it would be too dangerous to continue ...
483 */
484 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
485 data ? "Data" : "Instruction",
486 field, regs->cp0_epc, field, regs->regs[31]);
e3b28831 487 if (notify_die(DIE_OOPS, "bus error", regs, 0, current->thread.trap_nr,
dc73e4c1 488 SIGBUS) == NOTIFY_STOP)
c3fc5cd5 489 goto out;
88547001 490
1da177e4 491 die_if_kernel("Oops", regs);
3cf5d076 492 force_sig(SIGBUS);
c3fc5cd5
RB		 493
494out:
495 exception_exit(prev_state);
1da177e4
LT		 496}
497
1da177e4 498/*
60b0d655 499 * ll/sc, rdhwr, sync emulation
1da177e4
LT		 500 */
501
502#define OPCODE 0xfc000000
503#define BASE 0x03e00000
504#define RT 0x001f0000
505#define OFFSET 0x0000ffff
506#define LL 0xc0000000
507#define SC 0xe0000000
60b0d655 508#define SPEC0 0x00000000
3c37026d
RB		 509#define SPEC3 0x7c000000
510#define RD 0x0000f800
511#define FUNC 0x0000003f
60b0d655 512#define SYNC 0x0000000f
3c37026d 513#define RDHWR 0x0000003b
1da177e4 514
2a0b24f5
SH		 515/* microMIPS definitions */
516#define MM_POOL32A_FUNC 0xfc00ffff
517#define MM_RDHWR 0x00006b3c
518#define MM_RS 0x001f0000
519#define MM_RT 0x03e00000
520
1da177e4
LT		 521/*
522 * The ll_bit is cleared by r*_switch.S
523 */
524
f1e39a4a
RB		 525unsigned int ll_bit;
526struct task_struct *ll_task;
1da177e4 527
60b0d655 528static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode)
1da177e4 529{
fe00f943 530 unsigned long value, __user *vaddr;
1da177e4 531 long offset;
1da177e4
LT		 532
533 /*
534 * analyse the ll instruction that just caused a ri exception
535 * and put the referenced address to addr.
536 */
537
538 /* sign extend offset */
539 offset = opcode & OFFSET;
540 offset <<= 16;
541 offset >>= 16;
542
fe00f943 543 vaddr = (unsigned long __user *)
b9688310 544 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
1da177e4 545
60b0d655
MR		 546 if ((unsigned long)vaddr & 3)
547 return SIGBUS;
548 if (get_user(value, vaddr))
549 return SIGSEGV;
1da177e4
LT		 550
551 preempt_disable();
552
553 if (ll_task == NULL || ll_task == current) {
554 ll_bit = 1;
555 } else {
556 ll_bit = 0;
557 }
558 ll_task = current;
559
560 preempt_enable();
561
562 regs->regs[(opcode & RT) >> 16] = value;
563
60b0d655 564 return 0;
1da177e4
LT		 565}
566
60b0d655 567static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
1da177e4 568{
fe00f943
RB		 569 unsigned long __user *vaddr;
570 unsigned long reg;
1da177e4 571 long offset;
1da177e4
LT		 572
573 /*
574 * analyse the sc instruction that just caused a ri exception
575 * and put the referenced address to addr.
576 */
577
578 /* sign extend offset */
579 offset = opcode & OFFSET;
580 offset <<= 16;
581 offset >>= 16;
582
fe00f943 583 vaddr = (unsigned long __user *)
b9688310 584 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
1da177e4
LT		 585 reg = (opcode & RT) >> 16;
586
60b0d655
MR		 587 if ((unsigned long)vaddr & 3)
588 return SIGBUS;
1da177e4
LT		 589
590 preempt_disable();
591
592 if (ll_bit == 0 || ll_task != current) {
593 regs->regs[reg] = 0;
594 preempt_enable();
60b0d655 595 return 0;
1da177e4
LT		 596 }
597
598 preempt_enable();
599
60b0d655
MR		 600 if (put_user(regs->regs[reg], vaddr))
601 return SIGSEGV;
1da177e4
LT		 602
603 regs->regs[reg] = 1;
604
60b0d655 605 return 0;
1da177e4
LT		 606}
607
608/*
609 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
610 * opcodes are supposed to result in coprocessor unusable exceptions if
611 * executed on ll/sc-less processors. That's the theory. In practice a
612 * few processors such as NEC's VR4100 throw reserved instruction exceptions
613 * instead, so we're doing the emulation thing in both exception handlers.
614 */
60b0d655 615static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
1da177e4 616{
7f788d2d
DCZ		 617 if ((opcode & OPCODE) == LL) {
618 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
a8b0ca17 619 1, regs, 0);
60b0d655 620 return simulate_ll(regs, opcode);
7f788d2d
DCZ		 621 }
622 if ((opcode & OPCODE) == SC) {
623 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
a8b0ca17 624 1, regs, 0);
60b0d655 625 return simulate_sc(regs, opcode);
7f788d2d 626 }
1da177e4 627
60b0d655 628 return -1; /* Must be something else ... */
1da177e4
LT		 629}
630
3c37026d
RB		 631/*
632 * Simulate trapping 'rdhwr' instructions to provide user accessible
1f5826bd 633 * registers not implemented in hardware.
3c37026d 634 */
2a0b24f5 635static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt)
3c37026d 636{
dc8f6029 637 struct thread_info *ti = task_thread_info(current);
3c37026d 638
2a0b24f5
SH		 639 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
640 1, regs, 0);
641 switch (rd) {
aff565aa 642 case MIPS_HWR_CPUNUM: /* CPU number */
2a0b24f5
SH		 643 regs->regs[rt] = smp_processor_id();
644 return 0;
aff565aa 645 case MIPS_HWR_SYNCISTEP: /* SYNCI length */
2a0b24f5
SH		 646 regs->regs[rt] = min(current_cpu_data.dcache.linesz,
647 current_cpu_data.icache.linesz);
648 return 0;
aff565aa 649 case MIPS_HWR_CC: /* Read count register */
2a0b24f5
SH		 650 regs->regs[rt] = read_c0_count();
651 return 0;
aff565aa 652 case MIPS_HWR_CCRES: /* Count register resolution */
69f24d17 653 switch (current_cpu_type()) {
2a0b24f5
SH		 654 case CPU_20KC:
655 case CPU_25KF:
656 regs->regs[rt] = 1;
657 break;
658 default:
659 regs->regs[rt] = 2;
660 }
661 return 0;
aff565aa 662 case MIPS_HWR_ULR: /* Read UserLocal register */
2a0b24f5
SH		 663 regs->regs[rt] = ti->tp_value;
664 return 0;
665 default:
666 return -1;
667 }
668}
669
670static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode)
671{
3c37026d
RB		 672 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
673 int rd = (opcode & RD) >> 11;
674 int rt = (opcode & RT) >> 16;
2a0b24f5
SH		 675
676 simulate_rdhwr(regs, rd, rt);
677 return 0;
678 }
679
680 /* Not ours. */
681 return -1;
682}
683
7aa70471 684static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned int opcode)
2a0b24f5
SH		 685{
686 if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) {
687 int rd = (opcode & MM_RS) >> 16;
688 int rt = (opcode & MM_RT) >> 21;
689 simulate_rdhwr(regs, rd, rt);
690 return 0;
3c37026d
RB		 691 }
692
56ebd51b 693 /* Not ours. */
60b0d655
MR		 694 return -1;
695}
e5679882 696
60b0d655
MR		 697static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
698{
7f788d2d
DCZ		 699 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) {
700 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
a8b0ca17 701 1, regs, 0);
60b0d655 702 return 0;
7f788d2d 703 }
60b0d655
MR		 704
705 return -1; /* Must be something else ... */
3c37026d
RB		 706}
707
ec7a9318
WX		 708/*
709 * Loongson-3 CSR instructions emulation
710 */
711
712#ifdef CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION
713
714#define LWC2 0xc8000000
715#define RS BASE
716#define CSR_OPCODE2 0x00000118
717#define CSR_OPCODE2_MASK 0x000007ff
718#define CSR_FUNC_MASK RT
719#define CSR_FUNC_CPUCFG 0x8
720
721static int simulate_loongson3_cpucfg(struct pt_regs *regs,
722 unsigned int opcode)
723{
724 int op = opcode & OPCODE;
725 int op2 = opcode & CSR_OPCODE2_MASK;
726 int csr_func = (opcode & CSR_FUNC_MASK) >> 16;
727
728 if (op == LWC2 && op2 == CSR_OPCODE2 && csr_func == CSR_FUNC_CPUCFG) {
729 int rd = (opcode & RD) >> 11;
730 int rs = (opcode & RS) >> 21;
731 __u64 sel = regs->regs[rs];
732
733 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
734
70768eba 735 /* Do not emulate on unsupported core models. */
5868347a
XS		 736 preempt_disable();
737 if (!loongson3_cpucfg_emulation_enabled(&current_cpu_data)) {
738 preempt_enable();
70768eba 739 return -1;
5868347a 740 }
ec7a9318
WX		 741 regs->regs[rd] = loongson3_cpucfg_read_synthesized(
742 &current_cpu_data, sel);
5868347a 743 preempt_enable();
ec7a9318
WX		 744 return 0;
745 }
746
747 /* Not ours. */
748 return -1;
749}
750#endif /* CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION */
751
1da177e4
LT		 752asmlinkage void do_ov(struct pt_regs *regs)
753{
c3fc5cd5 754 enum ctx_state prev_state;
1da177e4 755
c3fc5cd5 756 prev_state = exception_enter();
36ccf1c0
RB		 757 die_if_kernel("Integer overflow", regs);
758
2e1661d2 759 force_sig_fault(SIGFPE, FPE_INTOVF, (void __user *)regs->cp0_epc);
c3fc5cd5 760 exception_exit(prev_state);
1da177e4
LT		 761}
762
5328f742
PB		 763#ifdef CONFIG_MIPS_FP_SUPPORT
764
5a1aca44
MR		 765/*
766 * Send SIGFPE according to FCSR Cause bits, which must have already
767 * been masked against Enable bits. This is impotant as Inexact can
768 * happen together with Overflow or Underflow, and `ptrace' can set
769 * any bits.
770 */
771void force_fcr31_sig(unsigned long fcr31, void __user *fault_addr,
772 struct task_struct *tsk)
773{
0bb0a114 774 int si_code = FPE_FLTUNK;
5a1aca44
MR		 775
776 if (fcr31 & FPU_CSR_INV_X)
f43a54a0 777 si_code = FPE_FLTINV;
5a1aca44 778 else if (fcr31 & FPU_CSR_DIV_X)
f43a54a0 779 si_code = FPE_FLTDIV;
5a1aca44 780 else if (fcr31 & FPU_CSR_OVF_X)
f43a54a0 781 si_code = FPE_FLTOVF;
5a1aca44 782 else if (fcr31 & FPU_CSR_UDF_X)
f43a54a0 783 si_code = FPE_FLTUND;
5a1aca44 784 else if (fcr31 & FPU_CSR_INE_X)
f43a54a0 785 si_code = FPE_FLTRES;
b123718b 786
91ca180d 787 force_sig_fault_to_task(SIGFPE, si_code, fault_addr, tsk);
5a1aca44
MR		 788}
789
304acb71 790int process_fpemu_return(int sig, void __user *fault_addr, unsigned long fcr31)
515b029d 791{
f43a54a0 792 int si_code;
304acb71
MR		 793
794 switch (sig) {
795 case 0:
796 return 0;
ad70c13a 797
304acb71 798 case SIGFPE:
5a1aca44 799 force_fcr31_sig(fcr31, fault_addr, current);
515b029d 800 return 1;
304acb71
MR		 801
802 case SIGBUS:
2e1661d2 803 force_sig_fault(SIGBUS, BUS_ADRERR, fault_addr);
304acb71
MR		 804 return 1;
805
806 case SIGSEGV:
d8ed45c5 807 mmap_read_lock(current->mm);
7f7020ac 808 if (vma_lookup(current->mm, (unsigned long)fault_addr))
f43a54a0 809 si_code = SEGV_ACCERR;
304acb71 810 else
f43a54a0 811 si_code = SEGV_MAPERR;
d8ed45c5 812 mmap_read_unlock(current->mm);
2e1661d2 813 force_sig_fault(SIGSEGV, si_code, fault_addr);
304acb71
MR		 814 return 1;
815
816 default:
3cf5d076 817 force_sig(sig);
515b029d 818 return 1;
515b029d
DD		 819 }
820}
821
4227a2d4
PB		 822static int simulate_fp(struct pt_regs *regs, unsigned int opcode,
823 unsigned long old_epc, unsigned long old_ra)
824{
825 union mips_instruction inst = { .word = opcode };
304acb71
MR		 826 void __user *fault_addr;
827 unsigned long fcr31;
4227a2d4
PB		 828 int sig;
829
830 /* If it's obviously not an FP instruction, skip it */
831 switch (inst.i_format.opcode) {
832 case cop1_op:
833 case cop1x_op:
834 case lwc1_op:
835 case ldc1_op:
836 case swc1_op:
837 case sdc1_op:
838 break;
839
840 default:
841 return -1;
842 }
843
844 /*
845 * do_ri skipped over the instruction via compute_return_epc, undo
846 * that for the FPU emulator.
847 */
848 regs->cp0_epc = old_epc;
849 regs->regs[31] = old_ra;
850
4227a2d4
PB		 851 /* Run the emulator */
852 sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1,
853 &fault_addr);
854
443c4403 855 /*
5a1aca44
MR		 856 * We can't allow the emulated instruction to leave any
857 * enabled Cause bits set in $fcr31.
443c4403 858 */
5a1aca44
MR		 859 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31);
860 current->thread.fpu.fcr31 &= ~fcr31;
4227a2d4
PB		 861
862 /* Restore the hardware register state */
863 own_fpu(1);
864
304acb71
MR		 865 /* Send a signal if required. */
866 process_fpemu_return(sig, fault_addr, fcr31);
867
4227a2d4
PB		 868 return 0;
869}
870
1da177e4
LT		 871/*
872 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
873 */
874asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
875{
c3fc5cd5 876 enum ctx_state prev_state;
304acb71
MR		 877 void __user *fault_addr;
878 int sig;
948a34cf 879
c3fc5cd5 880 prev_state = exception_enter();
e3b28831 881 if (notify_die(DIE_FP, "FP exception", regs, 0, current->thread.trap_nr,
dc73e4c1 882 SIGFPE) == NOTIFY_STOP)
c3fc5cd5 883 goto out;
64bedffe
JH		 884
885 /* Clear FCSR.Cause before enabling interrupts */
5a1aca44 886 write_32bit_cp1_register(CP1_STATUS, fcr31 & ~mask_fcr31_x(fcr31));
64bedffe
JH		 887 local_irq_enable();
888
57725f9e
CD		 889 die_if_kernel("FP exception in kernel code", regs);
890
1da177e4 891 if (fcr31 & FPU_CSR_UNI_X) {
1da177e4 892 /*
a3dddd56 893 * Unimplemented operation exception. If we've got the full
1da177e4
LT		 894 * software emulator on-board, let's use it...
895 *
896 * Force FPU to dump state into task/thread context. We're
897 * moving a lot of data here for what is probably a single
898 * instruction, but the alternative is to pre-decode the FP
899 * register operands before invoking the emulator, which seems
900 * a bit extreme for what should be an infrequent event.
901 */
1da177e4
LT		 902
903 /* Run the emulator */
515b029d
DD		 904 sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1,
905 &fault_addr);
1da177e4
LT		 906
907 /*
5a1aca44
MR		 908 * We can't allow the emulated instruction to leave any
909 * enabled Cause bits set in $fcr31.
1da177e4 910 */
5a1aca44
MR		 911 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31);
912 current->thread.fpu.fcr31 &= ~fcr31;
1da177e4
LT		 913
914 /* Restore the hardware register state */
70342287 915 own_fpu(1); /* Using the FPU again. */
304acb71
MR		 916 } else {
917 sig = SIGFPE;
918 fault_addr = (void __user *) regs->cp0_epc;
ed2d72c1 919 }
1da177e4 920
304acb71
MR		 921 /* Send a signal if required. */
922 process_fpemu_return(sig, fault_addr, fcr31);
c3fc5cd5
RB		 923
924out:
925 exception_exit(prev_state);
1da177e4
LT		 926}
927
5328f742
PB		 928/*
929 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
930 * emulated more than some threshold number of instructions, force migration to
931 * a "CPU" that has FP support.
932 */
933static void mt_ase_fp_affinity(void)
934{
935#ifdef CONFIG_MIPS_MT_FPAFF
936 if (mt_fpemul_threshold > 0 &&
937 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) {
938 /*
939 * If there's no FPU present, or if the application has already
940 * restricted the allowed set to exclude any CPUs with FPUs,
941 * we'll skip the procedure.
942 */
3bd37062 943 if (cpumask_intersects(&current->cpus_mask, &mt_fpu_cpumask)) {
5328f742
PB		 944 cpumask_t tmask;
945
946 current->thread.user_cpus_allowed
3bd37062
SAS		 947 = current->cpus_mask;
948 cpumask_and(&tmask, &current->cpus_mask,
5328f742
PB		 949 &mt_fpu_cpumask);
950 set_cpus_allowed_ptr(current, &tmask);
951 set_thread_flag(TIF_FPUBOUND);
952 }
953 }
954#endif /* CONFIG_MIPS_MT_FPAFF */
955}
956
957#else /* !CONFIG_MIPS_FP_SUPPORT */
958
959static int simulate_fp(struct pt_regs *regs, unsigned int opcode,
960 unsigned long old_epc, unsigned long old_ra)
961{
962 return -1;
963}
964
965#endif /* !CONFIG_MIPS_FP_SUPPORT */
966
3b143cca 967void do_trap_or_bp(struct pt_regs *regs, unsigned int code, int si_code,
df270051 968 const char *str)
1da177e4 969{
df270051 970 char b[40];
1da177e4 971
5dd11d5d 972#ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
e3b28831
RB		 973 if (kgdb_ll_trap(DIE_TRAP, str, regs, code, current->thread.trap_nr,
974 SIGTRAP) == NOTIFY_STOP)
5dd11d5d
JW		 975 return;
976#endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
977
e3b28831 978 if (notify_die(DIE_TRAP, str, regs, code, current->thread.trap_nr,
dc73e4c1 979 SIGTRAP) == NOTIFY_STOP)
88547001
JW		 980 return;
981
1da177e4 982 /*
df270051
RB		 983 * A short test says that IRIX 5.3 sends SIGTRAP for all trap
984 * insns, even for trap and break codes that indicate arithmetic
985 * failures. Weird ...
1da177e4
LT		 986 * But should we continue the brokenness??? --macro
987 */
df270051
RB		 988 switch (code) {
989 case BRK_OVERFLOW:
990 case BRK_DIVZERO:
991 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
992 die_if_kernel(b, regs);
f43a54a0
EB		 993 force_sig_fault(SIGFPE,
994 code == BRK_DIVZERO ? FPE_INTDIV : FPE_INTOVF,
2e1661d2 995 (void __user *) regs->cp0_epc);
1da177e4 996 break;
63dc68a8 997 case BRK_BUG:
df270051 998 die_if_kernel("Kernel bug detected", regs);
3cf5d076 999 force_sig(SIGTRAP);
63dc68a8 1000 break;
ba3049ed
RB		 1001 case BRK_MEMU:
1002 /*
1f443779
MR		 1003 * This breakpoint code is used by the FPU emulator to retake
1004 * control of the CPU after executing the instruction from the
1005 * delay slot of an emulated branch.
ba3049ed
RB		 1006 *
1007 * Terminate if exception was recognized as a delay slot return
1008 * otherwise handle as normal.
1009 */
1010 if (do_dsemulret(regs))
1011 return;
1012
1013 die_if_kernel("Math emu break/trap", regs);
3cf5d076 1014 force_sig(SIGTRAP);
ba3049ed 1015 break;
1da177e4 1016 default:
df270051
RB		 1017 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
1018 die_if_kernel(b, regs);
3b143cca 1019 if (si_code) {
2e1661d2 1020 force_sig_fault(SIGTRAP, si_code, NULL);
3b143cca 1021 } else {
3cf5d076 1022 force_sig(SIGTRAP);
3b143cca 1023 }
1da177e4 1024 }
df270051
RB		 1025}
1026
1027asmlinkage void do_bp(struct pt_regs *regs)
1028{
f6a31da5 1029 unsigned long epc = msk_isa16_mode(exception_epc(regs));
df270051 1030 unsigned int opcode, bcode;
c3fc5cd5 1031 enum ctx_state prev_state;
45deb5fa 1032 bool user = user_mode(regs);
2a0b24f5 1033
c3fc5cd5 1034 prev_state = exception_enter();
e3b28831 1035 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
2a0b24f5 1036 if (get_isa16_mode(regs->cp0_epc)) {
f6a31da5
MR		 1037 u16 instr[2];
1038
45deb5fa 1039 if (__get_inst16(&instr[0], (u16 *)epc, user))
f6a31da5
MR		 1040 goto out_sigsegv;
1041
1042 if (!cpu_has_mmips) {
b08a9c95 1043 /* MIPS16e mode */
68893e00 1044 bcode = (instr[0] >> 5) & 0x3f;
f6a31da5
MR		 1045 } else if (mm_insn_16bit(instr[0])) {
1046 /* 16-bit microMIPS BREAK */
1047 bcode = instr[0] & 0xf;
1048 } else {
1049 /* 32-bit microMIPS BREAK */
45deb5fa 1050 if (__get_inst16(&instr[1], (u16 *)(epc + 2), user))
2a0b24f5 1051 goto out_sigsegv;
f6a31da5
MR		 1052 opcode = (instr[0] << 16) | instr[1];
1053 bcode = (opcode >> 6) & ((1 << 20) - 1);
2a0b24f5
SH		 1054 }
1055 } else {
45deb5fa 1056 if (__get_inst32(&opcode, (u32 *)epc, user))
2a0b24f5 1057 goto out_sigsegv;
f6a31da5 1058 bcode = (opcode >> 6) & ((1 << 20) - 1);
2a0b24f5 1059 }
df270051
RB		 1060
1061 /*
1062 * There is the ancient bug in the MIPS assemblers that the break
1063 * code starts left to bit 16 instead to bit 6 in the opcode.
1064 * Gas is bug-compatible, but not always, grrr...
1065 * We handle both cases with a simple heuristics. --macro
1066 */
df270051 1067 if (bcode >= (1 << 10))
c9875032 1068 bcode = ((bcode & ((1 << 10) - 1)) << 10) | (bcode >> 10);
df270051 1069
c1bf207d
DD		 1070 /*
1071 * notify the kprobe handlers, if instruction is likely to
1072 * pertain to them.
1073 */
1074 switch (bcode) {
40e084a5
RB		 1075 case BRK_UPROBE:
1076 if (notify_die(DIE_UPROBE, "uprobe", regs, bcode,
1077 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1078 goto out;
1079 else
1080 break;
1081 case BRK_UPROBE_XOL:
1082 if (notify_die(DIE_UPROBE_XOL, "uprobe_xol", regs, bcode,
1083 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
1084 goto out;
1085 else
1086 break;
c1bf207d 1087 case BRK_KPROBE_BP:
dc73e4c1 1088 if (notify_die(DIE_BREAK, "debug", regs, bcode,
e3b28831 1089 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
c3fc5cd5 1090 goto out;
c1bf207d
DD		 1091 else
1092 break;
1093 case BRK_KPROBE_SSTEPBP:
dc73e4c1 1094 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode,
e3b28831 1095 current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
c3fc5cd5 1096 goto out;
c1bf207d
DD		 1097 else
1098 break;
1099 default:
1100 break;
1101 }
1102
3b143cca 1103 do_trap_or_bp(regs, bcode, TRAP_BRKPT, "Break");
c3fc5cd5
RB		 1104
1105out:
1106 exception_exit(prev_state);
90fccb13 1107 return;
e5679882
RB		 1108
1109out_sigsegv:
3cf5d076 1110 force_sig(SIGSEGV);
c3fc5cd5 1111 goto out;
1da177e4
LT		 1112}
1113
1114asmlinkage void do_tr(struct pt_regs *regs)
1115{
a9a6e7a0 1116 u32 opcode, tcode = 0;
c3fc5cd5 1117 enum ctx_state prev_state;
2a0b24f5 1118 u16 instr[2];
45deb5fa 1119 bool user = user_mode(regs);
a9a6e7a0 1120 unsigned long epc = msk_isa16_mode(exception_epc(regs));
1da177e4 1121
c3fc5cd5 1122 prev_state = exception_enter();
e3b28831 1123 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
a9a6e7a0 1124 if (get_isa16_mode(regs->cp0_epc)) {
45deb5fa
TB		 1125 if (__get_inst16(&instr[0], (u16 *)(epc + 0), user) ||
1126 __get_inst16(&instr[1], (u16 *)(epc + 2), user))
2a0b24f5 1127 goto out_sigsegv;
a9a6e7a0
MR		 1128 opcode = (instr[0] << 16) | instr[1];
1129 /* Immediate versions don't provide a code. */
1130 if (!(opcode & OPCODE))
1131 tcode = (opcode >> 12) & ((1 << 4) - 1);
1132 } else {
45deb5fa 1133 if (__get_inst32(&opcode, (u32 *)epc, user))
a9a6e7a0
MR		 1134 goto out_sigsegv;
1135 /* Immediate versions don't provide a code. */
1136 if (!(opcode & OPCODE))
1137 tcode = (opcode >> 6) & ((1 << 10) - 1);
2a0b24f5 1138 }
1da177e4 1139
3b143cca 1140 do_trap_or_bp(regs, tcode, 0, "Trap");
c3fc5cd5
RB		 1141
1142out:
1143 exception_exit(prev_state);
90fccb13 1144 return;
e5679882
RB		 1145
1146out_sigsegv:
3cf5d076 1147 force_sig(SIGSEGV);
c3fc5cd5 1148 goto out;
1da177e4
LT		 1149}
1150
1151asmlinkage void do_ri(struct pt_regs *regs)
1152{
60b0d655
MR		 1153 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs);
1154 unsigned long old_epc = regs->cp0_epc;
2a0b24f5 1155 unsigned long old31 = regs->regs[31];
c3fc5cd5 1156 enum ctx_state prev_state;
60b0d655
MR		 1157 unsigned int opcode = 0;
1158 int status = -1;
1da177e4 1159
b0a668fb
LY		 1160 /*
1161 * Avoid any kernel code. Just emulate the R2 instruction
1162 * as quickly as possible.
1163 */
1164 if (mipsr2_emulation && cpu_has_mips_r6 &&
4a7c2371
MR		 1165 likely(user_mode(regs)) &&
1166 likely(get_user(opcode, epc) >= 0)) {
304acb71
MR		 1167 unsigned long fcr31 = 0;
1168
1169 status = mipsr2_decoder(regs, opcode, &fcr31);
4a7c2371
MR		 1170 switch (status) {
1171 case 0:
1172 case SIGEMT:
4a7c2371
MR		 1173 return;
1174 case SIGILL:
1175 goto no_r2_instr;
1176 default:
1177 process_fpemu_return(status,
304acb71
MR		 1178 &current->thread.cp0_baduaddr,
1179 fcr31);
4a7c2371 1180 return;
b0a668fb
LY		 1181 }
1182 }
1183
1184no_r2_instr:
1185
c3fc5cd5 1186 prev_state = exception_enter();
e3b28831 1187 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
b0a668fb 1188
e3b28831 1189 if (notify_die(DIE_RI, "RI Fault", regs, 0, current->thread.trap_nr,
dc73e4c1 1190 SIGILL) == NOTIFY_STOP)
c3fc5cd5 1191 goto out;
88547001 1192
60b0d655 1193 die_if_kernel("Reserved instruction in kernel code", regs);
1da177e4 1194
60b0d655 1195 if (unlikely(compute_return_epc(regs) < 0))
c3fc5cd5 1196 goto out;
3c37026d 1197
3d50a7fb 1198 if (!get_isa16_mode(regs->cp0_epc)) {
2a0b24f5
SH		 1199 if (unlikely(get_user(opcode, epc) < 0))
1200 status = SIGSEGV;
60b0d655 1201
2a0b24f5
SH		 1202 if (!cpu_has_llsc && status < 0)
1203 status = simulate_llsc(regs, opcode);
1204
1205 if (status < 0)
1206 status = simulate_rdhwr_normal(regs, opcode);
1207
1208 if (status < 0)
1209 status = simulate_sync(regs, opcode);
4227a2d4
PB		 1210
1211 if (status < 0)
1212 status = simulate_fp(regs, opcode, old_epc, old31);
ec7a9318
WX		 1213
1214#ifdef CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION
1215 if (status < 0)
1216 status = simulate_loongson3_cpucfg(regs, opcode);
1217#endif
3d50a7fb
MR		 1218 } else if (cpu_has_mmips) {
1219 unsigned short mmop[2] = { 0 };
1220
1221 if (unlikely(get_user(mmop[0], (u16 __user *)epc + 0) < 0))
1222 status = SIGSEGV;
1223 if (unlikely(get_user(mmop[1], (u16 __user *)epc + 1) < 0))
1224 status = SIGSEGV;
1225 opcode = mmop[0];
1226 opcode = (opcode << 16) | mmop[1];
1227
1228 if (status < 0)
1229 status = simulate_rdhwr_mm(regs, opcode);
2a0b24f5 1230 }
60b0d655
MR		 1231
1232 if (status < 0)
1233 status = SIGILL;
1234
1235 if (unlikely(status > 0)) {
1236 regs->cp0_epc = old_epc; /* Undo skip-over. */
2a0b24f5 1237 regs->regs[31] = old31;
3cf5d076 1238 force_sig(status);
60b0d655 1239 }
c3fc5cd5
RB		 1240
1241out:
1242 exception_exit(prev_state);
1da177e4
LT		 1243}
1244
69f3a7de
RB		 1245/*
1246 * No lock; only written during early bootup by CPU 0.
1247 */
1248static RAW_NOTIFIER_HEAD(cu2_chain);
1249
1250int __ref register_cu2_notifier(struct notifier_block *nb)
1251{
1252 return raw_notifier_chain_register(&cu2_chain, nb);
1253}
1254
1255int cu2_notifier_call_chain(unsigned long val, void *v)
1256{
1257 return raw_notifier_call_chain(&cu2_chain, val, v);
1258}
1259
1260static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
70342287 1261 void *data)
69f3a7de
RB		 1262{
1263 struct pt_regs *regs = data;
1264
83bee792 1265 die_if_kernel("COP2: Unhandled kernel unaligned access or invalid "
69f3a7de 1266 "instruction", regs);
3cf5d076 1267 force_sig(SIGILL);
69f3a7de
RB		 1268
1269 return NOTIFY_OK;
1270}
1271
5328f742
PB		 1272#ifdef CONFIG_MIPS_FP_SUPPORT
1273
1db1af84
PB		 1274static int enable_restore_fp_context(int msa)
1275{
c9017757 1276 int err, was_fpu_owner, prior_msa;
cc97ab23 1277 bool first_fp;
1db1af84 1278
cc97ab23
PB		 1279 /* Initialize context if it hasn't been used already */
1280 first_fp = init_fp_ctx(current);
1db1af84 1281
cc97ab23 1282 if (first_fp) {
762a1f43 1283 preempt_disable();
cc97ab23 1284 err = own_fpu_inatomic(1);
c9017757 1285 if (msa && !err) {
1db1af84 1286 enable_msa();
bb067482
HP		 1287 /*
1288 * with MSA enabled, userspace can see MSACSR
1289 * and MSA regs, but the values in them are from
1290 * other task before current task, restore them
1291 * from saved fp/msa context
1292 */
1293 write_msa_csr(current->thread.fpu.msacsr);
1294 /*
1295 * own_fpu_inatomic(1) just restore low 64bit,
1296 * fix the high 64bit
1297 */
1298 init_msa_upper();
732c0c3c
PB		 1299 set_thread_flag(TIF_USEDMSA);
1300 set_thread_flag(TIF_MSA_CTX_LIVE);
c9017757 1301 }
762a1f43 1302 preempt_enable();
1db1af84
PB		 1303 return err;
1304 }
1305
1306 /*
1307 * This task has formerly used the FP context.
1308 *
1309 * If this thread has no live MSA vector context then we can simply
1310 * restore the scalar FP context. If it has live MSA vector context
1311 * (that is, it has or may have used MSA since last performing a
1312 * function call) then we'll need to restore the vector context. This
1313 * applies even if we're currently only executing a scalar FP
1314 * instruction. This is because if we were to later execute an MSA
1315 * instruction then we'd either have to:
1316 *
1317 * - Restore the vector context & clobber any registers modified by
1318 * scalar FP instructions between now & then.
1319 *
1320 * or
1321 *
1322 * - Not restore the vector context & lose the most significant bits
1323 * of all vector registers.
1324 *
1325 * Neither of those options is acceptable. We cannot restore the least
1326 * significant bits of the registers now & only restore the most
1327 * significant bits later because the most significant bits of any
1328 * vector registers whose aliased FP register is modified now will have
1329 * been zeroed. We'd have no way to know that when restoring the vector
1330 * context & thus may load an outdated value for the most significant
1331 * bits of a vector register.
1332 */
1333 if (!msa && !thread_msa_context_live())
1334 return own_fpu(1);
1335
1336 /*
1337 * This task is using or has previously used MSA. Thus we require
1338 * that Status.FR == 1.
1339 */
762a1f43 1340 preempt_disable();
1db1af84 1341 was_fpu_owner = is_fpu_owner();
762a1f43 1342 err = own_fpu_inatomic(0);
1db1af84 1343 if (err)
762a1f43 1344 goto out;
1db1af84
PB		 1345
1346 enable_msa();
1347 write_msa_csr(current->thread.fpu.msacsr);
1348 set_thread_flag(TIF_USEDMSA);
1349
1350 /*
1351 * If this is the first time that the task is using MSA and it has
1352 * previously used scalar FP in this time slice then we already nave
c9017757
PB		 1353 * FP context which we shouldn't clobber. We do however need to clear
1354 * the upper 64b of each vector register so that this task has no
1355 * opportunity to see data left behind by another.
1db1af84 1356 */
c9017757
PB		 1357 prior_msa = test_and_set_thread_flag(TIF_MSA_CTX_LIVE);
1358 if (!prior_msa && was_fpu_owner) {
e49d3848 1359 init_msa_upper();
762a1f43
PB		 1360
1361 goto out;
c9017757 1362 }
1db1af84 1363
c9017757
PB		 1364 if (!prior_msa) {
1365 /*
1366 * Restore the least significant 64b of each vector register
1367 * from the existing scalar FP context.
1368 */
1369 _restore_fp(current);
b8340673 1370
c9017757
PB		 1371 /*
1372 * The task has not formerly used MSA, so clear the upper 64b
1373 * of each vector register such that it cannot see data left
1374 * behind by another task.
1375 */
e49d3848 1376 init_msa_upper();
c9017757
PB		 1377 } else {
1378 /* We need to restore the vector context. */
1379 restore_msa(current);
b8340673 1380
c9017757
PB		 1381 /* Restore the scalar FP control & status register */
1382 if (!was_fpu_owner)
d76e9b9f
JH		 1383 write_32bit_cp1_register(CP1_STATUS,
1384 current->thread.fpu.fcr31);
c9017757 1385 }
762a1f43
PB		 1386
1387out:
1388 preempt_enable();
1389
1db1af84
PB		 1390 return 0;
1391}
1392
5328f742
PB		 1393#else /* !CONFIG_MIPS_FP_SUPPORT */
1394
1395static int enable_restore_fp_context(int msa)
1396{
1397 return SIGILL;
1398}
1399
1400#endif /* CONFIG_MIPS_FP_SUPPORT */
1401
1da177e4
LT		 1402asmlinkage void do_cpu(struct pt_regs *regs)
1403{
c3fc5cd5 1404 enum ctx_state prev_state;
60b0d655 1405 unsigned int __user *epc;
2a0b24f5 1406 unsigned long old_epc, old31;
60b0d655 1407 unsigned int opcode;
1da177e4 1408 unsigned int cpid;
5328f742 1409 int status;
1da177e4 1410
c3fc5cd5 1411 prev_state = exception_enter();
1da177e4
LT		 1412 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
1413
83bee792
J		 1414 if (cpid != 2)
1415 die_if_kernel("do_cpu invoked from kernel context!", regs);
1416
1da177e4
LT		 1417 switch (cpid) {
1418 case 0:
60b0d655
MR		 1419 epc = (unsigned int __user *)exception_epc(regs);
1420 old_epc = regs->cp0_epc;
2a0b24f5 1421 old31 = regs->regs[31];
60b0d655
MR		 1422 opcode = 0;
1423 status = -1;
1da177e4 1424
60b0d655 1425 if (unlikely(compute_return_epc(regs) < 0))
27e28e8e 1426 break;
3c37026d 1427
10f6d99f 1428 if (!get_isa16_mode(regs->cp0_epc)) {
2a0b24f5
SH		 1429 if (unlikely(get_user(opcode, epc) < 0))
1430 status = SIGSEGV;
1431
1432 if (!cpu_has_llsc && status < 0)
1433 status = simulate_llsc(regs, opcode);
2a0b24f5 1434 }
60b0d655
MR		 1435
1436 if (status < 0)
1437 status = SIGILL;
1438
1439 if (unlikely(status > 0)) {
1440 regs->cp0_epc = old_epc; /* Undo skip-over. */
2a0b24f5 1441 regs->regs[31] = old31;
3cf5d076 1442 force_sig(status);
60b0d655
MR		 1443 }
1444
27e28e8e 1445 break;
1da177e4 1446
5328f742 1447#ifdef CONFIG_MIPS_FP_SUPPORT
051ff44a
MR		 1448 case 3:
1449 /*
2d83fea7
MR		 1450 * The COP3 opcode space and consequently the CP0.Status.CU3
1451 * bit and the CP0.Cause.CE=3 encoding have been removed as
1452 * of the MIPS III ISA. From the MIPS IV and MIPS32r2 ISAs
1453 * up the space has been reused for COP1X instructions, that
1454 * are enabled by the CP0.Status.CU1 bit and consequently
1455 * use the CP0.Cause.CE=1 encoding for Coprocessor Unusable
1456 * exceptions. Some FPU-less processors that implement one
1457 * of these ISAs however use this code erroneously for COP1X
1458 * instructions. Therefore we redirect this trap to the FP
1459 * emulator too.
051ff44a 1460 */
2d83fea7 1461 if (raw_cpu_has_fpu || !cpu_has_mips_4_5_64_r2_r6) {
3cf5d076 1462 force_sig(SIGILL);
051ff44a 1463 break;
27e28e8e 1464 }
c9b02990 1465 fallthrough;
5328f742
PB		 1466 case 1: {
1467 void __user *fault_addr;
1468 unsigned long fcr31;
1469 int err, sig;
1470
1db1af84 1471 err = enable_restore_fp_context(0);
1da177e4 1472
304acb71
MR		 1473 if (raw_cpu_has_fpu && !err)
1474 break;
1da177e4 1475
304acb71
MR		 1476 sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 0,
1477 &fault_addr);
304acb71
MR		 1478
1479 /*
1480 * We can't allow the emulated instruction to leave
5a1aca44 1481 * any enabled Cause bits set in $fcr31.
304acb71 1482 */
5a1aca44
MR		 1483 fcr31 = mask_fcr31_x(current->thread.fpu.fcr31);
1484 current->thread.fpu.fcr31 &= ~fcr31;
304acb71
MR		 1485
1486 /* Send a signal if required. */
1487 if (!process_fpemu_return(sig, fault_addr, fcr31) && !err)
1488 mt_ase_fp_affinity();
1da177e4 1489
27e28e8e 1490 break;
5328f742
PB		 1491 }
1492#else /* CONFIG_MIPS_FP_SUPPORT */
1493 case 1:
1494 case 3:
3cf5d076 1495 force_sig(SIGILL);
5328f742
PB		 1496 break;
1497#endif /* CONFIG_MIPS_FP_SUPPORT */
1da177e4
LT		 1498
1499 case 2:
69f3a7de 1500 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
27e28e8e 1501 break;
1da177e4
LT		 1502 }
1503
c3fc5cd5 1504 exception_exit(prev_state);
1da177e4
LT		 1505}
1506
64bedffe 1507asmlinkage void do_msa_fpe(struct pt_regs *regs, unsigned int msacsr)
2bcb3fbc
PB		 1508{
1509 enum ctx_state prev_state;
1510
1511 prev_state = exception_enter();
e3b28831 1512 current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
64bedffe 1513 if (notify_die(DIE_MSAFP, "MSA FP exception", regs, 0,
e3b28831 1514 current->thread.trap_nr, SIGFPE) == NOTIFY_STOP)
64bedffe
JH		 1515 goto out;
1516
1517 /* Clear MSACSR.Cause before enabling interrupts */
1518 write_msa_csr(msacsr & ~MSA_CSR_CAUSEF);
1519 local_irq_enable();
1520
2bcb3fbc 1521 die_if_kernel("do_msa_fpe invoked from kernel context!", regs);
3cf5d076 1522 force_sig(SIGFPE);
64bedffe 1523out:
2bcb3fbc
PB		 1524 exception_exit(prev_state);
1525}
1526
1db1af84
PB		 1527asmlinkage void do_msa(struct pt_regs *regs)
1528{
1529 enum ctx_state prev_state;
1530 int err;
1531
1532 prev_state = exception_enter();
1533
1534 if (!cpu_has_msa || test_thread_flag(TIF_32BIT_FPREGS)) {
3cf5d076 1535 force_sig(SIGILL);
1db1af84
PB		 1536 goto out;
1537 }
1538
1539 die_if_kernel("do_msa invoked from kernel context!", regs);
1540
1541 err = enable_restore_fp_context(1);
1542 if (err)
3cf5d076 1543 force_sig(SIGILL);
1db1af84
PB		 1544out:
1545 exception_exit(prev_state);
1546}
1547
1da177e4
LT		 1548asmlinkage void do_mdmx(struct pt_regs *regs)
1549{
c3fc5cd5
RB		 1550 enum ctx_state prev_state;
1551
1552 prev_state = exception_enter();
3cf5d076 1553 force_sig(SIGILL);
c3fc5cd5 1554 exception_exit(prev_state);
1da177e4
LT		 1555}
1556
8bc6d05b
DD		 1557/*
1558 * Called with interrupts disabled.
1559 */
1da177e4
LT		 1560asmlinkage void do_watch(struct pt_regs *regs)
1561{
c3fc5cd5 1562 enum ctx_state prev_state;
b67b2b70 1563
c3fc5cd5 1564 prev_state = exception_enter();
1da177e4 1565 /*
b67b2b70
DD		 1566 * Clear WP (bit 22) bit of cause register so we don't loop
1567 * forever.
1da177e4 1568 */
e233c733 1569 clear_c0_cause(CAUSEF_WP);
b67b2b70
DD		 1570
1571 /*
1572 * If the current thread has the watch registers loaded, save
1573 * their values and send SIGTRAP. Otherwise another thread
1574 * left the registers set, clear them and continue.
1575 */
1576 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {
1577 mips_read_watch_registers();
8bc6d05b 1578 local_irq_enable();
2e1661d2 1579 force_sig_fault(SIGTRAP, TRAP_HWBKPT, NULL);
8bc6d05b 1580 } else {
b67b2b70 1581 mips_clear_watch_registers();
8bc6d05b
DD		 1582 local_irq_enable();
1583 }
c3fc5cd5 1584 exception_exit(prev_state);
1da177e4
LT		 1585}
1586
1587asmlinkage void do_mcheck(struct pt_regs *regs)
1588{
cac4bcbc 1589 int multi_match = regs->cp0_status & ST0_TS;
c3fc5cd5 1590 enum ctx_state prev_state;
cac4bcbc 1591
c3fc5cd5 1592 prev_state = exception_enter();
1da177e4 1593 show_regs(regs);
cac4bcbc
RB		 1594
1595 if (multi_match) {
3c865dd9
JH		 1596 dump_tlb_regs();
1597 pr_info("\n");
cac4bcbc
RB		 1598 dump_tlb_all();
1599 }
1600
45deb5fa 1601 show_code((void *)regs->cp0_epc, user_mode(regs));
55c723e1 1602
1da177e4
LT		 1603 /*
1604 * Some chips may have other causes of machine check (e.g. SB1
1605 * graduation timer)
1606 */
1607 panic("Caught Machine Check exception - %scaused by multiple "
1608 "matching entries in the TLB.",
cac4bcbc 1609 (multi_match) ? "" : "not ");
1da177e4
LT		 1610}
1611
340ee4b9
RB		 1612asmlinkage void do_mt(struct pt_regs *regs)
1613{
41c594ab
RB		 1614 int subcode;
1615
41c594ab
RB		 1616 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
1617 >> VPECONTROL_EXCPT_SHIFT;
1618 switch (subcode) {
1619 case 0:
e35a5e35 1620 printk(KERN_DEBUG "Thread Underflow\n");
41c594ab
RB		 1621 break;
1622 case 1:
e35a5e35 1623 printk(KERN_DEBUG "Thread Overflow\n");
41c594ab
RB		 1624 break;
1625 case 2:
e35a5e35 1626 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
41c594ab
RB		 1627 break;
1628 case 3:
e35a5e35 1629 printk(KERN_DEBUG "Gating Storage Exception\n");
41c594ab
RB		 1630 break;
1631 case 4:
e35a5e35 1632 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
41c594ab
RB		 1633 break;
1634 case 5:
f232c7e8 1635 printk(KERN_DEBUG "Gating Storage Scheduler Exception\n");
41c594ab
RB		 1636 break;
1637 default:
e35a5e35 1638 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
41c594ab
RB		 1639 subcode);
1640 break;
1641 }
340ee4b9
RB		 1642 die_if_kernel("MIPS MT Thread exception in kernel", regs);
1643
3cf5d076 1644 force_sig(SIGILL);
340ee4b9
RB		 1645}
1646
1647
e50c0a8f
RB		 1648asmlinkage void do_dsp(struct pt_regs *regs)
1649{
1650 if (cpu_has_dsp)
ab75dc02 1651 panic("Unexpected DSP exception");
e50c0a8f 1652
3cf5d076 1653 force_sig(SIGILL);
e50c0a8f
RB		 1654}
1655
1da177e4
LT		 1656asmlinkage void do_reserved(struct pt_regs *regs)
1657{
1658 /*
70342287 1659 * Game over - no way to handle this if it ever occurs. Most probably
1da177e4
LT		 1660 * caused by a new unknown cpu type or after another deadly
1661 * hard/software error.
1662 */
1663 show_regs(regs);
1664 panic("Caught reserved exception %ld - should not happen.",
1665 (regs->cp0_cause & 0x7f) >> 2);
1666}
1667
39b8d525
RB		 1668static int __initdata l1parity = 1;
1669static int __init nol1parity(char *s)
1670{
1671 l1parity = 0;
1672 return 1;
1673}
1674__setup("nol1par", nol1parity);
1675static int __initdata l2parity = 1;
1676static int __init nol2parity(char *s)
1677{
1678 l2parity = 0;
1679 return 1;
1680}
1681__setup("nol2par", nol2parity);
1682
1da177e4
LT		 1683/*
1684 * Some MIPS CPUs can enable/disable for cache parity detection, but do
1685 * it different ways.
1686 */
a2eec109 1687static inline __init void parity_protection_init(void)
1da177e4 1688{
35e6de38
PB		 1689#define ERRCTL_PE 0x80000000
1690#define ERRCTL_L2P 0x00800000
1691
1692 if (mips_cm_revision() >= CM_REV_CM3) {
1693 ulong gcr_ectl, cp0_ectl;
1694
1695 /*
1696 * With CM3 systems we need to ensure that the L1 & L2
1697 * parity enables are set to the same value, since this
1698 * is presumed by the hardware engineers.
1699 *
1700 * If the user disabled either of L1 or L2 ECC checking,
1701 * disable both.
1702 */
1703 l1parity &= l2parity;
1704 l2parity &= l1parity;
1705
1706 /* Probe L1 ECC support */
1707 cp0_ectl = read_c0_ecc();
1708 write_c0_ecc(cp0_ectl | ERRCTL_PE);
1709 back_to_back_c0_hazard();
1710 cp0_ectl = read_c0_ecc();
1711
1712 /* Probe L2 ECC support */
1713 gcr_ectl = read_gcr_err_control();
1714
93c5bba5 1715 if (!(gcr_ectl & CM_GCR_ERR_CONTROL_L2_ECC_SUPPORT) ||
35e6de38
PB		 1716 !(cp0_ectl & ERRCTL_PE)) {
1717 /*
1718 * One of L1 or L2 ECC checking isn't supported,
1719 * so we cannot enable either.
1720 */
1721 l1parity = l2parity = 0;
1722 }
1723
1724 /* Configure L1 ECC checking */
1725 if (l1parity)
1726 cp0_ectl |= ERRCTL_PE;
1727 else
1728 cp0_ectl &= ~ERRCTL_PE;
1729 write_c0_ecc(cp0_ectl);
1730 back_to_back_c0_hazard();
1731 WARN_ON(!!(read_c0_ecc() & ERRCTL_PE) != l1parity);
1732
1733 /* Configure L2 ECC checking */
1734 if (l2parity)
93c5bba5 1735 gcr_ectl |= CM_GCR_ERR_CONTROL_L2_ECC_EN;
35e6de38 1736 else
93c5bba5 1737 gcr_ectl &= ~CM_GCR_ERR_CONTROL_L2_ECC_EN;
35e6de38
PB		 1738 write_gcr_err_control(gcr_ectl);
1739 gcr_ectl = read_gcr_err_control();
93c5bba5 1740 gcr_ectl &= CM_GCR_ERR_CONTROL_L2_ECC_EN;
35e6de38
PB		 1741 WARN_ON(!!gcr_ectl != l2parity);
1742
1743 pr_info("Cache parity protection %sabled\n",
1744 l1parity ? "en" : "dis");
1745 return;
1746 }
1747
10cc3529 1748 switch (current_cpu_type()) {
1da177e4 1749 case CPU_24K:
98a41de9 1750 case CPU_34K:
39b8d525
RB		 1751 case CPU_74K:
1752 case CPU_1004K:
442e14a2 1753 case CPU_1074K:
26ab96df 1754 case CPU_INTERAPTIV:
708ac4b8 1755 case CPU_PROAPTIV:
aced4cbd 1756 case CPU_P5600:
4695089f 1757 case CPU_QEMU_GENERIC:
1091bfa2 1758 case CPU_P6600:
39b8d525 1759 {
39b8d525
RB		 1760 unsigned long errctl;
1761 unsigned int l1parity_present, l2parity_present;
1762
1763 errctl = read_c0_ecc();
1764 errctl &= ~(ERRCTL_PE|ERRCTL_L2P);
1765
1766 /* probe L1 parity support */
1767 write_c0_ecc(errctl | ERRCTL_PE);
1768 back_to_back_c0_hazard();
1769 l1parity_present = (read_c0_ecc() & ERRCTL_PE);
1770
1771 /* probe L2 parity support */
1772 write_c0_ecc(errctl|ERRCTL_L2P);
1773 back_to_back_c0_hazard();
1774 l2parity_present = (read_c0_ecc() & ERRCTL_L2P);
1775
1776 if (l1parity_present && l2parity_present) {
1777 if (l1parity)
1778 errctl |= ERRCTL_PE;
1779 if (l1parity ^ l2parity)
1780 errctl |= ERRCTL_L2P;
1781 } else if (l1parity_present) {
1782 if (l1parity)
1783 errctl |= ERRCTL_PE;
1784 } else if (l2parity_present) {
1785 if (l2parity)
1786 errctl |= ERRCTL_L2P;
1787 } else {
1788 /* No parity available */
1789 }
1790
1791 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl);
1792
1793 write_c0_ecc(errctl);
1794 back_to_back_c0_hazard();
1795 errctl = read_c0_ecc();
1796 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl);
1797
1798 if (l1parity_present)
1799 printk(KERN_INFO "Cache parity protection %sabled\n",
1800 (errctl & ERRCTL_PE) ? "en" : "dis");
1801
1802 if (l2parity_present) {
1803 if (l1parity_present && l1parity)
1804 errctl ^= ERRCTL_L2P;
1805 printk(KERN_INFO "L2 cache parity protection %sabled\n",
1806 (errctl & ERRCTL_L2P) ? "en" : "dis");
1807 }
1808 }
1809 break;
1810
1da177e4 1811 case CPU_5KC:
78d4803f 1812 case CPU_5KE:
b2afb64c 1813 case CPU_LOONGSON32:
14f18b7f
RB		 1814 write_c0_ecc(0x80000000);
1815 back_to_back_c0_hazard();
1816 /* Set the PE bit (bit 31) in the c0_errctl register. */
1817 printk(KERN_INFO "Cache parity protection %sabled\n",
1818 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
1da177e4
LT		 1819 break;
1820 case CPU_20KC:
1821 case CPU_25KF:
1822 /* Clear the DE bit (bit 16) in the c0_status register. */
1823 printk(KERN_INFO "Enable cache parity protection for "
1824 "MIPS 20KC/25KF CPUs.\n");
1825 clear_c0_status(ST0_DE);
1826 break;
1827 default:
1828 break;
1829 }
1830}
1831
1832asmlinkage void cache_parity_error(void)
1833{
1834 const int field = 2 * sizeof(unsigned long);
1835 unsigned int reg_val;
1836
1837 /* For the moment, report the problem and hang. */
1838 printk("Cache error exception:\n");
1839 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1840 reg_val = read_c0_cacheerr();
1841 printk("c0_cacheerr == %08x\n", reg_val);
1842
1843 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1844 reg_val & (1<<30) ? "secondary" : "primary",
1845 reg_val & (1<<31) ? "data" : "insn");
9c7d5768 1846 if ((cpu_has_mips_r2_r6) &&
721a9205 1847 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) {
6de20451
LY		 1848 pr_err("Error bits: %s%s%s%s%s%s%s%s\n",
1849 reg_val & (1<<29) ? "ED " : "",
1850 reg_val & (1<<28) ? "ET " : "",
1851 reg_val & (1<<27) ? "ES " : "",
1852 reg_val & (1<<26) ? "EE " : "",
1853 reg_val & (1<<25) ? "EB " : "",
1854 reg_val & (1<<24) ? "EI " : "",
1855 reg_val & (1<<23) ? "E1 " : "",
1856 reg_val & (1<<22) ? "E0 " : "");
1857 } else {
1858 pr_err("Error bits: %s%s%s%s%s%s%s\n",
1859 reg_val & (1<<29) ? "ED " : "",
1860 reg_val & (1<<28) ? "ET " : "",
1861 reg_val & (1<<26) ? "EE " : "",
1862 reg_val & (1<<25) ? "EB " : "",
1863 reg_val & (1<<24) ? "EI " : "",
1864 reg_val & (1<<23) ? "E1 " : "",
1865 reg_val & (1<<22) ? "E0 " : "");
1866 }
1da177e4
LT		 1867 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1868
ec917c2c 1869#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1da177e4
LT		 1870 if (reg_val & (1<<22))
1871 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
1872
1873 if (reg_val & (1<<23))
1874 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
1875#endif
1876
1877 panic("Can't handle the cache error!");
1878}
1879
75b5b5e0
LY		 1880asmlinkage void do_ftlb(void)
1881{
1882 const int field = 2 * sizeof(unsigned long);
1883 unsigned int reg_val;
1884
1885 /* For the moment, report the problem and hang. */
9c7d5768 1886 if ((cpu_has_mips_r2_r6) &&
b2edcfc8
HC		 1887 (((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS) ||
1888 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_LOONGSON))) {
75b5b5e0
LY		 1889 pr_err("FTLB error exception, cp0_ecc=0x%08x:\n",
1890 read_c0_ecc());
1891 pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1892 reg_val = read_c0_cacheerr();
1893 pr_err("c0_cacheerr == %08x\n", reg_val);
1894
1895 if ((reg_val & 0xc0000000) == 0xc0000000) {
1896 pr_err("Decoded c0_cacheerr: FTLB parity error\n");
1897 } else {
1898 pr_err("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1899 reg_val & (1<<30) ? "secondary" : "primary",
1900 reg_val & (1<<31) ? "data" : "insn");
1901 }
1902 } else {
1903 pr_err("FTLB error exception\n");
1904 }
1905 /* Just print the cacheerr bits for now */
1906 cache_parity_error();
1907}
1908
bc6e8dc1
WX		 1909asmlinkage void do_gsexc(struct pt_regs *regs, u32 diag1)
1910{
1911 u32 exccode = (diag1 & LOONGSON_DIAG1_EXCCODE) >>
1912 LOONGSON_DIAG1_EXCCODE_SHIFT;
1913 enum ctx_state prev_state;
1914
1915 prev_state = exception_enter();
1916
1917 switch (exccode) {
1918 case 0x08:
1919 /* Undocumented exception, will trigger on certain
1920 * also-undocumented instructions accessible from userspace.
1921 * Processor state is not otherwise corrupted, but currently
1922 * we don't know how to proceed. Maybe there is some
1923 * undocumented control flag to enable the instructions?
1924 */
1925 force_sig(SIGILL);
1926 break;
1927
1928 default:
1929 /* None of the other exceptions, documented or not, have
1930 * further details given; none are encountered in the wild
1931 * either. Panic in case some of them turn out to be fatal.
1932 */
1933 show_regs(regs);
1934 panic("Unhandled Loongson exception - GSCause = %08x", diag1);
1935 }
1936
1937 exception_exit(prev_state);
1938}
1939
1da177e4
LT		 1940/*
1941 * SDBBP EJTAG debug exception handler.
1942 * We skip the instruction and return to the next instruction.
1943 */
1944void ejtag_exception_handler(struct pt_regs *regs)
1945{
1946 const int field = 2 * sizeof(unsigned long);
2a0b24f5 1947 unsigned long depc, old_epc, old_ra;
1da177e4
LT		 1948 unsigned int debug;
1949
70ae6126 1950 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1da177e4
LT		 1951 depc = read_c0_depc();
1952 debug = read_c0_debug();
70ae6126 1953 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
1da177e4
LT		 1954 if (debug & 0x80000000) {
1955 /*
1956 * In branch delay slot.
1957 * We cheat a little bit here and use EPC to calculate the
1958 * debug return address (DEPC). EPC is restored after the
1959 * calculation.
1960 */
1961 old_epc = regs->cp0_epc;
2a0b24f5 1962 old_ra = regs->regs[31];
1da177e4 1963 regs->cp0_epc = depc;
2a0b24f5 1964 compute_return_epc(regs);
1da177e4
LT		 1965 depc = regs->cp0_epc;
1966 regs->cp0_epc = old_epc;
2a0b24f5 1967 regs->regs[31] = old_ra;
1da177e4
LT		 1968 } else
1969 depc += 4;
1970 write_c0_depc(depc);
1971
1972#if 0
70ae6126 1973 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1da177e4
LT		 1974 write_c0_debug(debug | 0x100);
1975#endif
1976}
1977
1978/*
1979 * NMI exception handler.
34bd92e2 1980 * No lock; only written during early bootup by CPU 0.
1da177e4 1981 */
34bd92e2
KC		 1982static RAW_NOTIFIER_HEAD(nmi_chain);
1983
1984int register_nmi_notifier(struct notifier_block *nb)
1985{
1986 return raw_notifier_chain_register(&nmi_chain, nb);
1987}
1988
ff2d8b19 1989void __noreturn nmi_exception_handler(struct pt_regs *regs)
1da177e4 1990{
83e4da1e
LY		 1991 char str[100];
1992
7963b3f1 1993 nmi_enter();
34bd92e2 1994 raw_notifier_call_chain(&nmi_chain, 0, regs);
41c594ab 1995 bust_spinlocks(1);
83e4da1e
LY		 1996 snprintf(str, 100, "CPU%d NMI taken, CP0_EPC=%lx\n",
1997 smp_processor_id(), regs->cp0_epc);
1998 regs->cp0_epc = read_c0_errorepc();
1999 die(str, regs);
7963b3f1 2000 nmi_exit();
1da177e4
LT		 2001}
2002
e01402b1 2003unsigned long ebase;
878edf01 2004EXPORT_SYMBOL_GPL(ebase);
1da177e4 2005unsigned long exception_handlers[32];
e01402b1 2006unsigned long vi_handlers[64];
1da177e4 2007
bd67b711
TB		 2008void reserve_exception_space(phys_addr_t addr, unsigned long size)
2009{
2010 memblock_reserve(addr, size);
2011}
2012
2d1b6e95 2013void __init *set_except_vector(int n, void *addr)
1da177e4
LT		 2014{
2015 unsigned long handler = (unsigned long) addr;
b22d1b6a 2016 unsigned long old_handler;
1da177e4 2017
2a0b24f5
SH		 2018#ifdef CONFIG_CPU_MICROMIPS
2019 /*
2020 * Only the TLB handlers are cache aligned with an even
2021 * address. All other handlers are on an odd address and
2022 * require no modification. Otherwise, MIPS32 mode will
2023 * be entered when handling any TLB exceptions. That
2024 * would be bad...since we must stay in microMIPS mode.
2025 */
2026 if (!(handler & 0x1))
2027 handler |= 1;
2028#endif
b22d1b6a 2029 old_handler = xchg(&exception_handlers[n], handler);
1da177e4 2030
1da177e4 2031 if (n == 0 && cpu_has_divec) {
2a0b24f5
SH		 2032#ifdef CONFIG_CPU_MICROMIPS
2033 unsigned long jump_mask = ~((1 << 27) - 1);
2034#else
92bbe1b9 2035 unsigned long jump_mask = ~((1 << 28) - 1);
2a0b24f5 2036#endif
92bbe1b9
FF		 2037 u32 *buf = (u32 *)(ebase + 0x200);
2038 unsigned int k0 = 26;
2039 if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) {
2040 uasm_i_j(&buf, handler & ~jump_mask);
2041 uasm_i_nop(&buf);
2042 } else {
2043 UASM_i_LA(&buf, k0, handler);
2044 uasm_i_jr(&buf, k0);
2045 uasm_i_nop(&buf);
2046 }
2047 local_flush_icache_range(ebase + 0x200, (unsigned long)buf);
e01402b1
RB		 2048 }
2049 return (void *)old_handler;
2050}
2051
86a1708a 2052static void do_default_vi(void)
6ba07e59
AN		 2053{
2054 show_regs(get_irq_regs());
2055 panic("Caught unexpected vectored interrupt.");
2056}
2057
ef300e42 2058static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
e01402b1
RB		 2059{
2060 unsigned long handler;
2061 unsigned long old_handler = vi_handlers[n];
f6771dbb 2062 int srssets = current_cpu_data.srsets;
2a0b24f5 2063 u16 *h;
e01402b1
RB		 2064 unsigned char *b;
2065
b72b7092 2066 BUG_ON(!cpu_has_veic && !cpu_has_vint);
e01402b1
RB		 2067
2068 if (addr == NULL) {
2069 handler = (unsigned long) do_default_vi;
2070 srs = 0;
41c594ab 2071 } else
e01402b1 2072 handler = (unsigned long) addr;
2a0b24f5 2073 vi_handlers[n] = handler;
e01402b1
RB		 2074
2075 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
2076
f6771dbb 2077 if (srs >= srssets)
e01402b1
RB		 2078 panic("Shadow register set %d not supported", srs);
2079
2080 if (cpu_has_veic) {
2081 if (board_bind_eic_interrupt)
49a89efb 2082 board_bind_eic_interrupt(n, srs);
41c594ab 2083 } else if (cpu_has_vint) {
e01402b1 2084 /* SRSMap is only defined if shadow sets are implemented */
f6771dbb 2085 if (srssets > 1)
49a89efb 2086 change_c0_srsmap(0xf << n*4, srs << n*4);
e01402b1
RB		 2087 }
2088
2089 if (srs == 0) {
2090 /*
2091 * If no shadow set is selected then use the default handler
2a0b24f5 2092 * that does normal register saving and standard interrupt exit
e01402b1 2093 */
d17b6641
AL		 2094 extern const u8 except_vec_vi[], except_vec_vi_lui[];
2095 extern const u8 except_vec_vi_ori[], except_vec_vi_end[];
2096 extern const u8 rollback_except_vec_vi[];
2097 const u8 *vec_start = using_rollback_handler() ?
2098 rollback_except_vec_vi : except_vec_vi;
2a0b24f5 2099#if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
d17b6641
AL		 2100 const int lui_offset = except_vec_vi_lui - vec_start + 2;
2101 const int ori_offset = except_vec_vi_ori - vec_start + 2;
2a0b24f5 2102#else
d17b6641
AL		 2103 const int lui_offset = except_vec_vi_lui - vec_start;
2104 const int ori_offset = except_vec_vi_ori - vec_start;
2a0b24f5 2105#endif
d17b6641 2106 const int handler_len = except_vec_vi_end - vec_start;
e01402b1
RB		 2107
2108 if (handler_len > VECTORSPACING) {
2109 /*
2110 * Sigh... panicing won't help as the console
2111 * is probably not configured :(
2112 */
49a89efb 2113 panic("VECTORSPACING too small");
e01402b1
RB		 2114 }
2115
2a0b24f5
SH		 2116 set_handler(((unsigned long)b - ebase), vec_start,
2117#ifdef CONFIG_CPU_MICROMIPS
2118 (handler_len - 1));
2119#else
2120 handler_len);
2121#endif
2a0b24f5
SH		 2122 h = (u16 *)(b + lui_offset);
2123 *h = (handler >> 16) & 0xffff;
2124 h = (u16 *)(b + ori_offset);
2125 *h = (handler & 0xffff);
e0cee3ee
TB		 2126 local_flush_icache_range((unsigned long)b,
2127 (unsigned long)(b+handler_len));
e01402b1
RB		 2128 }
2129 else {
2130 /*
2a0b24f5
SH		 2131 * In other cases jump directly to the interrupt handler. It
2132 * is the handler's responsibility to save registers if required
2133 * (eg hi/lo) and return from the exception using "eret".
e01402b1 2134 */
2a0b24f5
SH		 2135 u32 insn;
2136
2137 h = (u16 *)b;
2138 /* j handler */
2139#ifdef CONFIG_CPU_MICROMIPS
2140 insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1);
2141#else
2142 insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2);
2143#endif
2144 h[0] = (insn >> 16) & 0xffff;
2145 h[1] = insn & 0xffff;
2146 h[2] = 0;
2147 h[3] = 0;
e0cee3ee
TB		 2148 local_flush_icache_range((unsigned long)b,
2149 (unsigned long)(b+8));
1da177e4 2150 }
e01402b1 2151
1da177e4
LT		 2152 return (void *)old_handler;
2153}
2154
ef300e42 2155void *set_vi_handler(int n, vi_handler_t addr)
e01402b1 2156{
ff3eab2a 2157 return set_vi_srs_handler(n, addr, 0);
e01402b1 2158}
f41ae0b2 2159
1da177e4
LT		 2160extern void tlb_init(void);
2161
42f77542
RB		 2162/*
2163 * Timer interrupt
2164 */
2165int cp0_compare_irq;
68b6352c 2166EXPORT_SYMBOL_GPL(cp0_compare_irq);
010c108d 2167int cp0_compare_irq_shift;
42f77542
RB		 2168
2169/*
2170 * Performance counter IRQ or -1 if shared with timer
2171 */
2172int cp0_perfcount_irq;
2173EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
2174
8f7ff027
JH		 2175/*
2176 * Fast debug channel IRQ or -1 if not present
2177 */
2178int cp0_fdc_irq;
2179EXPORT_SYMBOL_GPL(cp0_fdc_irq);
2180
078a55fc 2181static int noulri;
bdc94eb4
CD		 2182
2183static int __init ulri_disable(char *s)
2184{
2185 pr_info("Disabling ulri\n");
2186 noulri = 1;
2187
2188 return 1;
2189}
2190__setup("noulri", ulri_disable);
2191
ae4ce454
JH		 2192/* configure STATUS register */
2193static void configure_status(void)
1da177e4 2194{
1da177e4
LT		 2195 /*
2196 * Disable coprocessors and select 32-bit or 64-bit addressing
2197 * and the 16/32 or 32/32 FPR register model. Reset the BEV
2198 * flag that some firmware may have left set and the TS bit (for
2199 * IP27). Set XX for ISA IV code to work.
2200 */
195615ec 2201 unsigned int status_set = ST0_KERNEL_CUMASK;
875d43e7 2202#ifdef CONFIG_64BIT
1da177e4
LT		 2203 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
2204#endif
adb37892 2205 if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV)
1da177e4 2206 status_set |= ST0_XX;
bbaf238b
CD		 2207 if (cpu_has_dsp)
2208 status_set |= ST0_MX;
2209
b38c7399 2210 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
1da177e4 2211 status_set);
fcec538e 2212 back_to_back_c0_hazard();
ae4ce454
JH		 2213}
2214
b937ff62
JH		 2215unsigned int hwrena;
2216EXPORT_SYMBOL_GPL(hwrena);
2217
ae4ce454
JH		 2218/* configure HWRENA register */
2219static void configure_hwrena(void)
2220{
b937ff62 2221 hwrena = cpu_hwrena_impl_bits;
1da177e4 2222
9c7d5768 2223 if (cpu_has_mips_r2_r6)
aff565aa
JH		 2224 hwrena |= MIPS_HWRENA_CPUNUM |
2225 MIPS_HWRENA_SYNCISTEP |
2226 MIPS_HWRENA_CC |
2227 MIPS_HWRENA_CCRES;
a3692020 2228
18d693b3 2229 if (!noulri && cpu_has_userlocal)
aff565aa 2230 hwrena |= MIPS_HWRENA_ULR;
a3692020 2231
18d693b3
KC		 2232 if (hwrena)
2233 write_c0_hwrena(hwrena);
ae4ce454 2234}
e01402b1 2235
ae4ce454
JH		 2236static void configure_exception_vector(void)
2237{
de56d4c1 2238 if (cpu_has_mips_r2_r6) {
9fb4c2b9 2239 unsigned long sr = set_c0_status(ST0_BEV);
4b22c693
MR		 2240 /* If available, use WG to set top bits of EBASE */
2241 if (cpu_has_ebase_wg) {
2242#ifdef CONFIG_64BIT
2243 write_c0_ebase_64(ebase | MIPS_EBASE_WG);
2244#else
2245 write_c0_ebase(ebase | MIPS_EBASE_WG);
2246#endif
2247 }
49a89efb 2248 write_c0_ebase(ebase);
9fb4c2b9 2249 write_c0_status(sr);
de56d4c1
PB		 2250 }
2251 if (cpu_has_veic || cpu_has_vint) {
e01402b1 2252 /* Setting vector spacing enables EI/VI mode */
49a89efb 2253 change_c0_intctl(0x3e0, VECTORSPACING);
e01402b1 2254 }
d03d0a57
RB		 2255 if (cpu_has_divec) {
2256 if (cpu_has_mipsmt) {
2257 unsigned int vpflags = dvpe();
2258 set_c0_cause(CAUSEF_IV);
2259 evpe(vpflags);
2260 } else
2261 set_c0_cause(CAUSEF_IV);
2262 }
ae4ce454
JH		 2263}
2264
2265void per_cpu_trap_init(bool is_boot_cpu)
2266{
2267 unsigned int cpu = smp_processor_id();
ae4ce454
JH		 2268
2269 configure_status();
2270 configure_hwrena();
2271
ae4ce454 2272 configure_exception_vector();
3b1d4ed5
RB		 2273
2274 /*
2275 * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
2276 *
2277 * o read IntCtl.IPTI to determine the timer interrupt
2278 * o read IntCtl.IPPCI to determine the performance counter interrupt
8f7ff027 2279 * o read IntCtl.IPFDC to determine the fast debug channel interrupt
3b1d4ed5 2280 */
9c7d5768 2281 if (cpu_has_mips_r2_r6) {
010c108d
DV		 2282 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
2283 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
2284 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
8f7ff027
JH		 2285 cp0_fdc_irq = (read_c0_intctl() >> INTCTLB_IPFDC) & 7;
2286 if (!cp0_fdc_irq)
2287 cp0_fdc_irq = -1;
2288
c3e838a2
CD		 2289 } else {
2290 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
c6a4ebb9 2291 cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ;
c3e838a2 2292 cp0_perfcount_irq = -1;
8f7ff027 2293 cp0_fdc_irq = -1;
3b1d4ed5
RB		 2294 }
2295
c8790d65
PB		 2296 if (cpu_has_mmid)
2297 cpu_data[cpu].asid_cache = 0;
2298 else if (!cpu_data[cpu].asid_cache)
4edf00a4 2299 cpu_data[cpu].asid_cache = asid_first_version(cpu);
1da177e4 2300
f1f10076 2301 mmgrab(&init_mm);
1da177e4
LT		 2302 current->active_mm = &init_mm;
2303 BUG_ON(current->mm);
2304 enter_lazy_tlb(&init_mm, current);
2305
761b4493
MC		 2306 /* Boot CPU's cache setup in setup_arch(). */
2307 if (!is_boot_cpu)
2308 cpu_cache_init();
2309 tlb_init();
3d8bfdd0 2310 TLBMISS_HANDLER_SETUP();
1da177e4
LT		 2311}
2312
e01402b1 2313/* Install CPU exception handler */
d17b6641 2314void set_handler(unsigned long offset, const void *addr, unsigned long size)
e01402b1 2315{
2a0b24f5
SH		 2316#ifdef CONFIG_CPU_MICROMIPS
2317 memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size);
2318#else
e01402b1 2319 memcpy((void *)(ebase + offset), addr, size);
2a0b24f5 2320#endif
e0cee3ee 2321 local_flush_icache_range(ebase + offset, ebase + offset + size);
e01402b1
RB		 2322}
2323
06324664
KC		 2324static const char panic_null_cerr[] =
2325 "Trying to set NULL cache error exception handler\n";
641e97f3 2326
42fe7ee3
RB		 2327/*
2328 * Install uncached CPU exception handler.
2329 * This is suitable only for the cache error exception which is the only
2330 * exception handler that is being run uncached.
2331 */
078a55fc 2332void set_uncached_handler(unsigned long offset, void *addr,
234fcd14 2333 unsigned long size)
e01402b1 2334{
4f81b01a 2335 unsigned long uncached_ebase = CKSEG1ADDR(ebase);
e01402b1 2336
641e97f3
RB		 2337 if (!addr)
2338 panic(panic_null_cerr);
2339
e01402b1
RB		 2340 memcpy((void *)(uncached_ebase + offset), addr, size);
2341}
2342
5b10496b
AN		 2343static int __initdata rdhwr_noopt;
2344static int __init set_rdhwr_noopt(char *str)
2345{
2346 rdhwr_noopt = 1;
2347 return 1;
2348}
2349
2350__setup("rdhwr_noopt", set_rdhwr_noopt);
2351
1da177e4
LT		 2352void __init trap_init(void)
2353{
2a0b24f5 2354 extern char except_vec3_generic;
1da177e4 2355 extern char except_vec4;
2a0b24f5 2356 extern char except_vec3_r4000;
172dcd93
PB		 2357 unsigned long i, vec_size;
2358 phys_addr_t ebase_pa;
c65a5480
AN		 2359
2360 check_wait();
1da177e4 2361
172dcd93
PB		 2362 if (!cpu_has_mips_r2_r6) {
2363 ebase = CAC_BASE;
172dcd93 2364 vec_size = 0x400;
172dcd93
PB		 2365 } else {
2366 if (cpu_has_veic || cpu_has_vint)
2367 vec_size = 0x200 + VECTORSPACING*64;
2368 else
2369 vec_size = PAGE_SIZE;
c195e079 2370
172dcd93 2371 ebase_pa = memblock_phys_alloc(vec_size, 1 << fls(vec_size));
f995adb0 2372 if (!ebase_pa)
8a7f97b9 2373 panic("%s: Failed to allocate %lu bytes align=0x%x\n",
172dcd93 2374 __func__, vec_size, 1 << fls(vec_size));
c195e079
JH		 2375
2376 /*
2377 * Try to ensure ebase resides in KSeg0 if possible.
2378 *
2379 * It shouldn't generally be in XKPhys on MIPS64 to avoid
2380 * hitting a poorly defined exception base for Cache Errors.
2381 * The allocation is likely to be in the low 512MB of physical,
2382 * in which case we should be able to convert to KSeg0.
2383 *
2384 * EVA is special though as it allows segments to be rearranged
2385 * and to become uncached during cache error handling.
2386 */
c195e079
JH		 2387 if (!IS_ENABLED(CONFIG_EVA) && !WARN_ON(ebase_pa >= 0x20000000))
2388 ebase = CKSEG0ADDR(ebase_pa);
f995adb0
PB		 2389 else
2390 ebase = (unsigned long)phys_to_virt(ebase_pa);
566f74f6 2391 }
e01402b1 2392
c6213c6c
SH		 2393 if (cpu_has_mmips) {
2394 unsigned int config3 = read_c0_config3();
2395
2396 if (IS_ENABLED(CONFIG_CPU_MICROMIPS))
2397 write_c0_config3(config3 | MIPS_CONF3_ISA_OE);
2398 else
2399 write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE);
2400 }
2401
6fb97eff
KC		 2402 if (board_ebase_setup)
2403 board_ebase_setup();
6650df3c 2404 per_cpu_trap_init(true);
25517ed4 2405 memblock_set_bottom_up(false);
1da177e4
LT		 2406
2407 /*
2408 * Copy the generic exception handlers to their final destination.
92a76f6d 2409 * This will be overridden later as suitable for a particular
1da177e4
LT		 2410 * configuration.
2411 */
e01402b1 2412 set_handler(0x180, &except_vec3_generic, 0x80);
1da177e4
LT		 2413
2414 /*
2415 * Setup default vectors
2416 */
2417 for (i = 0; i <= 31; i++)
2418 set_except_vector(i, handle_reserved);
2419
2420 /*
2421 * Copy the EJTAG debug exception vector handler code to it's final
2422 * destination.
2423 */
e01402b1 2424 if (cpu_has_ejtag && board_ejtag_handler_setup)
49a89efb 2425 board_ejtag_handler_setup();
1da177e4
LT		 2426
2427 /*
2428 * Only some CPUs have the watch exceptions.
2429 */
2430 if (cpu_has_watch)
1b505def 2431 set_except_vector(EXCCODE_WATCH, handle_watch);
1da177e4
LT		 2432
2433 /*
e01402b1 2434 * Initialise interrupt handlers
1da177e4 2435 */
e01402b1
RB		 2436 if (cpu_has_veic || cpu_has_vint) {
2437 int nvec = cpu_has_veic ? 64 : 8;
2438 for (i = 0; i < nvec; i++)
ff3eab2a 2439 set_vi_handler(i, NULL);
e01402b1
RB		 2440 }
2441 else if (cpu_has_divec)
2442 set_handler(0x200, &except_vec4, 0x8);
1da177e4
LT		 2443
2444 /*
2445 * Some CPUs can enable/disable for cache parity detection, but does
2446 * it different ways.
2447 */
2448 parity_protection_init();
2449
2450 /*
2451 * The Data Bus Errors / Instruction Bus Errors are signaled
2452 * by external hardware. Therefore these two exceptions
2453 * may have board specific handlers.
2454 */
2455 if (board_be_init)
2456 board_be_init();
2457
1b505def
JH		 2458 set_except_vector(EXCCODE_INT, using_rollback_handler() ?
2459 rollback_handle_int : handle_int);
2460 set_except_vector(EXCCODE_MOD, handle_tlbm);
2461 set_except_vector(EXCCODE_TLBL, handle_tlbl);
2462 set_except_vector(EXCCODE_TLBS, handle_tlbs);
1da177e4 2463
1b505def
JH		 2464 set_except_vector(EXCCODE_ADEL, handle_adel);
2465 set_except_vector(EXCCODE_ADES, handle_ades);
1da177e4 2466
1b505def
JH		 2467 set_except_vector(EXCCODE_IBE, handle_ibe);
2468 set_except_vector(EXCCODE_DBE, handle_dbe);
1da177e4 2469
1b505def
JH		 2470 set_except_vector(EXCCODE_SYS, handle_sys);
2471 set_except_vector(EXCCODE_BP, handle_bp);
5a341331
HC		 2472
2473 if (rdhwr_noopt)
2474 set_except_vector(EXCCODE_RI, handle_ri);
2475 else {
2476 if (cpu_has_vtag_icache)
2477 set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp);
268a2d60 2478 else if (current_cpu_type() == CPU_LOONGSON64)
5a341331
HC		 2479 set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp);
2480 else
2481 set_except_vector(EXCCODE_RI, handle_ri_rdhwr);
2482 }
2483
1b505def
JH		 2484 set_except_vector(EXCCODE_CPU, handle_cpu);
2485 set_except_vector(EXCCODE_OV, handle_ov);
2486 set_except_vector(EXCCODE_TR, handle_tr);
2487 set_except_vector(EXCCODE_MSAFPE, handle_msa_fpe);
1da177e4 2488
e01402b1
RB		 2489 if (board_nmi_handler_setup)
2490 board_nmi_handler_setup();
2491
e50c0a8f 2492 if (cpu_has_fpu && !cpu_has_nofpuex)
1b505def 2493 set_except_vector(EXCCODE_FPE, handle_fpe);
e50c0a8f 2494
efd1b4ad
WX		 2495 if (cpu_has_ftlbparex)
2496 set_except_vector(MIPS_EXCCODE_TLBPAR, handle_ftlb);
5890f70f 2497
bc6e8dc1
WX		 2498 if (cpu_has_gsexcex)
2499 set_except_vector(LOONGSON_EXCCODE_GSEXC, handle_gsexc);
5890f70f
LY		 2500
2501 if (cpu_has_rixiex) {
1b505def
JH		 2502 set_except_vector(EXCCODE_TLBRI, tlb_do_page_fault_0);
2503 set_except_vector(EXCCODE_TLBXI, tlb_do_page_fault_0);
5890f70f
LY		 2504 }
2505
1b505def
JH		 2506 set_except_vector(EXCCODE_MSADIS, handle_msa);
2507 set_except_vector(EXCCODE_MDMX, handle_mdmx);
e50c0a8f
RB		 2508
2509 if (cpu_has_mcheck)
1b505def 2510 set_except_vector(EXCCODE_MCHECK, handle_mcheck);
e50c0a8f 2511
340ee4b9 2512 if (cpu_has_mipsmt)
1b505def 2513 set_except_vector(EXCCODE_THREAD, handle_mt);
340ee4b9 2514
1b505def 2515 set_except_vector(EXCCODE_DSPDIS, handle_dsp);
e50c0a8f 2516
fcbf1dfd
DD		 2517 if (board_cache_error_setup)
2518 board_cache_error_setup();
2519
e50c0a8f
RB		 2520 if (cpu_has_vce)
2521 /* Special exception: R4[04]00 uses also the divec space. */
2a0b24f5 2522 set_handler(0x180, &except_vec3_r4000, 0x100);
e50c0a8f 2523 else if (cpu_has_4kex)
2a0b24f5 2524 set_handler(0x180, &except_vec3_generic, 0x80);
e50c0a8f 2525 else
2a0b24f5 2526 set_handler(0x080, &except_vec3_generic, 0x80);
e50c0a8f 2527
783454e2 2528 local_flush_icache_range(ebase, ebase + vec_size);
0510617b
TB		 2529
2530 sort_extable(__start___dbe_table, __stop___dbe_table);
69f3a7de 2531
4483b159 2532 cu2_notifier(default_cu2_call, 0x80000000); /* Run last */
1da177e4 2533}
ae4ce454
JH		 2534
2535static int trap_pm_notifier(struct notifier_block *self, unsigned long cmd,
2536 void *v)
2537{
2538 switch (cmd) {
2539 case CPU_PM_ENTER_FAILED:
2540 case CPU_PM_EXIT:
2541 configure_status();
2542 configure_hwrena();
2543 configure_exception_vector();
2544
2545 /* Restore register with CPU number for TLB handlers */
2546 TLBMISS_HANDLER_RESTORE();
2547
2548 break;
2549 }
2550
2551 return NOTIFY_OK;
2552}
2553
2554static struct notifier_block trap_pm_notifier_block = {
2555 .notifier_call = trap_pm_notifier,
2556};
2557
2558static int __init trap_pm_init(void)
2559{
2560 return cpu_pm_register_notifier(&trap_pm_notifier_block);
2561}
2562arch_initcall(trap_pm_init);
Linux 6.x block layer and io_uring tree(s)