Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Copyright 2001 MontaVista Software Inc. | |
3 | * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net | |
4 | * Copyright (c) 2003, 2004 Maciej W. Rozycki | |
5 | * | |
d9eec1a5 | 6 | * Common time service routines for MIPS machines. |
1da177e4 LT |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | */ | |
656db506 | 13 | #include <linux/bug.h> |
7bcf7717 | 14 | #include <linux/clockchips.h> |
1da177e4 LT |
15 | #include <linux/types.h> |
16 | #include <linux/kernel.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/sched.h> | |
19 | #include <linux/param.h> | |
20 | #include <linux/time.h> | |
21 | #include <linux/timex.h> | |
22 | #include <linux/smp.h> | |
1da177e4 | 23 | #include <linux/spinlock.h> |
1da177e4 LT |
24 | #include <linux/module.h> |
25 | ||
1da177e4 LT |
26 | #include <asm/cpu-features.h> |
27 | #include <asm/div64.h> | |
ea580401 | 28 | #include <asm/smtc_ipi.h> |
1da177e4 LT |
29 | #include <asm/time.h> |
30 | ||
1da177e4 LT |
31 | /* |
32 | * forward reference | |
33 | */ | |
1da177e4 | 34 | DEFINE_SPINLOCK(rtc_lock); |
4b550488 | 35 | EXPORT_SYMBOL(rtc_lock); |
1da177e4 | 36 | |
4b550488 | 37 | int __weak rtc_mips_set_time(unsigned long sec) |
1da177e4 | 38 | { |
4b550488 | 39 | return 0; |
1da177e4 LT |
40 | } |
41 | ||
4b550488 | 42 | int __weak rtc_mips_set_mmss(unsigned long nowtime) |
1da177e4 | 43 | { |
4b550488 | 44 | return rtc_mips_set_time(nowtime); |
1da177e4 LT |
45 | } |
46 | ||
f5ff0a28 RB |
47 | int update_persistent_clock(struct timespec now) |
48 | { | |
49 | return rtc_mips_set_mmss(now.tv_sec); | |
50 | } | |
1da177e4 | 51 | |
46684734 | 52 | static int null_perf_irq(void) |
ba339c03 RB |
53 | { |
54 | return 0; | |
55 | } | |
56 | ||
7d12e780 | 57 | int (*perf_irq)(void) = null_perf_irq; |
ba339c03 | 58 | |
ba339c03 RB |
59 | EXPORT_SYMBOL(perf_irq); |
60 | ||
1da177e4 LT |
61 | /* |
62 | * time_init() - it does the following things. | |
63 | * | |
4b550488 | 64 | * 1) plat_time_init() - |
1da177e4 LT |
65 | * a) (optional) set up RTC routines, |
66 | * b) (optional) calibrate and set the mips_hpt_frequency | |
16b7b2ac AN |
67 | * (only needed if you intended to use cpu counter as timer interrupt |
68 | * source) | |
4b550488 | 69 | * 2) calculate a couple of cached variables for later usage |
1da177e4 LT |
70 | */ |
71 | ||
1da177e4 LT |
72 | unsigned int mips_hpt_frequency; |
73 | ||
93c846f9 | 74 | void __init clocksource_set_clock(struct clocksource *cs, unsigned int clock) |
16b7b2ac AN |
75 | { |
76 | u64 temp; | |
77 | u32 shift; | |
78 | ||
93c846f9 RB |
79 | /* Find a shift value */ |
80 | for (shift = 32; shift > 0; shift--) { | |
81 | temp = (u64) NSEC_PER_SEC << shift; | |
82 | do_div(temp, clock); | |
83 | if ((temp >> 32) == 0) | |
84 | break; | |
85 | } | |
86 | cs->shift = shift; | |
87 | cs->mult = (u32) temp; | |
88 | } | |
89 | ||
90 | void __cpuinit clockevent_set_clock(struct clock_event_device *cd, | |
91 | unsigned int clock) | |
92 | { | |
93 | u64 temp; | |
94 | u32 shift; | |
16b7b2ac | 95 | |
16b7b2ac AN |
96 | /* Find a shift value */ |
97 | for (shift = 32; shift > 0; shift--) { | |
508a775a AN |
98 | temp = (u64) clock << shift; |
99 | do_div(temp, NSEC_PER_SEC); | |
16b7b2ac AN |
100 | if ((temp >> 32) == 0) |
101 | break; | |
102 | } | |
93c846f9 RB |
103 | cd->shift = shift; |
104 | cd->mult = (u32) temp; | |
105 | } | |
106 | ||
656db506 RB |
107 | /* |
108 | * This function exists in order to cause an error due to a duplicate | |
109 | * definition if platform code should have its own implementation. The hook | |
110 | * to use instead is plat_time_init. plat_time_init does not receive the | |
111 | * irqaction pointer argument anymore. This is because any function which | |
112 | * initializes an interrupt timer now takes care of its own request_irq rsp. | |
113 | * setup_irq calls and each clock_event_device should use its own | |
114 | * struct irqrequest. | |
115 | */ | |
d9eec1a5 | 116 | void __init plat_timer_setup(void) |
7bcf7717 | 117 | { |
656db506 | 118 | BUG(); |
7bcf7717 RB |
119 | } |
120 | ||
5aa85c9f RB |
121 | static __init int cpu_has_mfc0_count_bug(void) |
122 | { | |
123 | switch (current_cpu_type()) { | |
124 | case CPU_R4000PC: | |
125 | case CPU_R4000SC: | |
126 | case CPU_R4000MC: | |
127 | /* | |
128 | * V3.0 is documented as suffering from the mfc0 from count bug. | |
129 | * Afaik this is the last version of the R4000. Later versions | |
130 | * were marketed as R4400. | |
131 | */ | |
132 | return 1; | |
133 | ||
134 | case CPU_R4400PC: | |
135 | case CPU_R4400SC: | |
136 | case CPU_R4400MC: | |
137 | /* | |
138 | * The published errata for the R4400 upto 3.0 say the CPU | |
139 | * has the mfc0 from count bug. | |
140 | */ | |
141 | if ((current_cpu_data.processor_id & 0xff) <= 0x30) | |
142 | return 1; | |
143 | ||
144 | /* | |
ce202cbb | 145 | * we assume newer revisions are ok |
5aa85c9f | 146 | */ |
ce202cbb | 147 | return 0; |
5aa85c9f RB |
148 | } |
149 | ||
150 | return 0; | |
151 | } | |
152 | ||
4b550488 RB |
153 | void __init time_init(void) |
154 | { | |
155 | plat_time_init(); | |
1da177e4 | 156 | |
447cdf26 | 157 | if (!mips_clockevent_init() || !cpu_has_mfc0_count_bug()) |
d9eec1a5 | 158 | init_mips_clocksource(); |
1da177e4 | 159 | } |