Commit | Line | Data |
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8531a35e KK |
1 | /* |
2 | * This program is free software; you can redistribute it and/or | |
3 | * modify it under the terms of the GNU General Public License | |
4 | * as published by the Free Software Foundation; either version 2 | |
5 | * of the License, or (at your option) any later version. | |
6 | * | |
7 | * This program is distributed in the hope that it will be useful, | |
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
10 | * GNU General Public License for more details. | |
11 | * | |
12 | * You should have received a copy of the GNU General Public License | |
13 | * along with this program; if not, write to the Free Software | |
14 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
15 | * | |
16 | * Copyright (C) 2004 Mips Technologies, Inc | |
17 | * Copyright (C) 2008 Kevin D. Kissell | |
18 | */ | |
41c594ab | 19 | |
ea580401 | 20 | #include <linux/clockchips.h> |
41c594ab RB |
21 | #include <linux/kernel.h> |
22 | #include <linux/sched.h> | |
631330f5 | 23 | #include <linux/smp.h> |
41c594ab RB |
24 | #include <linux/cpumask.h> |
25 | #include <linux/interrupt.h> | |
ae036b79 | 26 | #include <linux/kernel_stat.h> |
ec43c014 | 27 | #include <linux/module.h> |
41c594ab RB |
28 | |
29 | #include <asm/cpu.h> | |
30 | #include <asm/processor.h> | |
31 | #include <asm/atomic.h> | |
32 | #include <asm/system.h> | |
33 | #include <asm/hardirq.h> | |
34 | #include <asm/hazards.h> | |
3b1d4ed5 | 35 | #include <asm/irq.h> |
41c594ab | 36 | #include <asm/mmu_context.h> |
41c594ab RB |
37 | #include <asm/mipsregs.h> |
38 | #include <asm/cacheflush.h> | |
39 | #include <asm/time.h> | |
40 | #include <asm/addrspace.h> | |
41 | #include <asm/smtc.h> | |
41c594ab RB |
42 | #include <asm/smtc_proc.h> |
43 | ||
44 | /* | |
1146fe30 RB |
45 | * SMTC Kernel needs to manipulate low-level CPU interrupt mask |
46 | * in do_IRQ. These are passed in setup_irq_smtc() and stored | |
47 | * in this table. | |
41c594ab | 48 | */ |
1146fe30 | 49 | unsigned long irq_hwmask[NR_IRQS]; |
41c594ab | 50 | |
41c594ab RB |
51 | #define LOCK_MT_PRA() \ |
52 | local_irq_save(flags); \ | |
53 | mtflags = dmt() | |
54 | ||
55 | #define UNLOCK_MT_PRA() \ | |
56 | emt(mtflags); \ | |
57 | local_irq_restore(flags) | |
58 | ||
59 | #define LOCK_CORE_PRA() \ | |
60 | local_irq_save(flags); \ | |
61 | mtflags = dvpe() | |
62 | ||
63 | #define UNLOCK_CORE_PRA() \ | |
64 | evpe(mtflags); \ | |
65 | local_irq_restore(flags) | |
66 | ||
67 | /* | |
68 | * Data structures purely associated with SMTC parallelism | |
69 | */ | |
70 | ||
71 | ||
72 | /* | |
73 | * Table for tracking ASIDs whose lifetime is prolonged. | |
74 | */ | |
75 | ||
76 | asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS]; | |
77 | ||
41c594ab RB |
78 | |
79 | /* | |
603e82ed | 80 | * Number of InterProcessor Interrupt (IPI) message buffers to allocate |
41c594ab RB |
81 | */ |
82 | ||
83 | #define IPIBUF_PER_CPU 4 | |
84 | ||
d2bb01b0 | 85 | struct smtc_ipi_q IPIQ[NR_CPUS]; |
5868756d | 86 | static struct smtc_ipi_q freeIPIq; |
41c594ab RB |
87 | |
88 | ||
89 | /* Forward declarations */ | |
90 | ||
937a8015 | 91 | void ipi_decode(struct smtc_ipi *); |
5868756d | 92 | static void post_direct_ipi(int cpu, struct smtc_ipi *pipi); |
20bb25d1 | 93 | static void setup_cross_vpe_interrupts(unsigned int nvpe); |
41c594ab RB |
94 | void init_smtc_stats(void); |
95 | ||
96 | /* Global SMTC Status */ | |
97 | ||
98 | unsigned int smtc_status = 0; | |
99 | ||
100 | /* Boot command line configuration overrides */ | |
101 | ||
be5f1f21 | 102 | static int vpe0limit; |
41c594ab RB |
103 | static int ipibuffers = 0; |
104 | static int nostlb = 0; | |
105 | static int asidmask = 0; | |
106 | unsigned long smtc_asid_mask = 0xff; | |
107 | ||
be5f1f21 KK |
108 | static int __init vpe0tcs(char *str) |
109 | { | |
110 | get_option(&str, &vpe0limit); | |
111 | ||
112 | return 1; | |
113 | } | |
114 | ||
41c594ab RB |
115 | static int __init ipibufs(char *str) |
116 | { | |
117 | get_option(&str, &ipibuffers); | |
118 | return 1; | |
119 | } | |
120 | ||
121 | static int __init stlb_disable(char *s) | |
122 | { | |
123 | nostlb = 1; | |
124 | return 1; | |
125 | } | |
126 | ||
127 | static int __init asidmask_set(char *str) | |
128 | { | |
129 | get_option(&str, &asidmask); | |
4bf42d42 | 130 | switch (asidmask) { |
41c594ab RB |
131 | case 0x1: |
132 | case 0x3: | |
133 | case 0x7: | |
134 | case 0xf: | |
135 | case 0x1f: | |
136 | case 0x3f: | |
137 | case 0x7f: | |
138 | case 0xff: | |
139 | smtc_asid_mask = (unsigned long)asidmask; | |
140 | break; | |
141 | default: | |
142 | printk("ILLEGAL ASID mask 0x%x from command line\n", asidmask); | |
143 | } | |
144 | return 1; | |
145 | } | |
146 | ||
be5f1f21 | 147 | __setup("vpe0tcs=", vpe0tcs); |
41c594ab RB |
148 | __setup("ipibufs=", ipibufs); |
149 | __setup("nostlb", stlb_disable); | |
150 | __setup("asidmask=", asidmask_set); | |
151 | ||
c68644d3 | 152 | #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG |
41c594ab RB |
153 | |
154 | static int hang_trig = 0; | |
155 | ||
156 | static int __init hangtrig_enable(char *s) | |
157 | { | |
158 | hang_trig = 1; | |
159 | return 1; | |
160 | } | |
161 | ||
162 | ||
163 | __setup("hangtrig", hangtrig_enable); | |
164 | ||
165 | #define DEFAULT_BLOCKED_IPI_LIMIT 32 | |
166 | ||
167 | static int timerq_limit = DEFAULT_BLOCKED_IPI_LIMIT; | |
168 | ||
169 | static int __init tintq(char *str) | |
170 | { | |
171 | get_option(&str, &timerq_limit); | |
172 | return 1; | |
173 | } | |
174 | ||
175 | __setup("tintq=", tintq); | |
176 | ||
97aef63c | 177 | static int imstuckcount[2][8]; |
41c594ab | 178 | /* vpemask represents IM/IE bits of per-VPE Status registers, low-to-high */ |
97aef63c | 179 | static int vpemask[2][8] = { |
20bb25d1 RB |
180 | {0, 0, 1, 0, 0, 0, 0, 1}, |
181 | {0, 0, 0, 0, 0, 0, 0, 1} | |
182 | }; | |
41c594ab RB |
183 | int tcnoprog[NR_CPUS]; |
184 | static atomic_t idle_hook_initialized = {0}; | |
185 | static int clock_hang_reported[NR_CPUS]; | |
186 | ||
c68644d3 | 187 | #endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */ |
41c594ab | 188 | |
41c594ab RB |
189 | /* |
190 | * Configure shared TLB - VPC configuration bit must be set by caller | |
191 | */ | |
192 | ||
5868756d | 193 | static void smtc_configure_tlb(void) |
41c594ab | 194 | { |
21a151d8 | 195 | int i, tlbsiz, vpes; |
41c594ab RB |
196 | unsigned long mvpconf0; |
197 | unsigned long config1val; | |
198 | ||
199 | /* Set up ASID preservation table */ | |
200 | for (vpes=0; vpes<MAX_SMTC_TLBS; vpes++) { | |
201 | for(i = 0; i < MAX_SMTC_ASIDS; i++) { | |
202 | smtc_live_asid[vpes][i] = 0; | |
203 | } | |
204 | } | |
205 | mvpconf0 = read_c0_mvpconf0(); | |
206 | ||
207 | if ((vpes = ((mvpconf0 & MVPCONF0_PVPE) | |
208 | >> MVPCONF0_PVPE_SHIFT) + 1) > 1) { | |
209 | /* If we have multiple VPEs, try to share the TLB */ | |
210 | if ((mvpconf0 & MVPCONF0_TLBS) && !nostlb) { | |
211 | /* | |
212 | * If TLB sizing is programmable, shared TLB | |
213 | * size is the total available complement. | |
214 | * Otherwise, we have to take the sum of all | |
215 | * static VPE TLB entries. | |
216 | */ | |
217 | if ((tlbsiz = ((mvpconf0 & MVPCONF0_PTLBE) | |
218 | >> MVPCONF0_PTLBE_SHIFT)) == 0) { | |
219 | /* | |
220 | * If there's more than one VPE, there had better | |
221 | * be more than one TC, because we need one to bind | |
222 | * to each VPE in turn to be able to read | |
223 | * its configuration state! | |
224 | */ | |
225 | settc(1); | |
226 | /* Stop the TC from doing anything foolish */ | |
227 | write_tc_c0_tchalt(TCHALT_H); | |
228 | mips_ihb(); | |
229 | /* No need to un-Halt - that happens later anyway */ | |
230 | for (i=0; i < vpes; i++) { | |
231 | write_tc_c0_tcbind(i); | |
232 | /* | |
233 | * To be 100% sure we're really getting the right | |
234 | * information, we exit the configuration state | |
235 | * and do an IHB after each rebinding. | |
236 | */ | |
237 | write_c0_mvpcontrol( | |
238 | read_c0_mvpcontrol() & ~ MVPCONTROL_VPC ); | |
239 | mips_ihb(); | |
240 | /* | |
241 | * Only count if the MMU Type indicated is TLB | |
242 | */ | |
4bf42d42 | 243 | if (((read_vpe_c0_config() & MIPS_CONF_MT) >> 7) == 1) { |
41c594ab RB |
244 | config1val = read_vpe_c0_config1(); |
245 | tlbsiz += ((config1val >> 25) & 0x3f) + 1; | |
246 | } | |
247 | ||
248 | /* Put core back in configuration state */ | |
249 | write_c0_mvpcontrol( | |
250 | read_c0_mvpcontrol() | MVPCONTROL_VPC ); | |
251 | mips_ihb(); | |
252 | } | |
253 | } | |
254 | write_c0_mvpcontrol(read_c0_mvpcontrol() | MVPCONTROL_STLB); | |
c80697b3 | 255 | ehb(); |
41c594ab RB |
256 | |
257 | /* | |
258 | * Setup kernel data structures to use software total, | |
259 | * rather than read the per-VPE Config1 value. The values | |
260 | * for "CPU 0" gets copied to all the other CPUs as part | |
261 | * of their initialization in smtc_cpu_setup(). | |
262 | */ | |
263 | ||
a0b62180 RB |
264 | /* MIPS32 limits TLB indices to 64 */ |
265 | if (tlbsiz > 64) | |
266 | tlbsiz = 64; | |
267 | cpu_data[0].tlbsize = current_cpu_data.tlbsize = tlbsiz; | |
41c594ab | 268 | smtc_status |= SMTC_TLB_SHARED; |
a0b62180 | 269 | local_flush_tlb_all(); |
41c594ab RB |
270 | |
271 | printk("TLB of %d entry pairs shared by %d VPEs\n", | |
272 | tlbsiz, vpes); | |
273 | } else { | |
274 | printk("WARNING: TLB Not Sharable on SMTC Boot!\n"); | |
275 | } | |
276 | } | |
277 | } | |
278 | ||
279 | ||
280 | /* | |
281 | * Incrementally build the CPU map out of constituent MIPS MT cores, | |
282 | * using the specified available VPEs and TCs. Plaform code needs | |
283 | * to ensure that each MIPS MT core invokes this routine on reset, | |
284 | * one at a time(!). | |
285 | * | |
286 | * This version of the build_cpu_map and prepare_cpus routines assumes | |
287 | * that *all* TCs of a MIPS MT core will be used for Linux, and that | |
288 | * they will be spread across *all* available VPEs (to minimise the | |
289 | * loss of efficiency due to exception service serialization). | |
290 | * An improved version would pick up configuration information and | |
291 | * possibly leave some TCs/VPEs as "slave" processors. | |
292 | * | |
293 | * Use c0_MVPConf0 to find out how many TCs are available, setting up | |
98a79d6a | 294 | * cpu_possible_map and the logical/physical mappings. |
41c594ab RB |
295 | */ |
296 | ||
8531a35e | 297 | int __init smtc_build_cpu_map(int start_cpu_slot) |
41c594ab RB |
298 | { |
299 | int i, ntcs; | |
300 | ||
301 | /* | |
302 | * The CPU map isn't actually used for anything at this point, | |
303 | * so it's not clear what else we should do apart from set | |
304 | * everything up so that "logical" = "physical". | |
305 | */ | |
306 | ntcs = ((read_c0_mvpconf0() & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1; | |
307 | for (i=start_cpu_slot; i<NR_CPUS && i<ntcs; i++) { | |
98a79d6a | 308 | cpu_set(i, cpu_possible_map); |
41c594ab RB |
309 | __cpu_number_map[i] = i; |
310 | __cpu_logical_map[i] = i; | |
311 | } | |
ea580401 | 312 | #ifdef CONFIG_MIPS_MT_FPAFF |
41c594ab RB |
313 | /* Initialize map of CPUs with FPUs */ |
314 | cpus_clear(mt_fpu_cpumask); | |
ea580401 | 315 | #endif |
41c594ab RB |
316 | |
317 | /* One of those TC's is the one booting, and not a secondary... */ | |
318 | printk("%i available secondary CPU TC(s)\n", i - 1); | |
319 | ||
320 | return i; | |
321 | } | |
322 | ||
323 | /* | |
324 | * Common setup before any secondaries are started | |
325 | * Make sure all CPU's are in a sensible state before we boot any of the | |
326 | * secondaries. | |
327 | * | |
328 | * For MIPS MT "SMTC" operation, we set up all TCs, spread as evenly | |
329 | * as possible across the available VPEs. | |
330 | */ | |
331 | ||
332 | static void smtc_tc_setup(int vpe, int tc, int cpu) | |
333 | { | |
334 | settc(tc); | |
335 | write_tc_c0_tchalt(TCHALT_H); | |
336 | mips_ihb(); | |
337 | write_tc_c0_tcstatus((read_tc_c0_tcstatus() | |
338 | & ~(TCSTATUS_TKSU | TCSTATUS_DA | TCSTATUS_IXMT)) | |
339 | | TCSTATUS_A); | |
8531a35e KK |
340 | /* |
341 | * TCContext gets an offset from the base of the IPIQ array | |
342 | * to be used in low-level code to detect the presence of | |
343 | * an active IPI queue | |
344 | */ | |
345 | write_tc_c0_tccontext((sizeof(struct smtc_ipi_q) * cpu) << 16); | |
41c594ab RB |
346 | /* Bind tc to vpe */ |
347 | write_tc_c0_tcbind(vpe); | |
348 | /* In general, all TCs should have the same cpu_data indications */ | |
349 | memcpy(&cpu_data[cpu], &cpu_data[0], sizeof(struct cpuinfo_mips)); | |
350 | /* For 34Kf, start with TC/CPU 0 as sole owner of single FPU context */ | |
39b8d525 RB |
351 | if (cpu_data[0].cputype == CPU_34K || |
352 | cpu_data[0].cputype == CPU_1004K) | |
41c594ab RB |
353 | cpu_data[cpu].options &= ~MIPS_CPU_FPU; |
354 | cpu_data[cpu].vpe_id = vpe; | |
355 | cpu_data[cpu].tc_id = tc; | |
8531a35e KK |
356 | /* Multi-core SMTC hasn't been tested, but be prepared */ |
357 | cpu_data[cpu].core = (read_vpe_c0_ebase() >> 1) & 0xff; | |
41c594ab RB |
358 | } |
359 | ||
8531a35e KK |
360 | /* |
361 | * Tweak to get Count registes in as close a sync as possible. | |
362 | * Value seems good for 34K-class cores. | |
363 | */ | |
364 | ||
365 | #define CP0_SKEW 8 | |
41c594ab | 366 | |
8531a35e | 367 | void smtc_prepare_cpus(int cpus) |
41c594ab | 368 | { |
be5f1f21 | 369 | int i, vpe, tc, ntc, nvpe, tcpervpe[NR_CPUS], slop, cpu; |
41c594ab RB |
370 | unsigned long flags; |
371 | unsigned long val; | |
372 | int nipi; | |
373 | struct smtc_ipi *pipi; | |
374 | ||
375 | /* disable interrupts so we can disable MT */ | |
376 | local_irq_save(flags); | |
377 | /* disable MT so we can configure */ | |
378 | dvpe(); | |
379 | dmt(); | |
380 | ||
34af946a | 381 | spin_lock_init(&freeIPIq.lock); |
41c594ab RB |
382 | |
383 | /* | |
384 | * We probably don't have as many VPEs as we do SMP "CPUs", | |
385 | * but it's possible - and in any case we'll never use more! | |
386 | */ | |
387 | for (i=0; i<NR_CPUS; i++) { | |
388 | IPIQ[i].head = IPIQ[i].tail = NULL; | |
34af946a | 389 | spin_lock_init(&IPIQ[i].lock); |
41c594ab | 390 | IPIQ[i].depth = 0; |
41c594ab RB |
391 | } |
392 | ||
393 | /* cpu_data index starts at zero */ | |
394 | cpu = 0; | |
395 | cpu_data[cpu].vpe_id = 0; | |
396 | cpu_data[cpu].tc_id = 0; | |
8531a35e | 397 | cpu_data[cpu].core = (read_c0_ebase() >> 1) & 0xff; |
41c594ab RB |
398 | cpu++; |
399 | ||
400 | /* Report on boot-time options */ | |
49a89efb | 401 | mips_mt_set_cpuoptions(); |
41c594ab RB |
402 | if (vpelimit > 0) |
403 | printk("Limit of %d VPEs set\n", vpelimit); | |
404 | if (tclimit > 0) | |
405 | printk("Limit of %d TCs set\n", tclimit); | |
406 | if (nostlb) { | |
407 | printk("Shared TLB Use Inhibited - UNSAFE for Multi-VPE Operation\n"); | |
408 | } | |
409 | if (asidmask) | |
410 | printk("ASID mask value override to 0x%x\n", asidmask); | |
411 | ||
412 | /* Temporary */ | |
c68644d3 | 413 | #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG |
41c594ab RB |
414 | if (hang_trig) |
415 | printk("Logic Analyser Trigger on suspected TC hang\n"); | |
c68644d3 | 416 | #endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */ |
41c594ab RB |
417 | |
418 | /* Put MVPE's into 'configuration state' */ | |
419 | write_c0_mvpcontrol( read_c0_mvpcontrol() | MVPCONTROL_VPC ); | |
420 | ||
421 | val = read_c0_mvpconf0(); | |
422 | nvpe = ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1; | |
423 | if (vpelimit > 0 && nvpe > vpelimit) | |
424 | nvpe = vpelimit; | |
425 | ntc = ((val & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1; | |
426 | if (ntc > NR_CPUS) | |
427 | ntc = NR_CPUS; | |
428 | if (tclimit > 0 && ntc > tclimit) | |
429 | ntc = tclimit; | |
be5f1f21 KK |
430 | slop = ntc % nvpe; |
431 | for (i = 0; i < nvpe; i++) { | |
432 | tcpervpe[i] = ntc / nvpe; | |
433 | if (slop) { | |
434 | if((slop - i) > 0) tcpervpe[i]++; | |
435 | } | |
436 | } | |
437 | /* Handle command line override for VPE0 */ | |
438 | if (vpe0limit > ntc) vpe0limit = ntc; | |
439 | if (vpe0limit > 0) { | |
440 | int slopslop; | |
441 | if (vpe0limit < tcpervpe[0]) { | |
442 | /* Reducing TC count - distribute to others */ | |
443 | slop = tcpervpe[0] - vpe0limit; | |
444 | slopslop = slop % (nvpe - 1); | |
445 | tcpervpe[0] = vpe0limit; | |
446 | for (i = 1; i < nvpe; i++) { | |
447 | tcpervpe[i] += slop / (nvpe - 1); | |
448 | if(slopslop && ((slopslop - (i - 1) > 0))) | |
449 | tcpervpe[i]++; | |
450 | } | |
451 | } else if (vpe0limit > tcpervpe[0]) { | |
452 | /* Increasing TC count - steal from others */ | |
453 | slop = vpe0limit - tcpervpe[0]; | |
454 | slopslop = slop % (nvpe - 1); | |
455 | tcpervpe[0] = vpe0limit; | |
456 | for (i = 1; i < nvpe; i++) { | |
457 | tcpervpe[i] -= slop / (nvpe - 1); | |
458 | if(slopslop && ((slopslop - (i - 1) > 0))) | |
459 | tcpervpe[i]--; | |
460 | } | |
461 | } | |
462 | } | |
41c594ab RB |
463 | |
464 | /* Set up shared TLB */ | |
465 | smtc_configure_tlb(); | |
466 | ||
467 | for (tc = 0, vpe = 0 ; (vpe < nvpe) && (tc < ntc) ; vpe++) { | |
468 | /* | |
469 | * Set the MVP bits. | |
470 | */ | |
471 | settc(tc); | |
472 | write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_MVP); | |
473 | if (vpe != 0) | |
474 | printk(", "); | |
475 | printk("VPE %d: TC", vpe); | |
be5f1f21 | 476 | for (i = 0; i < tcpervpe[vpe]; i++) { |
41c594ab RB |
477 | /* |
478 | * TC 0 is bound to VPE 0 at reset, | |
479 | * and is presumably executing this | |
480 | * code. Leave it alone! | |
481 | */ | |
482 | if (tc != 0) { | |
21a151d8 | 483 | smtc_tc_setup(vpe, tc, cpu); |
41c594ab RB |
484 | cpu++; |
485 | } | |
486 | printk(" %d", tc); | |
487 | tc++; | |
488 | } | |
41c594ab RB |
489 | if (vpe != 0) { |
490 | /* | |
491 | * Clear any stale software interrupts from VPE's Cause | |
492 | */ | |
493 | write_vpe_c0_cause(0); | |
494 | ||
495 | /* | |
496 | * Clear ERL/EXL of VPEs other than 0 | |
497 | * and set restricted interrupt enable/mask. | |
498 | */ | |
499 | write_vpe_c0_status((read_vpe_c0_status() | |
500 | & ~(ST0_BEV | ST0_ERL | ST0_EXL | ST0_IM)) | |
501 | | (STATUSF_IP0 | STATUSF_IP1 | STATUSF_IP7 | |
502 | | ST0_IE)); | |
503 | /* | |
504 | * set config to be the same as vpe0, | |
505 | * particularly kseg0 coherency alg | |
506 | */ | |
507 | write_vpe_c0_config(read_c0_config()); | |
508 | /* Clear any pending timer interrupt */ | |
509 | write_vpe_c0_compare(0); | |
510 | /* Propagate Config7 */ | |
511 | write_vpe_c0_config7(read_c0_config7()); | |
8531a35e KK |
512 | write_vpe_c0_count(read_c0_count() + CP0_SKEW); |
513 | ehb(); | |
41c594ab RB |
514 | } |
515 | /* enable multi-threading within VPE */ | |
516 | write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() | VPECONTROL_TE); | |
517 | /* enable the VPE */ | |
518 | write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA); | |
519 | } | |
520 | ||
521 | /* | |
522 | * Pull any physically present but unused TCs out of circulation. | |
523 | */ | |
524 | while (tc < (((val & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1)) { | |
98a79d6a | 525 | cpu_clear(tc, cpu_possible_map); |
41c594ab RB |
526 | cpu_clear(tc, cpu_present_map); |
527 | tc++; | |
528 | } | |
529 | ||
530 | /* release config state */ | |
531 | write_c0_mvpcontrol( read_c0_mvpcontrol() & ~ MVPCONTROL_VPC ); | |
532 | ||
533 | printk("\n"); | |
534 | ||
535 | /* Set up coprocessor affinity CPU mask(s) */ | |
536 | ||
ea580401 | 537 | #ifdef CONFIG_MIPS_MT_FPAFF |
41c594ab | 538 | for (tc = 0; tc < ntc; tc++) { |
4bf42d42 | 539 | if (cpu_data[tc].options & MIPS_CPU_FPU) |
41c594ab RB |
540 | cpu_set(tc, mt_fpu_cpumask); |
541 | } | |
ea580401 | 542 | #endif |
41c594ab RB |
543 | |
544 | /* set up ipi interrupts... */ | |
545 | ||
546 | /* If we have multiple VPEs running, set up the cross-VPE interrupt */ | |
547 | ||
20bb25d1 | 548 | setup_cross_vpe_interrupts(nvpe); |
41c594ab RB |
549 | |
550 | /* Set up queue of free IPI "messages". */ | |
551 | nipi = NR_CPUS * IPIBUF_PER_CPU; | |
552 | if (ipibuffers > 0) | |
553 | nipi = ipibuffers; | |
554 | ||
555 | pipi = kmalloc(nipi *sizeof(struct smtc_ipi), GFP_KERNEL); | |
556 | if (pipi == NULL) | |
557 | panic("kmalloc of IPI message buffers failed\n"); | |
558 | else | |
559 | printk("IPI buffer pool of %d buffers\n", nipi); | |
560 | for (i = 0; i < nipi; i++) { | |
561 | smtc_ipi_nq(&freeIPIq, pipi); | |
562 | pipi++; | |
563 | } | |
564 | ||
565 | /* Arm multithreading and enable other VPEs - but all TCs are Halted */ | |
566 | emt(EMT_ENABLE); | |
567 | evpe(EVPE_ENABLE); | |
568 | local_irq_restore(flags); | |
569 | /* Initialize SMTC /proc statistics/diagnostics */ | |
570 | init_smtc_stats(); | |
571 | } | |
572 | ||
573 | ||
574 | /* | |
575 | * Setup the PC, SP, and GP of a secondary processor and start it | |
576 | * running! | |
577 | * smp_bootstrap is the place to resume from | |
578 | * __KSTK_TOS(idle) is apparently the stack pointer | |
579 | * (unsigned long)idle->thread_info the gp | |
580 | * | |
581 | */ | |
e119d49a | 582 | void __cpuinit smtc_boot_secondary(int cpu, struct task_struct *idle) |
41c594ab RB |
583 | { |
584 | extern u32 kernelsp[NR_CPUS]; | |
b7e4226e | 585 | unsigned long flags; |
41c594ab RB |
586 | int mtflags; |
587 | ||
588 | LOCK_MT_PRA(); | |
589 | if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) { | |
590 | dvpe(); | |
591 | } | |
592 | settc(cpu_data[cpu].tc_id); | |
593 | ||
594 | /* pc */ | |
595 | write_tc_c0_tcrestart((unsigned long)&smp_bootstrap); | |
596 | ||
597 | /* stack pointer */ | |
598 | kernelsp[cpu] = __KSTK_TOS(idle); | |
599 | write_tc_gpr_sp(__KSTK_TOS(idle)); | |
600 | ||
601 | /* global pointer */ | |
c9f4f06d | 602 | write_tc_gpr_gp((unsigned long)task_thread_info(idle)); |
41c594ab RB |
603 | |
604 | smtc_status |= SMTC_MTC_ACTIVE; | |
605 | write_tc_c0_tchalt(0); | |
606 | if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) { | |
607 | evpe(EVPE_ENABLE); | |
608 | } | |
609 | UNLOCK_MT_PRA(); | |
610 | } | |
611 | ||
612 | void smtc_init_secondary(void) | |
613 | { | |
41c594ab RB |
614 | local_irq_enable(); |
615 | } | |
616 | ||
617 | void smtc_smp_finish(void) | |
618 | { | |
8531a35e KK |
619 | int cpu = smp_processor_id(); |
620 | ||
621 | /* | |
622 | * Lowest-numbered CPU per VPE starts a clock tick. | |
623 | * Like per_cpu_trap_init() hack, this assumes that | |
624 | * SMTC init code assigns TCs consdecutively and | |
625 | * in ascending order across available VPEs. | |
626 | */ | |
627 | if (cpu > 0 && (cpu_data[cpu].vpe_id != cpu_data[cpu - 1].vpe_id)) | |
628 | write_c0_compare(read_c0_count() + mips_hpt_frequency/HZ); | |
629 | ||
41c594ab RB |
630 | printk("TC %d going on-line as CPU %d\n", |
631 | cpu_data[smp_processor_id()].tc_id, smp_processor_id()); | |
632 | } | |
633 | ||
634 | void smtc_cpus_done(void) | |
635 | { | |
636 | } | |
637 | ||
638 | /* | |
639 | * Support for SMTC-optimized driver IRQ registration | |
640 | */ | |
641 | ||
642 | /* | |
643 | * SMTC Kernel needs to manipulate low-level CPU interrupt mask | |
644 | * in do_IRQ. These are passed in setup_irq_smtc() and stored | |
645 | * in this table. | |
646 | */ | |
647 | ||
648 | int setup_irq_smtc(unsigned int irq, struct irqaction * new, | |
649 | unsigned long hwmask) | |
650 | { | |
ef36fc3c | 651 | #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG |
20bb25d1 RB |
652 | unsigned int vpe = current_cpu_data.vpe_id; |
653 | ||
3b1d4ed5 | 654 | vpemask[vpe][irq - MIPS_CPU_IRQ_BASE] = 1; |
20bb25d1 | 655 | #endif |
ef36fc3c | 656 | irq_hwmask[irq] = hwmask; |
41c594ab RB |
657 | |
658 | return setup_irq(irq, new); | |
659 | } | |
660 | ||
f571eff0 KK |
661 | #ifdef CONFIG_MIPS_MT_SMTC_IRQAFF |
662 | /* | |
663 | * Support for IRQ affinity to TCs | |
664 | */ | |
665 | ||
666 | void smtc_set_irq_affinity(unsigned int irq, cpumask_t affinity) | |
667 | { | |
668 | /* | |
669 | * If a "fast path" cache of quickly decodable affinity state | |
670 | * is maintained, this is where it gets done, on a call up | |
671 | * from the platform affinity code. | |
672 | */ | |
673 | } | |
674 | ||
675 | void smtc_forward_irq(unsigned int irq) | |
676 | { | |
677 | int target; | |
678 | ||
679 | /* | |
680 | * OK wise guy, now figure out how to get the IRQ | |
681 | * to be serviced on an authorized "CPU". | |
682 | * | |
683 | * Ideally, to handle the situation where an IRQ has multiple | |
684 | * eligible CPUS, we would maintain state per IRQ that would | |
685 | * allow a fair distribution of service requests. Since the | |
686 | * expected use model is any-or-only-one, for simplicity | |
687 | * and efficiency, we just pick the easiest one to find. | |
688 | */ | |
689 | ||
e65e49d0 | 690 | target = cpumask_first(irq_desc[irq].affinity); |
f571eff0 KK |
691 | |
692 | /* | |
693 | * We depend on the platform code to have correctly processed | |
694 | * IRQ affinity change requests to ensure that the IRQ affinity | |
695 | * mask has been purged of bits corresponding to nonexistent and | |
696 | * offline "CPUs", and to TCs bound to VPEs other than the VPE | |
697 | * connected to the physical interrupt input for the interrupt | |
698 | * in question. Otherwise we have a nasty problem with interrupt | |
699 | * mask management. This is best handled in non-performance-critical | |
700 | * platform IRQ affinity setting code, to minimize interrupt-time | |
701 | * checks. | |
702 | */ | |
703 | ||
704 | /* If no one is eligible, service locally */ | |
705 | if (target >= NR_CPUS) { | |
706 | do_IRQ_no_affinity(irq); | |
707 | return; | |
708 | } | |
709 | ||
710 | smtc_send_ipi(target, IRQ_AFFINITY_IPI, irq); | |
711 | } | |
712 | ||
713 | #endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ | |
714 | ||
41c594ab RB |
715 | /* |
716 | * IPI model for SMTC is tricky, because interrupts aren't TC-specific. | |
717 | * Within a VPE one TC can interrupt another by different approaches. | |
718 | * The easiest to get right would probably be to make all TCs except | |
719 | * the target IXMT and set a software interrupt, but an IXMT-based | |
720 | * scheme requires that a handler must run before a new IPI could | |
721 | * be sent, which would break the "broadcast" loops in MIPS MT. | |
722 | * A more gonzo approach within a VPE is to halt the TC, extract | |
723 | * its Restart, Status, and a couple of GPRs, and program the Restart | |
724 | * address to emulate an interrupt. | |
725 | * | |
726 | * Within a VPE, one can be confident that the target TC isn't in | |
727 | * a critical EXL state when halted, since the write to the Halt | |
728 | * register could not have issued on the writing thread if the | |
729 | * halting thread had EXL set. So k0 and k1 of the target TC | |
730 | * can be used by the injection code. Across VPEs, one can't | |
731 | * be certain that the target TC isn't in a critical exception | |
732 | * state. So we try a two-step process of sending a software | |
733 | * interrupt to the target VPE, which either handles the event | |
734 | * itself (if it was the target) or injects the event within | |
735 | * the VPE. | |
736 | */ | |
737 | ||
5868756d | 738 | static void smtc_ipi_qdump(void) |
41c594ab RB |
739 | { |
740 | int i; | |
741 | ||
742 | for (i = 0; i < NR_CPUS ;i++) { | |
743 | printk("IPIQ[%d]: head = 0x%x, tail = 0x%x, depth = %d\n", | |
744 | i, (unsigned)IPIQ[i].head, (unsigned)IPIQ[i].tail, | |
745 | IPIQ[i].depth); | |
746 | } | |
747 | } | |
748 | ||
749 | /* | |
750 | * The standard atomic.h primitives don't quite do what we want | |
751 | * here: We need an atomic add-and-return-previous-value (which | |
752 | * could be done with atomic_add_return and a decrement) and an | |
753 | * atomic set/zero-and-return-previous-value (which can't really | |
754 | * be done with the atomic.h primitives). And since this is | |
755 | * MIPS MT, we can assume that we have LL/SC. | |
756 | */ | |
ea580401 | 757 | static inline int atomic_postincrement(atomic_t *v) |
41c594ab RB |
758 | { |
759 | unsigned long result; | |
760 | ||
761 | unsigned long temp; | |
762 | ||
763 | __asm__ __volatile__( | |
764 | "1: ll %0, %2 \n" | |
765 | " addu %1, %0, 1 \n" | |
766 | " sc %1, %2 \n" | |
767 | " beqz %1, 1b \n" | |
d87d0c93 | 768 | __WEAK_LLSC_MB |
ea580401 RB |
769 | : "=&r" (result), "=&r" (temp), "=m" (v->counter) |
770 | : "m" (v->counter) | |
41c594ab RB |
771 | : "memory"); |
772 | ||
773 | return result; | |
774 | } | |
775 | ||
41c594ab RB |
776 | void smtc_send_ipi(int cpu, int type, unsigned int action) |
777 | { | |
778 | int tcstatus; | |
779 | struct smtc_ipi *pipi; | |
b7e4226e | 780 | unsigned long flags; |
41c594ab | 781 | int mtflags; |
8531a35e KK |
782 | unsigned long tcrestart; |
783 | extern void r4k_wait_irqoff(void), __pastwait(void); | |
41c594ab RB |
784 | |
785 | if (cpu == smp_processor_id()) { | |
786 | printk("Cannot Send IPI to self!\n"); | |
787 | return; | |
788 | } | |
789 | /* Set up a descriptor, to be delivered either promptly or queued */ | |
790 | pipi = smtc_ipi_dq(&freeIPIq); | |
791 | if (pipi == NULL) { | |
792 | bust_spinlocks(1); | |
793 | mips_mt_regdump(dvpe()); | |
794 | panic("IPI Msg. Buffers Depleted\n"); | |
795 | } | |
796 | pipi->type = type; | |
797 | pipi->arg = (void *)action; | |
798 | pipi->dest = cpu; | |
799 | if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) { | |
603e82ed | 800 | /* If not on same VPE, enqueue and send cross-VPE interrupt */ |
41c594ab RB |
801 | smtc_ipi_nq(&IPIQ[cpu], pipi); |
802 | LOCK_CORE_PRA(); | |
803 | settc(cpu_data[cpu].tc_id); | |
804 | write_vpe_c0_cause(read_vpe_c0_cause() | C_SW1); | |
805 | UNLOCK_CORE_PRA(); | |
806 | } else { | |
807 | /* | |
808 | * Not sufficient to do a LOCK_MT_PRA (dmt) here, | |
809 | * since ASID shootdown on the other VPE may | |
810 | * collide with this operation. | |
811 | */ | |
812 | LOCK_CORE_PRA(); | |
813 | settc(cpu_data[cpu].tc_id); | |
814 | /* Halt the targeted TC */ | |
815 | write_tc_c0_tchalt(TCHALT_H); | |
816 | mips_ihb(); | |
817 | ||
818 | /* | |
819 | * Inspect TCStatus - if IXMT is set, we have to queue | |
820 | * a message. Otherwise, we set up the "interrupt" | |
821 | * of the other TC | |
822 | */ | |
823 | tcstatus = read_tc_c0_tcstatus(); | |
824 | ||
825 | if ((tcstatus & TCSTATUS_IXMT) != 0) { | |
826 | /* | |
8531a35e KK |
827 | * If we're in the the irq-off version of the wait |
828 | * loop, we need to force exit from the wait and | |
829 | * do a direct post of the IPI. | |
830 | */ | |
831 | if (cpu_wait == r4k_wait_irqoff) { | |
832 | tcrestart = read_tc_c0_tcrestart(); | |
833 | if (tcrestart >= (unsigned long)r4k_wait_irqoff | |
834 | && tcrestart < (unsigned long)__pastwait) { | |
835 | write_tc_c0_tcrestart(__pastwait); | |
836 | tcstatus &= ~TCSTATUS_IXMT; | |
837 | write_tc_c0_tcstatus(tcstatus); | |
838 | goto postdirect; | |
839 | } | |
840 | } | |
841 | /* | |
842 | * Otherwise we queue the message for the target TC | |
843 | * to pick up when he does a local_irq_restore() | |
41c594ab RB |
844 | */ |
845 | write_tc_c0_tchalt(0); | |
846 | UNLOCK_CORE_PRA(); | |
41c594ab RB |
847 | smtc_ipi_nq(&IPIQ[cpu], pipi); |
848 | } else { | |
8531a35e | 849 | postdirect: |
41c594ab RB |
850 | post_direct_ipi(cpu, pipi); |
851 | write_tc_c0_tchalt(0); | |
852 | UNLOCK_CORE_PRA(); | |
853 | } | |
854 | } | |
855 | } | |
856 | ||
857 | /* | |
858 | * Send IPI message to Halted TC, TargTC/TargVPE already having been set | |
859 | */ | |
5868756d | 860 | static void post_direct_ipi(int cpu, struct smtc_ipi *pipi) |
41c594ab RB |
861 | { |
862 | struct pt_regs *kstack; | |
863 | unsigned long tcstatus; | |
864 | unsigned long tcrestart; | |
865 | extern u32 kernelsp[NR_CPUS]; | |
866 | extern void __smtc_ipi_vector(void); | |
ea580401 | 867 | //printk("%s: on %d for %d\n", __func__, smp_processor_id(), cpu); |
41c594ab RB |
868 | |
869 | /* Extract Status, EPC from halted TC */ | |
870 | tcstatus = read_tc_c0_tcstatus(); | |
871 | tcrestart = read_tc_c0_tcrestart(); | |
872 | /* If TCRestart indicates a WAIT instruction, advance the PC */ | |
873 | if ((tcrestart & 0x80000000) | |
874 | && ((*(unsigned int *)tcrestart & 0xfe00003f) == 0x42000020)) { | |
875 | tcrestart += 4; | |
876 | } | |
877 | /* | |
878 | * Save on TC's future kernel stack | |
879 | * | |
880 | * CU bit of Status is indicator that TC was | |
881 | * already running on a kernel stack... | |
882 | */ | |
4bf42d42 | 883 | if (tcstatus & ST0_CU0) { |
41c594ab RB |
884 | /* Note that this "- 1" is pointer arithmetic */ |
885 | kstack = ((struct pt_regs *)read_tc_gpr_sp()) - 1; | |
886 | } else { | |
887 | kstack = ((struct pt_regs *)kernelsp[cpu]) - 1; | |
888 | } | |
889 | ||
890 | kstack->cp0_epc = (long)tcrestart; | |
891 | /* Save TCStatus */ | |
892 | kstack->cp0_tcstatus = tcstatus; | |
893 | /* Pass token of operation to be performed kernel stack pad area */ | |
894 | kstack->pad0[4] = (unsigned long)pipi; | |
895 | /* Pass address of function to be called likewise */ | |
896 | kstack->pad0[5] = (unsigned long)&ipi_decode; | |
897 | /* Set interrupt exempt and kernel mode */ | |
898 | tcstatus |= TCSTATUS_IXMT; | |
899 | tcstatus &= ~TCSTATUS_TKSU; | |
900 | write_tc_c0_tcstatus(tcstatus); | |
901 | ehb(); | |
902 | /* Set TC Restart address to be SMTC IPI vector */ | |
903 | write_tc_c0_tcrestart(__smtc_ipi_vector); | |
904 | } | |
905 | ||
937a8015 | 906 | static void ipi_resched_interrupt(void) |
41c594ab RB |
907 | { |
908 | /* Return from interrupt should be enough to cause scheduler check */ | |
909 | } | |
910 | ||
937a8015 | 911 | static void ipi_call_interrupt(void) |
41c594ab RB |
912 | { |
913 | /* Invoke generic function invocation code in smp.c */ | |
914 | smp_call_function_interrupt(); | |
915 | } | |
916 | ||
8531a35e | 917 | DECLARE_PER_CPU(struct clock_event_device, mips_clockevent_device); |
ea580401 | 918 | |
937a8015 | 919 | void ipi_decode(struct smtc_ipi *pipi) |
41c594ab | 920 | { |
ea580401 RB |
921 | unsigned int cpu = smp_processor_id(); |
922 | struct clock_event_device *cd; | |
41c594ab RB |
923 | void *arg_copy = pipi->arg; |
924 | int type_copy = pipi->type; | |
d2287f5e MT |
925 | int irq = MIPS_CPU_IRQ_BASE + 1; |
926 | ||
41c594ab | 927 | smtc_ipi_nq(&freeIPIq, pipi); |
dbc1d911 | 928 | |
41c594ab | 929 | switch (type_copy) { |
4bf42d42 | 930 | case SMTC_CLOCK_TICK: |
ae036b79 | 931 | irq_enter(); |
d2287f5e | 932 | kstat_incr_irqs_this_cpu(irq, irq_to_desc(irq)); |
8531a35e KK |
933 | cd = &per_cpu(mips_clockevent_device, cpu); |
934 | cd->event_handler(cd); | |
ae036b79 | 935 | irq_exit(); |
4bf42d42 | 936 | break; |
ea580401 | 937 | |
4bf42d42 RB |
938 | case LINUX_SMP_IPI: |
939 | switch ((int)arg_copy) { | |
940 | case SMP_RESCHEDULE_YOURSELF: | |
937a8015 | 941 | ipi_resched_interrupt(); |
41c594ab | 942 | break; |
4bf42d42 | 943 | case SMP_CALL_FUNCTION: |
937a8015 | 944 | ipi_call_interrupt(); |
41c594ab RB |
945 | break; |
946 | default: | |
4bf42d42 RB |
947 | printk("Impossible SMTC IPI Argument 0x%x\n", |
948 | (int)arg_copy); | |
41c594ab | 949 | break; |
4bf42d42 RB |
950 | } |
951 | break; | |
f571eff0 KK |
952 | #ifdef CONFIG_MIPS_MT_SMTC_IRQAFF |
953 | case IRQ_AFFINITY_IPI: | |
954 | /* | |
955 | * Accept a "forwarded" interrupt that was initially | |
956 | * taken by a TC who doesn't have affinity for the IRQ. | |
957 | */ | |
958 | do_IRQ_no_affinity((int)arg_copy); | |
959 | break; | |
960 | #endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ | |
4bf42d42 RB |
961 | default: |
962 | printk("Impossible SMTC IPI Type 0x%x\n", type_copy); | |
963 | break; | |
41c594ab RB |
964 | } |
965 | } | |
966 | ||
8531a35e KK |
967 | /* |
968 | * Similar to smtc_ipi_replay(), but invoked from context restore, | |
969 | * so it reuses the current exception frame rather than set up a | |
970 | * new one with self_ipi. | |
971 | */ | |
972 | ||
937a8015 | 973 | void deferred_smtc_ipi(void) |
41c594ab | 974 | { |
8531a35e | 975 | int cpu = smp_processor_id(); |
41c594ab RB |
976 | |
977 | /* | |
978 | * Test is not atomic, but much faster than a dequeue, | |
979 | * and the vast majority of invocations will have a null queue. | |
8531a35e KK |
980 | * If irq_disabled when this was called, then any IPIs queued |
981 | * after we test last will be taken on the next irq_enable/restore. | |
982 | * If interrupts were enabled, then any IPIs added after the | |
983 | * last test will be taken directly. | |
41c594ab | 984 | */ |
8531a35e KK |
985 | |
986 | while (IPIQ[cpu].head != NULL) { | |
987 | struct smtc_ipi_q *q = &IPIQ[cpu]; | |
988 | struct smtc_ipi *pipi; | |
989 | unsigned long flags; | |
990 | ||
991 | /* | |
992 | * It may be possible we'll come in with interrupts | |
993 | * already enabled. | |
994 | */ | |
995 | local_irq_save(flags); | |
996 | ||
997 | spin_lock(&q->lock); | |
998 | pipi = __smtc_ipi_dq(q); | |
999 | spin_unlock(&q->lock); | |
1000 | if (pipi != NULL) | |
937a8015 | 1001 | ipi_decode(pipi); |
8531a35e KK |
1002 | /* |
1003 | * The use of the __raw_local restore isn't | |
1004 | * as obviously necessary here as in smtc_ipi_replay(), | |
1005 | * but it's more efficient, given that we're already | |
1006 | * running down the IPI queue. | |
1007 | */ | |
1008 | __raw_local_irq_restore(flags); | |
41c594ab RB |
1009 | } |
1010 | } | |
1011 | ||
41c594ab RB |
1012 | /* |
1013 | * Cross-VPE interrupts in the SMTC prototype use "software interrupts" | |
1014 | * set via cross-VPE MTTR manipulation of the Cause register. It would be | |
1015 | * in some regards preferable to have external logic for "doorbell" hardware | |
1016 | * interrupts. | |
1017 | */ | |
1018 | ||
97dcb82d | 1019 | static int cpu_ipi_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_IRQ; |
41c594ab | 1020 | |
937a8015 | 1021 | static irqreturn_t ipi_interrupt(int irq, void *dev_idm) |
41c594ab RB |
1022 | { |
1023 | int my_vpe = cpu_data[smp_processor_id()].vpe_id; | |
1024 | int my_tc = cpu_data[smp_processor_id()].tc_id; | |
1025 | int cpu; | |
1026 | struct smtc_ipi *pipi; | |
1027 | unsigned long tcstatus; | |
1028 | int sent; | |
b7e4226e | 1029 | unsigned long flags; |
41c594ab RB |
1030 | unsigned int mtflags; |
1031 | unsigned int vpflags; | |
1032 | ||
1033 | /* | |
1034 | * So long as cross-VPE interrupts are done via | |
1035 | * MFTR/MTTR read-modify-writes of Cause, we need | |
1036 | * to stop other VPEs whenever the local VPE does | |
1037 | * anything similar. | |
1038 | */ | |
1039 | local_irq_save(flags); | |
1040 | vpflags = dvpe(); | |
1041 | clear_c0_cause(0x100 << MIPS_CPU_IPI_IRQ); | |
1042 | set_c0_status(0x100 << MIPS_CPU_IPI_IRQ); | |
1043 | irq_enable_hazard(); | |
1044 | evpe(vpflags); | |
1045 | local_irq_restore(flags); | |
1046 | ||
1047 | /* | |
1048 | * Cross-VPE Interrupt handler: Try to directly deliver IPIs | |
1049 | * queued for TCs on this VPE other than the current one. | |
1050 | * Return-from-interrupt should cause us to drain the queue | |
1051 | * for the current TC, so we ought not to have to do it explicitly here. | |
1052 | */ | |
1053 | ||
1054 | for_each_online_cpu(cpu) { | |
1055 | if (cpu_data[cpu].vpe_id != my_vpe) | |
1056 | continue; | |
1057 | ||
1058 | pipi = smtc_ipi_dq(&IPIQ[cpu]); | |
1059 | if (pipi != NULL) { | |
1060 | if (cpu_data[cpu].tc_id != my_tc) { | |
1061 | sent = 0; | |
1062 | LOCK_MT_PRA(); | |
1063 | settc(cpu_data[cpu].tc_id); | |
1064 | write_tc_c0_tchalt(TCHALT_H); | |
1065 | mips_ihb(); | |
1066 | tcstatus = read_tc_c0_tcstatus(); | |
1067 | if ((tcstatus & TCSTATUS_IXMT) == 0) { | |
1068 | post_direct_ipi(cpu, pipi); | |
1069 | sent = 1; | |
1070 | } | |
1071 | write_tc_c0_tchalt(0); | |
1072 | UNLOCK_MT_PRA(); | |
1073 | if (!sent) { | |
1074 | smtc_ipi_req(&IPIQ[cpu], pipi); | |
1075 | } | |
1076 | } else { | |
1077 | /* | |
1078 | * ipi_decode() should be called | |
1079 | * with interrupts off | |
1080 | */ | |
1081 | local_irq_save(flags); | |
937a8015 | 1082 | ipi_decode(pipi); |
41c594ab RB |
1083 | local_irq_restore(flags); |
1084 | } | |
1085 | } | |
1086 | } | |
1087 | ||
1088 | return IRQ_HANDLED; | |
1089 | } | |
1090 | ||
937a8015 | 1091 | static void ipi_irq_dispatch(void) |
41c594ab | 1092 | { |
937a8015 | 1093 | do_IRQ(cpu_ipi_irq); |
41c594ab RB |
1094 | } |
1095 | ||
033890b0 RB |
1096 | static struct irqaction irq_ipi = { |
1097 | .handler = ipi_interrupt, | |
1098 | .flags = IRQF_DISABLED, | |
1099 | .name = "SMTC_IPI", | |
1100 | .flags = IRQF_PERCPU | |
1101 | }; | |
41c594ab | 1102 | |
20bb25d1 | 1103 | static void setup_cross_vpe_interrupts(unsigned int nvpe) |
41c594ab | 1104 | { |
20bb25d1 RB |
1105 | if (nvpe < 1) |
1106 | return; | |
1107 | ||
41c594ab | 1108 | if (!cpu_has_vint) |
603e82ed | 1109 | panic("SMTC Kernel requires Vectored Interrupt support"); |
41c594ab RB |
1110 | |
1111 | set_vi_handler(MIPS_CPU_IPI_IRQ, ipi_irq_dispatch); | |
1112 | ||
41c594ab RB |
1113 | setup_irq_smtc(cpu_ipi_irq, &irq_ipi, (0x100 << MIPS_CPU_IPI_IRQ)); |
1114 | ||
1417836e | 1115 | set_irq_handler(cpu_ipi_irq, handle_percpu_irq); |
41c594ab RB |
1116 | } |
1117 | ||
1118 | /* | |
1119 | * SMTC-specific hacks invoked from elsewhere in the kernel. | |
1120 | */ | |
1121 | ||
8531a35e KK |
1122 | /* |
1123 | * smtc_ipi_replay is called from raw_local_irq_restore | |
1124 | */ | |
1125 | ||
1126 | void smtc_ipi_replay(void) | |
ac8be955 | 1127 | { |
8a1e97ee RB |
1128 | unsigned int cpu = smp_processor_id(); |
1129 | ||
ac8be955 RB |
1130 | /* |
1131 | * To the extent that we've ever turned interrupts off, | |
1132 | * we may have accumulated deferred IPIs. This is subtle. | |
ac8be955 RB |
1133 | * we should be OK: If we pick up something and dispatch |
1134 | * it here, that's great. If we see nothing, but concurrent | |
1135 | * with this operation, another TC sends us an IPI, IXMT | |
1136 | * is clear, and we'll handle it as a real pseudo-interrupt | |
8531a35e KK |
1137 | * and not a pseudo-pseudo interrupt. The important thing |
1138 | * is to do the last check for queued message *after* the | |
1139 | * re-enabling of interrupts. | |
ac8be955 | 1140 | */ |
8531a35e KK |
1141 | while (IPIQ[cpu].head != NULL) { |
1142 | struct smtc_ipi_q *q = &IPIQ[cpu]; | |
1143 | struct smtc_ipi *pipi; | |
1144 | unsigned long flags; | |
ac8be955 | 1145 | |
8531a35e KK |
1146 | /* |
1147 | * It's just possible we'll come in with interrupts | |
1148 | * already enabled. | |
1149 | */ | |
1150 | local_irq_save(flags); | |
1151 | ||
1152 | spin_lock(&q->lock); | |
1153 | pipi = __smtc_ipi_dq(q); | |
1154 | spin_unlock(&q->lock); | |
1155 | /* | |
1156 | ** But use a raw restore here to avoid recursion. | |
1157 | */ | |
1158 | __raw_local_irq_restore(flags); | |
1159 | ||
1160 | if (pipi) { | |
ac8be955 | 1161 | self_ipi(pipi); |
8a1e97ee | 1162 | smtc_cpu_stats[cpu].selfipis++; |
ac8be955 RB |
1163 | } |
1164 | } | |
1165 | } | |
1166 | ||
ec43c014 RB |
1167 | EXPORT_SYMBOL(smtc_ipi_replay); |
1168 | ||
41c594ab RB |
1169 | void smtc_idle_loop_hook(void) |
1170 | { | |
c68644d3 | 1171 | #ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG |
41c594ab RB |
1172 | int im; |
1173 | int flags; | |
1174 | int mtflags; | |
1175 | int bit; | |
1176 | int vpe; | |
1177 | int tc; | |
1178 | int hook_ntcs; | |
1179 | /* | |
1180 | * printk within DMT-protected regions can deadlock, | |
1181 | * so buffer diagnostic messages for later output. | |
1182 | */ | |
1183 | char *pdb_msg; | |
1184 | char id_ho_db_msg[768]; /* worst-case use should be less than 700 */ | |
1185 | ||
1186 | if (atomic_read(&idle_hook_initialized) == 0) { /* fast test */ | |
1187 | if (atomic_add_return(1, &idle_hook_initialized) == 1) { | |
1188 | int mvpconf0; | |
1189 | /* Tedious stuff to just do once */ | |
1190 | mvpconf0 = read_c0_mvpconf0(); | |
1191 | hook_ntcs = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1; | |
1192 | if (hook_ntcs > NR_CPUS) | |
1193 | hook_ntcs = NR_CPUS; | |
1194 | for (tc = 0; tc < hook_ntcs; tc++) { | |
1195 | tcnoprog[tc] = 0; | |
1196 | clock_hang_reported[tc] = 0; | |
1197 | } | |
1198 | for (vpe = 0; vpe < 2; vpe++) | |
1199 | for (im = 0; im < 8; im++) | |
1200 | imstuckcount[vpe][im] = 0; | |
1201 | printk("Idle loop test hook initialized for %d TCs\n", hook_ntcs); | |
1202 | atomic_set(&idle_hook_initialized, 1000); | |
1203 | } else { | |
1204 | /* Someone else is initializing in parallel - let 'em finish */ | |
1205 | while (atomic_read(&idle_hook_initialized) < 1000) | |
1206 | ; | |
1207 | } | |
1208 | } | |
1209 | ||
1210 | /* Have we stupidly left IXMT set somewhere? */ | |
1211 | if (read_c0_tcstatus() & 0x400) { | |
1212 | write_c0_tcstatus(read_c0_tcstatus() & ~0x400); | |
1213 | ehb(); | |
1214 | printk("Dangling IXMT in cpu_idle()\n"); | |
1215 | } | |
1216 | ||
1217 | /* Have we stupidly left an IM bit turned off? */ | |
1218 | #define IM_LIMIT 2000 | |
1219 | local_irq_save(flags); | |
1220 | mtflags = dmt(); | |
1221 | pdb_msg = &id_ho_db_msg[0]; | |
1222 | im = read_c0_status(); | |
8f8771a0 | 1223 | vpe = current_cpu_data.vpe_id; |
41c594ab RB |
1224 | for (bit = 0; bit < 8; bit++) { |
1225 | /* | |
1226 | * In current prototype, I/O interrupts | |
1227 | * are masked for VPE > 0 | |
1228 | */ | |
1229 | if (vpemask[vpe][bit]) { | |
1230 | if (!(im & (0x100 << bit))) | |
1231 | imstuckcount[vpe][bit]++; | |
1232 | else | |
1233 | imstuckcount[vpe][bit] = 0; | |
1234 | if (imstuckcount[vpe][bit] > IM_LIMIT) { | |
1235 | set_c0_status(0x100 << bit); | |
1236 | ehb(); | |
1237 | imstuckcount[vpe][bit] = 0; | |
1238 | pdb_msg += sprintf(pdb_msg, | |
1239 | "Dangling IM %d fixed for VPE %d\n", bit, | |
1240 | vpe); | |
1241 | } | |
1242 | } | |
1243 | } | |
1244 | ||
41c594ab RB |
1245 | emt(mtflags); |
1246 | local_irq_restore(flags); | |
1247 | if (pdb_msg != &id_ho_db_msg[0]) | |
1248 | printk("CPU%d: %s", smp_processor_id(), id_ho_db_msg); | |
c68644d3 | 1249 | #endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */ |
ac8be955 | 1250 | |
8531a35e | 1251 | smtc_ipi_replay(); |
41c594ab RB |
1252 | } |
1253 | ||
1254 | void smtc_soft_dump(void) | |
1255 | { | |
1256 | int i; | |
1257 | ||
1258 | printk("Counter Interrupts taken per CPU (TC)\n"); | |
1259 | for (i=0; i < NR_CPUS; i++) { | |
1260 | printk("%d: %ld\n", i, smtc_cpu_stats[i].timerints); | |
1261 | } | |
1262 | printk("Self-IPI invocations:\n"); | |
1263 | for (i=0; i < NR_CPUS; i++) { | |
1264 | printk("%d: %ld\n", i, smtc_cpu_stats[i].selfipis); | |
1265 | } | |
1266 | smtc_ipi_qdump(); | |
41c594ab RB |
1267 | printk("%d Recoveries of \"stolen\" FPU\n", |
1268 | atomic_read(&smtc_fpu_recoveries)); | |
1269 | } | |
1270 | ||
1271 | ||
1272 | /* | |
1273 | * TLB management routines special to SMTC | |
1274 | */ | |
1275 | ||
1276 | void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu) | |
1277 | { | |
1278 | unsigned long flags, mtflags, tcstat, prevhalt, asid; | |
1279 | int tlb, i; | |
1280 | ||
1281 | /* | |
1282 | * It would be nice to be able to use a spinlock here, | |
1283 | * but this is invoked from within TLB flush routines | |
1284 | * that protect themselves with DVPE, so if a lock is | |
e0daad44 | 1285 | * held by another TC, it'll never be freed. |
41c594ab RB |
1286 | * |
1287 | * DVPE/DMT must not be done with interrupts enabled, | |
1288 | * so even so most callers will already have disabled | |
1289 | * them, let's be really careful... | |
1290 | */ | |
1291 | ||
1292 | local_irq_save(flags); | |
1293 | if (smtc_status & SMTC_TLB_SHARED) { | |
1294 | mtflags = dvpe(); | |
1295 | tlb = 0; | |
1296 | } else { | |
1297 | mtflags = dmt(); | |
1298 | tlb = cpu_data[cpu].vpe_id; | |
1299 | } | |
1300 | asid = asid_cache(cpu); | |
1301 | ||
1302 | do { | |
1303 | if (!((asid += ASID_INC) & ASID_MASK) ) { | |
1304 | if (cpu_has_vtag_icache) | |
1305 | flush_icache_all(); | |
1306 | /* Traverse all online CPUs (hack requires contigous range) */ | |
b5eb5511 | 1307 | for_each_online_cpu(i) { |
41c594ab RB |
1308 | /* |
1309 | * We don't need to worry about our own CPU, nor those of | |
1310 | * CPUs who don't share our TLB. | |
1311 | */ | |
1312 | if ((i != smp_processor_id()) && | |
1313 | ((smtc_status & SMTC_TLB_SHARED) || | |
1314 | (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id))) { | |
1315 | settc(cpu_data[i].tc_id); | |
1316 | prevhalt = read_tc_c0_tchalt() & TCHALT_H; | |
1317 | if (!prevhalt) { | |
1318 | write_tc_c0_tchalt(TCHALT_H); | |
1319 | mips_ihb(); | |
1320 | } | |
1321 | tcstat = read_tc_c0_tcstatus(); | |
1322 | smtc_live_asid[tlb][(tcstat & ASID_MASK)] |= (asiduse)(0x1 << i); | |
1323 | if (!prevhalt) | |
1324 | write_tc_c0_tchalt(0); | |
1325 | } | |
1326 | } | |
1327 | if (!asid) /* fix version if needed */ | |
1328 | asid = ASID_FIRST_VERSION; | |
1329 | local_flush_tlb_all(); /* start new asid cycle */ | |
1330 | } | |
1331 | } while (smtc_live_asid[tlb][(asid & ASID_MASK)]); | |
1332 | ||
1333 | /* | |
1334 | * SMTC shares the TLB within VPEs and possibly across all VPEs. | |
1335 | */ | |
b5eb5511 | 1336 | for_each_online_cpu(i) { |
41c594ab RB |
1337 | if ((smtc_status & SMTC_TLB_SHARED) || |
1338 | (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id)) | |
1339 | cpu_context(i, mm) = asid_cache(i) = asid; | |
1340 | } | |
1341 | ||
1342 | if (smtc_status & SMTC_TLB_SHARED) | |
1343 | evpe(mtflags); | |
1344 | else | |
1345 | emt(mtflags); | |
1346 | local_irq_restore(flags); | |
1347 | } | |
1348 | ||
1349 | /* | |
1350 | * Invoked from macros defined in mmu_context.h | |
1351 | * which must already have disabled interrupts | |
1352 | * and done a DVPE or DMT as appropriate. | |
1353 | */ | |
1354 | ||
1355 | void smtc_flush_tlb_asid(unsigned long asid) | |
1356 | { | |
1357 | int entry; | |
1358 | unsigned long ehi; | |
1359 | ||
1360 | entry = read_c0_wired(); | |
1361 | ||
1362 | /* Traverse all non-wired entries */ | |
1363 | while (entry < current_cpu_data.tlbsize) { | |
1364 | write_c0_index(entry); | |
1365 | ehb(); | |
1366 | tlb_read(); | |
1367 | ehb(); | |
1368 | ehi = read_c0_entryhi(); | |
4bf42d42 | 1369 | if ((ehi & ASID_MASK) == asid) { |
41c594ab RB |
1370 | /* |
1371 | * Invalidate only entries with specified ASID, | |
1372 | * makiing sure all entries differ. | |
1373 | */ | |
1374 | write_c0_entryhi(CKSEG0 + (entry << (PAGE_SHIFT + 1))); | |
1375 | write_c0_entrylo0(0); | |
1376 | write_c0_entrylo1(0); | |
1377 | mtc0_tlbw_hazard(); | |
1378 | tlb_write_indexed(); | |
1379 | } | |
1380 | entry++; | |
1381 | } | |
1382 | write_c0_index(PARKED_INDEX); | |
1383 | tlbw_use_hazard(); | |
1384 | } | |
1385 | ||
1386 | /* | |
1387 | * Support for single-threading cache flush operations. | |
1388 | */ | |
1389 | ||
5868756d | 1390 | static int halt_state_save[NR_CPUS]; |
41c594ab RB |
1391 | |
1392 | /* | |
1393 | * To really, really be sure that nothing is being done | |
1394 | * by other TCs, halt them all. This code assumes that | |
1395 | * a DVPE has already been done, so while their Halted | |
1396 | * state is theoretically architecturally unstable, in | |
1397 | * practice, it's not going to change while we're looking | |
1398 | * at it. | |
1399 | */ | |
1400 | ||
1401 | void smtc_cflush_lockdown(void) | |
1402 | { | |
1403 | int cpu; | |
1404 | ||
1405 | for_each_online_cpu(cpu) { | |
1406 | if (cpu != smp_processor_id()) { | |
1407 | settc(cpu_data[cpu].tc_id); | |
1408 | halt_state_save[cpu] = read_tc_c0_tchalt(); | |
1409 | write_tc_c0_tchalt(TCHALT_H); | |
1410 | } | |
1411 | } | |
1412 | mips_ihb(); | |
1413 | } | |
1414 | ||
1415 | /* It would be cheating to change the cpu_online states during a flush! */ | |
1416 | ||
1417 | void smtc_cflush_release(void) | |
1418 | { | |
1419 | int cpu; | |
1420 | ||
1421 | /* | |
1422 | * Start with a hazard barrier to ensure | |
1423 | * that all CACHE ops have played through. | |
1424 | */ | |
1425 | mips_ihb(); | |
1426 | ||
1427 | for_each_online_cpu(cpu) { | |
1428 | if (cpu != smp_processor_id()) { | |
1429 | settc(cpu_data[cpu].tc_id); | |
1430 | write_tc_c0_tchalt(halt_state_save[cpu]); | |
1431 | } | |
1432 | } | |
1433 | mips_ihb(); | |
1434 | } |