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1da177e4 LT |
1 | /* |
2 | * This program is free software; you can redistribute it and/or | |
3 | * modify it under the terms of the GNU General Public License | |
4 | * as published by the Free Software Foundation; either version 2 | |
5 | * of the License, or (at your option) any later version. | |
6 | * | |
7 | * This program is distributed in the hope that it will be useful, | |
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
10 | * GNU General Public License for more details. | |
11 | * | |
12 | * You should have received a copy of the GNU General Public License | |
13 | * along with this program; if not, write to the Free Software | |
14 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
15 | * | |
16 | * Copyright (C) 2000, 2001 Kanoj Sarcar | |
17 | * Copyright (C) 2000, 2001 Ralf Baechle | |
18 | * Copyright (C) 2000, 2001 Silicon Graphics, Inc. | |
19 | * Copyright (C) 2000, 2001, 2003 Broadcom Corporation | |
20 | */ | |
21 | #include <linux/cache.h> | |
22 | #include <linux/delay.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/interrupt.h> | |
631330f5 | 25 | #include <linux/smp.h> |
1da177e4 LT |
26 | #include <linux/spinlock.h> |
27 | #include <linux/threads.h> | |
28 | #include <linux/module.h> | |
29 | #include <linux/time.h> | |
30 | #include <linux/timex.h> | |
31 | #include <linux/sched.h> | |
32 | #include <linux/cpumask.h> | |
1e35aaba | 33 | #include <linux/cpu.h> |
4e950f6f | 34 | #include <linux/err.h> |
8f99a162 | 35 | #include <linux/ftrace.h> |
1da177e4 | 36 | |
60063497 | 37 | #include <linux/atomic.h> |
1da177e4 LT |
38 | #include <asm/cpu.h> |
39 | #include <asm/processor.h> | |
39b8d525 | 40 | #include <asm/r4k-timer.h> |
1da177e4 | 41 | #include <asm/mmu_context.h> |
7bcf7717 | 42 | #include <asm/time.h> |
b81947c6 | 43 | #include <asm/setup.h> |
1da177e4 | 44 | |
41c594ab RB |
45 | #ifdef CONFIG_MIPS_MT_SMTC |
46 | #include <asm/mipsmtregs.h> | |
47 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
48 | ||
1b2bc75c | 49 | volatile cpumask_t cpu_callin_map; /* Bitmask of started secondaries */ |
2dc2ae34 | 50 | |
1da177e4 | 51 | int __cpu_number_map[NR_CPUS]; /* Map physical to logical */ |
2dc2ae34 DD |
52 | EXPORT_SYMBOL(__cpu_number_map); |
53 | ||
1da177e4 | 54 | int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */ |
2dc2ae34 | 55 | EXPORT_SYMBOL(__cpu_logical_map); |
1da177e4 | 56 | |
0ab7aefc RB |
57 | /* Number of TCs (or siblings in Intel speak) per CPU core */ |
58 | int smp_num_siblings = 1; | |
59 | EXPORT_SYMBOL(smp_num_siblings); | |
60 | ||
61 | /* representing the TCs (or siblings in Intel speak) of each logical CPU */ | |
62 | cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly; | |
63 | EXPORT_SYMBOL(cpu_sibling_map); | |
64 | ||
65 | /* representing cpus for which sibling maps can be computed */ | |
66 | static cpumask_t cpu_sibling_setup_map; | |
67 | ||
68 | static inline void set_cpu_sibling_map(int cpu) | |
69 | { | |
70 | int i; | |
71 | ||
72 | cpu_set(cpu, cpu_sibling_setup_map); | |
73 | ||
74 | if (smp_num_siblings > 1) { | |
75 | for_each_cpu_mask(i, cpu_sibling_setup_map) { | |
76 | if (cpu_data[cpu].core == cpu_data[i].core) { | |
77 | cpu_set(i, cpu_sibling_map[cpu]); | |
78 | cpu_set(cpu, cpu_sibling_map[i]); | |
79 | } | |
80 | } | |
81 | } else | |
82 | cpu_set(cpu, cpu_sibling_map[cpu]); | |
83 | } | |
84 | ||
87353d8a | 85 | struct plat_smp_ops *mp_ops; |
82d45de6 | 86 | EXPORT_SYMBOL(mp_ops); |
87353d8a RB |
87 | |
88 | __cpuinit void register_smp_ops(struct plat_smp_ops *ops) | |
89 | { | |
83738e30 TS |
90 | if (mp_ops) |
91 | printk(KERN_WARNING "Overriding previously set SMP ops\n"); | |
87353d8a RB |
92 | |
93 | mp_ops = ops; | |
94 | } | |
95 | ||
1da177e4 LT |
96 | /* |
97 | * First C code run on the secondary CPUs after being started up by | |
98 | * the master. | |
99 | */ | |
4ebd5233 | 100 | asmlinkage __cpuinit void start_secondary(void) |
1da177e4 | 101 | { |
5bfb5d69 | 102 | unsigned int cpu; |
1da177e4 | 103 | |
41c594ab RB |
104 | #ifdef CONFIG_MIPS_MT_SMTC |
105 | /* Only do cpu_probe for first TC of CPU */ | |
889a4c7b SH |
106 | if ((read_c0_tcbind() & TCBIND_CURTC) != 0) |
107 | __cpu_name[smp_processor_id()] = __cpu_name[0]; | |
108 | else | |
41c594ab | 109 | #endif /* CONFIG_MIPS_MT_SMTC */ |
1da177e4 LT |
110 | cpu_probe(); |
111 | cpu_report(); | |
6650df3c | 112 | per_cpu_trap_init(false); |
7bcf7717 | 113 | mips_clockevent_init(); |
87353d8a | 114 | mp_ops->init_secondary(); |
1da177e4 LT |
115 | |
116 | /* | |
117 | * XXX parity protection should be folded in here when it's converted | |
118 | * to an option instead of something based on .cputype | |
119 | */ | |
120 | ||
121 | calibrate_delay(); | |
5bfb5d69 NP |
122 | preempt_disable(); |
123 | cpu = smp_processor_id(); | |
1da177e4 LT |
124 | cpu_data[cpu].udelay_val = loops_per_jiffy; |
125 | ||
e545a614 MS |
126 | notify_cpu_starting(cpu); |
127 | ||
b9a09a06 YZ |
128 | set_cpu_online(cpu, true); |
129 | ||
0ab7aefc | 130 | set_cpu_sibling_map(cpu); |
1da177e4 LT |
131 | |
132 | cpu_set(cpu, cpu_callin_map); | |
133 | ||
cf9bfe55 | 134 | synchronise_count_slave(cpu); |
39b8d525 | 135 | |
b789ad63 YZ |
136 | /* |
137 | * irq will be enabled in ->smp_finish(), enabling it too early | |
138 | * is dangerous. | |
139 | */ | |
140 | WARN_ON_ONCE(!irqs_disabled()); | |
5309bdac YZ |
141 | mp_ops->smp_finish(); |
142 | ||
cdbedc61 | 143 | cpu_startup_entry(CPUHP_ONLINE); |
1da177e4 LT |
144 | } |
145 | ||
2f304c0a JA |
146 | /* |
147 | * Call into both interrupt handlers, as we share the IPI for them | |
148 | */ | |
8f99a162 | 149 | void __irq_entry smp_call_function_interrupt(void) |
1da177e4 | 150 | { |
1da177e4 | 151 | irq_enter(); |
2f304c0a JA |
152 | generic_smp_call_function_single_interrupt(); |
153 | generic_smp_call_function_interrupt(); | |
1da177e4 | 154 | irq_exit(); |
b4b2917c PW |
155 | } |
156 | ||
1da177e4 LT |
157 | static void stop_this_cpu(void *dummy) |
158 | { | |
159 | /* | |
160 | * Remove this CPU: | |
161 | */ | |
0b5f9c00 | 162 | set_cpu_online(smp_processor_id(), false); |
7920c4d6 RB |
163 | for (;;) { |
164 | if (cpu_wait) | |
165 | (*cpu_wait)(); /* Wait if available. */ | |
166 | } | |
1da177e4 LT |
167 | } |
168 | ||
169 | void smp_send_stop(void) | |
170 | { | |
8691e5a8 | 171 | smp_call_function(stop_this_cpu, NULL, 0); |
1da177e4 LT |
172 | } |
173 | ||
174 | void __init smp_cpus_done(unsigned int max_cpus) | |
175 | { | |
87353d8a | 176 | mp_ops->cpus_done(); |
1da177e4 LT |
177 | } |
178 | ||
179 | /* called from main before smp_init() */ | |
180 | void __init smp_prepare_cpus(unsigned int max_cpus) | |
181 | { | |
1da177e4 LT |
182 | init_new_context(current, &init_mm); |
183 | current_thread_info()->cpu = 0; | |
87353d8a | 184 | mp_ops->prepare_cpus(max_cpus); |
0ab7aefc | 185 | set_cpu_sibling_map(0); |
320e6aba | 186 | #ifndef CONFIG_HOTPLUG_CPU |
0b5f9c00 | 187 | init_cpu_present(cpu_possible_mask); |
320e6aba | 188 | #endif |
1da177e4 LT |
189 | } |
190 | ||
191 | /* preload SMP state for boot cpu */ | |
28eb0e46 | 192 | void smp_prepare_boot_cpu(void) |
1da177e4 | 193 | { |
4037ac6e RR |
194 | set_cpu_possible(0, true); |
195 | set_cpu_online(0, true); | |
1da177e4 LT |
196 | cpu_set(0, cpu_callin_map); |
197 | } | |
198 | ||
8239c25f | 199 | int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *tidle) |
1da177e4 | 200 | { |
360014a3 | 201 | mp_ops->boot_secondary(cpu, tidle); |
1da177e4 | 202 | |
b727a602 RB |
203 | /* |
204 | * Trust is futile. We should really have timeouts ... | |
205 | */ | |
1da177e4 LT |
206 | while (!cpu_isset(cpu, cpu_callin_map)) |
207 | udelay(100); | |
1da177e4 | 208 | |
cf9bfe55 | 209 | synchronise_count_master(cpu); |
1da177e4 LT |
210 | return 0; |
211 | } | |
212 | ||
1da177e4 LT |
213 | /* Not really SMP stuff ... */ |
214 | int setup_profiling_timer(unsigned int multiplier) | |
215 | { | |
216 | return 0; | |
217 | } | |
218 | ||
219 | static void flush_tlb_all_ipi(void *info) | |
220 | { | |
221 | local_flush_tlb_all(); | |
222 | } | |
223 | ||
224 | void flush_tlb_all(void) | |
225 | { | |
15c8b6c1 | 226 | on_each_cpu(flush_tlb_all_ipi, NULL, 1); |
1da177e4 LT |
227 | } |
228 | ||
229 | static void flush_tlb_mm_ipi(void *mm) | |
230 | { | |
231 | local_flush_tlb_mm((struct mm_struct *)mm); | |
232 | } | |
233 | ||
25969354 RB |
234 | /* |
235 | * Special Variant of smp_call_function for use by TLB functions: | |
236 | * | |
237 | * o No return value | |
238 | * o collapses to normal function call on UP kernels | |
239 | * o collapses to normal function call on systems with a single shared | |
240 | * primary cache. | |
241 | * o CONFIG_MIPS_MT_SMTC currently implies there is only one physical core. | |
242 | */ | |
243 | static inline void smp_on_other_tlbs(void (*func) (void *info), void *info) | |
244 | { | |
245 | #ifndef CONFIG_MIPS_MT_SMTC | |
8691e5a8 | 246 | smp_call_function(func, info, 1); |
25969354 RB |
247 | #endif |
248 | } | |
249 | ||
250 | static inline void smp_on_each_tlb(void (*func) (void *info), void *info) | |
251 | { | |
252 | preempt_disable(); | |
253 | ||
254 | smp_on_other_tlbs(func, info); | |
255 | func(info); | |
256 | ||
257 | preempt_enable(); | |
258 | } | |
259 | ||
1da177e4 LT |
260 | /* |
261 | * The following tlb flush calls are invoked when old translations are | |
262 | * being torn down, or pte attributes are changing. For single threaded | |
263 | * address spaces, a new context is obtained on the current cpu, and tlb | |
264 | * context on other cpus are invalidated to force a new context allocation | |
265 | * at switch_mm time, should the mm ever be used on other cpus. For | |
266 | * multithreaded address spaces, intercpu interrupts have to be sent. | |
267 | * Another case where intercpu interrupts are required is when the target | |
268 | * mm might be active on another cpu (eg debuggers doing the flushes on | |
269 | * behalf of debugees, kswapd stealing pages from another process etc). | |
270 | * Kanoj 07/00. | |
271 | */ | |
272 | ||
273 | void flush_tlb_mm(struct mm_struct *mm) | |
274 | { | |
275 | preempt_disable(); | |
276 | ||
277 | if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) { | |
c50cade9 | 278 | smp_on_other_tlbs(flush_tlb_mm_ipi, mm); |
1da177e4 | 279 | } else { |
b5eb5511 RB |
280 | unsigned int cpu; |
281 | ||
0b5f9c00 RR |
282 | for_each_online_cpu(cpu) { |
283 | if (cpu != smp_processor_id() && cpu_context(cpu, mm)) | |
b5eb5511 | 284 | cpu_context(cpu, mm) = 0; |
0b5f9c00 | 285 | } |
1da177e4 LT |
286 | } |
287 | local_flush_tlb_mm(mm); | |
288 | ||
289 | preempt_enable(); | |
290 | } | |
291 | ||
292 | struct flush_tlb_data { | |
293 | struct vm_area_struct *vma; | |
294 | unsigned long addr1; | |
295 | unsigned long addr2; | |
296 | }; | |
297 | ||
298 | static void flush_tlb_range_ipi(void *info) | |
299 | { | |
c50cade9 | 300 | struct flush_tlb_data *fd = info; |
1da177e4 LT |
301 | |
302 | local_flush_tlb_range(fd->vma, fd->addr1, fd->addr2); | |
303 | } | |
304 | ||
305 | void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) | |
306 | { | |
307 | struct mm_struct *mm = vma->vm_mm; | |
308 | ||
309 | preempt_disable(); | |
310 | if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) { | |
89a8a5a6 RB |
311 | struct flush_tlb_data fd = { |
312 | .vma = vma, | |
313 | .addr1 = start, | |
314 | .addr2 = end, | |
315 | }; | |
1da177e4 | 316 | |
c50cade9 | 317 | smp_on_other_tlbs(flush_tlb_range_ipi, &fd); |
1da177e4 | 318 | } else { |
b5eb5511 RB |
319 | unsigned int cpu; |
320 | ||
0b5f9c00 RR |
321 | for_each_online_cpu(cpu) { |
322 | if (cpu != smp_processor_id() && cpu_context(cpu, mm)) | |
b5eb5511 | 323 | cpu_context(cpu, mm) = 0; |
0b5f9c00 | 324 | } |
1da177e4 LT |
325 | } |
326 | local_flush_tlb_range(vma, start, end); | |
327 | preempt_enable(); | |
328 | } | |
329 | ||
330 | static void flush_tlb_kernel_range_ipi(void *info) | |
331 | { | |
c50cade9 | 332 | struct flush_tlb_data *fd = info; |
1da177e4 LT |
333 | |
334 | local_flush_tlb_kernel_range(fd->addr1, fd->addr2); | |
335 | } | |
336 | ||
337 | void flush_tlb_kernel_range(unsigned long start, unsigned long end) | |
338 | { | |
89a8a5a6 RB |
339 | struct flush_tlb_data fd = { |
340 | .addr1 = start, | |
341 | .addr2 = end, | |
342 | }; | |
1da177e4 | 343 | |
15c8b6c1 | 344 | on_each_cpu(flush_tlb_kernel_range_ipi, &fd, 1); |
1da177e4 LT |
345 | } |
346 | ||
347 | static void flush_tlb_page_ipi(void *info) | |
348 | { | |
c50cade9 | 349 | struct flush_tlb_data *fd = info; |
1da177e4 LT |
350 | |
351 | local_flush_tlb_page(fd->vma, fd->addr1); | |
352 | } | |
353 | ||
354 | void flush_tlb_page(struct vm_area_struct *vma, unsigned long page) | |
355 | { | |
356 | preempt_disable(); | |
357 | if ((atomic_read(&vma->vm_mm->mm_users) != 1) || (current->mm != vma->vm_mm)) { | |
89a8a5a6 RB |
358 | struct flush_tlb_data fd = { |
359 | .vma = vma, | |
360 | .addr1 = page, | |
361 | }; | |
1da177e4 | 362 | |
c50cade9 | 363 | smp_on_other_tlbs(flush_tlb_page_ipi, &fd); |
1da177e4 | 364 | } else { |
b5eb5511 RB |
365 | unsigned int cpu; |
366 | ||
0b5f9c00 RR |
367 | for_each_online_cpu(cpu) { |
368 | if (cpu != smp_processor_id() && cpu_context(cpu, vma->vm_mm)) | |
b5eb5511 | 369 | cpu_context(cpu, vma->vm_mm) = 0; |
0b5f9c00 | 370 | } |
1da177e4 LT |
371 | } |
372 | local_flush_tlb_page(vma, page); | |
373 | preempt_enable(); | |
374 | } | |
375 | ||
376 | static void flush_tlb_one_ipi(void *info) | |
377 | { | |
378 | unsigned long vaddr = (unsigned long) info; | |
379 | ||
380 | local_flush_tlb_one(vaddr); | |
381 | } | |
382 | ||
383 | void flush_tlb_one(unsigned long vaddr) | |
384 | { | |
25969354 | 385 | smp_on_each_tlb(flush_tlb_one_ipi, (void *) vaddr); |
1da177e4 LT |
386 | } |
387 | ||
388 | EXPORT_SYMBOL(flush_tlb_page); | |
389 | EXPORT_SYMBOL(flush_tlb_one); | |
7aa1c8f4 RB |
390 | |
391 | #if defined(CONFIG_KEXEC) | |
392 | void (*dump_ipi_function_ptr)(void *) = NULL; | |
393 | void dump_send_ipi(void (*dump_ipi_callback)(void *)) | |
394 | { | |
395 | int i; | |
396 | int cpu = smp_processor_id(); | |
397 | ||
398 | dump_ipi_function_ptr = dump_ipi_callback; | |
399 | smp_mb(); | |
400 | for_each_online_cpu(i) | |
401 | if (i != cpu) | |
402 | mp_ops->send_ipi_single(i, SMP_DUMP); | |
403 | ||
404 | } | |
405 | EXPORT_SYMBOL(dump_send_ipi); | |
406 | #endif |