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1da177e4 LT |
1 | /* |
2 | * This program is free software; you can redistribute it and/or | |
3 | * modify it under the terms of the GNU General Public License | |
4 | * as published by the Free Software Foundation; either version 2 | |
5 | * of the License, or (at your option) any later version. | |
6 | * | |
7 | * This program is distributed in the hope that it will be useful, | |
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
10 | * GNU General Public License for more details. | |
11 | * | |
12 | * You should have received a copy of the GNU General Public License | |
13 | * along with this program; if not, write to the Free Software | |
14 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
15 | * | |
16 | * Copyright (C) 2000, 2001 Kanoj Sarcar | |
17 | * Copyright (C) 2000, 2001 Ralf Baechle | |
18 | * Copyright (C) 2000, 2001 Silicon Graphics, Inc. | |
19 | * Copyright (C) 2000, 2001, 2003 Broadcom Corporation | |
20 | */ | |
21 | #include <linux/cache.h> | |
22 | #include <linux/delay.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/spinlock.h> | |
26 | #include <linux/threads.h> | |
27 | #include <linux/module.h> | |
28 | #include <linux/time.h> | |
29 | #include <linux/timex.h> | |
30 | #include <linux/sched.h> | |
31 | #include <linux/cpumask.h> | |
1e35aaba | 32 | #include <linux/cpu.h> |
4e950f6f | 33 | #include <linux/err.h> |
1da177e4 LT |
34 | |
35 | #include <asm/atomic.h> | |
36 | #include <asm/cpu.h> | |
37 | #include <asm/processor.h> | |
39b8d525 | 38 | #include <asm/r4k-timer.h> |
1da177e4 LT |
39 | #include <asm/system.h> |
40 | #include <asm/mmu_context.h> | |
7bcf7717 | 41 | #include <asm/time.h> |
1da177e4 | 42 | |
41c594ab RB |
43 | #ifdef CONFIG_MIPS_MT_SMTC |
44 | #include <asm/mipsmtregs.h> | |
45 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
46 | ||
1da177e4 LT |
47 | cpumask_t phys_cpu_present_map; /* Bitmask of available CPUs */ |
48 | volatile cpumask_t cpu_callin_map; /* Bitmask of started secondaries */ | |
49 | cpumask_t cpu_online_map; /* Bitmask of currently online CPUs */ | |
50 | int __cpu_number_map[NR_CPUS]; /* Map physical to logical */ | |
51 | int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */ | |
52 | ||
53 | EXPORT_SYMBOL(phys_cpu_present_map); | |
54 | EXPORT_SYMBOL(cpu_online_map); | |
55 | ||
b3f6df9f | 56 | extern void cpu_idle(void); |
1da177e4 | 57 | |
0ab7aefc RB |
58 | /* Number of TCs (or siblings in Intel speak) per CPU core */ |
59 | int smp_num_siblings = 1; | |
60 | EXPORT_SYMBOL(smp_num_siblings); | |
61 | ||
62 | /* representing the TCs (or siblings in Intel speak) of each logical CPU */ | |
63 | cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly; | |
64 | EXPORT_SYMBOL(cpu_sibling_map); | |
65 | ||
66 | /* representing cpus for which sibling maps can be computed */ | |
67 | static cpumask_t cpu_sibling_setup_map; | |
68 | ||
69 | static inline void set_cpu_sibling_map(int cpu) | |
70 | { | |
71 | int i; | |
72 | ||
73 | cpu_set(cpu, cpu_sibling_setup_map); | |
74 | ||
75 | if (smp_num_siblings > 1) { | |
76 | for_each_cpu_mask(i, cpu_sibling_setup_map) { | |
77 | if (cpu_data[cpu].core == cpu_data[i].core) { | |
78 | cpu_set(i, cpu_sibling_map[cpu]); | |
79 | cpu_set(cpu, cpu_sibling_map[i]); | |
80 | } | |
81 | } | |
82 | } else | |
83 | cpu_set(cpu, cpu_sibling_map[cpu]); | |
84 | } | |
85 | ||
87353d8a RB |
86 | struct plat_smp_ops *mp_ops; |
87 | ||
88 | __cpuinit void register_smp_ops(struct plat_smp_ops *ops) | |
89 | { | |
83738e30 TS |
90 | if (mp_ops) |
91 | printk(KERN_WARNING "Overriding previously set SMP ops\n"); | |
87353d8a RB |
92 | |
93 | mp_ops = ops; | |
94 | } | |
95 | ||
1da177e4 LT |
96 | /* |
97 | * First C code run on the secondary CPUs after being started up by | |
98 | * the master. | |
99 | */ | |
4ebd5233 | 100 | asmlinkage __cpuinit void start_secondary(void) |
1da177e4 | 101 | { |
5bfb5d69 | 102 | unsigned int cpu; |
1da177e4 | 103 | |
41c594ab RB |
104 | #ifdef CONFIG_MIPS_MT_SMTC |
105 | /* Only do cpu_probe for first TC of CPU */ | |
106 | if ((read_c0_tcbind() & TCBIND_CURTC) == 0) | |
107 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
1da177e4 LT |
108 | cpu_probe(); |
109 | cpu_report(); | |
110 | per_cpu_trap_init(); | |
7bcf7717 | 111 | mips_clockevent_init(); |
87353d8a | 112 | mp_ops->init_secondary(); |
1da177e4 LT |
113 | |
114 | /* | |
115 | * XXX parity protection should be folded in here when it's converted | |
116 | * to an option instead of something based on .cputype | |
117 | */ | |
118 | ||
119 | calibrate_delay(); | |
5bfb5d69 NP |
120 | preempt_disable(); |
121 | cpu = smp_processor_id(); | |
1da177e4 LT |
122 | cpu_data[cpu].udelay_val = loops_per_jiffy; |
123 | ||
87353d8a | 124 | mp_ops->smp_finish(); |
0ab7aefc | 125 | set_cpu_sibling_map(cpu); |
1da177e4 LT |
126 | |
127 | cpu_set(cpu, cpu_callin_map); | |
128 | ||
39b8d525 RB |
129 | synchronise_count_slave(); |
130 | ||
1da177e4 LT |
131 | cpu_idle(); |
132 | } | |
133 | ||
2f304c0a | 134 | void arch_send_call_function_ipi(cpumask_t mask) |
1da177e4 | 135 | { |
87353d8a | 136 | mp_ops->send_ipi_mask(mask, SMP_CALL_FUNCTION); |
1da177e4 LT |
137 | } |
138 | ||
2f304c0a JA |
139 | /* |
140 | * We reuse the same vector for the single IPI | |
141 | */ | |
142 | void arch_send_call_function_single_ipi(int cpu) | |
bd6aeeff | 143 | { |
2f304c0a | 144 | mp_ops->send_ipi_mask(cpumask_of_cpu(cpu), SMP_CALL_FUNCTION); |
bd6aeeff | 145 | } |
41c594ab | 146 | |
2f304c0a JA |
147 | /* |
148 | * Call into both interrupt handlers, as we share the IPI for them | |
149 | */ | |
1da177e4 LT |
150 | void smp_call_function_interrupt(void) |
151 | { | |
1da177e4 | 152 | irq_enter(); |
2f304c0a JA |
153 | generic_smp_call_function_single_interrupt(); |
154 | generic_smp_call_function_interrupt(); | |
1da177e4 | 155 | irq_exit(); |
b4b2917c PW |
156 | } |
157 | ||
1da177e4 LT |
158 | static void stop_this_cpu(void *dummy) |
159 | { | |
160 | /* | |
161 | * Remove this CPU: | |
162 | */ | |
163 | cpu_clear(smp_processor_id(), cpu_online_map); | |
164 | local_irq_enable(); /* May need to service _machine_restart IPI */ | |
165 | for (;;); /* Wait if available. */ | |
166 | } | |
167 | ||
168 | void smp_send_stop(void) | |
169 | { | |
8691e5a8 | 170 | smp_call_function(stop_this_cpu, NULL, 0); |
1da177e4 LT |
171 | } |
172 | ||
173 | void __init smp_cpus_done(unsigned int max_cpus) | |
174 | { | |
87353d8a | 175 | mp_ops->cpus_done(); |
39b8d525 | 176 | synchronise_count_master(); |
1da177e4 LT |
177 | } |
178 | ||
179 | /* called from main before smp_init() */ | |
180 | void __init smp_prepare_cpus(unsigned int max_cpus) | |
181 | { | |
1da177e4 LT |
182 | init_new_context(current, &init_mm); |
183 | current_thread_info()->cpu = 0; | |
87353d8a | 184 | mp_ops->prepare_cpus(max_cpus); |
0ab7aefc | 185 | set_cpu_sibling_map(0); |
320e6aba RB |
186 | #ifndef CONFIG_HOTPLUG_CPU |
187 | cpu_present_map = cpu_possible_map; | |
188 | #endif | |
1da177e4 LT |
189 | } |
190 | ||
191 | /* preload SMP state for boot cpu */ | |
192 | void __devinit smp_prepare_boot_cpu(void) | |
193 | { | |
194 | /* | |
195 | * This assumes that bootup is always handled by the processor | |
196 | * with the logic and physical number 0. | |
197 | */ | |
198 | __cpu_number_map[0] = 0; | |
199 | __cpu_logical_map[0] = 0; | |
200 | cpu_set(0, phys_cpu_present_map); | |
201 | cpu_set(0, cpu_online_map); | |
202 | cpu_set(0, cpu_callin_map); | |
203 | } | |
204 | ||
205 | /* | |
b727a602 RB |
206 | * Called once for each "cpu_possible(cpu)". Needs to spin up the cpu |
207 | * and keep control until "cpu_online(cpu)" is set. Note: cpu is | |
208 | * physical, not logical. | |
1da177e4 | 209 | */ |
b282b6f8 | 210 | int __cpuinit __cpu_up(unsigned int cpu) |
1da177e4 LT |
211 | { |
212 | struct task_struct *idle; | |
213 | ||
214 | /* | |
b727a602 | 215 | * Processor goes to start_secondary(), sets online flag |
1da177e4 LT |
216 | * The following code is purely to make sure |
217 | * Linux can schedule processes on this slave. | |
218 | */ | |
219 | idle = fork_idle(cpu); | |
220 | if (IS_ERR(idle)) | |
b727a602 | 221 | panic(KERN_ERR "Fork failed for CPU %d", cpu); |
1da177e4 | 222 | |
87353d8a | 223 | mp_ops->boot_secondary(cpu, idle); |
1da177e4 | 224 | |
b727a602 RB |
225 | /* |
226 | * Trust is futile. We should really have timeouts ... | |
227 | */ | |
1da177e4 LT |
228 | while (!cpu_isset(cpu, cpu_callin_map)) |
229 | udelay(100); | |
230 | ||
231 | cpu_set(cpu, cpu_online_map); | |
232 | ||
233 | return 0; | |
234 | } | |
235 | ||
1da177e4 LT |
236 | /* Not really SMP stuff ... */ |
237 | int setup_profiling_timer(unsigned int multiplier) | |
238 | { | |
239 | return 0; | |
240 | } | |
241 | ||
242 | static void flush_tlb_all_ipi(void *info) | |
243 | { | |
244 | local_flush_tlb_all(); | |
245 | } | |
246 | ||
247 | void flush_tlb_all(void) | |
248 | { | |
9a244b95 | 249 | on_each_cpu(flush_tlb_all_ipi, NULL, 1, 1); |
1da177e4 LT |
250 | } |
251 | ||
252 | static void flush_tlb_mm_ipi(void *mm) | |
253 | { | |
254 | local_flush_tlb_mm((struct mm_struct *)mm); | |
255 | } | |
256 | ||
25969354 RB |
257 | /* |
258 | * Special Variant of smp_call_function for use by TLB functions: | |
259 | * | |
260 | * o No return value | |
261 | * o collapses to normal function call on UP kernels | |
262 | * o collapses to normal function call on systems with a single shared | |
263 | * primary cache. | |
264 | * o CONFIG_MIPS_MT_SMTC currently implies there is only one physical core. | |
265 | */ | |
266 | static inline void smp_on_other_tlbs(void (*func) (void *info), void *info) | |
267 | { | |
268 | #ifndef CONFIG_MIPS_MT_SMTC | |
8691e5a8 | 269 | smp_call_function(func, info, 1); |
25969354 RB |
270 | #endif |
271 | } | |
272 | ||
273 | static inline void smp_on_each_tlb(void (*func) (void *info), void *info) | |
274 | { | |
275 | preempt_disable(); | |
276 | ||
277 | smp_on_other_tlbs(func, info); | |
278 | func(info); | |
279 | ||
280 | preempt_enable(); | |
281 | } | |
282 | ||
1da177e4 LT |
283 | /* |
284 | * The following tlb flush calls are invoked when old translations are | |
285 | * being torn down, or pte attributes are changing. For single threaded | |
286 | * address spaces, a new context is obtained on the current cpu, and tlb | |
287 | * context on other cpus are invalidated to force a new context allocation | |
288 | * at switch_mm time, should the mm ever be used on other cpus. For | |
289 | * multithreaded address spaces, intercpu interrupts have to be sent. | |
290 | * Another case where intercpu interrupts are required is when the target | |
291 | * mm might be active on another cpu (eg debuggers doing the flushes on | |
292 | * behalf of debugees, kswapd stealing pages from another process etc). | |
293 | * Kanoj 07/00. | |
294 | */ | |
295 | ||
296 | void flush_tlb_mm(struct mm_struct *mm) | |
297 | { | |
298 | preempt_disable(); | |
299 | ||
300 | if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) { | |
c50cade9 | 301 | smp_on_other_tlbs(flush_tlb_mm_ipi, mm); |
1da177e4 | 302 | } else { |
b5eb5511 RB |
303 | cpumask_t mask = cpu_online_map; |
304 | unsigned int cpu; | |
305 | ||
306 | cpu_clear(smp_processor_id(), mask); | |
ece8a9e4 | 307 | for_each_cpu_mask(cpu, mask) |
b5eb5511 RB |
308 | if (cpu_context(cpu, mm)) |
309 | cpu_context(cpu, mm) = 0; | |
1da177e4 LT |
310 | } |
311 | local_flush_tlb_mm(mm); | |
312 | ||
313 | preempt_enable(); | |
314 | } | |
315 | ||
316 | struct flush_tlb_data { | |
317 | struct vm_area_struct *vma; | |
318 | unsigned long addr1; | |
319 | unsigned long addr2; | |
320 | }; | |
321 | ||
322 | static void flush_tlb_range_ipi(void *info) | |
323 | { | |
c50cade9 | 324 | struct flush_tlb_data *fd = info; |
1da177e4 LT |
325 | |
326 | local_flush_tlb_range(fd->vma, fd->addr1, fd->addr2); | |
327 | } | |
328 | ||
329 | void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) | |
330 | { | |
331 | struct mm_struct *mm = vma->vm_mm; | |
332 | ||
333 | preempt_disable(); | |
334 | if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) { | |
89a8a5a6 RB |
335 | struct flush_tlb_data fd = { |
336 | .vma = vma, | |
337 | .addr1 = start, | |
338 | .addr2 = end, | |
339 | }; | |
1da177e4 | 340 | |
c50cade9 | 341 | smp_on_other_tlbs(flush_tlb_range_ipi, &fd); |
1da177e4 | 342 | } else { |
b5eb5511 RB |
343 | cpumask_t mask = cpu_online_map; |
344 | unsigned int cpu; | |
345 | ||
346 | cpu_clear(smp_processor_id(), mask); | |
ece8a9e4 | 347 | for_each_cpu_mask(cpu, mask) |
b5eb5511 RB |
348 | if (cpu_context(cpu, mm)) |
349 | cpu_context(cpu, mm) = 0; | |
1da177e4 LT |
350 | } |
351 | local_flush_tlb_range(vma, start, end); | |
352 | preempt_enable(); | |
353 | } | |
354 | ||
355 | static void flush_tlb_kernel_range_ipi(void *info) | |
356 | { | |
c50cade9 | 357 | struct flush_tlb_data *fd = info; |
1da177e4 LT |
358 | |
359 | local_flush_tlb_kernel_range(fd->addr1, fd->addr2); | |
360 | } | |
361 | ||
362 | void flush_tlb_kernel_range(unsigned long start, unsigned long end) | |
363 | { | |
89a8a5a6 RB |
364 | struct flush_tlb_data fd = { |
365 | .addr1 = start, | |
366 | .addr2 = end, | |
367 | }; | |
1da177e4 | 368 | |
c50cade9 | 369 | on_each_cpu(flush_tlb_kernel_range_ipi, &fd, 1, 1); |
1da177e4 LT |
370 | } |
371 | ||
372 | static void flush_tlb_page_ipi(void *info) | |
373 | { | |
c50cade9 | 374 | struct flush_tlb_data *fd = info; |
1da177e4 LT |
375 | |
376 | local_flush_tlb_page(fd->vma, fd->addr1); | |
377 | } | |
378 | ||
379 | void flush_tlb_page(struct vm_area_struct *vma, unsigned long page) | |
380 | { | |
381 | preempt_disable(); | |
382 | if ((atomic_read(&vma->vm_mm->mm_users) != 1) || (current->mm != vma->vm_mm)) { | |
89a8a5a6 RB |
383 | struct flush_tlb_data fd = { |
384 | .vma = vma, | |
385 | .addr1 = page, | |
386 | }; | |
1da177e4 | 387 | |
c50cade9 | 388 | smp_on_other_tlbs(flush_tlb_page_ipi, &fd); |
1da177e4 | 389 | } else { |
b5eb5511 RB |
390 | cpumask_t mask = cpu_online_map; |
391 | unsigned int cpu; | |
392 | ||
393 | cpu_clear(smp_processor_id(), mask); | |
ece8a9e4 | 394 | for_each_cpu_mask(cpu, mask) |
b5eb5511 RB |
395 | if (cpu_context(cpu, vma->vm_mm)) |
396 | cpu_context(cpu, vma->vm_mm) = 0; | |
1da177e4 LT |
397 | } |
398 | local_flush_tlb_page(vma, page); | |
399 | preempt_enable(); | |
400 | } | |
401 | ||
402 | static void flush_tlb_one_ipi(void *info) | |
403 | { | |
404 | unsigned long vaddr = (unsigned long) info; | |
405 | ||
406 | local_flush_tlb_one(vaddr); | |
407 | } | |
408 | ||
409 | void flush_tlb_one(unsigned long vaddr) | |
410 | { | |
25969354 | 411 | smp_on_each_tlb(flush_tlb_one_ipi, (void *) vaddr); |
1da177e4 LT |
412 | } |
413 | ||
414 | EXPORT_SYMBOL(flush_tlb_page); | |
415 | EXPORT_SYMBOL(flush_tlb_one); |