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1da177e4 LT |
1 | /* |
2 | * r2300_switch.S: R2300 specific task switching code. | |
3 | * | |
4 | * Copyright (C) 1994, 1995, 1996, 1999 by Ralf Baechle | |
5 | * Copyright (C) 1994, 1995, 1996 by Andreas Busse | |
6 | * | |
7 | * Multi-cpu abstraction and macros for easier reading: | |
79add627 | 8 | * Copyright (C) 1996 David S. Miller (davem@davemloft.net) |
1da177e4 LT |
9 | * |
10 | * Further modifications to make this work: | |
11 | * Copyright (c) 1998-2000 Harald Koerfgen | |
12 | */ | |
1da177e4 LT |
13 | #include <asm/asm.h> |
14 | #include <asm/cachectl.h> | |
29830c12 | 15 | #include <asm/export.h> |
1da177e4 LT |
16 | #include <asm/fpregdef.h> |
17 | #include <asm/mipsregs.h> | |
048eb582 | 18 | #include <asm/asm-offsets.h> |
1da177e4 LT |
19 | #include <asm/regdef.h> |
20 | #include <asm/stackframe.h> | |
21 | #include <asm/thread_info.h> | |
22 | ||
23 | #include <asm/asmmacro.h> | |
24 | ||
25 | .set mips1 | |
26 | .align 5 | |
27 | ||
1da177e4 LT |
28 | /* |
29 | * task_struct *resume(task_struct *prev, task_struct *next, | |
085c2f25 | 30 | * struct thread_info *next_ti) |
1da177e4 LT |
31 | */ |
32 | LEAF(resume) | |
5323180d AN |
33 | mfc0 t1, CP0_STATUS |
34 | sw t1, THREAD_STATUS(a0) | |
1da177e4 LT |
35 | cpu_save_nonscratch a0 |
36 | sw ra, THREAD_REG31(a0) | |
37 | ||
1400eb65 | 38 | #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) |
8b3c569a | 39 | PTR_LA t8, __stack_chk_guard |
1400eb65 GF |
40 | LONG_L t9, TASK_STACK_CANARY(a1) |
41 | LONG_S t9, 0(t8) | |
42 | #endif | |
43 | ||
1da177e4 LT |
44 | /* |
45 | * The order of restoring the registers takes care of the race | |
46 | * updating $28, $29 and kernelsp without disabling ints. | |
47 | */ | |
48 | move $28, a2 | |
49 | cpu_restore_nonscratch a1 | |
50 | ||
51 | addiu t1, $28, _THREAD_SIZE - 32 | |
52 | sw t1, kernelsp | |
53 | ||
54 | mfc0 t1, CP0_STATUS /* Do we really need this? */ | |
55 | li a3, 0xff01 | |
56 | and t1, a3 | |
57 | lw a2, THREAD_STATUS(a1) | |
58 | nor a3, $0, a3 | |
59 | and a2, a3 | |
60 | or a2, t1 | |
61 | mtc0 a2, CP0_STATUS | |
62 | move v0, a0 | |
63 | jr ra | |
64 | END(resume) |