[linux-2.6-block.git] / arch / mips / kernel / ptrace32.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1992 Ross Biro
 * Copyright (C) Linus Torvalds
 * Copyright (C) 1994, 95, 96, 97, 98, 2000 Ralf Baechle
 * Copyright (C) 1996 David S. Miller
 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
 * Copyright (C) 1999 MIPS Technologies, Inc.
 * Copyright (C) 2000 Ulf Carlsson
 *
 * At this time Linux/MIPS64 only supports syscall tracing, even for 32-bit
 * binaries.
 */
#include <linux/compiler.h>
#include <linux/compat.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/sched/task_stack.h>
#include <linux/mm.h>
#include <linux/errno.h>
#include <linux/ptrace.h>
#include <linux/smp.h>
#include <linux/security.h>

#include <asm/cpu.h>
#include <asm/dsp.h>
#include <asm/fpu.h>
#include <asm/mipsregs.h>
#include <asm/mipsmtregs.h>
#include <asm/page.h>
#include <asm/reg.h>
#include <asm/syscall.h>
#include <linux/uaccess.h>
#include <asm/bootinfo.h>

/*
 * Tracing a 32-bit process with a 64-bit strace and vice versa will not
 * work.  I don't know how to fix this.
 */
long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
			compat_ulong_t caddr, compat_ulong_t cdata)
{
	int addr = caddr;
	int data = cdata;
	int ret;

	switch (request) {

	/*
	 * Read 4 bytes of the other process' storage
	 *  data is a pointer specifying where the user wants the
	 *	4 bytes copied into
	 *  addr is a pointer in the user's storage that contains an 8 byte
	 *	address in the other process of the 4 bytes that is to be read
	 * (this is run in a 32-bit process looking at a 64-bit process)
	 * when I and D space are separate, these will need to be fixed.
	 */
	case PTRACE_PEEKTEXT_3264:
	case PTRACE_PEEKDATA_3264: {
		u32 tmp;
		int copied;
		u32 __user * addrOthers;

		ret = -EIO;

		/* Get the addr in the other process that we want to read */
		if (get_user(addrOthers, (u32 __user * __user *) (unsigned long) addr) != 0)
			break;

		copied = ptrace_access_vm(child, (u64)addrOthers, &tmp,
				sizeof(tmp), FOLL_FORCE);
		if (copied != sizeof(tmp))
			break;
		ret = put_user(tmp, (u32 __user *) (unsigned long) data);
		break;
	}

	/* Read the word at location addr in the USER area. */
	case PTRACE_PEEKUSR: {
		struct pt_regs *regs;
		unsigned int tmp;

		regs = task_pt_regs(child);
		ret = 0;  /* Default return value. */

		switch (addr) {
		case 0 ... 31:
			tmp = regs->regs[addr];
			break;
#ifdef CONFIG_MIPS_FP_SUPPORT
		case FPR_BASE ... FPR_BASE + 31: {
			union fpureg *fregs;

			if (!tsk_used_math(child)) {
				/* FP not yet used */
				tmp = -1;
				break;
			}
			fregs = get_fpu_regs(child);
			if (test_tsk_thread_flag(child, TIF_32BIT_FPREGS)) {
				/*
				 * The odd registers are actually the high
				 * order bits of the values stored in the even
				 * registers.
				 */
				tmp = get_fpr32(&fregs[(addr & ~1) - FPR_BASE],
						addr & 1);
				break;
			}
			tmp = get_fpr64(&fregs[addr - FPR_BASE], 0);
			break;
		}
		case FPC_CSR:
			tmp = child->thread.fpu.fcr31;
			break;
		case FPC_EIR:
			/* implementation / version register */
			tmp = boot_cpu_data.fpu_id;
			break;
#endif /* CONFIG_MIPS_FP_SUPPORT */
		case PC:
			tmp = regs->cp0_epc;
			break;
		case CAUSE:
			tmp = regs->cp0_cause;
			break;
		case BADVADDR:
			tmp = regs->cp0_badvaddr;
			break;
		case MMHI:
			tmp = regs->hi;
			break;
		case MMLO:
			tmp = regs->lo;
			break;
		case DSP_BASE ... DSP_BASE + 5: {
			dspreg_t *dregs;

			if (!cpu_has_dsp) {
				tmp = 0;
				ret = -EIO;
				goto out;
			}
			dregs = __get_dsp_regs(child);
			tmp = dregs[addr - DSP_BASE];
			break;
		}
		case DSP_CONTROL:
			if (!cpu_has_dsp) {
				tmp = 0;
				ret = -EIO;
				goto out;
			}
			tmp = child->thread.dsp.dspcontrol;
			break;
		default:
			tmp = 0;
			ret = -EIO;
			goto out;
		}
		ret = put_user(tmp, (unsigned __user *) (unsigned long) data);
		break;
	}

	/*
	 * Write 4 bytes into the other process' storage
	 *  data is the 4 bytes that the user wants written
	 *  addr is a pointer in the user's storage that contains an
	 *	8 byte address in the other process where the 4 bytes
	 *	that is to be written
	 * (this is run in a 32-bit process looking at a 64-bit process)
	 * when I and D space are separate, these will need to be fixed.
	 */
	case PTRACE_POKETEXT_3264:
	case PTRACE_POKEDATA_3264: {
		u32 __user * addrOthers;

		/* Get the addr in the other process that we want to write into */
		ret = -EIO;
		if (get_user(addrOthers, (u32 __user * __user *) (unsigned long) addr) != 0)
			break;
		ret = 0;
		if (ptrace_access_vm(child, (u64)addrOthers, &data,
					sizeof(data),
					FOLL_FORCE | FOLL_WRITE) == sizeof(data))
			break;
		ret = -EIO;
		break;
	}

	case PTRACE_POKEUSR: {
		struct pt_regs *regs;
		ret = 0;
		regs = task_pt_regs(child);

		switch (addr) {
		case 0 ... 31:
			regs->regs[addr] = data;
			/* System call number may have been changed */
			if (addr == 2)
				mips_syscall_update_nr(child, regs);
			else if (addr == 4 &&
				 mips_syscall_is_indirect(child, regs))
				mips_syscall_update_nr(child, regs);
			break;
#ifdef CONFIG_MIPS_FP_SUPPORT
		case FPR_BASE ... FPR_BASE + 31: {
			union fpureg *fregs = get_fpu_regs(child);

			if (!tsk_used_math(child)) {
				/* FP not yet used  */
				memset(&child->thread.fpu, ~0,
				       sizeof(child->thread.fpu));
				child->thread.fpu.fcr31 = 0;
			}
			if (test_tsk_thread_flag(child, TIF_32BIT_FPREGS)) {
				/*
				 * The odd registers are actually the high
				 * order bits of the values stored in the even
				 * registers.
				 */
				set_fpr32(&fregs[(addr & ~1) - FPR_BASE],
					  addr & 1, data);
				break;
			}
			set_fpr64(&fregs[addr - FPR_BASE], 0, data);
			break;
		}
		case FPC_CSR:
			child->thread.fpu.fcr31 = data;
			break;
#endif /* CONFIG_MIPS_FP_SUPPORT */
		case PC:
			regs->cp0_epc = data;
			break;
		case MMHI:
			regs->hi = data;
			break;
		case MMLO:
			regs->lo = data;
			break;
		case DSP_BASE ... DSP_BASE + 5: {
			dspreg_t *dregs;

			if (!cpu_has_dsp) {
				ret = -EIO;
				break;
			}

			dregs = __get_dsp_regs(child);
			dregs[addr - DSP_BASE] = data;
			break;
		}
		case DSP_CONTROL:
			if (!cpu_has_dsp) {
				ret = -EIO;
				break;
			}
			child->thread.dsp.dspcontrol = data;
			break;
		default:
			/* The rest are not allowed. */
			ret = -EIO;
			break;
		}
		break;
		}

	case PTRACE_GETREGS:
		ret = ptrace_getregs(child,
				(struct user_pt_regs __user *) (__u64) data);
		break;

	case PTRACE_SETREGS:
		ret = ptrace_setregs(child,
				(struct user_pt_regs __user *) (__u64) data);
		break;

#ifdef CONFIG_MIPS_FP_SUPPORT
	case PTRACE_GETFPREGS:
		ret = ptrace_getfpregs(child, (__u32 __user *) (__u64) data);
		break;

	case PTRACE_SETFPREGS:
		ret = ptrace_setfpregs(child, (__u32 __user *) (__u64) data);
		break;
#endif
	case PTRACE_GET_THREAD_AREA:
		ret = put_user(task_thread_info(child)->tp_value,
				(unsigned int __user *) (unsigned long) data);
		break;

	case PTRACE_GET_THREAD_AREA_3264:
		ret = put_user(task_thread_info(child)->tp_value,
				(unsigned long __user *) (unsigned long) data);
		break;

	case PTRACE_GET_WATCH_REGS:
		ret = ptrace_get_watch_regs(child,
			(struct pt_watch_regs __user *) (unsigned long) addr);
		break;

	case PTRACE_SET_WATCH_REGS:
		ret = ptrace_set_watch_regs(child,
			(struct pt_watch_regs __user *) (unsigned long) addr);
		break;

	default:
		ret = compat_ptrace_request(child, request, addr, data);
		break;
	}
out:
	return ret;
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 1992 Ross Biro
	7	* Copyright (C) Linus Torvalds
	8	* Copyright (C) 1994, 95, 96, 97, 98, 2000 Ralf Baechle
	9	* Copyright (C) 1996 David S. Miller
	10	* Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
	11	* Copyright (C) 1999 MIPS Technologies, Inc.
	12	* Copyright (C) 2000 Ulf Carlsson
	13	*
	14	* At this time Linux/MIPS64 only supports syscall tracing, even for 32-bit
	15	* binaries.
	16	*/
	17	#include <linux/compiler.h>
5d9a76cd	18	#include <linux/compat.h>
1da177e4 LT	19	#include <linux/kernel.h>
1da177e4 LT	20	#include <linux/sched.h>
68db0cf1	21	#include <linux/sched/task_stack.h>
1da177e4 LT	22	#include <linux/mm.h>
	23	#include <linux/errno.h>
	24	#include <linux/ptrace.h>
	25	#include <linux/smp.h>
1da177e4 LT	26	#include <linux/security.h>
	27
	28	#include <asm/cpu.h>
e50c0a8f	29	#include <asm/dsp.h>
1da177e4 LT	30	#include <asm/fpu.h>
1da177e4 LT	31	#include <asm/mipsregs.h>
101b3531	32	#include <asm/mipsmtregs.h>
1da177e4	33	#include <asm/page.h>
60be939c	34	#include <asm/reg.h>
de8cd0dc	35	#include <asm/syscall.h>
7c0f6ba6	36	#include <linux/uaccess.h>
1da177e4 LT	37	#include <asm/bootinfo.h>
	38
	39	/*
	40	* Tracing a 32-bit process with a 64-bit strace and vice versa will not
	41	* work. I don't know how to fix this.
	42	*/
5d9a76cd TB	43	long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
5d9a76cd TB	44	compat_ulong_t caddr, compat_ulong_t cdata)
1da177e4	45	{
5d9a76cd TB	46	int addr = caddr;
5d9a76cd TB	47	int data = cdata;
1da177e4 LT	48	int ret;
1da177e4 LT	49
1da177e4	50	switch (request) {
1da177e4	51
ea3d710f DJ	52	/*
	53	* Read 4 bytes of the other process' storage
	54	* data is a pointer specifying where the user wants the
	55	* 4 bytes copied into
	56	* addr is a pointer in the user's storage that contains an 8 byte
	57	* address in the other process of the 4 bytes that is to be read
	58	* (this is run in a 32-bit process looking at a 64-bit process)
	59	* when I and D space are separate, these will need to be fixed.
	60	*/
	61	case PTRACE_PEEKTEXT_3264:
	62	case PTRACE_PEEKDATA_3264: {
	63	u32 tmp;
	64	int copied;
	65	u32 __user * addrOthers;
	66
	67	ret = -EIO;
	68
	69	/* Get the addr in the other process that we want to read */
	70	if (get_user(addrOthers, (u32 __user * __user *) (unsigned long) addr) != 0)
	71	break;
	72
84d77d3f	73	copied = ptrace_access_vm(child, (u64)addrOthers, &tmp,
f307ab6d	74	sizeof(tmp), FOLL_FORCE);
ea3d710f DJ	75	if (copied != sizeof(tmp))
	76	break;
	77	ret = put_user(tmp, (u32 __user *) (unsigned long) data);
	78	break;
	79	}
	80
1da177e4 LT	81	/* Read the word at location addr in the USER area. */
	82	case PTRACE_PEEKUSR: {
	83	struct pt_regs *regs;
	84	unsigned int tmp;
	85
40bc9c67	86	regs = task_pt_regs(child);
1da177e4 LT	87	ret = 0; /* Default return value. */
	88
	89	switch (addr) {
	90	case 0 ... 31:
	91	tmp = regs->regs[addr];
	92	break;
6c79759e PB	93	#ifdef CONFIG_MIPS_FP_SUPPORT
	94	case FPR_BASE ... FPR_BASE + 31: {
	95	union fpureg *fregs;
	96
597ce172 PB	97	if (!tsk_used_math(child)) {
	98	/* FP not yet used */
	99	tmp = -1;
	100	break;
	101	}
	102	fregs = get_fpu_regs(child);
9a3a92cc	103	if (test_tsk_thread_flag(child, TIF_32BIT_FPREGS)) {
1da177e4 LT	104	/*
	105	* The odd registers are actually the high
	106	* order bits of the values stored in the even
d1157b10	107	* registers.
1da177e4	108	*/
bbd426f5 PB	109	tmp = get_fpr32(&fregs[(addr & ~1) - FPR_BASE],
bbd426f5 PB	110	addr & 1);
597ce172	111	break;
1da177e4	112	}
c7e81462	113	tmp = get_fpr64(&fregs[addr - FPR_BASE], 0);
1da177e4	114	break;
6c79759e PB	115	}
	116	case FPC_CSR:
	117	tmp = child->thread.fpu.fcr31;
	118	break;
	119	case FPC_EIR:
	120	/* implementation / version register */
	121	tmp = boot_cpu_data.fpu_id;
	122	break;
	123	#endif /* CONFIG_MIPS_FP_SUPPORT */
1da177e4 LT	124	case PC:
	125	tmp = regs->cp0_epc;
	126	break;
	127	case CAUSE:
	128	tmp = regs->cp0_cause;
	129	break;
	130	case BADVADDR:
	131	tmp = regs->cp0_badvaddr;
	132	break;
	133	case MMHI:
	134	tmp = regs->hi;
	135	break;
	136	case MMLO:
	137	tmp = regs->lo;
	138	break;
3055acb0 AN	139	case DSP_BASE ... DSP_BASE + 5: {
	140	dspreg_t *dregs;
	141
e50c0a8f RB	142	if (!cpu_has_dsp) {
	143	tmp = 0;
	144	ret = -EIO;
5d9a76cd	145	goto out;
e50c0a8f	146	}
3055acb0	147	dregs = __get_dsp_regs(child);
f5958b4c	148	tmp = dregs[addr - DSP_BASE];
e50c0a8f	149	break;
3055acb0	150	}
e50c0a8f RB	151	case DSP_CONTROL:
	152	if (!cpu_has_dsp) {
	153	tmp = 0;
	154	ret = -EIO;
5d9a76cd	155	goto out;
e50c0a8f RB	156	}
	157	tmp = child->thread.dsp.dspcontrol;
	158	break;
1da177e4 LT	159	default:
	160	tmp = 0;
	161	ret = -EIO;
5d9a76cd	162	goto out;
1da177e4	163	}
3055acb0	164	ret = put_user(tmp, (unsigned __user *) (unsigned long) data);
1da177e4 LT	165	break;
	166	}
	167
ea3d710f DJ	168	/*
	169	* Write 4 bytes into the other process' storage
	170	* data is the 4 bytes that the user wants written
	171	* addr is a pointer in the user's storage that contains an
	172	* 8 byte address in the other process where the 4 bytes
	173	* that is to be written
	174	* (this is run in a 32-bit process looking at a 64-bit process)
	175	* when I and D space are separate, these will need to be fixed.
	176	*/
	177	case PTRACE_POKETEXT_3264:
	178	case PTRACE_POKEDATA_3264: {
	179	u32 __user * addrOthers;
	180
	181	/* Get the addr in the other process that we want to write into */
	182	ret = -EIO;
	183	if (get_user(addrOthers, (u32 __user * __user *) (unsigned long) addr) != 0)
	184	break;
	185	ret = 0;
84d77d3f	186	if (ptrace_access_vm(child, (u64)addrOthers, &data,
f307ab6d LS	187	sizeof(data),
f307ab6d LS	188	FOLL_FORCE \| FOLL_WRITE) == sizeof(data))
ea3d710f DJ	189	break;
	190	ret = -EIO;
	191	break;
	192	}
	193
1da177e4 LT	194	case PTRACE_POKEUSR: {
	195	struct pt_regs *regs;
	196	ret = 0;
40bc9c67	197	regs = task_pt_regs(child);
1da177e4 LT	198
	199	switch (addr) {
	200	case 0 ... 31:
	201	regs->regs[addr] = data;
de8cd0dc JH	202	/* System call number may have been changed */
	203	if (addr == 2)
	204	mips_syscall_update_nr(child, regs);
	205	else if (addr == 4 &&
	206	mips_syscall_is_indirect(child, regs))
	207	mips_syscall_update_nr(child, regs);
1da177e4	208	break;
6c79759e	209	#ifdef CONFIG_MIPS_FP_SUPPORT
1da177e4	210	case FPR_BASE ... FPR_BASE + 31: {
bbd426f5	211	union fpureg *fregs = get_fpu_regs(child);
1da177e4 LT	212
	213	if (!tsk_used_math(child)) {
	214	/* FP not yet used */
eae89076 AN	215	memset(&child->thread.fpu, ~0,
	216	sizeof(child->thread.fpu));
	217	child->thread.fpu.fcr31 = 0;
1da177e4	218	}
9a3a92cc	219	if (test_tsk_thread_flag(child, TIF_32BIT_FPREGS)) {
597ce172 PB	220	/*
	221	* The odd registers are actually the high
	222	* order bits of the values stored in the even
d1157b10	223	* registers.
597ce172	224	*/
bbd426f5 PB	225	set_fpr32(&fregs[(addr & ~1) - FPR_BASE],
bbd426f5 PB	226	addr & 1, data);
597ce172	227	break;
1da177e4	228	}
bbd426f5	229	set_fpr64(&fregs[addr - FPR_BASE], 0, data);
1da177e4 LT	230	break;
1da177e4 LT	231	}
6c79759e PB	232	case FPC_CSR:
	233	child->thread.fpu.fcr31 = data;
	234	break;
	235	#endif /* CONFIG_MIPS_FP_SUPPORT */
1da177e4 LT	236	case PC:
	237	regs->cp0_epc = data;
	238	break;
	239	case MMHI:
	240	regs->hi = data;
	241	break;
	242	case MMLO:
	243	regs->lo = data;
	244	break;
3055acb0 AN	245	case DSP_BASE ... DSP_BASE + 5: {
	246	dspreg_t *dregs;
	247
e50c0a8f RB	248	if (!cpu_has_dsp) {
	249	ret = -EIO;
	250	break;
	251	}
	252
3055acb0	253	dregs = __get_dsp_regs(child);
e50c0a8f RB	254	dregs[addr - DSP_BASE] = data;
e50c0a8f RB	255	break;
3055acb0	256	}
e50c0a8f RB	257	case DSP_CONTROL:
	258	if (!cpu_has_dsp) {
	259	ret = -EIO;
	260	break;
	261	}
	262	child->thread.dsp.dspcontrol = data;
	263	break;
1da177e4 LT	264	default:
	265	/* The rest are not allowed. */
	266	ret = -EIO;
	267	break;
	268	}
	269	break;
	270	}
	271
ea3d710f	272	case PTRACE_GETREGS:
a79ebea6 AS	273	ret = ptrace_getregs(child,
a79ebea6 AS	274	(struct user_pt_regs __user *) (__u64) data);
ea3d710f DJ	275	break;
	276
	277	case PTRACE_SETREGS:
a79ebea6 AS	278	ret = ptrace_setregs(child,
a79ebea6 AS	279	(struct user_pt_regs __user *) (__u64) data);
ea3d710f DJ	280	break;
ea3d710f DJ	281
6c79759e	282	#ifdef CONFIG_MIPS_FP_SUPPORT
ea3d710f	283	case PTRACE_GETFPREGS:
49a89efb	284	ret = ptrace_getfpregs(child, (__u32 __user *) (__u64) data);
ea3d710f DJ	285	break;
	286
	287	case PTRACE_SETFPREGS:
49a89efb	288	ret = ptrace_setfpregs(child, (__u32 __user *) (__u64) data);
ea3d710f	289	break;
6c79759e	290	#endif
3c37026d	291	case PTRACE_GET_THREAD_AREA:
dc8f6029	292	ret = put_user(task_thread_info(child)->tp_value,
3c37026d RB	293	(unsigned int __user *) (unsigned long) data);
	294	break;
	295
ea3d710f	296	case PTRACE_GET_THREAD_AREA_3264:
dc8f6029	297	ret = put_user(task_thread_info(child)->tp_value,
ea3d710f DJ	298	(unsigned long __user *) (unsigned long) data);
	299	break;
	300
0926bf95 DD	301	case PTRACE_GET_WATCH_REGS:
	302	ret = ptrace_get_watch_regs(child,
	303	(struct pt_watch_regs __user *) (unsigned long) addr);
	304	break;
	305
	306	case PTRACE_SET_WATCH_REGS:
	307	ret = ptrace_set_watch_regs(child,
	308	(struct pt_watch_regs __user *) (unsigned long) addr);
	309	break;
	310
1da177e4	311	default:
797c3f32	312	ret = compat_ptrace_request(child, request, addr, data);
1da177e4 LT	313	break;
1da177e4 LT	314	}
1da177e4	315	out:
1da177e4 LT	316	return ret;
1da177e4 LT	317	}