Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 1992 Ross Biro | |
7 | * Copyright (C) Linus Torvalds | |
8 | * Copyright (C) 1994, 95, 96, 97, 98, 2000 Ralf Baechle | |
9 | * Copyright (C) 1996 David S. Miller | |
10 | * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com | |
11 | * Copyright (C) 1999 MIPS Technologies, Inc. | |
12 | * Copyright (C) 2000 Ulf Carlsson | |
13 | * | |
14 | * At this time Linux/MIPS64 only supports syscall tracing, even for 32-bit | |
15 | * binaries. | |
16 | */ | |
1da177e4 | 17 | #include <linux/compiler.h> |
c3fc5cd5 | 18 | #include <linux/context_tracking.h> |
7aeb753b | 19 | #include <linux/elf.h> |
1da177e4 LT |
20 | #include <linux/kernel.h> |
21 | #include <linux/sched.h> | |
68db0cf1 | 22 | #include <linux/sched/task_stack.h> |
1da177e4 LT |
23 | #include <linux/mm.h> |
24 | #include <linux/errno.h> | |
25 | #include <linux/ptrace.h> | |
7aeb753b | 26 | #include <linux/regset.h> |
1da177e4 | 27 | #include <linux/smp.h> |
1da177e4 | 28 | #include <linux/security.h> |
40e084a5 | 29 | #include <linux/stddef.h> |
bc3d22c1 | 30 | #include <linux/tracehook.h> |
293c5bd1 RB |
31 | #include <linux/audit.h> |
32 | #include <linux/seccomp.h> | |
1d7bf993 | 33 | #include <linux/ftrace.h> |
1da177e4 | 34 | |
f8280c8d | 35 | #include <asm/byteorder.h> |
1da177e4 | 36 | #include <asm/cpu.h> |
9b26616c | 37 | #include <asm/cpu-info.h> |
e50c0a8f | 38 | #include <asm/dsp.h> |
1da177e4 LT |
39 | #include <asm/fpu.h> |
40 | #include <asm/mipsregs.h> | |
101b3531 | 41 | #include <asm/mipsmtregs.h> |
1da177e4 LT |
42 | #include <asm/pgtable.h> |
43 | #include <asm/page.h> | |
bec9b2b2 | 44 | #include <asm/syscall.h> |
7c0f6ba6 | 45 | #include <linux/uaccess.h> |
1da177e4 | 46 | #include <asm/bootinfo.h> |
ea3d710f | 47 | #include <asm/reg.h> |
1da177e4 | 48 | |
1d7bf993 RB |
49 | #define CREATE_TRACE_POINTS |
50 | #include <trace/events/syscalls.h> | |
51 | ||
ac9ad83b PB |
52 | static void init_fp_ctx(struct task_struct *target) |
53 | { | |
54 | /* If FP has been used then the target already has context */ | |
55 | if (tsk_used_math(target)) | |
56 | return; | |
57 | ||
58 | /* Begin with data registers set to all 1s... */ | |
59 | memset(&target->thread.fpu.fpr, ~0, sizeof(target->thread.fpu.fpr)); | |
60 | ||
abf378be | 61 | /* FCSR has been preset by `mips_set_personality_nan'. */ |
ac9ad83b PB |
62 | |
63 | /* | |
64 | * Record that the target has "used" math, such that the context | |
65 | * just initialised, and any modifications made by the caller, | |
66 | * aren't discarded. | |
67 | */ | |
68 | set_stopped_child_used_math(target); | |
69 | } | |
70 | ||
1da177e4 LT |
71 | /* |
72 | * Called by kernel/ptrace.c when detaching.. | |
73 | * | |
74 | * Make sure single step bits etc are not set. | |
75 | */ | |
76 | void ptrace_disable(struct task_struct *child) | |
77 | { | |
0926bf95 DD |
78 | /* Don't load the watchpoint registers for the ex-child. */ |
79 | clear_tsk_thread_flag(child, TIF_LOAD_WATCH); | |
1da177e4 LT |
80 | } |
81 | ||
abf378be | 82 | /* |
5a1aca44 MR |
83 | * Poke at FCSR according to its mask. Set the Cause bits even |
84 | * if a corresponding Enable bit is set. This will be noticed at | |
85 | * the time the thread is switched to and SIGFPE thrown accordingly. | |
abf378be MR |
86 | */ |
87 | static void ptrace_setfcr31(struct task_struct *child, u32 value) | |
88 | { | |
89 | u32 fcr31; | |
90 | u32 mask; | |
91 | ||
abf378be MR |
92 | fcr31 = child->thread.fpu.fcr31; |
93 | mask = boot_cpu_data.fpu_msk31; | |
94 | child->thread.fpu.fcr31 = (value & ~mask) | (fcr31 & mask); | |
95 | } | |
96 | ||
ea3d710f | 97 | /* |
70342287 | 98 | * Read a general register set. We always use the 64-bit format, even |
ea3d710f DJ |
99 | * for 32-bit kernels and for 32-bit processes on a 64-bit kernel. |
100 | * Registers are sign extended to fill the available space. | |
101 | */ | |
a79ebea6 | 102 | int ptrace_getregs(struct task_struct *child, struct user_pt_regs __user *data) |
ea3d710f DJ |
103 | { |
104 | struct pt_regs *regs; | |
105 | int i; | |
106 | ||
107 | if (!access_ok(VERIFY_WRITE, data, 38 * 8)) | |
108 | return -EIO; | |
109 | ||
40bc9c67 | 110 | regs = task_pt_regs(child); |
ea3d710f DJ |
111 | |
112 | for (i = 0; i < 32; i++) | |
a79ebea6 AS |
113 | __put_user((long)regs->regs[i], (__s64 __user *)&data->regs[i]); |
114 | __put_user((long)regs->lo, (__s64 __user *)&data->lo); | |
115 | __put_user((long)regs->hi, (__s64 __user *)&data->hi); | |
116 | __put_user((long)regs->cp0_epc, (__s64 __user *)&data->cp0_epc); | |
117 | __put_user((long)regs->cp0_badvaddr, (__s64 __user *)&data->cp0_badvaddr); | |
118 | __put_user((long)regs->cp0_status, (__s64 __user *)&data->cp0_status); | |
119 | __put_user((long)regs->cp0_cause, (__s64 __user *)&data->cp0_cause); | |
ea3d710f DJ |
120 | |
121 | return 0; | |
122 | } | |
123 | ||
124 | /* | |
125 | * Write a general register set. As for PTRACE_GETREGS, we always use | |
126 | * the 64-bit format. On a 32-bit kernel only the lower order half | |
127 | * (according to endianness) will be used. | |
128 | */ | |
a79ebea6 | 129 | int ptrace_setregs(struct task_struct *child, struct user_pt_regs __user *data) |
ea3d710f DJ |
130 | { |
131 | struct pt_regs *regs; | |
132 | int i; | |
133 | ||
134 | if (!access_ok(VERIFY_READ, data, 38 * 8)) | |
135 | return -EIO; | |
136 | ||
40bc9c67 | 137 | regs = task_pt_regs(child); |
ea3d710f DJ |
138 | |
139 | for (i = 0; i < 32; i++) | |
a79ebea6 AS |
140 | __get_user(regs->regs[i], (__s64 __user *)&data->regs[i]); |
141 | __get_user(regs->lo, (__s64 __user *)&data->lo); | |
142 | __get_user(regs->hi, (__s64 __user *)&data->hi); | |
143 | __get_user(regs->cp0_epc, (__s64 __user *)&data->cp0_epc); | |
ea3d710f DJ |
144 | |
145 | /* badvaddr, status, and cause may not be written. */ | |
146 | ||
147 | return 0; | |
148 | } | |
149 | ||
49a89efb | 150 | int ptrace_getfpregs(struct task_struct *child, __u32 __user *data) |
ea3d710f DJ |
151 | { |
152 | int i; | |
153 | ||
154 | if (!access_ok(VERIFY_WRITE, data, 33 * 8)) | |
155 | return -EIO; | |
156 | ||
157 | if (tsk_used_math(child)) { | |
bbd426f5 | 158 | union fpureg *fregs = get_fpu_regs(child); |
ea3d710f | 159 | for (i = 0; i < 32; i++) |
bbd426f5 PB |
160 | __put_user(get_fpr64(&fregs[i], 0), |
161 | i + (__u64 __user *)data); | |
ea3d710f DJ |
162 | } else { |
163 | for (i = 0; i < 32; i++) | |
49a89efb | 164 | __put_user((__u64) -1, i + (__u64 __user *) data); |
ea3d710f DJ |
165 | } |
166 | ||
49a89efb | 167 | __put_user(child->thread.fpu.fcr31, data + 64); |
656ff9be | 168 | __put_user(boot_cpu_data.fpu_id, data + 65); |
ea3d710f DJ |
169 | |
170 | return 0; | |
171 | } | |
172 | ||
49a89efb | 173 | int ptrace_setfpregs(struct task_struct *child, __u32 __user *data) |
ea3d710f | 174 | { |
bbd426f5 PB |
175 | union fpureg *fregs; |
176 | u64 fpr_val; | |
9b26616c | 177 | u32 value; |
ea3d710f DJ |
178 | int i; |
179 | ||
180 | if (!access_ok(VERIFY_READ, data, 33 * 8)) | |
181 | return -EIO; | |
182 | ||
ac9ad83b | 183 | init_fp_ctx(child); |
ea3d710f DJ |
184 | fregs = get_fpu_regs(child); |
185 | ||
bbd426f5 PB |
186 | for (i = 0; i < 32; i++) { |
187 | __get_user(fpr_val, i + (__u64 __user *)data); | |
188 | set_fpr64(&fregs[i], 0, fpr_val); | |
189 | } | |
ea3d710f | 190 | |
9b26616c | 191 | __get_user(value, data + 64); |
abf378be | 192 | ptrace_setfcr31(child, value); |
ea3d710f DJ |
193 | |
194 | /* FIR may not be written. */ | |
195 | ||
196 | return 0; | |
197 | } | |
198 | ||
0926bf95 DD |
199 | int ptrace_get_watch_regs(struct task_struct *child, |
200 | struct pt_watch_regs __user *addr) | |
201 | { | |
202 | enum pt_watch_style style; | |
203 | int i; | |
204 | ||
57c7ea51 | 205 | if (!cpu_has_watch || boot_cpu_data.watch_reg_use_cnt == 0) |
0926bf95 DD |
206 | return -EIO; |
207 | if (!access_ok(VERIFY_WRITE, addr, sizeof(struct pt_watch_regs))) | |
208 | return -EIO; | |
209 | ||
210 | #ifdef CONFIG_32BIT | |
211 | style = pt_watch_style_mips32; | |
212 | #define WATCH_STYLE mips32 | |
213 | #else | |
214 | style = pt_watch_style_mips64; | |
215 | #define WATCH_STYLE mips64 | |
216 | #endif | |
217 | ||
218 | __put_user(style, &addr->style); | |
57c7ea51 | 219 | __put_user(boot_cpu_data.watch_reg_use_cnt, |
0926bf95 | 220 | &addr->WATCH_STYLE.num_valid); |
57c7ea51 | 221 | for (i = 0; i < boot_cpu_data.watch_reg_use_cnt; i++) { |
0926bf95 DD |
222 | __put_user(child->thread.watch.mips3264.watchlo[i], |
223 | &addr->WATCH_STYLE.watchlo[i]); | |
50af501c JH |
224 | __put_user(child->thread.watch.mips3264.watchhi[i] & |
225 | (MIPS_WATCHHI_MASK | MIPS_WATCHHI_IRW), | |
0926bf95 | 226 | &addr->WATCH_STYLE.watchhi[i]); |
57c7ea51 | 227 | __put_user(boot_cpu_data.watch_reg_masks[i], |
0926bf95 DD |
228 | &addr->WATCH_STYLE.watch_masks[i]); |
229 | } | |
230 | for (; i < 8; i++) { | |
231 | __put_user(0, &addr->WATCH_STYLE.watchlo[i]); | |
232 | __put_user(0, &addr->WATCH_STYLE.watchhi[i]); | |
233 | __put_user(0, &addr->WATCH_STYLE.watch_masks[i]); | |
234 | } | |
235 | ||
236 | return 0; | |
237 | } | |
238 | ||
239 | int ptrace_set_watch_regs(struct task_struct *child, | |
240 | struct pt_watch_regs __user *addr) | |
241 | { | |
242 | int i; | |
243 | int watch_active = 0; | |
244 | unsigned long lt[NUM_WATCH_REGS]; | |
245 | u16 ht[NUM_WATCH_REGS]; | |
246 | ||
57c7ea51 | 247 | if (!cpu_has_watch || boot_cpu_data.watch_reg_use_cnt == 0) |
0926bf95 DD |
248 | return -EIO; |
249 | if (!access_ok(VERIFY_READ, addr, sizeof(struct pt_watch_regs))) | |
250 | return -EIO; | |
251 | /* Check the values. */ | |
57c7ea51 | 252 | for (i = 0; i < boot_cpu_data.watch_reg_use_cnt; i++) { |
0926bf95 DD |
253 | __get_user(lt[i], &addr->WATCH_STYLE.watchlo[i]); |
254 | #ifdef CONFIG_32BIT | |
255 | if (lt[i] & __UA_LIMIT) | |
256 | return -EINVAL; | |
257 | #else | |
258 | if (test_tsk_thread_flag(child, TIF_32BIT_ADDR)) { | |
259 | if (lt[i] & 0xffffffff80000000UL) | |
260 | return -EINVAL; | |
261 | } else { | |
262 | if (lt[i] & __UA_LIMIT) | |
263 | return -EINVAL; | |
264 | } | |
265 | #endif | |
266 | __get_user(ht[i], &addr->WATCH_STYLE.watchhi[i]); | |
50af501c | 267 | if (ht[i] & ~MIPS_WATCHHI_MASK) |
0926bf95 DD |
268 | return -EINVAL; |
269 | } | |
270 | /* Install them. */ | |
57c7ea51 | 271 | for (i = 0; i < boot_cpu_data.watch_reg_use_cnt; i++) { |
50af501c | 272 | if (lt[i] & MIPS_WATCHLO_IRW) |
0926bf95 DD |
273 | watch_active = 1; |
274 | child->thread.watch.mips3264.watchlo[i] = lt[i]; | |
275 | /* Set the G bit. */ | |
276 | child->thread.watch.mips3264.watchhi[i] = ht[i]; | |
277 | } | |
278 | ||
279 | if (watch_active) | |
280 | set_tsk_thread_flag(child, TIF_LOAD_WATCH); | |
281 | else | |
282 | clear_tsk_thread_flag(child, TIF_LOAD_WATCH); | |
283 | ||
284 | return 0; | |
285 | } | |
286 | ||
7aeb753b RB |
287 | /* regset get/set implementations */ |
288 | ||
c23b3d1a AS |
289 | #if defined(CONFIG_32BIT) || defined(CONFIG_MIPS32_O32) |
290 | ||
291 | static int gpr32_get(struct task_struct *target, | |
292 | const struct user_regset *regset, | |
293 | unsigned int pos, unsigned int count, | |
294 | void *kbuf, void __user *ubuf) | |
7aeb753b RB |
295 | { |
296 | struct pt_regs *regs = task_pt_regs(target); | |
c23b3d1a | 297 | u32 uregs[ELF_NGREG] = {}; |
7aeb753b | 298 | |
08c941bf | 299 | mips_dump_regs32(uregs, regs); |
c23b3d1a AS |
300 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, uregs, 0, |
301 | sizeof(uregs)); | |
7aeb753b RB |
302 | } |
303 | ||
c23b3d1a AS |
304 | static int gpr32_set(struct task_struct *target, |
305 | const struct user_regset *regset, | |
306 | unsigned int pos, unsigned int count, | |
307 | const void *kbuf, const void __user *ubuf) | |
7aeb753b | 308 | { |
c23b3d1a AS |
309 | struct pt_regs *regs = task_pt_regs(target); |
310 | u32 uregs[ELF_NGREG]; | |
311 | unsigned start, num_regs, i; | |
312 | int err; | |
313 | ||
314 | start = pos / sizeof(u32); | |
315 | num_regs = count / sizeof(u32); | |
316 | ||
317 | if (start + num_regs > ELF_NGREG) | |
318 | return -EIO; | |
319 | ||
320 | err = user_regset_copyin(&pos, &count, &kbuf, &ubuf, uregs, 0, | |
321 | sizeof(uregs)); | |
322 | if (err) | |
323 | return err; | |
324 | ||
325 | for (i = start; i < num_regs; i++) { | |
326 | /* | |
327 | * Cast all values to signed here so that if this is a 64-bit | |
328 | * kernel, the supplied 32-bit values will be sign extended. | |
329 | */ | |
330 | switch (i) { | |
331 | case MIPS32_EF_R1 ... MIPS32_EF_R25: | |
332 | /* k0/k1 are ignored. */ | |
333 | case MIPS32_EF_R28 ... MIPS32_EF_R31: | |
334 | regs->regs[i - MIPS32_EF_R0] = (s32)uregs[i]; | |
335 | break; | |
336 | case MIPS32_EF_LO: | |
337 | regs->lo = (s32)uregs[i]; | |
338 | break; | |
339 | case MIPS32_EF_HI: | |
340 | regs->hi = (s32)uregs[i]; | |
341 | break; | |
342 | case MIPS32_EF_CP0_EPC: | |
343 | regs->cp0_epc = (s32)uregs[i]; | |
344 | break; | |
345 | } | |
346 | } | |
347 | ||
348 | return 0; | |
349 | } | |
350 | ||
351 | #endif /* CONFIG_32BIT || CONFIG_MIPS32_O32 */ | |
352 | ||
353 | #ifdef CONFIG_64BIT | |
354 | ||
355 | static int gpr64_get(struct task_struct *target, | |
356 | const struct user_regset *regset, | |
357 | unsigned int pos, unsigned int count, | |
358 | void *kbuf, void __user *ubuf) | |
359 | { | |
360 | struct pt_regs *regs = task_pt_regs(target); | |
361 | u64 uregs[ELF_NGREG] = {}; | |
c23b3d1a | 362 | |
08c941bf | 363 | mips_dump_regs64(uregs, regs); |
c23b3d1a AS |
364 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, uregs, 0, |
365 | sizeof(uregs)); | |
366 | } | |
7aeb753b | 367 | |
c23b3d1a AS |
368 | static int gpr64_set(struct task_struct *target, |
369 | const struct user_regset *regset, | |
370 | unsigned int pos, unsigned int count, | |
371 | const void *kbuf, const void __user *ubuf) | |
372 | { | |
373 | struct pt_regs *regs = task_pt_regs(target); | |
374 | u64 uregs[ELF_NGREG]; | |
375 | unsigned start, num_regs, i; | |
376 | int err; | |
377 | ||
378 | start = pos / sizeof(u64); | |
379 | num_regs = count / sizeof(u64); | |
380 | ||
381 | if (start + num_regs > ELF_NGREG) | |
382 | return -EIO; | |
7aeb753b | 383 | |
c23b3d1a AS |
384 | err = user_regset_copyin(&pos, &count, &kbuf, &ubuf, uregs, 0, |
385 | sizeof(uregs)); | |
386 | if (err) | |
387 | return err; | |
388 | ||
389 | for (i = start; i < num_regs; i++) { | |
390 | switch (i) { | |
391 | case MIPS64_EF_R1 ... MIPS64_EF_R25: | |
392 | /* k0/k1 are ignored. */ | |
393 | case MIPS64_EF_R28 ... MIPS64_EF_R31: | |
394 | regs->regs[i - MIPS64_EF_R0] = uregs[i]; | |
395 | break; | |
396 | case MIPS64_EF_LO: | |
397 | regs->lo = uregs[i]; | |
398 | break; | |
399 | case MIPS64_EF_HI: | |
400 | regs->hi = uregs[i]; | |
401 | break; | |
402 | case MIPS64_EF_CP0_EPC: | |
403 | regs->cp0_epc = uregs[i]; | |
404 | break; | |
405 | } | |
406 | } | |
7aeb753b RB |
407 | |
408 | return 0; | |
409 | } | |
410 | ||
c23b3d1a AS |
411 | #endif /* CONFIG_64BIT */ |
412 | ||
7aeb753b RB |
413 | static int fpr_get(struct task_struct *target, |
414 | const struct user_regset *regset, | |
415 | unsigned int pos, unsigned int count, | |
416 | void *kbuf, void __user *ubuf) | |
417 | { | |
72b22bba PB |
418 | unsigned i; |
419 | int err; | |
420 | u64 fpr_val; | |
421 | ||
7aeb753b | 422 | /* XXX fcr31 */ |
72b22bba PB |
423 | |
424 | if (sizeof(target->thread.fpu.fpr[i]) == sizeof(elf_fpreg_t)) | |
425 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
426 | &target->thread.fpu, | |
427 | 0, sizeof(elf_fpregset_t)); | |
428 | ||
429 | for (i = 0; i < NUM_FPU_REGS; i++) { | |
430 | fpr_val = get_fpr64(&target->thread.fpu.fpr[i], 0); | |
431 | err = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
432 | &fpr_val, i * sizeof(elf_fpreg_t), | |
433 | (i + 1) * sizeof(elf_fpreg_t)); | |
434 | if (err) | |
435 | return err; | |
436 | } | |
437 | ||
438 | return 0; | |
7aeb753b RB |
439 | } |
440 | ||
441 | static int fpr_set(struct task_struct *target, | |
442 | const struct user_regset *regset, | |
443 | unsigned int pos, unsigned int count, | |
444 | const void *kbuf, const void __user *ubuf) | |
445 | { | |
72b22bba PB |
446 | unsigned i; |
447 | int err; | |
448 | u64 fpr_val; | |
449 | ||
7aeb753b | 450 | /* XXX fcr31 */ |
72b22bba | 451 | |
ac9ad83b PB |
452 | init_fp_ctx(target); |
453 | ||
72b22bba PB |
454 | if (sizeof(target->thread.fpu.fpr[i]) == sizeof(elf_fpreg_t)) |
455 | return user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
456 | &target->thread.fpu, | |
457 | 0, sizeof(elf_fpregset_t)); | |
458 | ||
d614fd58 DM |
459 | BUILD_BUG_ON(sizeof(fpr_val) != sizeof(elf_fpreg_t)); |
460 | for (i = 0; i < NUM_FPU_REGS && count >= sizeof(elf_fpreg_t); i++) { | |
72b22bba PB |
461 | err = user_regset_copyin(&pos, &count, &kbuf, &ubuf, |
462 | &fpr_val, i * sizeof(elf_fpreg_t), | |
463 | (i + 1) * sizeof(elf_fpreg_t)); | |
464 | if (err) | |
465 | return err; | |
466 | set_fpr64(&target->thread.fpu.fpr[i], 0, fpr_val); | |
467 | } | |
468 | ||
469 | return 0; | |
7aeb753b RB |
470 | } |
471 | ||
472 | enum mips_regset { | |
473 | REGSET_GPR, | |
474 | REGSET_FPR, | |
475 | }; | |
476 | ||
40e084a5 RB |
477 | struct pt_regs_offset { |
478 | const char *name; | |
479 | int offset; | |
480 | }; | |
481 | ||
482 | #define REG_OFFSET_NAME(reg, r) { \ | |
483 | .name = #reg, \ | |
484 | .offset = offsetof(struct pt_regs, r) \ | |
485 | } | |
486 | ||
487 | #define REG_OFFSET_END { \ | |
488 | .name = NULL, \ | |
489 | .offset = 0 \ | |
490 | } | |
491 | ||
492 | static const struct pt_regs_offset regoffset_table[] = { | |
493 | REG_OFFSET_NAME(r0, regs[0]), | |
494 | REG_OFFSET_NAME(r1, regs[1]), | |
495 | REG_OFFSET_NAME(r2, regs[2]), | |
496 | REG_OFFSET_NAME(r3, regs[3]), | |
497 | REG_OFFSET_NAME(r4, regs[4]), | |
498 | REG_OFFSET_NAME(r5, regs[5]), | |
499 | REG_OFFSET_NAME(r6, regs[6]), | |
500 | REG_OFFSET_NAME(r7, regs[7]), | |
501 | REG_OFFSET_NAME(r8, regs[8]), | |
502 | REG_OFFSET_NAME(r9, regs[9]), | |
503 | REG_OFFSET_NAME(r10, regs[10]), | |
504 | REG_OFFSET_NAME(r11, regs[11]), | |
505 | REG_OFFSET_NAME(r12, regs[12]), | |
506 | REG_OFFSET_NAME(r13, regs[13]), | |
507 | REG_OFFSET_NAME(r14, regs[14]), | |
508 | REG_OFFSET_NAME(r15, regs[15]), | |
509 | REG_OFFSET_NAME(r16, regs[16]), | |
510 | REG_OFFSET_NAME(r17, regs[17]), | |
511 | REG_OFFSET_NAME(r18, regs[18]), | |
512 | REG_OFFSET_NAME(r19, regs[19]), | |
513 | REG_OFFSET_NAME(r20, regs[20]), | |
514 | REG_OFFSET_NAME(r21, regs[21]), | |
515 | REG_OFFSET_NAME(r22, regs[22]), | |
516 | REG_OFFSET_NAME(r23, regs[23]), | |
517 | REG_OFFSET_NAME(r24, regs[24]), | |
518 | REG_OFFSET_NAME(r25, regs[25]), | |
519 | REG_OFFSET_NAME(r26, regs[26]), | |
520 | REG_OFFSET_NAME(r27, regs[27]), | |
521 | REG_OFFSET_NAME(r28, regs[28]), | |
522 | REG_OFFSET_NAME(r29, regs[29]), | |
523 | REG_OFFSET_NAME(r30, regs[30]), | |
524 | REG_OFFSET_NAME(r31, regs[31]), | |
525 | REG_OFFSET_NAME(c0_status, cp0_status), | |
526 | REG_OFFSET_NAME(hi, hi), | |
527 | REG_OFFSET_NAME(lo, lo), | |
528 | #ifdef CONFIG_CPU_HAS_SMARTMIPS | |
529 | REG_OFFSET_NAME(acx, acx), | |
530 | #endif | |
531 | REG_OFFSET_NAME(c0_badvaddr, cp0_badvaddr), | |
532 | REG_OFFSET_NAME(c0_cause, cp0_cause), | |
533 | REG_OFFSET_NAME(c0_epc, cp0_epc), | |
40e084a5 RB |
534 | #ifdef CONFIG_CPU_CAVIUM_OCTEON |
535 | REG_OFFSET_NAME(mpl0, mpl[0]), | |
536 | REG_OFFSET_NAME(mpl1, mpl[1]), | |
537 | REG_OFFSET_NAME(mpl2, mpl[2]), | |
538 | REG_OFFSET_NAME(mtp0, mtp[0]), | |
539 | REG_OFFSET_NAME(mtp1, mtp[1]), | |
540 | REG_OFFSET_NAME(mtp2, mtp[2]), | |
541 | #endif | |
542 | REG_OFFSET_END, | |
543 | }; | |
544 | ||
545 | /** | |
546 | * regs_query_register_offset() - query register offset from its name | |
547 | * @name: the name of a register | |
548 | * | |
549 | * regs_query_register_offset() returns the offset of a register in struct | |
550 | * pt_regs from its name. If the name is invalid, this returns -EINVAL; | |
551 | */ | |
552 | int regs_query_register_offset(const char *name) | |
553 | { | |
554 | const struct pt_regs_offset *roff; | |
555 | for (roff = regoffset_table; roff->name != NULL; roff++) | |
556 | if (!strcmp(roff->name, name)) | |
557 | return roff->offset; | |
558 | return -EINVAL; | |
559 | } | |
560 | ||
c23b3d1a AS |
561 | #if defined(CONFIG_32BIT) || defined(CONFIG_MIPS32_O32) |
562 | ||
7aeb753b RB |
563 | static const struct user_regset mips_regsets[] = { |
564 | [REGSET_GPR] = { | |
565 | .core_note_type = NT_PRSTATUS, | |
566 | .n = ELF_NGREG, | |
567 | .size = sizeof(unsigned int), | |
568 | .align = sizeof(unsigned int), | |
c23b3d1a AS |
569 | .get = gpr32_get, |
570 | .set = gpr32_set, | |
7aeb753b RB |
571 | }, |
572 | [REGSET_FPR] = { | |
573 | .core_note_type = NT_PRFPREG, | |
574 | .n = ELF_NFPREG, | |
575 | .size = sizeof(elf_fpreg_t), | |
576 | .align = sizeof(elf_fpreg_t), | |
577 | .get = fpr_get, | |
578 | .set = fpr_set, | |
579 | }, | |
580 | }; | |
581 | ||
582 | static const struct user_regset_view user_mips_view = { | |
583 | .name = "mips", | |
584 | .e_machine = ELF_ARCH, | |
585 | .ei_osabi = ELF_OSABI, | |
586 | .regsets = mips_regsets, | |
587 | .n = ARRAY_SIZE(mips_regsets), | |
588 | }; | |
589 | ||
c23b3d1a AS |
590 | #endif /* CONFIG_32BIT || CONFIG_MIPS32_O32 */ |
591 | ||
592 | #ifdef CONFIG_64BIT | |
593 | ||
7aeb753b RB |
594 | static const struct user_regset mips64_regsets[] = { |
595 | [REGSET_GPR] = { | |
596 | .core_note_type = NT_PRSTATUS, | |
597 | .n = ELF_NGREG, | |
598 | .size = sizeof(unsigned long), | |
599 | .align = sizeof(unsigned long), | |
c23b3d1a AS |
600 | .get = gpr64_get, |
601 | .set = gpr64_set, | |
7aeb753b RB |
602 | }, |
603 | [REGSET_FPR] = { | |
604 | .core_note_type = NT_PRFPREG, | |
605 | .n = ELF_NFPREG, | |
606 | .size = sizeof(elf_fpreg_t), | |
607 | .align = sizeof(elf_fpreg_t), | |
608 | .get = fpr_get, | |
609 | .set = fpr_set, | |
610 | }, | |
611 | }; | |
612 | ||
613 | static const struct user_regset_view user_mips64_view = { | |
c23b3d1a | 614 | .name = "mips64", |
7aeb753b RB |
615 | .e_machine = ELF_ARCH, |
616 | .ei_osabi = ELF_OSABI, | |
617 | .regsets = mips64_regsets, | |
c23b3d1a | 618 | .n = ARRAY_SIZE(mips64_regsets), |
7aeb753b RB |
619 | }; |
620 | ||
547da673 MR |
621 | #ifdef CONFIG_MIPS32_N32 |
622 | ||
623 | static const struct user_regset_view user_mipsn32_view = { | |
624 | .name = "mipsn32", | |
625 | .e_flags = EF_MIPS_ABI2, | |
626 | .e_machine = ELF_ARCH, | |
627 | .ei_osabi = ELF_OSABI, | |
628 | .regsets = mips64_regsets, | |
629 | .n = ARRAY_SIZE(mips64_regsets), | |
630 | }; | |
631 | ||
632 | #endif /* CONFIG_MIPS32_N32 */ | |
633 | ||
c23b3d1a AS |
634 | #endif /* CONFIG_64BIT */ |
635 | ||
7aeb753b RB |
636 | const struct user_regset_view *task_user_regset_view(struct task_struct *task) |
637 | { | |
638 | #ifdef CONFIG_32BIT | |
639 | return &user_mips_view; | |
c23b3d1a | 640 | #else |
7aeb753b | 641 | #ifdef CONFIG_MIPS32_O32 |
c23b3d1a AS |
642 | if (test_tsk_thread_flag(task, TIF_32BIT_REGS)) |
643 | return &user_mips_view; | |
547da673 MR |
644 | #endif |
645 | #ifdef CONFIG_MIPS32_N32 | |
646 | if (test_tsk_thread_flag(task, TIF_32BIT_ADDR)) | |
647 | return &user_mipsn32_view; | |
7aeb753b | 648 | #endif |
7aeb753b | 649 | return &user_mips64_view; |
c23b3d1a | 650 | #endif |
7aeb753b RB |
651 | } |
652 | ||
9b05a69e NK |
653 | long arch_ptrace(struct task_struct *child, long request, |
654 | unsigned long addr, unsigned long data) | |
1da177e4 | 655 | { |
1da177e4 | 656 | int ret; |
fb671139 NK |
657 | void __user *addrp = (void __user *) addr; |
658 | void __user *datavp = (void __user *) data; | |
659 | unsigned long __user *datalp = (void __user *) data; | |
1da177e4 | 660 | |
1da177e4 LT |
661 | switch (request) { |
662 | /* when I and D space are separate, these will need to be fixed. */ | |
663 | case PTRACE_PEEKTEXT: /* read word at location addr. */ | |
76647323 AD |
664 | case PTRACE_PEEKDATA: |
665 | ret = generic_ptrace_peekdata(child, addr, data); | |
1da177e4 | 666 | break; |
1da177e4 LT |
667 | |
668 | /* Read the word at location addr in the USER area. */ | |
669 | case PTRACE_PEEKUSR: { | |
670 | struct pt_regs *regs; | |
bbd426f5 | 671 | union fpureg *fregs; |
1da177e4 LT |
672 | unsigned long tmp = 0; |
673 | ||
40bc9c67 | 674 | regs = task_pt_regs(child); |
1da177e4 LT |
675 | ret = 0; /* Default return value. */ |
676 | ||
677 | switch (addr) { | |
678 | case 0 ... 31: | |
679 | tmp = regs->regs[addr]; | |
680 | break; | |
681 | case FPR_BASE ... FPR_BASE + 31: | |
597ce172 PB |
682 | if (!tsk_used_math(child)) { |
683 | /* FP not yet used */ | |
684 | tmp = -1; | |
685 | break; | |
686 | } | |
687 | fregs = get_fpu_regs(child); | |
1da177e4 | 688 | |
875d43e7 | 689 | #ifdef CONFIG_32BIT |
597ce172 | 690 | if (test_thread_flag(TIF_32BIT_FPREGS)) { |
1da177e4 LT |
691 | /* |
692 | * The odd registers are actually the high | |
693 | * order bits of the values stored in the even | |
694 | * registers - unless we're using r2k_switch.S. | |
695 | */ | |
bbd426f5 PB |
696 | tmp = get_fpr32(&fregs[(addr & ~1) - FPR_BASE], |
697 | addr & 1); | |
597ce172 | 698 | break; |
1da177e4 | 699 | } |
597ce172 | 700 | #endif |
bbd426f5 | 701 | tmp = get_fpr32(&fregs[addr - FPR_BASE], 0); |
1da177e4 LT |
702 | break; |
703 | case PC: | |
704 | tmp = regs->cp0_epc; | |
705 | break; | |
706 | case CAUSE: | |
707 | tmp = regs->cp0_cause; | |
708 | break; | |
709 | case BADVADDR: | |
710 | tmp = regs->cp0_badvaddr; | |
711 | break; | |
712 | case MMHI: | |
713 | tmp = regs->hi; | |
714 | break; | |
715 | case MMLO: | |
716 | tmp = regs->lo; | |
717 | break; | |
9693a853 FBH |
718 | #ifdef CONFIG_CPU_HAS_SMARTMIPS |
719 | case ACX: | |
720 | tmp = regs->acx; | |
721 | break; | |
722 | #endif | |
1da177e4 | 723 | case FPC_CSR: |
eae89076 | 724 | tmp = child->thread.fpu.fcr31; |
1da177e4 | 725 | break; |
3351047f PB |
726 | case FPC_EIR: |
727 | /* implementation / version register */ | |
656ff9be | 728 | tmp = boot_cpu_data.fpu_id; |
1da177e4 | 729 | break; |
c134a5ec RB |
730 | case DSP_BASE ... DSP_BASE + 5: { |
731 | dspreg_t *dregs; | |
732 | ||
e50c0a8f RB |
733 | if (!cpu_has_dsp) { |
734 | tmp = 0; | |
735 | ret = -EIO; | |
481bed45 | 736 | goto out; |
e50c0a8f | 737 | } |
6c355852 RB |
738 | dregs = __get_dsp_regs(child); |
739 | tmp = (unsigned long) (dregs[addr - DSP_BASE]); | |
e50c0a8f | 740 | break; |
c134a5ec | 741 | } |
e50c0a8f RB |
742 | case DSP_CONTROL: |
743 | if (!cpu_has_dsp) { | |
744 | tmp = 0; | |
745 | ret = -EIO; | |
481bed45 | 746 | goto out; |
e50c0a8f RB |
747 | } |
748 | tmp = child->thread.dsp.dspcontrol; | |
749 | break; | |
1da177e4 LT |
750 | default: |
751 | tmp = 0; | |
752 | ret = -EIO; | |
481bed45 | 753 | goto out; |
1da177e4 | 754 | } |
fb671139 | 755 | ret = put_user(tmp, datalp); |
1da177e4 LT |
756 | break; |
757 | } | |
758 | ||
759 | /* when I and D space are separate, this will have to be fixed. */ | |
760 | case PTRACE_POKETEXT: /* write the word at location addr. */ | |
761 | case PTRACE_POKEDATA: | |
f284ce72 | 762 | ret = generic_ptrace_pokedata(child, addr, data); |
1da177e4 LT |
763 | break; |
764 | ||
765 | case PTRACE_POKEUSR: { | |
766 | struct pt_regs *regs; | |
767 | ret = 0; | |
40bc9c67 | 768 | regs = task_pt_regs(child); |
1da177e4 LT |
769 | |
770 | switch (addr) { | |
771 | case 0 ... 31: | |
772 | regs->regs[addr] = data; | |
773 | break; | |
774 | case FPR_BASE ... FPR_BASE + 31: { | |
bbd426f5 | 775 | union fpureg *fregs = get_fpu_regs(child); |
1da177e4 | 776 | |
ac9ad83b | 777 | init_fp_ctx(child); |
875d43e7 | 778 | #ifdef CONFIG_32BIT |
597ce172 PB |
779 | if (test_thread_flag(TIF_32BIT_FPREGS)) { |
780 | /* | |
781 | * The odd registers are actually the high | |
782 | * order bits of the values stored in the even | |
783 | * registers - unless we're using r2k_switch.S. | |
784 | */ | |
bbd426f5 PB |
785 | set_fpr32(&fregs[(addr & ~1) - FPR_BASE], |
786 | addr & 1, data); | |
597ce172 | 787 | break; |
1da177e4 LT |
788 | } |
789 | #endif | |
bbd426f5 | 790 | set_fpr64(&fregs[addr - FPR_BASE], 0, data); |
1da177e4 LT |
791 | break; |
792 | } | |
793 | case PC: | |
794 | regs->cp0_epc = data; | |
795 | break; | |
796 | case MMHI: | |
797 | regs->hi = data; | |
798 | break; | |
799 | case MMLO: | |
800 | regs->lo = data; | |
801 | break; | |
9693a853 FBH |
802 | #ifdef CONFIG_CPU_HAS_SMARTMIPS |
803 | case ACX: | |
804 | regs->acx = data; | |
805 | break; | |
806 | #endif | |
1da177e4 | 807 | case FPC_CSR: |
c9e56039 | 808 | init_fp_ctx(child); |
abf378be | 809 | ptrace_setfcr31(child, data); |
1da177e4 | 810 | break; |
c134a5ec RB |
811 | case DSP_BASE ... DSP_BASE + 5: { |
812 | dspreg_t *dregs; | |
813 | ||
e50c0a8f RB |
814 | if (!cpu_has_dsp) { |
815 | ret = -EIO; | |
816 | break; | |
817 | } | |
818 | ||
c134a5ec | 819 | dregs = __get_dsp_regs(child); |
e50c0a8f RB |
820 | dregs[addr - DSP_BASE] = data; |
821 | break; | |
c134a5ec | 822 | } |
e50c0a8f RB |
823 | case DSP_CONTROL: |
824 | if (!cpu_has_dsp) { | |
825 | ret = -EIO; | |
826 | break; | |
827 | } | |
828 | child->thread.dsp.dspcontrol = data; | |
829 | break; | |
1da177e4 LT |
830 | default: |
831 | /* The rest are not allowed. */ | |
832 | ret = -EIO; | |
833 | break; | |
834 | } | |
835 | break; | |
836 | } | |
837 | ||
ea3d710f | 838 | case PTRACE_GETREGS: |
fb671139 | 839 | ret = ptrace_getregs(child, datavp); |
ea3d710f DJ |
840 | break; |
841 | ||
842 | case PTRACE_SETREGS: | |
fb671139 | 843 | ret = ptrace_setregs(child, datavp); |
ea3d710f DJ |
844 | break; |
845 | ||
846 | case PTRACE_GETFPREGS: | |
fb671139 | 847 | ret = ptrace_getfpregs(child, datavp); |
ea3d710f DJ |
848 | break; |
849 | ||
850 | case PTRACE_SETFPREGS: | |
fb671139 | 851 | ret = ptrace_setfpregs(child, datavp); |
ea3d710f DJ |
852 | break; |
853 | ||
3c37026d | 854 | case PTRACE_GET_THREAD_AREA: |
fb671139 | 855 | ret = put_user(task_thread_info(child)->tp_value, datalp); |
3c37026d RB |
856 | break; |
857 | ||
0926bf95 | 858 | case PTRACE_GET_WATCH_REGS: |
fb671139 | 859 | ret = ptrace_get_watch_regs(child, addrp); |
0926bf95 DD |
860 | break; |
861 | ||
862 | case PTRACE_SET_WATCH_REGS: | |
fb671139 | 863 | ret = ptrace_set_watch_regs(child, addrp); |
0926bf95 DD |
864 | break; |
865 | ||
1da177e4 LT |
866 | default: |
867 | ret = ptrace_request(child, request, addr, data); | |
868 | break; | |
869 | } | |
481bed45 | 870 | out: |
1da177e4 LT |
871 | return ret; |
872 | } | |
873 | ||
874 | /* | |
875 | * Notification of system call entry/exit | |
876 | * - triggered by current->work.syscall_trace | |
877 | */ | |
4c21b8fd | 878 | asmlinkage long syscall_trace_enter(struct pt_regs *regs, long syscall) |
1da177e4 | 879 | { |
c3fc5cd5 RB |
880 | user_exit(); |
881 | ||
c2d9f177 LP |
882 | current_thread_info()->syscall = syscall; |
883 | ||
b6318a90 JH |
884 | if (test_thread_flag(TIF_SYSCALL_TRACE)) { |
885 | if (tracehook_report_syscall_entry(regs)) | |
886 | return -1; | |
887 | syscall = current_thread_info()->syscall; | |
888 | } | |
2ac3c8d1 | 889 | |
669c4092 DD |
890 | #ifdef CONFIG_SECCOMP |
891 | if (unlikely(test_thread_flag(TIF_SECCOMP))) { | |
892 | int ret, i; | |
893 | struct seccomp_data sd; | |
3d729dea | 894 | unsigned long args[6]; |
669c4092 DD |
895 | |
896 | sd.nr = syscall; | |
897 | sd.arch = syscall_get_arch(); | |
3d729dea JH |
898 | syscall_get_arguments(current, regs, 0, 6, args); |
899 | for (i = 0; i < 6; i++) | |
900 | sd.args[i] = args[i]; | |
669c4092 DD |
901 | sd.instruction_pointer = KSTK_EIP(current); |
902 | ||
903 | ret = __secure_computing(&sd); | |
904 | if (ret == -1) | |
905 | return ret; | |
b6318a90 | 906 | syscall = current_thread_info()->syscall; |
669c4092 DD |
907 | } |
908 | #endif | |
293c5bd1 | 909 | |
1d7bf993 RB |
910 | if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT))) |
911 | trace_sys_enter(regs, regs->regs[2]); | |
912 | ||
91397401 | 913 | audit_syscall_entry(syscall, regs->regs[4], regs->regs[5], |
b05d8447 | 914 | regs->regs[6], regs->regs[7]); |
828db212 JH |
915 | |
916 | /* | |
917 | * Negative syscall numbers are mistaken for rejected syscalls, but | |
918 | * won't have had the return value set appropriately, so we do so now. | |
919 | */ | |
920 | if (syscall < 0) | |
921 | syscall_set_return_value(current, regs, -ENOSYS, 0); | |
1225eb82 | 922 | return syscall; |
1da177e4 | 923 | } |
8b659a39 RB |
924 | |
925 | /* | |
926 | * Notification of system call entry/exit | |
927 | * - triggered by current->work.syscall_trace | |
928 | */ | |
929 | asmlinkage void syscall_trace_leave(struct pt_regs *regs) | |
930 | { | |
c3fc5cd5 RB |
931 | /* |
932 | * We may come here right after calling schedule_user() | |
933 | * or do_notify_resume(), in which case we can be in RCU | |
934 | * user mode. | |
935 | */ | |
936 | user_exit(); | |
937 | ||
d7e7528b | 938 | audit_syscall_exit(regs); |
8b659a39 | 939 | |
1d7bf993 | 940 | if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT))) |
4f32a39d | 941 | trace_sys_exit(regs, regs_return_value(regs)); |
1d7bf993 | 942 | |
bc3d22c1 RB |
943 | if (test_thread_flag(TIF_SYSCALL_TRACE)) |
944 | tracehook_report_syscall_exit(regs, 0); | |
c3fc5cd5 RB |
945 | |
946 | user_enter(); | |
8b659a39 | 947 | } |