Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 1994 - 1999, 2000 by Ralf Baechle and others. | |
40ac5d47 | 7 | * Copyright (C) 2005, 2006 by Ralf Baechle (ralf@linux-mips.org) |
1da177e4 LT |
8 | * Copyright (C) 1999, 2000 Silicon Graphics, Inc. |
9 | * Copyright (C) 2004 Thiemo Seufer | |
34c2f668 | 10 | * Copyright (C) 2013 Imagination Technologies Ltd. |
1da177e4 | 11 | */ |
1da177e4 | 12 | #include <linux/errno.h> |
1da177e4 | 13 | #include <linux/sched.h> |
b17b0153 | 14 | #include <linux/sched/debug.h> |
29930025 | 15 | #include <linux/sched/task.h> |
68db0cf1 | 16 | #include <linux/sched/task_stack.h> |
7bcf7717 | 17 | #include <linux/tick.h> |
1da177e4 LT |
18 | #include <linux/kernel.h> |
19 | #include <linux/mm.h> | |
20 | #include <linux/stddef.h> | |
21 | #include <linux/unistd.h> | |
cae39d13 | 22 | #include <linux/export.h> |
1da177e4 | 23 | #include <linux/ptrace.h> |
1da177e4 LT |
24 | #include <linux/mman.h> |
25 | #include <linux/personality.h> | |
26 | #include <linux/sys.h> | |
1da177e4 LT |
27 | #include <linux/init.h> |
28 | #include <linux/completion.h> | |
63077519 | 29 | #include <linux/kallsyms.h> |
94109102 | 30 | #include <linux/random.h> |
9791554b | 31 | #include <linux/prctl.h> |
1da177e4 | 32 | |
94109102 | 33 | #include <asm/asm.h> |
1da177e4 LT |
34 | #include <asm/bootinfo.h> |
35 | #include <asm/cpu.h> | |
432c6bac | 36 | #include <asm/dsemul.h> |
e50c0a8f | 37 | #include <asm/dsp.h> |
1da177e4 | 38 | #include <asm/fpu.h> |
d42d8d10 | 39 | #include <asm/irq.h> |
1db1af84 | 40 | #include <asm/msa.h> |
1da177e4 | 41 | #include <asm/pgtable.h> |
1da177e4 LT |
42 | #include <asm/mipsregs.h> |
43 | #include <asm/processor.h> | |
60be939c | 44 | #include <asm/reg.h> |
7c0f6ba6 | 45 | #include <linux/uaccess.h> |
1da177e4 LT |
46 | #include <asm/io.h> |
47 | #include <asm/elf.h> | |
48 | #include <asm/isadep.h> | |
49 | #include <asm/inst.h> | |
1df0f0ff | 50 | #include <asm/stacktrace.h> |
856839b7 | 51 | #include <asm/irq_regs.h> |
1da177e4 | 52 | |
cdbedc61 TG |
53 | #ifdef CONFIG_HOTPLUG_CPU |
54 | void arch_cpu_idle_dead(void) | |
1da177e4 | 55 | { |
a00eeede | 56 | play_dead(); |
cdbedc61 TG |
57 | } |
58 | #endif | |
1b2bc75c | 59 | |
1da177e4 | 60 | asmlinkage void ret_from_fork(void); |
8f54bcac | 61 | asmlinkage void ret_from_kernel_thread(void); |
1da177e4 LT |
62 | |
63 | void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp) | |
64 | { | |
65 | unsigned long status; | |
66 | ||
67 | /* New thread loses kernel privileges. */ | |
bbaf238b | 68 | status = regs->cp0_status & ~(ST0_CU0|ST0_CU1|ST0_FR|KU_MASK); |
1da177e4 LT |
69 | status |= KU_USER; |
70 | regs->cp0_status = status; | |
76e5846d JH |
71 | lose_fpu(0); |
72 | clear_thread_flag(TIF_MSA_CTX_LIVE); | |
1da177e4 | 73 | clear_used_math(); |
432c6bac | 74 | atomic_set(¤t->thread.bd_emu_frame, BD_EMUFRAME_NONE); |
a3056b1c | 75 | init_dsp(); |
1da177e4 LT |
76 | regs->cp0_epc = pc; |
77 | regs->regs[29] = sp; | |
1da177e4 LT |
78 | } |
79 | ||
432c6bac PB |
80 | void exit_thread(struct task_struct *tsk) |
81 | { | |
82 | /* | |
83 | * User threads may have allocated a delay slot emulation frame. | |
84 | * If so, clean up that allocation. | |
85 | */ | |
86 | if (!(current->flags & PF_KTHREAD)) | |
87 | dsemul_thread_cleanup(tsk); | |
88 | } | |
89 | ||
39148e94 JH |
90 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) |
91 | { | |
92 | /* | |
93 | * Save any process state which is live in hardware registers to the | |
94 | * parent context prior to duplication. This prevents the new child | |
95 | * state becoming stale if the parent is preempted before copy_thread() | |
96 | * gets a chance to save the parent's live hardware registers to the | |
97 | * child context. | |
98 | */ | |
99 | preempt_disable(); | |
100 | ||
101 | if (is_msa_enabled()) | |
102 | save_msa(current); | |
103 | else if (is_fpu_owner()) | |
104 | _save_fp(current); | |
105 | ||
106 | save_dsp(current); | |
107 | ||
108 | preempt_enable(); | |
109 | ||
110 | *dst = *src; | |
111 | return 0; | |
112 | } | |
113 | ||
e2c5aaa5 AD |
114 | /* |
115 | * Copy architecture-specific thread state | |
116 | */ | |
6f2c55b8 | 117 | int copy_thread(unsigned long clone_flags, unsigned long usp, |
e2c5aaa5 | 118 | unsigned long kthread_arg, struct task_struct *p) |
1da177e4 | 119 | { |
75bb07e7 | 120 | struct thread_info *ti = task_thread_info(p); |
afa86fc4 | 121 | struct pt_regs *childregs, *regs = current_pt_regs(); |
484889fc | 122 | unsigned long childksp; |
3c37026d | 123 | p->set_child_tid = p->clear_child_tid = NULL; |
1da177e4 | 124 | |
75bb07e7 | 125 | childksp = (unsigned long)task_stack_page(p) + THREAD_SIZE - 32; |
1da177e4 | 126 | |
1da177e4 LT |
127 | /* set up new TSS. */ |
128 | childregs = (struct pt_regs *) childksp - 1; | |
484889fc DD |
129 | /* Put the stack after the struct pt_regs. */ |
130 | childksp = (unsigned long) childregs; | |
8f54bcac AV |
131 | p->thread.cp0_status = read_c0_status() & ~(ST0_CU2|ST0_CU1); |
132 | if (unlikely(p->flags & PF_KTHREAD)) { | |
e2c5aaa5 | 133 | /* kernel thread */ |
8f54bcac AV |
134 | unsigned long status = p->thread.cp0_status; |
135 | memset(childregs, 0, sizeof(struct pt_regs)); | |
136 | ti->addr_limit = KERNEL_DS; | |
137 | p->thread.reg16 = usp; /* fn */ | |
e2c5aaa5 | 138 | p->thread.reg17 = kthread_arg; |
8f54bcac AV |
139 | p->thread.reg29 = childksp; |
140 | p->thread.reg31 = (unsigned long) ret_from_kernel_thread; | |
141 | #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) | |
142 | status = (status & ~(ST0_KUP | ST0_IEP | ST0_IEC)) | | |
143 | ((status & (ST0_KUC | ST0_IEC)) << 2); | |
144 | #else | |
145 | status |= ST0_EXL; | |
146 | #endif | |
147 | childregs->cp0_status = status; | |
148 | return 0; | |
149 | } | |
e2c5aaa5 AD |
150 | |
151 | /* user thread */ | |
1da177e4 | 152 | *childregs = *regs; |
70342287 RB |
153 | childregs->regs[7] = 0; /* Clear error flag */ |
154 | childregs->regs[2] = 0; /* Child gets zero as return value */ | |
64b3122d AV |
155 | if (usp) |
156 | childregs->regs[29] = usp; | |
8f54bcac | 157 | ti->addr_limit = USER_DS; |
1da177e4 | 158 | |
1da177e4 LT |
159 | p->thread.reg29 = (unsigned long) childregs; |
160 | p->thread.reg31 = (unsigned long) ret_from_fork; | |
161 | ||
162 | /* | |
163 | * New tasks lose permission to use the fpu. This accelerates context | |
164 | * switching for most programs since they don't use the fpu. | |
165 | */ | |
1da177e4 | 166 | childregs->cp0_status &= ~(ST0_CU2|ST0_CU1); |
1da177e4 | 167 | |
1da177e4 | 168 | clear_tsk_thread_flag(p, TIF_USEDFPU); |
7daef8f2 PB |
169 | clear_tsk_thread_flag(p, TIF_USEDMSA); |
170 | clear_tsk_thread_flag(p, TIF_MSA_CTX_LIVE); | |
1da177e4 | 171 | |
f088fc84 | 172 | #ifdef CONFIG_MIPS_MT_FPAFF |
6657fe0a | 173 | clear_tsk_thread_flag(p, TIF_FPUBOUND); |
f088fc84 RB |
174 | #endif /* CONFIG_MIPS_MT_FPAFF */ |
175 | ||
432c6bac PB |
176 | atomic_set(&p->thread.bd_emu_frame, BD_EMUFRAME_NONE); |
177 | ||
3c37026d RB |
178 | if (clone_flags & CLONE_SETTLS) |
179 | ti->tp_value = regs->regs[7]; | |
180 | ||
1da177e4 LT |
181 | return 0; |
182 | } | |
183 | ||
36ecafc5 GF |
184 | #ifdef CONFIG_CC_STACKPROTECTOR |
185 | #include <linux/stackprotector.h> | |
186 | unsigned long __stack_chk_guard __read_mostly; | |
187 | EXPORT_SYMBOL(__stack_chk_guard); | |
188 | #endif | |
189 | ||
b5943182 FBH |
190 | struct mips_frame_info { |
191 | void *func; | |
192 | unsigned long func_size; | |
193 | int frame_size; | |
194 | int pc_offset; | |
195 | }; | |
dc953df1 | 196 | |
5000653e TW |
197 | #define J_TARGET(pc,target) \ |
198 | (((unsigned long)(pc) & 0xf0000000) | ((target) << 2)) | |
199 | ||
bb9bc468 | 200 | static inline int is_ra_save_ins(union mips_instruction *ip, int *poff) |
c0efbb6d | 201 | { |
34c2f668 | 202 | #ifdef CONFIG_CPU_MICROMIPS |
34c2f668 LY |
203 | /* |
204 | * swsp ra,offset | |
205 | * swm16 reglist,offset(sp) | |
206 | * swm32 reglist,offset(sp) | |
207 | * sw32 ra,offset(sp) | |
208 | * jradiussp - NOT SUPPORTED | |
209 | * | |
210 | * microMIPS is way more fun... | |
211 | */ | |
a3552dac | 212 | if (mm_insn_16bit(ip->halfword[1])) { |
bb9bc468 PB |
213 | switch (ip->mm16_r5_format.opcode) { |
214 | case mm_swsp16_op: | |
215 | if (ip->mm16_r5_format.rt != 31) | |
216 | return 0; | |
217 | ||
218 | *poff = ip->mm16_r5_format.simmediate; | |
219 | *poff = (*poff << 2) / sizeof(ulong); | |
220 | return 1; | |
221 | ||
222 | case mm_pool16c_op: | |
223 | switch (ip->mm16_m_format.func) { | |
224 | case mm_swm16_op: | |
225 | *poff = ip->mm16_m_format.imm; | |
226 | *poff += 1 + ip->mm16_m_format.rlist; | |
227 | *poff = (*poff << 2) / sizeof(ulong); | |
228 | return 1; | |
229 | ||
230 | default: | |
231 | return 0; | |
232 | } | |
233 | ||
234 | default: | |
235 | return 0; | |
236 | } | |
34c2f668 | 237 | } |
bb9bc468 PB |
238 | |
239 | switch (ip->i_format.opcode) { | |
240 | case mm_sw32_op: | |
241 | if (ip->i_format.rs != 29) | |
242 | return 0; | |
243 | if (ip->i_format.rt != 31) | |
244 | return 0; | |
245 | ||
246 | *poff = ip->i_format.simmediate / sizeof(ulong); | |
247 | return 1; | |
248 | ||
249 | case mm_pool32b_op: | |
250 | switch (ip->mm_m_format.func) { | |
251 | case mm_swm32_func: | |
252 | if (ip->mm_m_format.rd < 0x10) | |
253 | return 0; | |
254 | if (ip->mm_m_format.base != 29) | |
255 | return 0; | |
256 | ||
257 | *poff = ip->mm_m_format.simmediate; | |
258 | *poff += (ip->mm_m_format.rd & 0xf) * sizeof(u32); | |
259 | *poff /= sizeof(ulong); | |
260 | return 1; | |
261 | default: | |
262 | return 0; | |
263 | } | |
264 | ||
265 | default: | |
266 | return 0; | |
34c2f668 LY |
267 | } |
268 | #else | |
c0efbb6d | 269 | /* sw / sd $ra, offset($sp) */ |
bb9bc468 PB |
270 | if ((ip->i_format.opcode == sw_op || ip->i_format.opcode == sd_op) && |
271 | ip->i_format.rs == 29 && ip->i_format.rt == 31) { | |
272 | *poff = ip->i_format.simmediate / sizeof(ulong); | |
273 | return 1; | |
274 | } | |
275 | ||
276 | return 0; | |
34c2f668 | 277 | #endif |
c0efbb6d FBH |
278 | } |
279 | ||
e7438c4b | 280 | static inline int is_jump_ins(union mips_instruction *ip) |
c0efbb6d | 281 | { |
34c2f668 LY |
282 | #ifdef CONFIG_CPU_MICROMIPS |
283 | /* | |
284 | * jr16,jrc,jalr16,jalr16 | |
285 | * jal | |
286 | * jalr/jr,jalr.hb/jr.hb,jalrs,jalrs.hb | |
287 | * jraddiusp - NOT SUPPORTED | |
288 | * | |
289 | * microMIPS is kind of more fun... | |
290 | */ | |
67c75057 PB |
291 | if (mm_insn_16bit(ip->halfword[1])) { |
292 | if ((ip->mm16_r5_format.opcode == mm_pool16c_op && | |
293 | (ip->mm16_r5_format.rt & mm_jr16_op) == mm_jr16_op)) | |
294 | return 1; | |
295 | return 0; | |
296 | } | |
297 | ||
096a0de4 PB |
298 | if (ip->j_format.opcode == mm_j32_op) |
299 | return 1; | |
67c75057 | 300 | if (ip->j_format.opcode == mm_jal32_op) |
34c2f668 LY |
301 | return 1; |
302 | if (ip->r_format.opcode != mm_pool32a_op || | |
303 | ip->r_format.func != mm_pool32axf_op) | |
304 | return 0; | |
635c9907 | 305 | return ((ip->u_format.uimmediate >> 6) & mm_jalr_op) == mm_jalr_op; |
34c2f668 | 306 | #else |
e7438c4b TW |
307 | if (ip->j_format.opcode == j_op) |
308 | return 1; | |
c0efbb6d FBH |
309 | if (ip->j_format.opcode == jal_op) |
310 | return 1; | |
311 | if (ip->r_format.opcode != spec_op) | |
312 | return 0; | |
313 | return ip->r_format.func == jalr_op || ip->r_format.func == jr_op; | |
34c2f668 | 314 | #endif |
c0efbb6d FBH |
315 | } |
316 | ||
317 | static inline int is_sp_move_ins(union mips_instruction *ip) | |
318 | { | |
34c2f668 LY |
319 | #ifdef CONFIG_CPU_MICROMIPS |
320 | /* | |
321 | * addiusp -imm | |
322 | * addius5 sp,-imm | |
323 | * addiu32 sp,sp,-imm | |
324 | * jradiussp - NOT SUPPORTED | |
325 | * | |
326 | * microMIPS is not more fun... | |
327 | */ | |
a3552dac PB |
328 | if (mm_insn_16bit(ip->halfword[1])) { |
329 | return (ip->mm16_r3_format.opcode == mm_pool16d_op && | |
330 | ip->mm16_r3_format.simmediate && mm_addiusp_func) || | |
331 | (ip->mm16_r5_format.opcode == mm_pool16d_op && | |
332 | ip->mm16_r5_format.rt == 29); | |
34c2f668 | 333 | } |
a3552dac | 334 | |
635c9907 RB |
335 | return ip->mm_i_format.opcode == mm_addiu32_op && |
336 | ip->mm_i_format.rt == 29 && ip->mm_i_format.rs == 29; | |
34c2f668 | 337 | #else |
c0efbb6d FBH |
338 | /* addiu/daddiu sp,sp,-imm */ |
339 | if (ip->i_format.rs != 29 || ip->i_format.rt != 29) | |
340 | return 0; | |
341 | if (ip->i_format.opcode == addiu_op || ip->i_format.opcode == daddiu_op) | |
342 | return 1; | |
34c2f668 | 343 | #endif |
c0efbb6d FBH |
344 | return 0; |
345 | } | |
346 | ||
f66686f7 | 347 | static int get_frame_info(struct mips_frame_info *info) |
1da177e4 | 348 | { |
a3552dac | 349 | bool is_mmips = IS_ENABLED(CONFIG_CPU_MICROMIPS); |
b6c7a324 PB |
350 | union mips_instruction insn, *ip, *ip_end; |
351 | const unsigned int max_insns = 128; | |
352 | unsigned int i; | |
c0efbb6d | 353 | |
1da177e4 | 354 | info->pc_offset = -1; |
63077519 | 355 | info->frame_size = 0; |
1da177e4 | 356 | |
ccaf7caf | 357 | ip = (void *)msk_isa16_mode((ulong)info->func); |
29b376ff FBH |
358 | if (!ip) |
359 | goto err; | |
360 | ||
b6c7a324 | 361 | ip_end = (void *)ip + info->func_size; |
29b376ff | 362 | |
b6c7a324 | 363 | for (i = 0; i < max_insns && ip < ip_end; i++, ip++) { |
a3552dac PB |
364 | if (is_mmips && mm_insn_16bit(ip->halfword[0])) { |
365 | insn.halfword[0] = 0; | |
366 | insn.halfword[1] = ip->halfword[0]; | |
367 | } else if (is_mmips) { | |
368 | insn.halfword[0] = ip->halfword[1]; | |
369 | insn.halfword[1] = ip->halfword[0]; | |
370 | } else { | |
371 | insn.word = ip->word; | |
372 | } | |
c0efbb6d | 373 | |
a3552dac | 374 | if (is_jump_ins(&insn)) |
63077519 | 375 | break; |
a3552dac | 376 | |
0cceb4aa | 377 | if (!info->frame_size) { |
a3552dac | 378 | if (is_sp_move_ins(&insn)) |
34c2f668 LY |
379 | { |
380 | #ifdef CONFIG_CPU_MICROMIPS | |
381 | if (mm_insn_16bit(ip->halfword[0])) | |
382 | { | |
383 | unsigned short tmp; | |
384 | ||
385 | if (ip->halfword[0] & mm_addiusp_func) | |
386 | { | |
387 | tmp = (((ip->halfword[0] >> 1) & 0x1ff) << 2); | |
388 | info->frame_size = -(signed short)(tmp | ((tmp & 0x100) ? 0xfe00 : 0)); | |
389 | } else { | |
390 | tmp = (ip->halfword[0] >> 1); | |
391 | info->frame_size = -(signed short)(tmp & 0xf); | |
392 | } | |
393 | ip = (void *) &ip->halfword[1]; | |
394 | ip--; | |
395 | } else | |
396 | #endif | |
0cceb4aa | 397 | info->frame_size = - ip->i_format.simmediate; |
34c2f668 | 398 | } |
0cceb4aa | 399 | continue; |
63077519 | 400 | } |
bb9bc468 PB |
401 | if (info->pc_offset == -1 && |
402 | is_ra_save_ins(&insn, &info->pc_offset)) | |
0cceb4aa | 403 | break; |
1da177e4 | 404 | } |
f66686f7 AN |
405 | if (info->frame_size && info->pc_offset >= 0) /* nested */ |
406 | return 0; | |
407 | if (info->pc_offset < 0) /* leaf */ | |
408 | return 1; | |
a90c59e6 | 409 | /* prologue seems bogus... */ |
29b376ff | 410 | err: |
f66686f7 | 411 | return -1; |
1da177e4 LT |
412 | } |
413 | ||
b5943182 FBH |
414 | static struct mips_frame_info schedule_mfi __read_mostly; |
415 | ||
5000653e TW |
416 | #ifdef CONFIG_KALLSYMS |
417 | static unsigned long get___schedule_addr(void) | |
418 | { | |
419 | return kallsyms_lookup_name("__schedule"); | |
420 | } | |
421 | #else | |
422 | static unsigned long get___schedule_addr(void) | |
423 | { | |
424 | union mips_instruction *ip = (void *)schedule; | |
425 | int max_insns = 8; | |
426 | int i; | |
427 | ||
428 | for (i = 0; i < max_insns; i++, ip++) { | |
429 | if (ip->j_format.opcode == j_op) | |
430 | return J_TARGET(ip, ip->j_format.target); | |
431 | } | |
432 | return 0; | |
433 | } | |
434 | #endif | |
435 | ||
1da177e4 LT |
436 | static int __init frame_info_init(void) |
437 | { | |
b5943182 | 438 | unsigned long size = 0; |
63077519 | 439 | #ifdef CONFIG_KALLSYMS |
b5943182 | 440 | unsigned long ofs; |
5000653e TW |
441 | #endif |
442 | unsigned long addr; | |
b5943182 | 443 | |
5000653e TW |
444 | addr = get___schedule_addr(); |
445 | if (!addr) | |
446 | addr = (unsigned long)schedule; | |
447 | ||
448 | #ifdef CONFIG_KALLSYMS | |
449 | kallsyms_lookup_size_offset(addr, &size, &ofs); | |
63077519 | 450 | #endif |
5000653e | 451 | schedule_mfi.func = (void *)addr; |
b5943182 FBH |
452 | schedule_mfi.func_size = size; |
453 | ||
454 | get_frame_info(&schedule_mfi); | |
6057a798 FBH |
455 | |
456 | /* | |
457 | * Without schedule() frame info, result given by | |
458 | * thread_saved_pc() and get_wchan() are not reliable. | |
459 | */ | |
b5943182 | 460 | if (schedule_mfi.pc_offset < 0) |
6057a798 | 461 | printk("Can't analyze schedule() prologue at %p\n", schedule); |
63077519 | 462 | |
1da177e4 LT |
463 | return 0; |
464 | } | |
465 | ||
466 | arch_initcall(frame_info_init); | |
467 | ||
468 | /* | |
469 | * Return saved PC of a blocked thread. | |
470 | */ | |
471 | unsigned long thread_saved_pc(struct task_struct *tsk) | |
472 | { | |
473 | struct thread_struct *t = &tsk->thread; | |
474 | ||
475 | /* New born processes are a special case */ | |
476 | if (t->reg31 == (unsigned long) ret_from_fork) | |
477 | return t->reg31; | |
b5943182 | 478 | if (schedule_mfi.pc_offset < 0) |
1da177e4 | 479 | return 0; |
b5943182 | 480 | return ((unsigned long *)t->reg29)[schedule_mfi.pc_offset]; |
1da177e4 LT |
481 | } |
482 | ||
1da177e4 | 483 | |
f66686f7 | 484 | #ifdef CONFIG_KALLSYMS |
94ea09c6 DK |
485 | /* generic stack unwinding function */ |
486 | unsigned long notrace unwind_stack_by_address(unsigned long stack_page, | |
487 | unsigned long *sp, | |
488 | unsigned long pc, | |
489 | unsigned long *ra) | |
f66686f7 | 490 | { |
f66686f7 | 491 | struct mips_frame_info info; |
f66686f7 | 492 | unsigned long size, ofs; |
4d157d5e | 493 | int leaf; |
1924600c AN |
494 | extern void ret_from_irq(void); |
495 | extern void ret_from_exception(void); | |
f66686f7 | 496 | |
f66686f7 AN |
497 | if (!stack_page) |
498 | return 0; | |
499 | ||
1924600c AN |
500 | /* |
501 | * If we reached the bottom of interrupt context, | |
502 | * return saved pc in pt_regs. | |
503 | */ | |
504 | if (pc == (unsigned long)ret_from_irq || | |
505 | pc == (unsigned long)ret_from_exception) { | |
506 | struct pt_regs *regs; | |
507 | if (*sp >= stack_page && | |
508 | *sp + sizeof(*regs) <= stack_page + THREAD_SIZE - 32) { | |
509 | regs = (struct pt_regs *)*sp; | |
510 | pc = regs->cp0_epc; | |
a816b306 | 511 | if (!user_mode(regs) && __kernel_text_address(pc)) { |
1924600c AN |
512 | *sp = regs->regs[29]; |
513 | *ra = regs->regs[31]; | |
514 | return pc; | |
515 | } | |
516 | } | |
517 | return 0; | |
518 | } | |
55b74283 | 519 | if (!kallsyms_lookup_size_offset(pc, &size, &ofs)) |
f66686f7 | 520 | return 0; |
1fd69098 | 521 | /* |
25985edc | 522 | * Return ra if an exception occurred at the first instruction |
1fd69098 | 523 | */ |
1924600c AN |
524 | if (unlikely(ofs == 0)) { |
525 | pc = *ra; | |
526 | *ra = 0; | |
527 | return pc; | |
528 | } | |
f66686f7 AN |
529 | |
530 | info.func = (void *)(pc - ofs); | |
531 | info.func_size = ofs; /* analyze from start to ofs */ | |
4d157d5e FBH |
532 | leaf = get_frame_info(&info); |
533 | if (leaf < 0) | |
f66686f7 | 534 | return 0; |
4d157d5e FBH |
535 | |
536 | if (*sp < stack_page || | |
537 | *sp + info.frame_size > stack_page + THREAD_SIZE - 32) | |
f66686f7 AN |
538 | return 0; |
539 | ||
4d157d5e FBH |
540 | if (leaf) |
541 | /* | |
542 | * For some extreme cases, get_frame_info() can | |
543 | * consider wrongly a nested function as a leaf | |
544 | * one. In that cases avoid to return always the | |
545 | * same value. | |
546 | */ | |
1924600c | 547 | pc = pc != *ra ? *ra : 0; |
4d157d5e FBH |
548 | else |
549 | pc = ((unsigned long *)(*sp))[info.pc_offset]; | |
550 | ||
551 | *sp += info.frame_size; | |
1924600c | 552 | *ra = 0; |
4d157d5e | 553 | return __kernel_text_address(pc) ? pc : 0; |
f66686f7 | 554 | } |
94ea09c6 DK |
555 | EXPORT_SYMBOL(unwind_stack_by_address); |
556 | ||
557 | /* used by show_backtrace() */ | |
558 | unsigned long unwind_stack(struct task_struct *task, unsigned long *sp, | |
559 | unsigned long pc, unsigned long *ra) | |
560 | { | |
d42d8d10 MR |
561 | unsigned long stack_page = 0; |
562 | int cpu; | |
563 | ||
564 | for_each_possible_cpu(cpu) { | |
565 | if (on_irq_stack(cpu, *sp)) { | |
566 | stack_page = (unsigned long)irq_stack[cpu]; | |
567 | break; | |
568 | } | |
569 | } | |
570 | ||
571 | if (!stack_page) | |
572 | stack_page = (unsigned long)task_stack_page(task); | |
573 | ||
94ea09c6 DK |
574 | return unwind_stack_by_address(stack_page, sp, pc, ra); |
575 | } | |
f66686f7 | 576 | #endif |
b5943182 FBH |
577 | |
578 | /* | |
579 | * get_wchan - a maintenance nightmare^W^Wpain in the ass ... | |
580 | */ | |
581 | unsigned long get_wchan(struct task_struct *task) | |
582 | { | |
583 | unsigned long pc = 0; | |
584 | #ifdef CONFIG_KALLSYMS | |
585 | unsigned long sp; | |
1924600c | 586 | unsigned long ra = 0; |
b5943182 FBH |
587 | #endif |
588 | ||
589 | if (!task || task == current || task->state == TASK_RUNNING) | |
590 | goto out; | |
591 | if (!task_stack_page(task)) | |
592 | goto out; | |
593 | ||
594 | pc = thread_saved_pc(task); | |
595 | ||
596 | #ifdef CONFIG_KALLSYMS | |
597 | sp = task->thread.reg29 + schedule_mfi.frame_size; | |
598 | ||
599 | while (in_sched_functions(pc)) | |
1924600c | 600 | pc = unwind_stack(task, &sp, pc, &ra); |
b5943182 FBH |
601 | #endif |
602 | ||
603 | out: | |
604 | return pc; | |
605 | } | |
94109102 FBH |
606 | |
607 | /* | |
608 | * Don't forget that the stack pointer must be aligned on a 8 bytes | |
609 | * boundary for 32-bits ABI and 16 bytes for 64-bits ABI. | |
610 | */ | |
611 | unsigned long arch_align_stack(unsigned long sp) | |
612 | { | |
613 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) | |
614 | sp -= get_random_int() & ~PAGE_MASK; | |
615 | ||
616 | return sp & ALMASK; | |
617 | } | |
856839b7 ES |
618 | |
619 | static void arch_dump_stack(void *info) | |
620 | { | |
621 | struct pt_regs *regs; | |
622 | ||
623 | regs = get_irq_regs(); | |
624 | ||
625 | if (regs) | |
626 | show_regs(regs); | |
627 | ||
628 | dump_stack(); | |
629 | } | |
630 | ||
9a01c3ed | 631 | void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self) |
856839b7 | 632 | { |
9a01c3ed CM |
633 | long this_cpu = get_cpu(); |
634 | ||
635 | if (cpumask_test_cpu(this_cpu, mask) && !exclude_self) | |
636 | dump_stack(); | |
637 | ||
638 | smp_call_function_many(mask, arch_dump_stack, NULL, 1); | |
639 | ||
640 | put_cpu(); | |
856839b7 | 641 | } |
9791554b PB |
642 | |
643 | int mips_get_process_fp_mode(struct task_struct *task) | |
644 | { | |
645 | int value = 0; | |
646 | ||
647 | if (!test_tsk_thread_flag(task, TIF_32BIT_FPREGS)) | |
648 | value |= PR_FP_MODE_FR; | |
649 | if (test_tsk_thread_flag(task, TIF_HYBRID_FPREGS)) | |
650 | value |= PR_FP_MODE_FRE; | |
651 | ||
652 | return value; | |
653 | } | |
654 | ||
6b832257 PB |
655 | static void prepare_for_fp_mode_switch(void *info) |
656 | { | |
657 | struct mm_struct *mm = info; | |
658 | ||
659 | if (current->mm == mm) | |
660 | lose_fpu(1); | |
661 | } | |
662 | ||
9791554b PB |
663 | int mips_set_process_fp_mode(struct task_struct *task, unsigned int value) |
664 | { | |
665 | const unsigned int known_bits = PR_FP_MODE_FR | PR_FP_MODE_FRE; | |
9791554b | 666 | struct task_struct *t; |
6b832257 | 667 | int max_users; |
9791554b PB |
668 | |
669 | /* Check the value is valid */ | |
670 | if (value & ~known_bits) | |
671 | return -EOPNOTSUPP; | |
672 | ||
673 | /* Avoid inadvertently triggering emulation */ | |
b244614a MN |
674 | if ((value & PR_FP_MODE_FR) && raw_cpu_has_fpu && |
675 | !(raw_current_cpu_data.fpu_id & MIPS_FPIR_F64)) | |
9791554b | 676 | return -EOPNOTSUPP; |
b244614a | 677 | if ((value & PR_FP_MODE_FRE) && raw_cpu_has_fpu && !cpu_has_fre) |
9791554b PB |
678 | return -EOPNOTSUPP; |
679 | ||
13e45f09 | 680 | /* FR = 0 not supported in MIPS R6 */ |
b244614a | 681 | if (!(value & PR_FP_MODE_FR) && raw_cpu_has_fpu && cpu_has_mips_r6) |
13e45f09 MC |
682 | return -EOPNOTSUPP; |
683 | ||
bd239f1e PB |
684 | /* Proceed with the mode switch */ |
685 | preempt_disable(); | |
686 | ||
9791554b PB |
687 | /* Save FP & vector context, then disable FPU & MSA */ |
688 | if (task->signal == current->signal) | |
689 | lose_fpu(1); | |
690 | ||
691 | /* Prevent any threads from obtaining live FP context */ | |
692 | atomic_set(&task->mm->context.fp_mode_switching, 1); | |
693 | smp_mb__after_atomic(); | |
694 | ||
695 | /* | |
6b832257 PB |
696 | * If there are multiple online CPUs then force any which are running |
697 | * threads in this process to lose their FPU context, which they can't | |
698 | * regain until fp_mode_switching is cleared later. | |
9791554b PB |
699 | */ |
700 | if (num_online_cpus() > 1) { | |
6b832257 PB |
701 | /* No need to send an IPI for the local CPU */ |
702 | max_users = (task->mm == current->mm) ? 1 : 0; | |
9791554b | 703 | |
6b832257 PB |
704 | if (atomic_read(¤t->mm->mm_users) > max_users) |
705 | smp_call_function(prepare_for_fp_mode_switch, | |
706 | (void *)current->mm, 1); | |
9791554b PB |
707 | } |
708 | ||
709 | /* | |
710 | * There are now no threads of the process with live FP context, so it | |
711 | * is safe to proceed with the FP mode switch. | |
712 | */ | |
713 | for_each_thread(task, t) { | |
714 | /* Update desired FP register width */ | |
715 | if (value & PR_FP_MODE_FR) { | |
716 | clear_tsk_thread_flag(t, TIF_32BIT_FPREGS); | |
717 | } else { | |
718 | set_tsk_thread_flag(t, TIF_32BIT_FPREGS); | |
719 | clear_tsk_thread_flag(t, TIF_MSA_CTX_LIVE); | |
720 | } | |
721 | ||
722 | /* Update desired FP single layout */ | |
723 | if (value & PR_FP_MODE_FRE) | |
724 | set_tsk_thread_flag(t, TIF_HYBRID_FPREGS); | |
725 | else | |
726 | clear_tsk_thread_flag(t, TIF_HYBRID_FPREGS); | |
727 | } | |
728 | ||
729 | /* Allow threads to use FP again */ | |
730 | atomic_set(&task->mm->context.fp_mode_switching, 0); | |
bd239f1e | 731 | preempt_enable(); |
9791554b PB |
732 | |
733 | return 0; | |
734 | } | |
08c941bf MN |
735 | |
736 | #if defined(CONFIG_32BIT) || defined(CONFIG_MIPS32_O32) | |
737 | void mips_dump_regs32(u32 *uregs, const struct pt_regs *regs) | |
738 | { | |
739 | unsigned int i; | |
740 | ||
741 | for (i = MIPS32_EF_R1; i <= MIPS32_EF_R31; i++) { | |
742 | /* k0/k1 are copied as zero. */ | |
743 | if (i == MIPS32_EF_R26 || i == MIPS32_EF_R27) | |
744 | uregs[i] = 0; | |
745 | else | |
746 | uregs[i] = regs->regs[i - MIPS32_EF_R0]; | |
747 | } | |
748 | ||
749 | uregs[MIPS32_EF_LO] = regs->lo; | |
750 | uregs[MIPS32_EF_HI] = regs->hi; | |
751 | uregs[MIPS32_EF_CP0_EPC] = regs->cp0_epc; | |
752 | uregs[MIPS32_EF_CP0_BADVADDR] = regs->cp0_badvaddr; | |
753 | uregs[MIPS32_EF_CP0_STATUS] = regs->cp0_status; | |
754 | uregs[MIPS32_EF_CP0_CAUSE] = regs->cp0_cause; | |
755 | } | |
756 | #endif /* CONFIG_32BIT || CONFIG_MIPS32_O32 */ | |
757 | ||
758 | #ifdef CONFIG_64BIT | |
759 | void mips_dump_regs64(u64 *uregs, const struct pt_regs *regs) | |
760 | { | |
761 | unsigned int i; | |
762 | ||
763 | for (i = MIPS64_EF_R1; i <= MIPS64_EF_R31; i++) { | |
764 | /* k0/k1 are copied as zero. */ | |
765 | if (i == MIPS64_EF_R26 || i == MIPS64_EF_R27) | |
766 | uregs[i] = 0; | |
767 | else | |
768 | uregs[i] = regs->regs[i - MIPS64_EF_R0]; | |
769 | } | |
770 | ||
771 | uregs[MIPS64_EF_LO] = regs->lo; | |
772 | uregs[MIPS64_EF_HI] = regs->hi; | |
773 | uregs[MIPS64_EF_CP0_EPC] = regs->cp0_epc; | |
774 | uregs[MIPS64_EF_CP0_BADVADDR] = regs->cp0_badvaddr; | |
775 | uregs[MIPS64_EF_CP0_STATUS] = regs->cp0_status; | |
776 | uregs[MIPS64_EF_CP0_CAUSE] = regs->cp0_cause; | |
777 | } | |
778 | #endif /* CONFIG_64BIT */ |