Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 1994 - 1999, 2000 by Ralf Baechle and others. | |
40ac5d47 | 7 | * Copyright (C) 2005, 2006 by Ralf Baechle (ralf@linux-mips.org) |
1da177e4 LT |
8 | * Copyright (C) 1999, 2000 Silicon Graphics, Inc. |
9 | * Copyright (C) 2004 Thiemo Seufer | |
34c2f668 | 10 | * Copyright (C) 2013 Imagination Technologies Ltd. |
1da177e4 | 11 | */ |
1da177e4 | 12 | #include <linux/errno.h> |
1da177e4 | 13 | #include <linux/sched.h> |
b17b0153 | 14 | #include <linux/sched/debug.h> |
29930025 | 15 | #include <linux/sched/task.h> |
68db0cf1 | 16 | #include <linux/sched/task_stack.h> |
7bcf7717 | 17 | #include <linux/tick.h> |
1da177e4 LT |
18 | #include <linux/kernel.h> |
19 | #include <linux/mm.h> | |
20 | #include <linux/stddef.h> | |
21 | #include <linux/unistd.h> | |
cae39d13 | 22 | #include <linux/export.h> |
1da177e4 | 23 | #include <linux/ptrace.h> |
1da177e4 LT |
24 | #include <linux/mman.h> |
25 | #include <linux/personality.h> | |
26 | #include <linux/sys.h> | |
1da177e4 LT |
27 | #include <linux/init.h> |
28 | #include <linux/completion.h> | |
63077519 | 29 | #include <linux/kallsyms.h> |
94109102 | 30 | #include <linux/random.h> |
9791554b | 31 | #include <linux/prctl.h> |
b63e132b | 32 | #include <linux/nmi.h> |
8c8d953c | 33 | #include <linux/cpu.h> |
1da177e4 | 34 | |
ea7e0480 | 35 | #include <asm/abi.h> |
94109102 | 36 | #include <asm/asm.h> |
1da177e4 LT |
37 | #include <asm/bootinfo.h> |
38 | #include <asm/cpu.h> | |
432c6bac | 39 | #include <asm/dsemul.h> |
e50c0a8f | 40 | #include <asm/dsp.h> |
1da177e4 | 41 | #include <asm/fpu.h> |
d42d8d10 | 42 | #include <asm/irq.h> |
ea7e0480 | 43 | #include <asm/mips-cps.h> |
1db1af84 | 44 | #include <asm/msa.h> |
1da177e4 LT |
45 | #include <asm/mipsregs.h> |
46 | #include <asm/processor.h> | |
60be939c | 47 | #include <asm/reg.h> |
7c0f6ba6 | 48 | #include <linux/uaccess.h> |
1da177e4 LT |
49 | #include <asm/io.h> |
50 | #include <asm/elf.h> | |
51 | #include <asm/isadep.h> | |
52 | #include <asm/inst.h> | |
1df0f0ff | 53 | #include <asm/stacktrace.h> |
856839b7 | 54 | #include <asm/irq_regs.h> |
047248ca | 55 | #include <asm/exec.h> |
1da177e4 | 56 | |
cdbedc61 TG |
57 | #ifdef CONFIG_HOTPLUG_CPU |
58 | void arch_cpu_idle_dead(void) | |
1da177e4 | 59 | { |
a00eeede | 60 | play_dead(); |
cdbedc61 TG |
61 | } |
62 | #endif | |
1b2bc75c | 63 | |
1da177e4 | 64 | asmlinkage void ret_from_fork(void); |
8f54bcac | 65 | asmlinkage void ret_from_kernel_thread(void); |
1da177e4 LT |
66 | |
67 | void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp) | |
68 | { | |
69 | unsigned long status; | |
70 | ||
71 | /* New thread loses kernel privileges. */ | |
195615ec | 72 | status = regs->cp0_status & ~(ST0_CU0|ST0_CU1|ST0_CU2|ST0_FR|KU_MASK); |
1da177e4 LT |
73 | status |= KU_USER; |
74 | regs->cp0_status = status; | |
76e5846d JH |
75 | lose_fpu(0); |
76 | clear_thread_flag(TIF_MSA_CTX_LIVE); | |
1da177e4 | 77 | clear_used_math(); |
aebdc6ff | 78 | #ifdef CONFIG_MIPS_FP_SUPPORT |
432c6bac | 79 | atomic_set(¤t->thread.bd_emu_frame, BD_EMUFRAME_NONE); |
aebdc6ff | 80 | #endif |
a3056b1c | 81 | init_dsp(); |
1da177e4 LT |
82 | regs->cp0_epc = pc; |
83 | regs->regs[29] = sp; | |
1da177e4 LT |
84 | } |
85 | ||
432c6bac PB |
86 | void exit_thread(struct task_struct *tsk) |
87 | { | |
88 | /* | |
89 | * User threads may have allocated a delay slot emulation frame. | |
90 | * If so, clean up that allocation. | |
91 | */ | |
92 | if (!(current->flags & PF_KTHREAD)) | |
93 | dsemul_thread_cleanup(tsk); | |
94 | } | |
95 | ||
39148e94 JH |
96 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) |
97 | { | |
98 | /* | |
99 | * Save any process state which is live in hardware registers to the | |
100 | * parent context prior to duplication. This prevents the new child | |
101 | * state becoming stale if the parent is preempted before copy_thread() | |
102 | * gets a chance to save the parent's live hardware registers to the | |
103 | * child context. | |
104 | */ | |
105 | preempt_disable(); | |
106 | ||
107 | if (is_msa_enabled()) | |
108 | save_msa(current); | |
109 | else if (is_fpu_owner()) | |
110 | _save_fp(current); | |
111 | ||
112 | save_dsp(current); | |
113 | ||
114 | preempt_enable(); | |
115 | ||
116 | *dst = *src; | |
117 | return 0; | |
118 | } | |
119 | ||
e2c5aaa5 AD |
120 | /* |
121 | * Copy architecture-specific thread state | |
122 | */ | |
714acdbd CB |
123 | int copy_thread(unsigned long clone_flags, unsigned long usp, |
124 | unsigned long kthread_arg, struct task_struct *p, | |
125 | unsigned long tls) | |
1da177e4 | 126 | { |
75bb07e7 | 127 | struct thread_info *ti = task_thread_info(p); |
afa86fc4 | 128 | struct pt_regs *childregs, *regs = current_pt_regs(); |
484889fc | 129 | unsigned long childksp; |
1da177e4 | 130 | |
75bb07e7 | 131 | childksp = (unsigned long)task_stack_page(p) + THREAD_SIZE - 32; |
1da177e4 | 132 | |
1da177e4 LT |
133 | /* set up new TSS. */ |
134 | childregs = (struct pt_regs *) childksp - 1; | |
484889fc DD |
135 | /* Put the stack after the struct pt_regs. */ |
136 | childksp = (unsigned long) childregs; | |
195615ec | 137 | p->thread.cp0_status = (read_c0_status() & ~(ST0_CU2|ST0_CU1)) | ST0_KERNEL_CUMASK; |
8f54bcac | 138 | if (unlikely(p->flags & PF_KTHREAD)) { |
e2c5aaa5 | 139 | /* kernel thread */ |
8f54bcac AV |
140 | unsigned long status = p->thread.cp0_status; |
141 | memset(childregs, 0, sizeof(struct pt_regs)); | |
142 | ti->addr_limit = KERNEL_DS; | |
143 | p->thread.reg16 = usp; /* fn */ | |
e2c5aaa5 | 144 | p->thread.reg17 = kthread_arg; |
8f54bcac AV |
145 | p->thread.reg29 = childksp; |
146 | p->thread.reg31 = (unsigned long) ret_from_kernel_thread; | |
147 | #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) | |
148 | status = (status & ~(ST0_KUP | ST0_IEP | ST0_IEC)) | | |
149 | ((status & (ST0_KUC | ST0_IEC)) << 2); | |
150 | #else | |
151 | status |= ST0_EXL; | |
152 | #endif | |
153 | childregs->cp0_status = status; | |
154 | return 0; | |
155 | } | |
e2c5aaa5 AD |
156 | |
157 | /* user thread */ | |
1da177e4 | 158 | *childregs = *regs; |
70342287 RB |
159 | childregs->regs[7] = 0; /* Clear error flag */ |
160 | childregs->regs[2] = 0; /* Child gets zero as return value */ | |
64b3122d AV |
161 | if (usp) |
162 | childregs->regs[29] = usp; | |
8f54bcac | 163 | ti->addr_limit = USER_DS; |
1da177e4 | 164 | |
1da177e4 LT |
165 | p->thread.reg29 = (unsigned long) childregs; |
166 | p->thread.reg31 = (unsigned long) ret_from_fork; | |
167 | ||
168 | /* | |
169 | * New tasks lose permission to use the fpu. This accelerates context | |
170 | * switching for most programs since they don't use the fpu. | |
171 | */ | |
1da177e4 | 172 | childregs->cp0_status &= ~(ST0_CU2|ST0_CU1); |
1da177e4 | 173 | |
1da177e4 | 174 | clear_tsk_thread_flag(p, TIF_USEDFPU); |
7daef8f2 PB |
175 | clear_tsk_thread_flag(p, TIF_USEDMSA); |
176 | clear_tsk_thread_flag(p, TIF_MSA_CTX_LIVE); | |
1da177e4 | 177 | |
f088fc84 | 178 | #ifdef CONFIG_MIPS_MT_FPAFF |
6657fe0a | 179 | clear_tsk_thread_flag(p, TIF_FPUBOUND); |
f088fc84 RB |
180 | #endif /* CONFIG_MIPS_MT_FPAFF */ |
181 | ||
aebdc6ff | 182 | #ifdef CONFIG_MIPS_FP_SUPPORT |
432c6bac | 183 | atomic_set(&p->thread.bd_emu_frame, BD_EMUFRAME_NONE); |
aebdc6ff | 184 | #endif |
432c6bac | 185 | |
3c37026d | 186 | if (clone_flags & CLONE_SETTLS) |
f9c4e3a6 | 187 | ti->tp_value = tls; |
3c37026d | 188 | |
1da177e4 LT |
189 | return 0; |
190 | } | |
191 | ||
050e9baa | 192 | #ifdef CONFIG_STACKPROTECTOR |
36ecafc5 GF |
193 | #include <linux/stackprotector.h> |
194 | unsigned long __stack_chk_guard __read_mostly; | |
195 | EXPORT_SYMBOL(__stack_chk_guard); | |
196 | #endif | |
197 | ||
b5943182 FBH |
198 | struct mips_frame_info { |
199 | void *func; | |
200 | unsigned long func_size; | |
201 | int frame_size; | |
202 | int pc_offset; | |
203 | }; | |
dc953df1 | 204 | |
5000653e TW |
205 | #define J_TARGET(pc,target) \ |
206 | (((unsigned long)(pc) & 0xf0000000) | ((target) << 2)) | |
207 | ||
bb9bc468 | 208 | static inline int is_ra_save_ins(union mips_instruction *ip, int *poff) |
c0efbb6d | 209 | { |
34c2f668 | 210 | #ifdef CONFIG_CPU_MICROMIPS |
34c2f668 LY |
211 | /* |
212 | * swsp ra,offset | |
213 | * swm16 reglist,offset(sp) | |
214 | * swm32 reglist,offset(sp) | |
215 | * sw32 ra,offset(sp) | |
216 | * jradiussp - NOT SUPPORTED | |
217 | * | |
218 | * microMIPS is way more fun... | |
219 | */ | |
41885b02 | 220 | if (mm_insn_16bit(ip->word >> 16)) { |
bb9bc468 PB |
221 | switch (ip->mm16_r5_format.opcode) { |
222 | case mm_swsp16_op: | |
223 | if (ip->mm16_r5_format.rt != 31) | |
224 | return 0; | |
225 | ||
cea8cd49 | 226 | *poff = ip->mm16_r5_format.imm; |
bb9bc468 PB |
227 | *poff = (*poff << 2) / sizeof(ulong); |
228 | return 1; | |
229 | ||
230 | case mm_pool16c_op: | |
231 | switch (ip->mm16_m_format.func) { | |
232 | case mm_swm16_op: | |
233 | *poff = ip->mm16_m_format.imm; | |
234 | *poff += 1 + ip->mm16_m_format.rlist; | |
235 | *poff = (*poff << 2) / sizeof(ulong); | |
236 | return 1; | |
237 | ||
238 | default: | |
239 | return 0; | |
240 | } | |
241 | ||
242 | default: | |
243 | return 0; | |
244 | } | |
34c2f668 | 245 | } |
bb9bc468 PB |
246 | |
247 | switch (ip->i_format.opcode) { | |
248 | case mm_sw32_op: | |
249 | if (ip->i_format.rs != 29) | |
250 | return 0; | |
251 | if (ip->i_format.rt != 31) | |
252 | return 0; | |
253 | ||
254 | *poff = ip->i_format.simmediate / sizeof(ulong); | |
255 | return 1; | |
256 | ||
257 | case mm_pool32b_op: | |
258 | switch (ip->mm_m_format.func) { | |
259 | case mm_swm32_func: | |
260 | if (ip->mm_m_format.rd < 0x10) | |
261 | return 0; | |
262 | if (ip->mm_m_format.base != 29) | |
263 | return 0; | |
264 | ||
265 | *poff = ip->mm_m_format.simmediate; | |
266 | *poff += (ip->mm_m_format.rd & 0xf) * sizeof(u32); | |
267 | *poff /= sizeof(ulong); | |
268 | return 1; | |
269 | default: | |
270 | return 0; | |
271 | } | |
272 | ||
273 | default: | |
274 | return 0; | |
34c2f668 LY |
275 | } |
276 | #else | |
c0efbb6d | 277 | /* sw / sd $ra, offset($sp) */ |
bb9bc468 PB |
278 | if ((ip->i_format.opcode == sw_op || ip->i_format.opcode == sd_op) && |
279 | ip->i_format.rs == 29 && ip->i_format.rt == 31) { | |
280 | *poff = ip->i_format.simmediate / sizeof(ulong); | |
281 | return 1; | |
282 | } | |
bc1c969f HC |
283 | #ifdef CONFIG_CPU_LOONGSON64 |
284 | if ((ip->loongson3_lswc2_format.opcode == swc2_op) && | |
285 | (ip->loongson3_lswc2_format.ls == 1) && | |
286 | (ip->loongson3_lswc2_format.fr == 0) && | |
287 | (ip->loongson3_lswc2_format.base == 29)) { | |
288 | if (ip->loongson3_lswc2_format.rt == 31) { | |
289 | *poff = ip->loongson3_lswc2_format.offset << 1; | |
290 | return 1; | |
291 | } | |
292 | if (ip->loongson3_lswc2_format.rq == 31) { | |
293 | *poff = (ip->loongson3_lswc2_format.offset << 1) + 1; | |
294 | return 1; | |
295 | } | |
296 | } | |
297 | #endif | |
bb9bc468 | 298 | return 0; |
34c2f668 | 299 | #endif |
c0efbb6d FBH |
300 | } |
301 | ||
e7438c4b | 302 | static inline int is_jump_ins(union mips_instruction *ip) |
c0efbb6d | 303 | { |
34c2f668 LY |
304 | #ifdef CONFIG_CPU_MICROMIPS |
305 | /* | |
306 | * jr16,jrc,jalr16,jalr16 | |
307 | * jal | |
308 | * jalr/jr,jalr.hb/jr.hb,jalrs,jalrs.hb | |
309 | * jraddiusp - NOT SUPPORTED | |
310 | * | |
311 | * microMIPS is kind of more fun... | |
312 | */ | |
41885b02 | 313 | if (mm_insn_16bit(ip->word >> 16)) { |
67c75057 PB |
314 | if ((ip->mm16_r5_format.opcode == mm_pool16c_op && |
315 | (ip->mm16_r5_format.rt & mm_jr16_op) == mm_jr16_op)) | |
316 | return 1; | |
317 | return 0; | |
318 | } | |
319 | ||
096a0de4 PB |
320 | if (ip->j_format.opcode == mm_j32_op) |
321 | return 1; | |
67c75057 | 322 | if (ip->j_format.opcode == mm_jal32_op) |
34c2f668 LY |
323 | return 1; |
324 | if (ip->r_format.opcode != mm_pool32a_op || | |
325 | ip->r_format.func != mm_pool32axf_op) | |
326 | return 0; | |
635c9907 | 327 | return ((ip->u_format.uimmediate >> 6) & mm_jalr_op) == mm_jalr_op; |
34c2f668 | 328 | #else |
e7438c4b TW |
329 | if (ip->j_format.opcode == j_op) |
330 | return 1; | |
c0efbb6d FBH |
331 | if (ip->j_format.opcode == jal_op) |
332 | return 1; | |
333 | if (ip->r_format.opcode != spec_op) | |
334 | return 0; | |
335 | return ip->r_format.func == jalr_op || ip->r_format.func == jr_op; | |
34c2f668 | 336 | #endif |
c0efbb6d FBH |
337 | } |
338 | ||
56dfb700 | 339 | static inline int is_sp_move_ins(union mips_instruction *ip, int *frame_size) |
c0efbb6d | 340 | { |
34c2f668 | 341 | #ifdef CONFIG_CPU_MICROMIPS |
56dfb700 MR |
342 | unsigned short tmp; |
343 | ||
34c2f668 LY |
344 | /* |
345 | * addiusp -imm | |
346 | * addius5 sp,-imm | |
347 | * addiu32 sp,sp,-imm | |
348 | * jradiussp - NOT SUPPORTED | |
349 | * | |
350 | * microMIPS is not more fun... | |
351 | */ | |
41885b02 | 352 | if (mm_insn_16bit(ip->word >> 16)) { |
56dfb700 MR |
353 | if (ip->mm16_r3_format.opcode == mm_pool16d_op && |
354 | ip->mm16_r3_format.simmediate & mm_addiusp_func) { | |
355 | tmp = ip->mm_b0_format.simmediate >> 1; | |
356 | tmp = ((tmp & 0x1ff) ^ 0x100) - 0x100; | |
357 | if ((tmp + 2) < 4) /* 0x0,0x1,0x1fe,0x1ff are special */ | |
358 | tmp ^= 0x100; | |
359 | *frame_size = -(signed short)(tmp << 2); | |
360 | return 1; | |
361 | } | |
362 | if (ip->mm16_r5_format.opcode == mm_pool16d_op && | |
363 | ip->mm16_r5_format.rt == 29) { | |
364 | tmp = ip->mm16_r5_format.imm >> 1; | |
365 | *frame_size = -(signed short)(tmp & 0xf); | |
366 | return 1; | |
367 | } | |
368 | return 0; | |
34c2f668 | 369 | } |
a3552dac | 370 | |
56dfb700 MR |
371 | if (ip->mm_i_format.opcode == mm_addiu32_op && |
372 | ip->mm_i_format.rt == 29 && ip->mm_i_format.rs == 29) { | |
373 | *frame_size = -ip->i_format.simmediate; | |
374 | return 1; | |
375 | } | |
34c2f668 | 376 | #else |
c0efbb6d FBH |
377 | /* addiu/daddiu sp,sp,-imm */ |
378 | if (ip->i_format.rs != 29 || ip->i_format.rt != 29) | |
379 | return 0; | |
56dfb700 MR |
380 | |
381 | if (ip->i_format.opcode == addiu_op || | |
382 | ip->i_format.opcode == daddiu_op) { | |
383 | *frame_size = -ip->i_format.simmediate; | |
c0efbb6d | 384 | return 1; |
56dfb700 | 385 | } |
34c2f668 | 386 | #endif |
c0efbb6d FBH |
387 | return 0; |
388 | } | |
389 | ||
f66686f7 | 390 | static int get_frame_info(struct mips_frame_info *info) |
1da177e4 | 391 | { |
a3552dac | 392 | bool is_mmips = IS_ENABLED(CONFIG_CPU_MICROMIPS); |
2b424cfc | 393 | union mips_instruction insn, *ip; |
b6c7a324 | 394 | const unsigned int max_insns = 128; |
11887ed1 | 395 | unsigned int last_insn_size = 0; |
b6c7a324 | 396 | unsigned int i; |
aee16625 | 397 | bool saw_jump = false; |
c0efbb6d | 398 | |
1da177e4 | 399 | info->pc_offset = -1; |
63077519 | 400 | info->frame_size = 0; |
1da177e4 | 401 | |
ccaf7caf | 402 | ip = (void *)msk_isa16_mode((ulong)info->func); |
29b376ff FBH |
403 | if (!ip) |
404 | goto err; | |
405 | ||
2b424cfc | 406 | for (i = 0; i < max_insns; i++) { |
11887ed1 | 407 | ip = (void *)ip + last_insn_size; |
2b424cfc | 408 | |
a3552dac | 409 | if (is_mmips && mm_insn_16bit(ip->halfword[0])) { |
41885b02 | 410 | insn.word = ip->halfword[0] << 16; |
11887ed1 | 411 | last_insn_size = 2; |
a3552dac | 412 | } else if (is_mmips) { |
41885b02 | 413 | insn.word = ip->halfword[0] << 16 | ip->halfword[1]; |
11887ed1 | 414 | last_insn_size = 4; |
a3552dac PB |
415 | } else { |
416 | insn.word = ip->word; | |
11887ed1 | 417 | last_insn_size = 4; |
a3552dac | 418 | } |
c0efbb6d | 419 | |
0cceb4aa | 420 | if (!info->frame_size) { |
56dfb700 | 421 | is_sp_move_ins(&insn, &info->frame_size); |
0cceb4aa | 422 | continue; |
aee16625 CM |
423 | } else if (!saw_jump && is_jump_ins(ip)) { |
424 | /* | |
425 | * If we see a jump instruction, we are finished | |
426 | * with the frame save. | |
427 | * | |
428 | * Some functions can have a shortcut return at | |
429 | * the beginning of the function, so don't start | |
430 | * looking for jump instruction until we see the | |
431 | * frame setup. | |
432 | * | |
433 | * The RA save instruction can get put into the | |
434 | * delay slot of the jump instruction, so look | |
435 | * at the next instruction, too. | |
436 | */ | |
437 | saw_jump = true; | |
438 | continue; | |
63077519 | 439 | } |
bb9bc468 PB |
440 | if (info->pc_offset == -1 && |
441 | is_ra_save_ins(&insn, &info->pc_offset)) | |
0cceb4aa | 442 | break; |
aee16625 CM |
443 | if (saw_jump) |
444 | break; | |
1da177e4 | 445 | } |
f66686f7 AN |
446 | if (info->frame_size && info->pc_offset >= 0) /* nested */ |
447 | return 0; | |
448 | if (info->pc_offset < 0) /* leaf */ | |
449 | return 1; | |
a90c59e6 | 450 | /* prologue seems bogus... */ |
29b376ff | 451 | err: |
f66686f7 | 452 | return -1; |
1da177e4 LT |
453 | } |
454 | ||
b5943182 FBH |
455 | static struct mips_frame_info schedule_mfi __read_mostly; |
456 | ||
5000653e TW |
457 | #ifdef CONFIG_KALLSYMS |
458 | static unsigned long get___schedule_addr(void) | |
459 | { | |
460 | return kallsyms_lookup_name("__schedule"); | |
461 | } | |
462 | #else | |
463 | static unsigned long get___schedule_addr(void) | |
464 | { | |
465 | union mips_instruction *ip = (void *)schedule; | |
466 | int max_insns = 8; | |
467 | int i; | |
468 | ||
469 | for (i = 0; i < max_insns; i++, ip++) { | |
470 | if (ip->j_format.opcode == j_op) | |
471 | return J_TARGET(ip, ip->j_format.target); | |
472 | } | |
473 | return 0; | |
474 | } | |
475 | #endif | |
476 | ||
1da177e4 LT |
477 | static int __init frame_info_init(void) |
478 | { | |
b5943182 | 479 | unsigned long size = 0; |
63077519 | 480 | #ifdef CONFIG_KALLSYMS |
b5943182 | 481 | unsigned long ofs; |
5000653e TW |
482 | #endif |
483 | unsigned long addr; | |
b5943182 | 484 | |
5000653e TW |
485 | addr = get___schedule_addr(); |
486 | if (!addr) | |
487 | addr = (unsigned long)schedule; | |
488 | ||
489 | #ifdef CONFIG_KALLSYMS | |
490 | kallsyms_lookup_size_offset(addr, &size, &ofs); | |
63077519 | 491 | #endif |
5000653e | 492 | schedule_mfi.func = (void *)addr; |
b5943182 FBH |
493 | schedule_mfi.func_size = size; |
494 | ||
495 | get_frame_info(&schedule_mfi); | |
6057a798 FBH |
496 | |
497 | /* | |
498 | * Without schedule() frame info, result given by | |
499 | * thread_saved_pc() and get_wchan() are not reliable. | |
500 | */ | |
b5943182 | 501 | if (schedule_mfi.pc_offset < 0) |
6057a798 | 502 | printk("Can't analyze schedule() prologue at %p\n", schedule); |
63077519 | 503 | |
1da177e4 LT |
504 | return 0; |
505 | } | |
506 | ||
507 | arch_initcall(frame_info_init); | |
508 | ||
509 | /* | |
510 | * Return saved PC of a blocked thread. | |
511 | */ | |
508c5757 | 512 | static unsigned long thread_saved_pc(struct task_struct *tsk) |
1da177e4 LT |
513 | { |
514 | struct thread_struct *t = &tsk->thread; | |
515 | ||
516 | /* New born processes are a special case */ | |
517 | if (t->reg31 == (unsigned long) ret_from_fork) | |
518 | return t->reg31; | |
b5943182 | 519 | if (schedule_mfi.pc_offset < 0) |
1da177e4 | 520 | return 0; |
b5943182 | 521 | return ((unsigned long *)t->reg29)[schedule_mfi.pc_offset]; |
1da177e4 LT |
522 | } |
523 | ||
1da177e4 | 524 | |
f66686f7 | 525 | #ifdef CONFIG_KALLSYMS |
94ea09c6 DK |
526 | /* generic stack unwinding function */ |
527 | unsigned long notrace unwind_stack_by_address(unsigned long stack_page, | |
528 | unsigned long *sp, | |
529 | unsigned long pc, | |
530 | unsigned long *ra) | |
f66686f7 | 531 | { |
db8466c5 | 532 | unsigned long low, high, irq_stack_high; |
f66686f7 | 533 | struct mips_frame_info info; |
f66686f7 | 534 | unsigned long size, ofs; |
db8466c5 | 535 | struct pt_regs *regs; |
4d157d5e | 536 | int leaf; |
f66686f7 | 537 | |
f66686f7 AN |
538 | if (!stack_page) |
539 | return 0; | |
540 | ||
1924600c | 541 | /* |
db8466c5 MR |
542 | * IRQ stacks start at IRQ_STACK_START |
543 | * task stacks at THREAD_SIZE - 32 | |
1924600c | 544 | */ |
db8466c5 MR |
545 | low = stack_page; |
546 | if (!preemptible() && on_irq_stack(raw_smp_processor_id(), *sp)) { | |
547 | high = stack_page + IRQ_STACK_START; | |
548 | irq_stack_high = high; | |
549 | } else { | |
550 | high = stack_page + THREAD_SIZE - 32; | |
551 | irq_stack_high = 0; | |
552 | } | |
553 | ||
554 | /* | |
555 | * If we reached the top of the interrupt stack, start unwinding | |
556 | * the interrupted task stack. | |
557 | */ | |
558 | if (unlikely(*sp == irq_stack_high)) { | |
559 | unsigned long task_sp = *(unsigned long *)*sp; | |
560 | ||
561 | /* | |
562 | * Check that the pointer saved in the IRQ stack head points to | |
563 | * something within the stack of the current task | |
564 | */ | |
565 | if (!object_is_on_stack((void *)task_sp)) | |
566 | return 0; | |
567 | ||
568 | /* | |
569 | * Follow pointer to tasks kernel stack frame where interrupted | |
570 | * state was saved. | |
571 | */ | |
572 | regs = (struct pt_regs *)task_sp; | |
573 | pc = regs->cp0_epc; | |
574 | if (!user_mode(regs) && __kernel_text_address(pc)) { | |
575 | *sp = regs->regs[29]; | |
576 | *ra = regs->regs[31]; | |
577 | return pc; | |
1924600c AN |
578 | } |
579 | return 0; | |
580 | } | |
55b74283 | 581 | if (!kallsyms_lookup_size_offset(pc, &size, &ofs)) |
f66686f7 | 582 | return 0; |
1fd69098 | 583 | /* |
25985edc | 584 | * Return ra if an exception occurred at the first instruction |
1fd69098 | 585 | */ |
1924600c AN |
586 | if (unlikely(ofs == 0)) { |
587 | pc = *ra; | |
588 | *ra = 0; | |
589 | return pc; | |
590 | } | |
f66686f7 AN |
591 | |
592 | info.func = (void *)(pc - ofs); | |
593 | info.func_size = ofs; /* analyze from start to ofs */ | |
4d157d5e FBH |
594 | leaf = get_frame_info(&info); |
595 | if (leaf < 0) | |
f66686f7 | 596 | return 0; |
4d157d5e | 597 | |
db8466c5 | 598 | if (*sp < low || *sp + info.frame_size > high) |
f66686f7 AN |
599 | return 0; |
600 | ||
4d157d5e FBH |
601 | if (leaf) |
602 | /* | |
603 | * For some extreme cases, get_frame_info() can | |
604 | * consider wrongly a nested function as a leaf | |
605 | * one. In that cases avoid to return always the | |
606 | * same value. | |
607 | */ | |
1924600c | 608 | pc = pc != *ra ? *ra : 0; |
4d157d5e FBH |
609 | else |
610 | pc = ((unsigned long *)(*sp))[info.pc_offset]; | |
611 | ||
612 | *sp += info.frame_size; | |
1924600c | 613 | *ra = 0; |
4d157d5e | 614 | return __kernel_text_address(pc) ? pc : 0; |
f66686f7 | 615 | } |
94ea09c6 DK |
616 | EXPORT_SYMBOL(unwind_stack_by_address); |
617 | ||
618 | /* used by show_backtrace() */ | |
619 | unsigned long unwind_stack(struct task_struct *task, unsigned long *sp, | |
620 | unsigned long pc, unsigned long *ra) | |
621 | { | |
d42d8d10 MR |
622 | unsigned long stack_page = 0; |
623 | int cpu; | |
624 | ||
625 | for_each_possible_cpu(cpu) { | |
626 | if (on_irq_stack(cpu, *sp)) { | |
627 | stack_page = (unsigned long)irq_stack[cpu]; | |
628 | break; | |
629 | } | |
630 | } | |
631 | ||
632 | if (!stack_page) | |
633 | stack_page = (unsigned long)task_stack_page(task); | |
634 | ||
94ea09c6 DK |
635 | return unwind_stack_by_address(stack_page, sp, pc, ra); |
636 | } | |
f66686f7 | 637 | #endif |
b5943182 FBH |
638 | |
639 | /* | |
640 | * get_wchan - a maintenance nightmare^W^Wpain in the ass ... | |
641 | */ | |
642 | unsigned long get_wchan(struct task_struct *task) | |
643 | { | |
644 | unsigned long pc = 0; | |
645 | #ifdef CONFIG_KALLSYMS | |
646 | unsigned long sp; | |
1924600c | 647 | unsigned long ra = 0; |
b5943182 FBH |
648 | #endif |
649 | ||
650 | if (!task || task == current || task->state == TASK_RUNNING) | |
651 | goto out; | |
652 | if (!task_stack_page(task)) | |
653 | goto out; | |
654 | ||
655 | pc = thread_saved_pc(task); | |
656 | ||
657 | #ifdef CONFIG_KALLSYMS | |
658 | sp = task->thread.reg29 + schedule_mfi.frame_size; | |
659 | ||
660 | while (in_sched_functions(pc)) | |
1924600c | 661 | pc = unwind_stack(task, &sp, pc, &ra); |
b5943182 FBH |
662 | #endif |
663 | ||
664 | out: | |
665 | return pc; | |
666 | } | |
94109102 | 667 | |
ea7e0480 PB |
668 | unsigned long mips_stack_top(void) |
669 | { | |
670 | unsigned long top = TASK_SIZE & PAGE_MASK; | |
671 | ||
aebdc6ff YZ |
672 | if (IS_ENABLED(CONFIG_MIPS_FP_SUPPORT)) { |
673 | /* One page for branch delay slot "emulation" */ | |
674 | top -= PAGE_SIZE; | |
675 | } | |
ea7e0480 PB |
676 | |
677 | /* Space for the VDSO, data page & GIC user page */ | |
678 | top -= PAGE_ALIGN(current->thread.abi->vdso->size); | |
679 | top -= PAGE_SIZE; | |
680 | top -= mips_gic_present() ? PAGE_SIZE : 0; | |
681 | ||
682 | /* Space for cache colour alignment */ | |
683 | if (cpu_has_dc_aliases) | |
684 | top -= shm_align_mask + 1; | |
685 | ||
686 | /* Space to randomize the VDSO base */ | |
687 | if (current->flags & PF_RANDOMIZE) | |
688 | top -= VDSO_RANDOMIZE_SIZE; | |
689 | ||
690 | return top; | |
691 | } | |
692 | ||
94109102 FBH |
693 | /* |
694 | * Don't forget that the stack pointer must be aligned on a 8 bytes | |
695 | * boundary for 32-bits ABI and 16 bytes for 64-bits ABI. | |
696 | */ | |
697 | unsigned long arch_align_stack(unsigned long sp) | |
698 | { | |
699 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) | |
700 | sp -= get_random_int() & ~PAGE_MASK; | |
701 | ||
702 | return sp & ALMASK; | |
703 | } | |
856839b7 | 704 | |
b63e132b PB |
705 | static DEFINE_PER_CPU(call_single_data_t, backtrace_csd); |
706 | static struct cpumask backtrace_csd_busy; | |
856839b7 | 707 | |
b63e132b PB |
708 | static void handle_backtrace(void *info) |
709 | { | |
710 | nmi_cpu_backtrace(get_irq_regs()); | |
711 | cpumask_clear_cpu(smp_processor_id(), &backtrace_csd_busy); | |
856839b7 ES |
712 | } |
713 | ||
b63e132b | 714 | static void raise_backtrace(cpumask_t *mask) |
856839b7 | 715 | { |
b63e132b PB |
716 | call_single_data_t *csd; |
717 | int cpu; | |
9a01c3ed | 718 | |
b63e132b PB |
719 | for_each_cpu(cpu, mask) { |
720 | /* | |
721 | * If we previously sent an IPI to the target CPU & it hasn't | |
722 | * cleared its bit in the busy cpumask then it didn't handle | |
723 | * our previous IPI & it's not safe for us to reuse the | |
724 | * call_single_data_t. | |
725 | */ | |
726 | if (cpumask_test_and_set_cpu(cpu, &backtrace_csd_busy)) { | |
727 | pr_warn("Unable to send backtrace IPI to CPU%u - perhaps it hung?\n", | |
728 | cpu); | |
729 | continue; | |
730 | } | |
9a01c3ed | 731 | |
b63e132b PB |
732 | csd = &per_cpu(backtrace_csd, cpu); |
733 | csd->func = handle_backtrace; | |
734 | smp_call_function_single_async(cpu, csd); | |
735 | } | |
736 | } | |
9a01c3ed | 737 | |
b63e132b PB |
738 | void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self) |
739 | { | |
740 | nmi_trigger_cpumask_backtrace(mask, exclude_self, raise_backtrace); | |
856839b7 | 741 | } |
9791554b PB |
742 | |
743 | int mips_get_process_fp_mode(struct task_struct *task) | |
744 | { | |
745 | int value = 0; | |
746 | ||
747 | if (!test_tsk_thread_flag(task, TIF_32BIT_FPREGS)) | |
748 | value |= PR_FP_MODE_FR; | |
749 | if (test_tsk_thread_flag(task, TIF_HYBRID_FPREGS)) | |
750 | value |= PR_FP_MODE_FRE; | |
751 | ||
752 | return value; | |
753 | } | |
754 | ||
8c8d953c | 755 | static long prepare_for_fp_mode_switch(void *unused) |
6b832257 | 756 | { |
8c8d953c PB |
757 | /* |
758 | * This is icky, but we use this to simply ensure that all CPUs have | |
759 | * context switched, regardless of whether they were previously running | |
41e486f4 PB |
760 | * kernel or user code. This ensures that no CPU that a mode-switching |
761 | * program may execute on keeps its FPU enabled (& in the old mode) | |
762 | * throughout the mode switch. | |
8c8d953c PB |
763 | */ |
764 | return 0; | |
6b832257 PB |
765 | } |
766 | ||
9791554b PB |
767 | int mips_set_process_fp_mode(struct task_struct *task, unsigned int value) |
768 | { | |
769 | const unsigned int known_bits = PR_FP_MODE_FR | PR_FP_MODE_FRE; | |
9791554b | 770 | struct task_struct *t; |
8c8d953c PB |
771 | struct cpumask process_cpus; |
772 | int cpu; | |
9791554b | 773 | |
b67336ee MR |
774 | /* If nothing to change, return right away, successfully. */ |
775 | if (value == mips_get_process_fp_mode(task)) | |
776 | return 0; | |
777 | ||
778 | /* Only accept a mode change if 64-bit FP enabled for o32. */ | |
779 | if (!IS_ENABLED(CONFIG_MIPS_O32_FP64_SUPPORT)) | |
780 | return -EOPNOTSUPP; | |
781 | ||
782 | /* And only for o32 tasks. */ | |
783 | if (IS_ENABLED(CONFIG_64BIT) && !test_thread_flag(TIF_32BIT_REGS)) | |
784 | return -EOPNOTSUPP; | |
785 | ||
9791554b PB |
786 | /* Check the value is valid */ |
787 | if (value & ~known_bits) | |
788 | return -EOPNOTSUPP; | |
789 | ||
28e4213d MR |
790 | /* Setting FRE without FR is not supported. */ |
791 | if ((value & (PR_FP_MODE_FR | PR_FP_MODE_FRE)) == PR_FP_MODE_FRE) | |
792 | return -EOPNOTSUPP; | |
793 | ||
9791554b | 794 | /* Avoid inadvertently triggering emulation */ |
b244614a MN |
795 | if ((value & PR_FP_MODE_FR) && raw_cpu_has_fpu && |
796 | !(raw_current_cpu_data.fpu_id & MIPS_FPIR_F64)) | |
9791554b | 797 | return -EOPNOTSUPP; |
b244614a | 798 | if ((value & PR_FP_MODE_FRE) && raw_cpu_has_fpu && !cpu_has_fre) |
9791554b PB |
799 | return -EOPNOTSUPP; |
800 | ||
13e45f09 | 801 | /* FR = 0 not supported in MIPS R6 */ |
b244614a | 802 | if (!(value & PR_FP_MODE_FR) && raw_cpu_has_fpu && cpu_has_mips_r6) |
13e45f09 MC |
803 | return -EOPNOTSUPP; |
804 | ||
8c8d953c | 805 | /* Indicate the new FP mode in each thread */ |
9791554b PB |
806 | for_each_thread(task, t) { |
807 | /* Update desired FP register width */ | |
808 | if (value & PR_FP_MODE_FR) { | |
809 | clear_tsk_thread_flag(t, TIF_32BIT_FPREGS); | |
810 | } else { | |
811 | set_tsk_thread_flag(t, TIF_32BIT_FPREGS); | |
812 | clear_tsk_thread_flag(t, TIF_MSA_CTX_LIVE); | |
813 | } | |
814 | ||
815 | /* Update desired FP single layout */ | |
816 | if (value & PR_FP_MODE_FRE) | |
817 | set_tsk_thread_flag(t, TIF_HYBRID_FPREGS); | |
818 | else | |
819 | clear_tsk_thread_flag(t, TIF_HYBRID_FPREGS); | |
820 | } | |
821 | ||
8c8d953c PB |
822 | /* |
823 | * We need to ensure that all threads in the process have switched mode | |
824 | * before returning, in order to allow userland to not worry about | |
825 | * races. We can do this by forcing all CPUs that any thread in the | |
826 | * process may be running on to schedule something else - in this case | |
827 | * prepare_for_fp_mode_switch(). | |
828 | * | |
829 | * We begin by generating a mask of all CPUs that any thread in the | |
830 | * process may be running on. | |
831 | */ | |
832 | cpumask_clear(&process_cpus); | |
833 | for_each_thread(task, t) | |
834 | cpumask_set_cpu(task_cpu(t), &process_cpus); | |
835 | ||
836 | /* | |
837 | * Now we schedule prepare_for_fp_mode_switch() on each of those CPUs. | |
838 | * | |
839 | * The CPUs may have rescheduled already since we switched mode or | |
840 | * generated the cpumask, but that doesn't matter. If the task in this | |
841 | * process is scheduled out then our scheduling | |
842 | * prepare_for_fp_mode_switch() will simply be redundant. If it's | |
843 | * scheduled in then it will already have picked up the new FP mode | |
844 | * whilst doing so. | |
845 | */ | |
846 | get_online_cpus(); | |
847 | for_each_cpu_and(cpu, &process_cpus, cpu_online_mask) | |
848 | work_on_cpu(cpu, prepare_for_fp_mode_switch, NULL); | |
849 | put_online_cpus(); | |
9791554b PB |
850 | |
851 | return 0; | |
852 | } | |
08c941bf MN |
853 | |
854 | #if defined(CONFIG_32BIT) || defined(CONFIG_MIPS32_O32) | |
855 | void mips_dump_regs32(u32 *uregs, const struct pt_regs *regs) | |
856 | { | |
857 | unsigned int i; | |
858 | ||
859 | for (i = MIPS32_EF_R1; i <= MIPS32_EF_R31; i++) { | |
860 | /* k0/k1 are copied as zero. */ | |
861 | if (i == MIPS32_EF_R26 || i == MIPS32_EF_R27) | |
862 | uregs[i] = 0; | |
863 | else | |
864 | uregs[i] = regs->regs[i - MIPS32_EF_R0]; | |
865 | } | |
866 | ||
867 | uregs[MIPS32_EF_LO] = regs->lo; | |
868 | uregs[MIPS32_EF_HI] = regs->hi; | |
869 | uregs[MIPS32_EF_CP0_EPC] = regs->cp0_epc; | |
870 | uregs[MIPS32_EF_CP0_BADVADDR] = regs->cp0_badvaddr; | |
871 | uregs[MIPS32_EF_CP0_STATUS] = regs->cp0_status; | |
872 | uregs[MIPS32_EF_CP0_CAUSE] = regs->cp0_cause; | |
873 | } | |
874 | #endif /* CONFIG_32BIT || CONFIG_MIPS32_O32 */ | |
875 | ||
876 | #ifdef CONFIG_64BIT | |
877 | void mips_dump_regs64(u64 *uregs, const struct pt_regs *regs) | |
878 | { | |
879 | unsigned int i; | |
880 | ||
881 | for (i = MIPS64_EF_R1; i <= MIPS64_EF_R31; i++) { | |
882 | /* k0/k1 are copied as zero. */ | |
883 | if (i == MIPS64_EF_R26 || i == MIPS64_EF_R27) | |
884 | uregs[i] = 0; | |
885 | else | |
886 | uregs[i] = regs->regs[i - MIPS64_EF_R0]; | |
887 | } | |
888 | ||
889 | uregs[MIPS64_EF_LO] = regs->lo; | |
890 | uregs[MIPS64_EF_HI] = regs->hi; | |
891 | uregs[MIPS64_EF_CP0_EPC] = regs->cp0_epc; | |
892 | uregs[MIPS64_EF_CP0_BADVADDR] = regs->cp0_badvaddr; | |
893 | uregs[MIPS64_EF_CP0_STATUS] = regs->cp0_status; | |
894 | uregs[MIPS64_EF_CP0_CAUSE] = regs->cp0_cause; | |
895 | } | |
896 | #endif /* CONFIG_64BIT */ |