Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 | 2 | * Copyright (C) 1995, 1996, 2001 Ralf Baechle |
4194318c RB |
3 | * Copyright (C) 2001, 2004 MIPS Technologies, Inc. |
4 | * Copyright (C) 2004 Maciej W. Rozycki | |
1da177e4 | 5 | */ |
1da177e4 LT |
6 | #include <linux/delay.h> |
7 | #include <linux/kernel.h> | |
8 | #include <linux/sched.h> | |
9 | #include <linux/seq_file.h> | |
10 | #include <asm/bootinfo.h> | |
11 | #include <asm/cpu.h> | |
12 | #include <asm/cpu-features.h> | |
13 | #include <asm/mipsregs.h> | |
14 | #include <asm/processor.h> | |
1da177e4 LT |
15 | |
16 | unsigned int vced_count, vcei_count; | |
17 | ||
1da177e4 LT |
18 | static int show_cpuinfo(struct seq_file *m, void *v) |
19 | { | |
1da177e4 | 20 | unsigned long n = (unsigned long) v - 1; |
31aa3665 KJK |
21 | unsigned int version = cpu_data[n].processor_id; |
22 | unsigned int fp_vers = cpu_data[n].fpu_id; | |
1da177e4 | 23 | char fmt [64]; |
654f57bf | 24 | int i; |
1da177e4 LT |
25 | |
26 | #ifdef CONFIG_SMP | |
27 | if (!cpu_isset(n, cpu_online_map)) | |
28 | return 0; | |
29 | #endif | |
30 | ||
31 | /* | |
32 | * For the first processor also print the system type | |
33 | */ | |
34 | if (n == 0) | |
35 | seq_printf(m, "system type\t\t: %s\n", get_system_type()); | |
36 | ||
37 | seq_printf(m, "processor\t\t: %ld\n", n); | |
38 | sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n", | |
e04582b7 | 39 | cpu_data[n].options & MIPS_CPU_FPU ? " FPU V%d.%d" : ""); |
e47c659b | 40 | seq_printf(m, fmt, __cpu_name[n], |
1da177e4 LT |
41 | (version >> 4) & 0x0f, version & 0x0f, |
42 | (fp_vers >> 4) & 0x0f, fp_vers & 0x0f); | |
5636919b | 43 | seq_printf(m, "BogoMIPS\t\t: %u.%02u\n", |
0ac35480 RB |
44 | cpu_data[n].udelay_val / (500000/HZ), |
45 | (cpu_data[n].udelay_val / (5000/HZ)) % 100); | |
1da177e4 LT |
46 | seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no"); |
47 | seq_printf(m, "microsecond timers\t: %s\n", | |
48 | cpu_has_counter ? "yes" : "no"); | |
31aa3665 | 49 | seq_printf(m, "tlb_entries\t\t: %d\n", cpu_data[n].tlbsize); |
1da177e4 LT |
50 | seq_printf(m, "extra interrupt vector\t: %s\n", |
51 | cpu_has_divec ? "yes" : "no"); | |
654f57bf DD |
52 | seq_printf(m, "hardware watchpoint\t: %s", |
53 | cpu_has_watch ? "yes, " : "no\n"); | |
54 | if (cpu_has_watch) { | |
55 | seq_printf(m, "count: %d, address/irw mask: [", | |
56 | cpu_data[n].watch_reg_count); | |
57 | for (i = 0; i < cpu_data[n].watch_reg_count; i++) | |
58 | seq_printf(m, "%s0x%04x", i ? ", " : "" , | |
59 | cpu_data[n].watch_reg_masks[i]); | |
60 | seq_printf(m, "]\n"); | |
61 | } | |
e027802e | 62 | seq_printf(m, "ASEs implemented\t:%s%s%s%s%s%s\n", |
4194318c RB |
63 | cpu_has_mips16 ? " mips16" : "", |
64 | cpu_has_mdmx ? " mdmx" : "", | |
65 | cpu_has_mips3d ? " mips3d" : "", | |
e027802e RB |
66 | cpu_has_smartmips ? " smartmips" : "", |
67 | cpu_has_dsp ? " dsp" : "", | |
68 | cpu_has_mipsmt ? " mt" : "" | |
69 | ); | |
f6771dbb RB |
70 | seq_printf(m, "shadow register sets\t: %d\n", |
71 | cpu_data[n].srsets); | |
0ab7aefc | 72 | seq_printf(m, "core\t\t\t: %d\n", cpu_data[n].core); |
1da177e4 LT |
73 | |
74 | sprintf(fmt, "VCE%%c exceptions\t\t: %s\n", | |
75 | cpu_has_vce ? "%u" : "not available"); | |
76 | seq_printf(m, fmt, 'D', vced_count); | |
77 | seq_printf(m, fmt, 'I', vcei_count); | |
17256052 | 78 | seq_printf(m, "\n"); |
1da177e4 LT |
79 | |
80 | return 0; | |
81 | } | |
82 | ||
83 | static void *c_start(struct seq_file *m, loff_t *pos) | |
84 | { | |
85 | unsigned long i = *pos; | |
86 | ||
87 | return i < NR_CPUS ? (void *) (i + 1) : NULL; | |
88 | } | |
89 | ||
90 | static void *c_next(struct seq_file *m, void *v, loff_t *pos) | |
91 | { | |
92 | ++*pos; | |
93 | return c_start(m, pos); | |
94 | } | |
95 | ||
96 | static void c_stop(struct seq_file *m, void *v) | |
97 | { | |
98 | } | |
99 | ||
12323cac | 100 | const struct seq_operations cpuinfo_op = { |
1da177e4 LT |
101 | .start = c_start, |
102 | .next = c_next, | |
103 | .stop = c_stop, | |
104 | .show = show_cpuinfo, | |
105 | }; |