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e5dcb58a DD |
1 | /* |
2 | * Linux performance counter support for MIPS. | |
3 | * | |
4 | * Copyright (C) 2010 MIPS Technologies, Inc. | |
82091564 | 5 | * Copyright (C) 2011 Cavium Networks, Inc. |
e5dcb58a DD |
6 | * Author: Deng-Cheng Zhu |
7 | * | |
8 | * This code is based on the implementation for ARM, which is in turn | |
9 | * based on the sparc64 perf event code and the x86 code. Performance | |
10 | * counter access is based on the MIPS Oprofile code. And the callchain | |
11 | * support references the code of MIPS stacktrace.c. | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License version 2 as | |
15 | * published by the Free Software Foundation. | |
16 | */ | |
17 | ||
18 | #include <linux/cpumask.h> | |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/smp.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/perf_event.h> | |
23 | #include <linux/uaccess.h> | |
24 | ||
25 | #include <asm/irq.h> | |
26 | #include <asm/irq_regs.h> | |
27 | #include <asm/stacktrace.h> | |
28 | #include <asm/time.h> /* For perf_irq */ | |
29 | ||
e5dcb58a DD |
30 | #define MIPS_MAX_HWEVENTS 4 |
31 | ||
32 | struct cpu_hw_events { | |
33 | /* Array of events on this cpu. */ | |
34 | struct perf_event *events[MIPS_MAX_HWEVENTS]; | |
35 | ||
36 | /* | |
37 | * Set the bit (indexed by the counter number) when the counter | |
38 | * is used for an event. | |
39 | */ | |
40 | unsigned long used_mask[BITS_TO_LONGS(MIPS_MAX_HWEVENTS)]; | |
41 | ||
e5dcb58a DD |
42 | /* |
43 | * Software copy of the control register for each performance counter. | |
44 | * MIPS CPUs vary in performance counters. They use this differently, | |
45 | * and even may not use it. | |
46 | */ | |
47 | unsigned int saved_ctrl[MIPS_MAX_HWEVENTS]; | |
48 | }; | |
49 | DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { | |
50 | .saved_ctrl = {0}, | |
51 | }; | |
52 | ||
53 | /* The description of MIPS performance events. */ | |
54 | struct mips_perf_event { | |
55 | unsigned int event_id; | |
56 | /* | |
57 | * MIPS performance counters are indexed starting from 0. | |
58 | * CNTR_EVEN indicates the indexes of the counters to be used are | |
59 | * even numbers. | |
60 | */ | |
61 | unsigned int cntr_mask; | |
62 | #define CNTR_EVEN 0x55555555 | |
63 | #define CNTR_ODD 0xaaaaaaaa | |
82091564 | 64 | #define CNTR_ALL 0xffffffff |
e5dcb58a DD |
65 | #ifdef CONFIG_MIPS_MT_SMP |
66 | enum { | |
67 | T = 0, | |
68 | V = 1, | |
69 | P = 2, | |
70 | } range; | |
71 | #else | |
72 | #define T | |
73 | #define V | |
74 | #define P | |
75 | #endif | |
76 | }; | |
77 | ||
78 | static struct mips_perf_event raw_event; | |
79 | static DEFINE_MUTEX(raw_event_mutex); | |
80 | ||
e5dcb58a DD |
81 | #define C(x) PERF_COUNT_HW_CACHE_##x |
82 | ||
83 | struct mips_pmu { | |
82091564 DD |
84 | u64 max_period; |
85 | u64 valid_count; | |
86 | u64 overflow; | |
e5dcb58a DD |
87 | const char *name; |
88 | int irq; | |
e5dcb58a DD |
89 | u64 (*read_counter)(unsigned int idx); |
90 | void (*write_counter)(unsigned int idx, u64 val); | |
e5dcb58a DD |
91 | const struct mips_perf_event *(*map_raw_event)(u64 config); |
92 | const struct mips_perf_event (*general_event_map)[PERF_COUNT_HW_MAX]; | |
93 | const struct mips_perf_event (*cache_event_map) | |
94 | [PERF_COUNT_HW_CACHE_MAX] | |
95 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
96 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
97 | unsigned int num_counters; | |
98 | }; | |
99 | ||
82091564 DD |
100 | static struct mips_pmu mipspmu; |
101 | ||
102 | #define M_CONFIG1_PC (1 << 4) | |
103 | ||
104 | #define M_PERFCTL_EXL (1 << 0) | |
105 | #define M_PERFCTL_KERNEL (1 << 1) | |
106 | #define M_PERFCTL_SUPERVISOR (1 << 2) | |
107 | #define M_PERFCTL_USER (1 << 3) | |
108 | #define M_PERFCTL_INTERRUPT_ENABLE (1 << 4) | |
109 | #define M_PERFCTL_EVENT(event) (((event) & 0x3ff) << 5) | |
110 | #define M_PERFCTL_VPEID(vpe) ((vpe) << 16) | |
111 | #define M_PERFCTL_MT_EN(filter) ((filter) << 20) | |
112 | #define M_TC_EN_ALL M_PERFCTL_MT_EN(0) | |
113 | #define M_TC_EN_VPE M_PERFCTL_MT_EN(1) | |
114 | #define M_TC_EN_TC M_PERFCTL_MT_EN(2) | |
115 | #define M_PERFCTL_TCID(tcid) ((tcid) << 22) | |
116 | #define M_PERFCTL_WIDE (1 << 30) | |
117 | #define M_PERFCTL_MORE (1 << 31) | |
118 | ||
119 | #define M_PERFCTL_COUNT_EVENT_WHENEVER (M_PERFCTL_EXL | \ | |
120 | M_PERFCTL_KERNEL | \ | |
121 | M_PERFCTL_USER | \ | |
122 | M_PERFCTL_SUPERVISOR | \ | |
123 | M_PERFCTL_INTERRUPT_ENABLE) | |
124 | ||
125 | #ifdef CONFIG_MIPS_MT_SMP | |
126 | #define M_PERFCTL_CONFIG_MASK 0x3fff801f | |
127 | #else | |
128 | #define M_PERFCTL_CONFIG_MASK 0x1f | |
129 | #endif | |
130 | #define M_PERFCTL_EVENT_MASK 0xfe0 | |
131 | ||
132 | ||
133 | #ifdef CONFIG_MIPS_MT_SMP | |
134 | static int cpu_has_mipsmt_pertccounters; | |
135 | ||
136 | static DEFINE_RWLOCK(pmuint_rwlock); | |
137 | ||
138 | /* | |
139 | * FIXME: For VSMP, vpe_id() is redefined for Perf-events, because | |
140 | * cpu_data[cpuid].vpe_id reports 0 for _both_ CPUs. | |
141 | */ | |
82091564 DD |
142 | #define vpe_id() (cpu_has_mipsmt_pertccounters ? \ |
143 | 0 : smp_processor_id()) | |
82091564 DD |
144 | |
145 | /* Copied from op_model_mipsxx.c */ | |
146 | static unsigned int vpe_shift(void) | |
147 | { | |
148 | if (num_possible_cpus() > 1) | |
149 | return 1; | |
150 | ||
151 | return 0; | |
152 | } | |
153 | ||
154 | static unsigned int counters_total_to_per_cpu(unsigned int counters) | |
155 | { | |
156 | return counters >> vpe_shift(); | |
157 | } | |
158 | ||
82091564 DD |
159 | #else /* !CONFIG_MIPS_MT_SMP */ |
160 | #define vpe_id() 0 | |
161 | ||
162 | #endif /* CONFIG_MIPS_MT_SMP */ | |
163 | ||
164 | static void resume_local_counters(void); | |
165 | static void pause_local_counters(void); | |
166 | static irqreturn_t mipsxx_pmu_handle_irq(int, void *); | |
167 | static int mipsxx_pmu_handle_shared_irq(void); | |
168 | ||
169 | static unsigned int mipsxx_pmu_swizzle_perf_idx(unsigned int idx) | |
170 | { | |
171 | if (vpe_id() == 1) | |
172 | idx = (idx + 2) & 3; | |
173 | return idx; | |
174 | } | |
175 | ||
176 | static u64 mipsxx_pmu_read_counter(unsigned int idx) | |
177 | { | |
178 | idx = mipsxx_pmu_swizzle_perf_idx(idx); | |
179 | ||
180 | switch (idx) { | |
181 | case 0: | |
182 | /* | |
183 | * The counters are unsigned, we must cast to truncate | |
184 | * off the high bits. | |
185 | */ | |
186 | return (u32)read_c0_perfcntr0(); | |
187 | case 1: | |
188 | return (u32)read_c0_perfcntr1(); | |
189 | case 2: | |
190 | return (u32)read_c0_perfcntr2(); | |
191 | case 3: | |
192 | return (u32)read_c0_perfcntr3(); | |
193 | default: | |
194 | WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx); | |
195 | return 0; | |
196 | } | |
197 | } | |
198 | ||
199 | static u64 mipsxx_pmu_read_counter_64(unsigned int idx) | |
200 | { | |
201 | idx = mipsxx_pmu_swizzle_perf_idx(idx); | |
202 | ||
203 | switch (idx) { | |
204 | case 0: | |
205 | return read_c0_perfcntr0_64(); | |
206 | case 1: | |
207 | return read_c0_perfcntr1_64(); | |
208 | case 2: | |
209 | return read_c0_perfcntr2_64(); | |
210 | case 3: | |
211 | return read_c0_perfcntr3_64(); | |
212 | default: | |
213 | WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx); | |
214 | return 0; | |
215 | } | |
216 | } | |
217 | ||
218 | static void mipsxx_pmu_write_counter(unsigned int idx, u64 val) | |
219 | { | |
220 | idx = mipsxx_pmu_swizzle_perf_idx(idx); | |
221 | ||
222 | switch (idx) { | |
223 | case 0: | |
224 | write_c0_perfcntr0(val); | |
225 | return; | |
226 | case 1: | |
227 | write_c0_perfcntr1(val); | |
228 | return; | |
229 | case 2: | |
230 | write_c0_perfcntr2(val); | |
231 | return; | |
232 | case 3: | |
233 | write_c0_perfcntr3(val); | |
234 | return; | |
235 | } | |
236 | } | |
237 | ||
238 | static void mipsxx_pmu_write_counter_64(unsigned int idx, u64 val) | |
239 | { | |
240 | idx = mipsxx_pmu_swizzle_perf_idx(idx); | |
241 | ||
242 | switch (idx) { | |
243 | case 0: | |
244 | write_c0_perfcntr0_64(val); | |
245 | return; | |
246 | case 1: | |
247 | write_c0_perfcntr1_64(val); | |
248 | return; | |
249 | case 2: | |
250 | write_c0_perfcntr2_64(val); | |
251 | return; | |
252 | case 3: | |
253 | write_c0_perfcntr3_64(val); | |
254 | return; | |
255 | } | |
256 | } | |
257 | ||
258 | static unsigned int mipsxx_pmu_read_control(unsigned int idx) | |
259 | { | |
260 | idx = mipsxx_pmu_swizzle_perf_idx(idx); | |
261 | ||
262 | switch (idx) { | |
263 | case 0: | |
264 | return read_c0_perfctrl0(); | |
265 | case 1: | |
266 | return read_c0_perfctrl1(); | |
267 | case 2: | |
268 | return read_c0_perfctrl2(); | |
269 | case 3: | |
270 | return read_c0_perfctrl3(); | |
271 | default: | |
272 | WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx); | |
273 | return 0; | |
274 | } | |
275 | } | |
276 | ||
277 | static void mipsxx_pmu_write_control(unsigned int idx, unsigned int val) | |
278 | { | |
279 | idx = mipsxx_pmu_swizzle_perf_idx(idx); | |
280 | ||
281 | switch (idx) { | |
282 | case 0: | |
283 | write_c0_perfctrl0(val); | |
284 | return; | |
285 | case 1: | |
286 | write_c0_perfctrl1(val); | |
287 | return; | |
288 | case 2: | |
289 | write_c0_perfctrl2(val); | |
290 | return; | |
291 | case 3: | |
292 | write_c0_perfctrl3(val); | |
293 | return; | |
294 | } | |
295 | } | |
296 | ||
297 | static int mipsxx_pmu_alloc_counter(struct cpu_hw_events *cpuc, | |
298 | struct hw_perf_event *hwc) | |
299 | { | |
300 | int i; | |
301 | ||
302 | /* | |
303 | * We only need to care the counter mask. The range has been | |
304 | * checked definitely. | |
305 | */ | |
306 | unsigned long cntr_mask = (hwc->event_base >> 8) & 0xffff; | |
307 | ||
308 | for (i = mipspmu.num_counters - 1; i >= 0; i--) { | |
309 | /* | |
310 | * Note that some MIPS perf events can be counted by both | |
311 | * even and odd counters, wheresas many other are only by | |
312 | * even _or_ odd counters. This introduces an issue that | |
313 | * when the former kind of event takes the counter the | |
314 | * latter kind of event wants to use, then the "counter | |
315 | * allocation" for the latter event will fail. In fact if | |
316 | * they can be dynamically swapped, they both feel happy. | |
317 | * But here we leave this issue alone for now. | |
318 | */ | |
319 | if (test_bit(i, &cntr_mask) && | |
320 | !test_and_set_bit(i, cpuc->used_mask)) | |
321 | return i; | |
322 | } | |
323 | ||
324 | return -EAGAIN; | |
325 | } | |
326 | ||
327 | static void mipsxx_pmu_enable_event(struct hw_perf_event *evt, int idx) | |
328 | { | |
329 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
330 | ||
331 | WARN_ON(idx < 0 || idx >= mipspmu.num_counters); | |
332 | ||
333 | cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base & 0xff) | | |
334 | (evt->config_base & M_PERFCTL_CONFIG_MASK) | | |
335 | /* Make sure interrupt enabled. */ | |
336 | M_PERFCTL_INTERRUPT_ENABLE; | |
337 | /* | |
338 | * We do not actually let the counter run. Leave it until start(). | |
339 | */ | |
340 | } | |
341 | ||
342 | static void mipsxx_pmu_disable_event(int idx) | |
343 | { | |
344 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
345 | unsigned long flags; | |
346 | ||
347 | WARN_ON(idx < 0 || idx >= mipspmu.num_counters); | |
348 | ||
349 | local_irq_save(flags); | |
350 | cpuc->saved_ctrl[idx] = mipsxx_pmu_read_control(idx) & | |
351 | ~M_PERFCTL_COUNT_EVENT_WHENEVER; | |
352 | mipsxx_pmu_write_control(idx, cpuc->saved_ctrl[idx]); | |
353 | local_irq_restore(flags); | |
354 | } | |
e5dcb58a DD |
355 | |
356 | static int mipspmu_event_set_period(struct perf_event *event, | |
357 | struct hw_perf_event *hwc, | |
358 | int idx) | |
359 | { | |
82091564 DD |
360 | u64 left = local64_read(&hwc->period_left); |
361 | u64 period = hwc->sample_period; | |
e5dcb58a | 362 | int ret = 0; |
e5dcb58a | 363 | |
82091564 DD |
364 | if (unlikely((left + period) & (1ULL << 63))) { |
365 | /* left underflowed by more than period. */ | |
e5dcb58a DD |
366 | left = period; |
367 | local64_set(&hwc->period_left, left); | |
368 | hwc->last_period = period; | |
369 | ret = 1; | |
82091564 DD |
370 | } else if (unlikely((left + period) <= period)) { |
371 | /* left underflowed by less than period. */ | |
e5dcb58a DD |
372 | left += period; |
373 | local64_set(&hwc->period_left, left); | |
374 | hwc->last_period = period; | |
375 | ret = 1; | |
376 | } | |
377 | ||
82091564 DD |
378 | if (left > mipspmu.max_period) { |
379 | left = mipspmu.max_period; | |
380 | local64_set(&hwc->period_left, left); | |
381 | } | |
e5dcb58a | 382 | |
82091564 | 383 | local64_set(&hwc->prev_count, mipspmu.overflow - left); |
e5dcb58a | 384 | |
82091564 | 385 | mipspmu.write_counter(idx, mipspmu.overflow - left); |
e5dcb58a DD |
386 | |
387 | perf_event_update_userpage(event); | |
388 | ||
389 | return ret; | |
390 | } | |
391 | ||
392 | static void mipspmu_event_update(struct perf_event *event, | |
393 | struct hw_perf_event *hwc, | |
394 | int idx) | |
395 | { | |
82091564 | 396 | u64 prev_raw_count, new_raw_count; |
e5dcb58a DD |
397 | u64 delta; |
398 | ||
399 | again: | |
400 | prev_raw_count = local64_read(&hwc->prev_count); | |
82091564 | 401 | new_raw_count = mipspmu.read_counter(idx); |
e5dcb58a DD |
402 | |
403 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, | |
404 | new_raw_count) != prev_raw_count) | |
405 | goto again; | |
406 | ||
82091564 | 407 | delta = new_raw_count - prev_raw_count; |
e5dcb58a DD |
408 | |
409 | local64_add(delta, &event->count); | |
410 | local64_sub(delta, &hwc->period_left); | |
411 | } | |
412 | ||
413 | static void mipspmu_start(struct perf_event *event, int flags) | |
414 | { | |
415 | struct hw_perf_event *hwc = &event->hw; | |
416 | ||
e5dcb58a DD |
417 | if (flags & PERF_EF_RELOAD) |
418 | WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); | |
419 | ||
420 | hwc->state = 0; | |
421 | ||
422 | /* Set the period for the event. */ | |
423 | mipspmu_event_set_period(event, hwc, hwc->idx); | |
424 | ||
425 | /* Enable the event. */ | |
82091564 | 426 | mipsxx_pmu_enable_event(hwc, hwc->idx); |
e5dcb58a DD |
427 | } |
428 | ||
429 | static void mipspmu_stop(struct perf_event *event, int flags) | |
430 | { | |
431 | struct hw_perf_event *hwc = &event->hw; | |
432 | ||
e5dcb58a DD |
433 | if (!(hwc->state & PERF_HES_STOPPED)) { |
434 | /* We are working on a local event. */ | |
82091564 | 435 | mipsxx_pmu_disable_event(hwc->idx); |
e5dcb58a DD |
436 | barrier(); |
437 | mipspmu_event_update(event, hwc, hwc->idx); | |
438 | hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; | |
439 | } | |
440 | } | |
441 | ||
442 | static int mipspmu_add(struct perf_event *event, int flags) | |
443 | { | |
444 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
445 | struct hw_perf_event *hwc = &event->hw; | |
446 | int idx; | |
447 | int err = 0; | |
448 | ||
449 | perf_pmu_disable(event->pmu); | |
450 | ||
451 | /* To look for a free counter for this event. */ | |
82091564 | 452 | idx = mipsxx_pmu_alloc_counter(cpuc, hwc); |
e5dcb58a DD |
453 | if (idx < 0) { |
454 | err = idx; | |
455 | goto out; | |
456 | } | |
457 | ||
458 | /* | |
459 | * If there is an event in the counter we are going to use then | |
460 | * make sure it is disabled. | |
461 | */ | |
462 | event->hw.idx = idx; | |
82091564 | 463 | mipsxx_pmu_disable_event(idx); |
e5dcb58a DD |
464 | cpuc->events[idx] = event; |
465 | ||
466 | hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE; | |
467 | if (flags & PERF_EF_START) | |
468 | mipspmu_start(event, PERF_EF_RELOAD); | |
469 | ||
470 | /* Propagate our changes to the userspace mapping. */ | |
471 | perf_event_update_userpage(event); | |
472 | ||
473 | out: | |
474 | perf_pmu_enable(event->pmu); | |
475 | return err; | |
476 | } | |
477 | ||
478 | static void mipspmu_del(struct perf_event *event, int flags) | |
479 | { | |
480 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
481 | struct hw_perf_event *hwc = &event->hw; | |
482 | int idx = hwc->idx; | |
483 | ||
82091564 | 484 | WARN_ON(idx < 0 || idx >= mipspmu.num_counters); |
e5dcb58a DD |
485 | |
486 | mipspmu_stop(event, PERF_EF_UPDATE); | |
487 | cpuc->events[idx] = NULL; | |
488 | clear_bit(idx, cpuc->used_mask); | |
489 | ||
490 | perf_event_update_userpage(event); | |
491 | } | |
492 | ||
493 | static void mipspmu_read(struct perf_event *event) | |
494 | { | |
495 | struct hw_perf_event *hwc = &event->hw; | |
496 | ||
497 | /* Don't read disabled counters! */ | |
498 | if (hwc->idx < 0) | |
499 | return; | |
500 | ||
501 | mipspmu_event_update(event, hwc, hwc->idx); | |
502 | } | |
503 | ||
504 | static void mipspmu_enable(struct pmu *pmu) | |
505 | { | |
82091564 DD |
506 | #ifdef CONFIG_MIPS_MT_SMP |
507 | write_unlock(&pmuint_rwlock); | |
508 | #endif | |
509 | resume_local_counters(); | |
e5dcb58a DD |
510 | } |
511 | ||
82091564 DD |
512 | /* |
513 | * MIPS performance counters can be per-TC. The control registers can | |
514 | * not be directly accessed accross CPUs. Hence if we want to do global | |
515 | * control, we need cross CPU calls. on_each_cpu() can help us, but we | |
516 | * can not make sure this function is called with interrupts enabled. So | |
517 | * here we pause local counters and then grab a rwlock and leave the | |
518 | * counters on other CPUs alone. If any counter interrupt raises while | |
519 | * we own the write lock, simply pause local counters on that CPU and | |
520 | * spin in the handler. Also we know we won't be switched to another | |
521 | * CPU after pausing local counters and before grabbing the lock. | |
522 | */ | |
e5dcb58a DD |
523 | static void mipspmu_disable(struct pmu *pmu) |
524 | { | |
82091564 DD |
525 | pause_local_counters(); |
526 | #ifdef CONFIG_MIPS_MT_SMP | |
527 | write_lock(&pmuint_rwlock); | |
528 | #endif | |
e5dcb58a DD |
529 | } |
530 | ||
531 | static atomic_t active_events = ATOMIC_INIT(0); | |
532 | static DEFINE_MUTEX(pmu_reserve_mutex); | |
533 | static int (*save_perf_irq)(void); | |
534 | ||
535 | static int mipspmu_get_irq(void) | |
536 | { | |
537 | int err; | |
538 | ||
82091564 | 539 | if (mipspmu.irq >= 0) { |
e5dcb58a | 540 | /* Request my own irq handler. */ |
82091564 DD |
541 | err = request_irq(mipspmu.irq, mipsxx_pmu_handle_irq, |
542 | IRQF_PERCPU | IRQF_NOBALANCING, | |
e5dcb58a DD |
543 | "mips_perf_pmu", NULL); |
544 | if (err) { | |
545 | pr_warning("Unable to request IRQ%d for MIPS " | |
82091564 | 546 | "performance counters!\n", mipspmu.irq); |
e5dcb58a DD |
547 | } |
548 | } else if (cp0_perfcount_irq < 0) { | |
549 | /* | |
550 | * We are sharing the irq number with the timer interrupt. | |
551 | */ | |
552 | save_perf_irq = perf_irq; | |
82091564 | 553 | perf_irq = mipsxx_pmu_handle_shared_irq; |
e5dcb58a DD |
554 | err = 0; |
555 | } else { | |
556 | pr_warning("The platform hasn't properly defined its " | |
557 | "interrupt controller.\n"); | |
558 | err = -ENOENT; | |
559 | } | |
560 | ||
561 | return err; | |
562 | } | |
563 | ||
564 | static void mipspmu_free_irq(void) | |
565 | { | |
82091564 DD |
566 | if (mipspmu.irq >= 0) |
567 | free_irq(mipspmu.irq, NULL); | |
e5dcb58a DD |
568 | else if (cp0_perfcount_irq < 0) |
569 | perf_irq = save_perf_irq; | |
570 | } | |
571 | ||
572 | /* | |
573 | * mipsxx/rm9000/loongson2 have different performance counters, they have | |
574 | * specific low-level init routines. | |
575 | */ | |
576 | static void reset_counters(void *arg); | |
577 | static int __hw_perf_event_init(struct perf_event *event); | |
578 | ||
579 | static void hw_perf_event_destroy(struct perf_event *event) | |
580 | { | |
581 | if (atomic_dec_and_mutex_lock(&active_events, | |
582 | &pmu_reserve_mutex)) { | |
583 | /* | |
584 | * We must not call the destroy function with interrupts | |
585 | * disabled. | |
586 | */ | |
587 | on_each_cpu(reset_counters, | |
82091564 | 588 | (void *)(long)mipspmu.num_counters, 1); |
e5dcb58a DD |
589 | mipspmu_free_irq(); |
590 | mutex_unlock(&pmu_reserve_mutex); | |
591 | } | |
592 | } | |
593 | ||
594 | static int mipspmu_event_init(struct perf_event *event) | |
595 | { | |
596 | int err = 0; | |
597 | ||
2481c5fa SE |
598 | /* does not support taken branch sampling */ |
599 | if (has_branch_stack(event)) | |
600 | return -EOPNOTSUPP; | |
601 | ||
e5dcb58a DD |
602 | switch (event->attr.type) { |
603 | case PERF_TYPE_RAW: | |
604 | case PERF_TYPE_HARDWARE: | |
605 | case PERF_TYPE_HW_CACHE: | |
606 | break; | |
607 | ||
608 | default: | |
609 | return -ENOENT; | |
610 | } | |
611 | ||
82091564 DD |
612 | if (event->cpu >= nr_cpumask_bits || |
613 | (event->cpu >= 0 && !cpu_online(event->cpu))) | |
e5dcb58a DD |
614 | return -ENODEV; |
615 | ||
616 | if (!atomic_inc_not_zero(&active_events)) { | |
e5dcb58a DD |
617 | mutex_lock(&pmu_reserve_mutex); |
618 | if (atomic_read(&active_events) == 0) | |
619 | err = mipspmu_get_irq(); | |
620 | ||
621 | if (!err) | |
622 | atomic_inc(&active_events); | |
623 | mutex_unlock(&pmu_reserve_mutex); | |
624 | } | |
625 | ||
626 | if (err) | |
627 | return err; | |
628 | ||
ff5d7265 | 629 | return __hw_perf_event_init(event); |
e5dcb58a DD |
630 | } |
631 | ||
632 | static struct pmu pmu = { | |
633 | .pmu_enable = mipspmu_enable, | |
634 | .pmu_disable = mipspmu_disable, | |
635 | .event_init = mipspmu_event_init, | |
636 | .add = mipspmu_add, | |
637 | .del = mipspmu_del, | |
638 | .start = mipspmu_start, | |
639 | .stop = mipspmu_stop, | |
640 | .read = mipspmu_read, | |
641 | }; | |
642 | ||
643 | static unsigned int mipspmu_perf_event_encode(const struct mips_perf_event *pev) | |
644 | { | |
645 | /* | |
646 | * Top 8 bits for range, next 16 bits for cntr_mask, lowest 8 bits for | |
647 | * event_id. | |
648 | */ | |
649 | #ifdef CONFIG_MIPS_MT_SMP | |
650 | return ((unsigned int)pev->range << 24) | | |
651 | (pev->cntr_mask & 0xffff00) | | |
652 | (pev->event_id & 0xff); | |
653 | #else | |
654 | return (pev->cntr_mask & 0xffff00) | | |
655 | (pev->event_id & 0xff); | |
656 | #endif | |
657 | } | |
658 | ||
659 | static const struct mips_perf_event *mipspmu_map_general_event(int idx) | |
660 | { | |
e5dcb58a | 661 | |
c5600b2d AC |
662 | if ((*mipspmu.general_event_map)[idx].cntr_mask == 0) |
663 | return ERR_PTR(-EOPNOTSUPP); | |
664 | return &(*mipspmu.general_event_map)[idx]; | |
e5dcb58a DD |
665 | } |
666 | ||
667 | static const struct mips_perf_event *mipspmu_map_cache_event(u64 config) | |
668 | { | |
669 | unsigned int cache_type, cache_op, cache_result; | |
670 | const struct mips_perf_event *pev; | |
671 | ||
672 | cache_type = (config >> 0) & 0xff; | |
673 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
674 | return ERR_PTR(-EINVAL); | |
675 | ||
676 | cache_op = (config >> 8) & 0xff; | |
677 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
678 | return ERR_PTR(-EINVAL); | |
679 | ||
680 | cache_result = (config >> 16) & 0xff; | |
681 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
682 | return ERR_PTR(-EINVAL); | |
683 | ||
82091564 | 684 | pev = &((*mipspmu.cache_event_map) |
e5dcb58a DD |
685 | [cache_type] |
686 | [cache_op] | |
687 | [cache_result]); | |
688 | ||
c5600b2d | 689 | if (pev->cntr_mask == 0) |
e5dcb58a DD |
690 | return ERR_PTR(-EOPNOTSUPP); |
691 | ||
692 | return pev; | |
693 | ||
694 | } | |
695 | ||
e5dcb58a DD |
696 | static int validate_group(struct perf_event *event) |
697 | { | |
698 | struct perf_event *sibling, *leader = event->group_leader; | |
699 | struct cpu_hw_events fake_cpuc; | |
700 | ||
701 | memset(&fake_cpuc, 0, sizeof(fake_cpuc)); | |
702 | ||
266623b7 | 703 | if (mipsxx_pmu_alloc_counter(&fake_cpuc, &leader->hw) < 0) |
aa2bc1ad | 704 | return -EINVAL; |
e5dcb58a DD |
705 | |
706 | list_for_each_entry(sibling, &leader->sibling_list, group_entry) { | |
266623b7 | 707 | if (mipsxx_pmu_alloc_counter(&fake_cpuc, &sibling->hw) < 0) |
aa2bc1ad | 708 | return -EINVAL; |
e5dcb58a DD |
709 | } |
710 | ||
266623b7 | 711 | if (mipsxx_pmu_alloc_counter(&fake_cpuc, &event->hw) < 0) |
aa2bc1ad | 712 | return -EINVAL; |
e5dcb58a DD |
713 | |
714 | return 0; | |
715 | } | |
716 | ||
717 | /* This is needed by specific irq handlers in perf_event_*.c */ | |
718 | static void handle_associated_event(struct cpu_hw_events *cpuc, | |
719 | int idx, struct perf_sample_data *data, | |
720 | struct pt_regs *regs) | |
721 | { | |
722 | struct perf_event *event = cpuc->events[idx]; | |
723 | struct hw_perf_event *hwc = &event->hw; | |
724 | ||
725 | mipspmu_event_update(event, hwc, idx); | |
726 | data->period = event->hw.last_period; | |
727 | if (!mipspmu_event_set_period(event, hwc, idx)) | |
728 | return; | |
729 | ||
730 | if (perf_event_overflow(event, data, regs)) | |
82091564 | 731 | mipsxx_pmu_disable_event(idx); |
e5dcb58a | 732 | } |
3a9ab99e | 733 | |
3a9ab99e | 734 | |
4409af37 | 735 | static int __n_counters(void) |
3a9ab99e DCZ |
736 | { |
737 | if (!(read_c0_config1() & M_CONFIG1_PC)) | |
738 | return 0; | |
739 | if (!(read_c0_perfctrl0() & M_PERFCTL_MORE)) | |
740 | return 1; | |
741 | if (!(read_c0_perfctrl1() & M_PERFCTL_MORE)) | |
742 | return 2; | |
743 | if (!(read_c0_perfctrl2() & M_PERFCTL_MORE)) | |
744 | return 3; | |
745 | ||
746 | return 4; | |
747 | } | |
748 | ||
4409af37 | 749 | static int n_counters(void) |
3a9ab99e DCZ |
750 | { |
751 | int counters; | |
752 | ||
753 | switch (current_cpu_type()) { | |
754 | case CPU_R10000: | |
755 | counters = 2; | |
756 | break; | |
757 | ||
758 | case CPU_R12000: | |
759 | case CPU_R14000: | |
760 | counters = 4; | |
761 | break; | |
762 | ||
763 | default: | |
764 | counters = __n_counters(); | |
765 | } | |
766 | ||
767 | return counters; | |
768 | } | |
769 | ||
770 | static void reset_counters(void *arg) | |
771 | { | |
772 | int counters = (int)(long)arg; | |
773 | switch (counters) { | |
774 | case 4: | |
82091564 DD |
775 | mipsxx_pmu_write_control(3, 0); |
776 | mipspmu.write_counter(3, 0); | |
3a9ab99e | 777 | case 3: |
82091564 DD |
778 | mipsxx_pmu_write_control(2, 0); |
779 | mipspmu.write_counter(2, 0); | |
3a9ab99e | 780 | case 2: |
82091564 DD |
781 | mipsxx_pmu_write_control(1, 0); |
782 | mipspmu.write_counter(1, 0); | |
3a9ab99e | 783 | case 1: |
82091564 DD |
784 | mipsxx_pmu_write_control(0, 0); |
785 | mipspmu.write_counter(0, 0); | |
3a9ab99e DCZ |
786 | } |
787 | } | |
788 | ||
3a9ab99e DCZ |
789 | /* 24K/34K/1004K cores can share the same event map. */ |
790 | static const struct mips_perf_event mipsxxcore_event_map | |
791 | [PERF_COUNT_HW_MAX] = { | |
792 | [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P }, | |
793 | [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T }, | |
3a9ab99e DCZ |
794 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x02, CNTR_EVEN, T }, |
795 | [PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T }, | |
3a9ab99e DCZ |
796 | }; |
797 | ||
798 | /* 74K core has different branch event code. */ | |
799 | static const struct mips_perf_event mipsxx74Kcore_event_map | |
800 | [PERF_COUNT_HW_MAX] = { | |
801 | [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P }, | |
802 | [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T }, | |
3a9ab99e DCZ |
803 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x27, CNTR_EVEN, T }, |
804 | [PERF_COUNT_HW_BRANCH_MISSES] = { 0x27, CNTR_ODD, T }, | |
3a9ab99e DCZ |
805 | }; |
806 | ||
939991cf DD |
807 | static const struct mips_perf_event octeon_event_map[PERF_COUNT_HW_MAX] = { |
808 | [PERF_COUNT_HW_CPU_CYCLES] = { 0x01, CNTR_ALL }, | |
809 | [PERF_COUNT_HW_INSTRUCTIONS] = { 0x03, CNTR_ALL }, | |
810 | [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x2b, CNTR_ALL }, | |
811 | [PERF_COUNT_HW_CACHE_MISSES] = { 0x2e, CNTR_ALL }, | |
812 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x08, CNTR_ALL }, | |
813 | [PERF_COUNT_HW_BRANCH_MISSES] = { 0x09, CNTR_ALL }, | |
814 | [PERF_COUNT_HW_BUS_CYCLES] = { 0x25, CNTR_ALL }, | |
815 | }; | |
816 | ||
3a9ab99e DCZ |
817 | /* 24K/34K/1004K cores can share the same cache event map. */ |
818 | static const struct mips_perf_event mipsxxcore_cache_map | |
819 | [PERF_COUNT_HW_CACHE_MAX] | |
820 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
821 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = { | |
822 | [C(L1D)] = { | |
823 | /* | |
824 | * Like some other architectures (e.g. ARM), the performance | |
825 | * counters don't differentiate between read and write | |
826 | * accesses/misses, so this isn't strictly correct, but it's the | |
827 | * best we can do. Writes and reads get combined. | |
828 | */ | |
829 | [C(OP_READ)] = { | |
830 | [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T }, | |
831 | [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T }, | |
832 | }, | |
833 | [C(OP_WRITE)] = { | |
834 | [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T }, | |
835 | [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T }, | |
836 | }, | |
3a9ab99e DCZ |
837 | }, |
838 | [C(L1I)] = { | |
839 | [C(OP_READ)] = { | |
840 | [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T }, | |
841 | [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T }, | |
842 | }, | |
843 | [C(OP_WRITE)] = { | |
844 | [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T }, | |
845 | [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T }, | |
846 | }, | |
847 | [C(OP_PREFETCH)] = { | |
848 | [C(RESULT_ACCESS)] = { 0x14, CNTR_EVEN, T }, | |
849 | /* | |
850 | * Note that MIPS has only "hit" events countable for | |
851 | * the prefetch operation. | |
852 | */ | |
3a9ab99e DCZ |
853 | }, |
854 | }, | |
855 | [C(LL)] = { | |
856 | [C(OP_READ)] = { | |
857 | [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P }, | |
858 | [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P }, | |
859 | }, | |
860 | [C(OP_WRITE)] = { | |
861 | [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P }, | |
862 | [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P }, | |
863 | }, | |
3a9ab99e DCZ |
864 | }, |
865 | [C(DTLB)] = { | |
866 | [C(OP_READ)] = { | |
867 | [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T }, | |
868 | [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T }, | |
869 | }, | |
870 | [C(OP_WRITE)] = { | |
871 | [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T }, | |
872 | [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T }, | |
873 | }, | |
3a9ab99e DCZ |
874 | }, |
875 | [C(ITLB)] = { | |
876 | [C(OP_READ)] = { | |
877 | [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T }, | |
878 | [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T }, | |
879 | }, | |
880 | [C(OP_WRITE)] = { | |
881 | [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T }, | |
882 | [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T }, | |
883 | }, | |
3a9ab99e DCZ |
884 | }, |
885 | [C(BPU)] = { | |
886 | /* Using the same code for *HW_BRANCH* */ | |
887 | [C(OP_READ)] = { | |
888 | [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T }, | |
889 | [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T }, | |
890 | }, | |
891 | [C(OP_WRITE)] = { | |
892 | [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T }, | |
893 | [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T }, | |
894 | }, | |
89d6c0b5 | 895 | }, |
3a9ab99e DCZ |
896 | }; |
897 | ||
898 | /* 74K core has completely different cache event map. */ | |
899 | static const struct mips_perf_event mipsxx74Kcore_cache_map | |
900 | [PERF_COUNT_HW_CACHE_MAX] | |
901 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
902 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = { | |
903 | [C(L1D)] = { | |
904 | /* | |
905 | * Like some other architectures (e.g. ARM), the performance | |
906 | * counters don't differentiate between read and write | |
907 | * accesses/misses, so this isn't strictly correct, but it's the | |
908 | * best we can do. Writes and reads get combined. | |
909 | */ | |
910 | [C(OP_READ)] = { | |
911 | [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T }, | |
912 | [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T }, | |
913 | }, | |
914 | [C(OP_WRITE)] = { | |
915 | [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T }, | |
916 | [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T }, | |
917 | }, | |
3a9ab99e DCZ |
918 | }, |
919 | [C(L1I)] = { | |
920 | [C(OP_READ)] = { | |
921 | [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T }, | |
922 | [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T }, | |
923 | }, | |
924 | [C(OP_WRITE)] = { | |
925 | [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T }, | |
926 | [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T }, | |
927 | }, | |
928 | [C(OP_PREFETCH)] = { | |
929 | [C(RESULT_ACCESS)] = { 0x34, CNTR_EVEN, T }, | |
930 | /* | |
931 | * Note that MIPS has only "hit" events countable for | |
932 | * the prefetch operation. | |
933 | */ | |
3a9ab99e DCZ |
934 | }, |
935 | }, | |
936 | [C(LL)] = { | |
937 | [C(OP_READ)] = { | |
938 | [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P }, | |
939 | [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN | CNTR_ODD, P }, | |
940 | }, | |
941 | [C(OP_WRITE)] = { | |
942 | [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P }, | |
943 | [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN | CNTR_ODD, P }, | |
944 | }, | |
3a9ab99e DCZ |
945 | }, |
946 | [C(ITLB)] = { | |
947 | [C(OP_READ)] = { | |
948 | [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T }, | |
949 | [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T }, | |
950 | }, | |
951 | [C(OP_WRITE)] = { | |
952 | [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T }, | |
953 | [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T }, | |
954 | }, | |
3a9ab99e DCZ |
955 | }, |
956 | [C(BPU)] = { | |
957 | /* Using the same code for *HW_BRANCH* */ | |
958 | [C(OP_READ)] = { | |
959 | [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T }, | |
960 | [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T }, | |
961 | }, | |
962 | [C(OP_WRITE)] = { | |
963 | [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T }, | |
964 | [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T }, | |
965 | }, | |
89d6c0b5 | 966 | }, |
3a9ab99e DCZ |
967 | }; |
968 | ||
939991cf DD |
969 | |
970 | static const struct mips_perf_event octeon_cache_map | |
971 | [PERF_COUNT_HW_CACHE_MAX] | |
972 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
973 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = { | |
974 | [C(L1D)] = { | |
975 | [C(OP_READ)] = { | |
976 | [C(RESULT_ACCESS)] = { 0x2b, CNTR_ALL }, | |
977 | [C(RESULT_MISS)] = { 0x2e, CNTR_ALL }, | |
978 | }, | |
979 | [C(OP_WRITE)] = { | |
980 | [C(RESULT_ACCESS)] = { 0x30, CNTR_ALL }, | |
939991cf DD |
981 | }, |
982 | }, | |
983 | [C(L1I)] = { | |
984 | [C(OP_READ)] = { | |
985 | [C(RESULT_ACCESS)] = { 0x18, CNTR_ALL }, | |
939991cf DD |
986 | }, |
987 | [C(OP_PREFETCH)] = { | |
988 | [C(RESULT_ACCESS)] = { 0x19, CNTR_ALL }, | |
939991cf DD |
989 | }, |
990 | }, | |
991 | [C(DTLB)] = { | |
992 | /* | |
993 | * Only general DTLB misses are counted use the same event for | |
994 | * read and write. | |
995 | */ | |
996 | [C(OP_READ)] = { | |
939991cf DD |
997 | [C(RESULT_MISS)] = { 0x35, CNTR_ALL }, |
998 | }, | |
999 | [C(OP_WRITE)] = { | |
939991cf DD |
1000 | [C(RESULT_MISS)] = { 0x35, CNTR_ALL }, |
1001 | }, | |
939991cf DD |
1002 | }, |
1003 | [C(ITLB)] = { | |
1004 | [C(OP_READ)] = { | |
939991cf DD |
1005 | [C(RESULT_MISS)] = { 0x37, CNTR_ALL }, |
1006 | }, | |
939991cf DD |
1007 | }, |
1008 | }; | |
1009 | ||
3a9ab99e | 1010 | #ifdef CONFIG_MIPS_MT_SMP |
4409af37 DD |
1011 | static void check_and_calc_range(struct perf_event *event, |
1012 | const struct mips_perf_event *pev) | |
3a9ab99e DCZ |
1013 | { |
1014 | struct hw_perf_event *hwc = &event->hw; | |
1015 | ||
1016 | if (event->cpu >= 0) { | |
1017 | if (pev->range > V) { | |
1018 | /* | |
1019 | * The user selected an event that is processor | |
1020 | * wide, while expecting it to be VPE wide. | |
1021 | */ | |
1022 | hwc->config_base |= M_TC_EN_ALL; | |
1023 | } else { | |
1024 | /* | |
1025 | * FIXME: cpu_data[event->cpu].vpe_id reports 0 | |
1026 | * for both CPUs. | |
1027 | */ | |
1028 | hwc->config_base |= M_PERFCTL_VPEID(event->cpu); | |
1029 | hwc->config_base |= M_TC_EN_VPE; | |
1030 | } | |
1031 | } else | |
1032 | hwc->config_base |= M_TC_EN_ALL; | |
1033 | } | |
1034 | #else | |
4409af37 DD |
1035 | static void check_and_calc_range(struct perf_event *event, |
1036 | const struct mips_perf_event *pev) | |
3a9ab99e DCZ |
1037 | { |
1038 | } | |
1039 | #endif | |
1040 | ||
1041 | static int __hw_perf_event_init(struct perf_event *event) | |
1042 | { | |
1043 | struct perf_event_attr *attr = &event->attr; | |
1044 | struct hw_perf_event *hwc = &event->hw; | |
1045 | const struct mips_perf_event *pev; | |
1046 | int err; | |
1047 | ||
1048 | /* Returning MIPS event descriptor for generic perf event. */ | |
1049 | if (PERF_TYPE_HARDWARE == event->attr.type) { | |
1050 | if (event->attr.config >= PERF_COUNT_HW_MAX) | |
1051 | return -EINVAL; | |
1052 | pev = mipspmu_map_general_event(event->attr.config); | |
1053 | } else if (PERF_TYPE_HW_CACHE == event->attr.type) { | |
1054 | pev = mipspmu_map_cache_event(event->attr.config); | |
1055 | } else if (PERF_TYPE_RAW == event->attr.type) { | |
1056 | /* We are working on the global raw event. */ | |
1057 | mutex_lock(&raw_event_mutex); | |
82091564 | 1058 | pev = mipspmu.map_raw_event(event->attr.config); |
3a9ab99e DCZ |
1059 | } else { |
1060 | /* The event type is not (yet) supported. */ | |
1061 | return -EOPNOTSUPP; | |
1062 | } | |
1063 | ||
1064 | if (IS_ERR(pev)) { | |
1065 | if (PERF_TYPE_RAW == event->attr.type) | |
1066 | mutex_unlock(&raw_event_mutex); | |
1067 | return PTR_ERR(pev); | |
1068 | } | |
1069 | ||
1070 | /* | |
1071 | * We allow max flexibility on how each individual counter shared | |
1072 | * by the single CPU operates (the mode exclusion and the range). | |
1073 | */ | |
1074 | hwc->config_base = M_PERFCTL_INTERRUPT_ENABLE; | |
1075 | ||
1076 | /* Calculate range bits and validate it. */ | |
1077 | if (num_possible_cpus() > 1) | |
1078 | check_and_calc_range(event, pev); | |
1079 | ||
1080 | hwc->event_base = mipspmu_perf_event_encode(pev); | |
1081 | if (PERF_TYPE_RAW == event->attr.type) | |
1082 | mutex_unlock(&raw_event_mutex); | |
1083 | ||
1084 | if (!attr->exclude_user) | |
1085 | hwc->config_base |= M_PERFCTL_USER; | |
1086 | if (!attr->exclude_kernel) { | |
1087 | hwc->config_base |= M_PERFCTL_KERNEL; | |
1088 | /* MIPS kernel mode: KSU == 00b || EXL == 1 || ERL == 1 */ | |
1089 | hwc->config_base |= M_PERFCTL_EXL; | |
1090 | } | |
1091 | if (!attr->exclude_hv) | |
1092 | hwc->config_base |= M_PERFCTL_SUPERVISOR; | |
1093 | ||
1094 | hwc->config_base &= M_PERFCTL_CONFIG_MASK; | |
1095 | /* | |
1096 | * The event can belong to another cpu. We do not assign a local | |
1097 | * counter for it for now. | |
1098 | */ | |
1099 | hwc->idx = -1; | |
1100 | hwc->config = 0; | |
1101 | ||
1102 | if (!hwc->sample_period) { | |
82091564 | 1103 | hwc->sample_period = mipspmu.max_period; |
3a9ab99e DCZ |
1104 | hwc->last_period = hwc->sample_period; |
1105 | local64_set(&hwc->period_left, hwc->sample_period); | |
1106 | } | |
1107 | ||
1108 | err = 0; | |
ff5d7265 | 1109 | if (event->group_leader != event) |
3a9ab99e | 1110 | err = validate_group(event); |
3a9ab99e DCZ |
1111 | |
1112 | event->destroy = hw_perf_event_destroy; | |
ff5d7265 DCZ |
1113 | |
1114 | if (err) | |
1115 | event->destroy(event); | |
1116 | ||
3a9ab99e DCZ |
1117 | return err; |
1118 | } | |
1119 | ||
1120 | static void pause_local_counters(void) | |
1121 | { | |
1122 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
82091564 | 1123 | int ctr = mipspmu.num_counters; |
3a9ab99e DCZ |
1124 | unsigned long flags; |
1125 | ||
1126 | local_irq_save(flags); | |
82091564 DD |
1127 | do { |
1128 | ctr--; | |
1129 | cpuc->saved_ctrl[ctr] = mipsxx_pmu_read_control(ctr); | |
1130 | mipsxx_pmu_write_control(ctr, cpuc->saved_ctrl[ctr] & | |
1131 | ~M_PERFCTL_COUNT_EVENT_WHENEVER); | |
1132 | } while (ctr > 0); | |
3a9ab99e DCZ |
1133 | local_irq_restore(flags); |
1134 | } | |
1135 | ||
1136 | static void resume_local_counters(void) | |
1137 | { | |
1138 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
82091564 | 1139 | int ctr = mipspmu.num_counters; |
3a9ab99e | 1140 | |
82091564 DD |
1141 | do { |
1142 | ctr--; | |
1143 | mipsxx_pmu_write_control(ctr, cpuc->saved_ctrl[ctr]); | |
1144 | } while (ctr > 0); | |
3a9ab99e DCZ |
1145 | } |
1146 | ||
1147 | static int mipsxx_pmu_handle_shared_irq(void) | |
1148 | { | |
1149 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1150 | struct perf_sample_data data; | |
82091564 DD |
1151 | unsigned int counters = mipspmu.num_counters; |
1152 | u64 counter; | |
3a9ab99e DCZ |
1153 | int handled = IRQ_NONE; |
1154 | struct pt_regs *regs; | |
1155 | ||
da4b62cd | 1156 | if (cpu_has_perf_cntr_intr_bit && !(read_c0_cause() & CAUSEF_PCI)) |
3a9ab99e | 1157 | return handled; |
3a9ab99e DCZ |
1158 | /* |
1159 | * First we pause the local counters, so that when we are locked | |
1160 | * here, the counters are all paused. When it gets locked due to | |
1161 | * perf_disable(), the timer interrupt handler will be delayed. | |
1162 | * | |
1163 | * See also mipsxx_pmu_start(). | |
1164 | */ | |
1165 | pause_local_counters(); | |
1166 | #ifdef CONFIG_MIPS_MT_SMP | |
1167 | read_lock(&pmuint_rwlock); | |
1168 | #endif | |
1169 | ||
1170 | regs = get_irq_regs(); | |
1171 | ||
fd0d000b | 1172 | perf_sample_data_init(&data, 0, 0); |
3a9ab99e DCZ |
1173 | |
1174 | switch (counters) { | |
1175 | #define HANDLE_COUNTER(n) \ | |
1176 | case n + 1: \ | |
1177 | if (test_bit(n, cpuc->used_mask)) { \ | |
82091564 DD |
1178 | counter = mipspmu.read_counter(n); \ |
1179 | if (counter & mipspmu.overflow) { \ | |
1180 | handle_associated_event(cpuc, n, &data, regs); \ | |
3a9ab99e DCZ |
1181 | handled = IRQ_HANDLED; \ |
1182 | } \ | |
1183 | } | |
1184 | HANDLE_COUNTER(3) | |
1185 | HANDLE_COUNTER(2) | |
1186 | HANDLE_COUNTER(1) | |
1187 | HANDLE_COUNTER(0) | |
1188 | } | |
1189 | ||
1190 | /* | |
1191 | * Do all the work for the pending perf events. We can do this | |
1192 | * in here because the performance counter interrupt is a regular | |
1193 | * interrupt, not NMI. | |
1194 | */ | |
1195 | if (handled == IRQ_HANDLED) | |
91f01737 | 1196 | irq_work_run(); |
3a9ab99e DCZ |
1197 | |
1198 | #ifdef CONFIG_MIPS_MT_SMP | |
1199 | read_unlock(&pmuint_rwlock); | |
1200 | #endif | |
1201 | resume_local_counters(); | |
1202 | return handled; | |
1203 | } | |
1204 | ||
4409af37 | 1205 | static irqreturn_t mipsxx_pmu_handle_irq(int irq, void *dev) |
3a9ab99e DCZ |
1206 | { |
1207 | return mipsxx_pmu_handle_shared_irq(); | |
1208 | } | |
1209 | ||
3a9ab99e | 1210 | /* 24K */ |
3a9ab99e DCZ |
1211 | #define IS_BOTH_COUNTERS_24K_EVENT(b) \ |
1212 | ((b) == 0 || (b) == 1 || (b) == 11) | |
1213 | ||
1214 | /* 34K */ | |
3a9ab99e DCZ |
1215 | #define IS_BOTH_COUNTERS_34K_EVENT(b) \ |
1216 | ((b) == 0 || (b) == 1 || (b) == 11) | |
1217 | #ifdef CONFIG_MIPS_MT_SMP | |
1218 | #define IS_RANGE_P_34K_EVENT(r, b) \ | |
1219 | ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 || \ | |
1220 | (b) == 25 || (b) == 39 || (r) == 44 || (r) == 174 || \ | |
1221 | (r) == 176 || ((b) >= 50 && (b) <= 55) || \ | |
1222 | ((b) >= 64 && (b) <= 67)) | |
1223 | #define IS_RANGE_V_34K_EVENT(r) ((r) == 47) | |
1224 | #endif | |
1225 | ||
1226 | /* 74K */ | |
3a9ab99e DCZ |
1227 | #define IS_BOTH_COUNTERS_74K_EVENT(b) \ |
1228 | ((b) == 0 || (b) == 1) | |
1229 | ||
1230 | /* 1004K */ | |
3a9ab99e DCZ |
1231 | #define IS_BOTH_COUNTERS_1004K_EVENT(b) \ |
1232 | ((b) == 0 || (b) == 1 || (b) == 11) | |
1233 | #ifdef CONFIG_MIPS_MT_SMP | |
1234 | #define IS_RANGE_P_1004K_EVENT(r, b) \ | |
1235 | ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 || \ | |
1236 | (b) == 25 || (b) == 36 || (b) == 39 || (r) == 44 || \ | |
1237 | (r) == 174 || (r) == 176 || ((b) >= 50 && (b) <= 59) || \ | |
1238 | (r) == 188 || (b) == 61 || (b) == 62 || \ | |
1239 | ((b) >= 64 && (b) <= 67)) | |
1240 | #define IS_RANGE_V_1004K_EVENT(r) ((r) == 47) | |
1241 | #endif | |
1242 | ||
1243 | /* | |
1244 | * User can use 0-255 raw events, where 0-127 for the events of even | |
1245 | * counters, and 128-255 for odd counters. Note that bit 7 is used to | |
1246 | * indicate the parity. So, for example, when user wants to take the | |
1247 | * Event Num of 15 for odd counters (by referring to the user manual), | |
1248 | * then 128 needs to be added to 15 as the input for the event config, | |
1249 | * i.e., 143 (0x8F) to be used. | |
1250 | */ | |
4409af37 | 1251 | static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config) |
3a9ab99e DCZ |
1252 | { |
1253 | unsigned int raw_id = config & 0xff; | |
1254 | unsigned int base_id = raw_id & 0x7f; | |
1255 | ||
2c1b54d3 DCZ |
1256 | raw_event.event_id = base_id; |
1257 | ||
3a9ab99e DCZ |
1258 | switch (current_cpu_type()) { |
1259 | case CPU_24K: | |
3a9ab99e DCZ |
1260 | if (IS_BOTH_COUNTERS_24K_EVENT(base_id)) |
1261 | raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; | |
1262 | else | |
1263 | raw_event.cntr_mask = | |
1264 | raw_id > 127 ? CNTR_ODD : CNTR_EVEN; | |
1265 | #ifdef CONFIG_MIPS_MT_SMP | |
1266 | /* | |
1267 | * This is actually doing nothing. Non-multithreading | |
1268 | * CPUs will not check and calculate the range. | |
1269 | */ | |
1270 | raw_event.range = P; | |
1271 | #endif | |
1272 | break; | |
1273 | case CPU_34K: | |
3a9ab99e DCZ |
1274 | if (IS_BOTH_COUNTERS_34K_EVENT(base_id)) |
1275 | raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; | |
1276 | else | |
1277 | raw_event.cntr_mask = | |
1278 | raw_id > 127 ? CNTR_ODD : CNTR_EVEN; | |
1279 | #ifdef CONFIG_MIPS_MT_SMP | |
1280 | if (IS_RANGE_P_34K_EVENT(raw_id, base_id)) | |
1281 | raw_event.range = P; | |
1282 | else if (unlikely(IS_RANGE_V_34K_EVENT(raw_id))) | |
1283 | raw_event.range = V; | |
1284 | else | |
1285 | raw_event.range = T; | |
1286 | #endif | |
1287 | break; | |
1288 | case CPU_74K: | |
3a9ab99e DCZ |
1289 | if (IS_BOTH_COUNTERS_74K_EVENT(base_id)) |
1290 | raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; | |
1291 | else | |
1292 | raw_event.cntr_mask = | |
1293 | raw_id > 127 ? CNTR_ODD : CNTR_EVEN; | |
1294 | #ifdef CONFIG_MIPS_MT_SMP | |
1295 | raw_event.range = P; | |
1296 | #endif | |
1297 | break; | |
1298 | case CPU_1004K: | |
3a9ab99e DCZ |
1299 | if (IS_BOTH_COUNTERS_1004K_EVENT(base_id)) |
1300 | raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; | |
1301 | else | |
1302 | raw_event.cntr_mask = | |
1303 | raw_id > 127 ? CNTR_ODD : CNTR_EVEN; | |
1304 | #ifdef CONFIG_MIPS_MT_SMP | |
1305 | if (IS_RANGE_P_1004K_EVENT(raw_id, base_id)) | |
1306 | raw_event.range = P; | |
1307 | else if (unlikely(IS_RANGE_V_1004K_EVENT(raw_id))) | |
1308 | raw_event.range = V; | |
1309 | else | |
1310 | raw_event.range = T; | |
1311 | #endif | |
1312 | break; | |
1313 | } | |
1314 | ||
1315 | return &raw_event; | |
1316 | } | |
1317 | ||
939991cf DD |
1318 | static const struct mips_perf_event *octeon_pmu_map_raw_event(u64 config) |
1319 | { | |
1320 | unsigned int raw_id = config & 0xff; | |
1321 | unsigned int base_id = raw_id & 0x7f; | |
1322 | ||
1323 | ||
1324 | raw_event.cntr_mask = CNTR_ALL; | |
1325 | raw_event.event_id = base_id; | |
1326 | ||
1327 | if (current_cpu_type() == CPU_CAVIUM_OCTEON2) { | |
1328 | if (base_id > 0x42) | |
1329 | return ERR_PTR(-EOPNOTSUPP); | |
1330 | } else { | |
1331 | if (base_id > 0x3a) | |
1332 | return ERR_PTR(-EOPNOTSUPP); | |
1333 | } | |
1334 | ||
1335 | switch (base_id) { | |
1336 | case 0x00: | |
1337 | case 0x0f: | |
1338 | case 0x1e: | |
1339 | case 0x1f: | |
1340 | case 0x2f: | |
1341 | case 0x34: | |
1342 | case 0x3b ... 0x3f: | |
1343 | return ERR_PTR(-EOPNOTSUPP); | |
1344 | default: | |
1345 | break; | |
1346 | } | |
1347 | ||
1348 | return &raw_event; | |
1349 | } | |
1350 | ||
3a9ab99e DCZ |
1351 | static int __init |
1352 | init_hw_perf_events(void) | |
1353 | { | |
1354 | int counters, irq; | |
82091564 | 1355 | int counter_bits; |
3a9ab99e DCZ |
1356 | |
1357 | pr_info("Performance counters: "); | |
1358 | ||
1359 | counters = n_counters(); | |
1360 | if (counters == 0) { | |
1361 | pr_cont("No available PMU.\n"); | |
1362 | return -ENODEV; | |
1363 | } | |
1364 | ||
1365 | #ifdef CONFIG_MIPS_MT_SMP | |
1366 | cpu_has_mipsmt_pertccounters = read_c0_config7() & (1<<19); | |
1367 | if (!cpu_has_mipsmt_pertccounters) | |
1368 | counters = counters_total_to_per_cpu(counters); | |
1369 | #endif | |
1370 | ||
1371 | #ifdef MSC01E_INT_BASE | |
1372 | if (cpu_has_veic) { | |
1373 | /* | |
1374 | * Using platform specific interrupt controller defines. | |
1375 | */ | |
1376 | irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR; | |
1377 | } else { | |
1378 | #endif | |
3572a2c3 FF |
1379 | if ((cp0_perfcount_irq >= 0) && |
1380 | (cp0_compare_irq != cp0_perfcount_irq)) | |
3a9ab99e DCZ |
1381 | irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; |
1382 | else | |
1383 | irq = -1; | |
1384 | #ifdef MSC01E_INT_BASE | |
1385 | } | |
1386 | #endif | |
1387 | ||
82091564 | 1388 | mipspmu.map_raw_event = mipsxx_pmu_map_raw_event; |
3a9ab99e DCZ |
1389 | |
1390 | switch (current_cpu_type()) { | |
1391 | case CPU_24K: | |
82091564 DD |
1392 | mipspmu.name = "mips/24K"; |
1393 | mipspmu.general_event_map = &mipsxxcore_event_map; | |
1394 | mipspmu.cache_event_map = &mipsxxcore_cache_map; | |
3a9ab99e DCZ |
1395 | break; |
1396 | case CPU_34K: | |
82091564 DD |
1397 | mipspmu.name = "mips/34K"; |
1398 | mipspmu.general_event_map = &mipsxxcore_event_map; | |
1399 | mipspmu.cache_event_map = &mipsxxcore_cache_map; | |
3a9ab99e DCZ |
1400 | break; |
1401 | case CPU_74K: | |
82091564 DD |
1402 | mipspmu.name = "mips/74K"; |
1403 | mipspmu.general_event_map = &mipsxx74Kcore_event_map; | |
1404 | mipspmu.cache_event_map = &mipsxx74Kcore_cache_map; | |
3a9ab99e DCZ |
1405 | break; |
1406 | case CPU_1004K: | |
82091564 DD |
1407 | mipspmu.name = "mips/1004K"; |
1408 | mipspmu.general_event_map = &mipsxxcore_event_map; | |
1409 | mipspmu.cache_event_map = &mipsxxcore_cache_map; | |
3a9ab99e | 1410 | break; |
2fa36399 KC |
1411 | case CPU_LOONGSON1: |
1412 | mipspmu.name = "mips/loongson1"; | |
1413 | mipspmu.general_event_map = &mipsxxcore_event_map; | |
1414 | mipspmu.cache_event_map = &mipsxxcore_cache_map; | |
1415 | break; | |
939991cf DD |
1416 | case CPU_CAVIUM_OCTEON: |
1417 | case CPU_CAVIUM_OCTEON_PLUS: | |
1418 | case CPU_CAVIUM_OCTEON2: | |
1419 | mipspmu.name = "octeon"; | |
1420 | mipspmu.general_event_map = &octeon_event_map; | |
1421 | mipspmu.cache_event_map = &octeon_cache_map; | |
1422 | mipspmu.map_raw_event = octeon_pmu_map_raw_event; | |
1423 | break; | |
3a9ab99e DCZ |
1424 | default: |
1425 | pr_cont("Either hardware does not support performance " | |
1426 | "counters, or not yet implemented.\n"); | |
1427 | return -ENODEV; | |
1428 | } | |
1429 | ||
82091564 DD |
1430 | mipspmu.num_counters = counters; |
1431 | mipspmu.irq = irq; | |
1432 | ||
1433 | if (read_c0_perfctrl0() & M_PERFCTL_WIDE) { | |
1434 | mipspmu.max_period = (1ULL << 63) - 1; | |
1435 | mipspmu.valid_count = (1ULL << 63) - 1; | |
1436 | mipspmu.overflow = 1ULL << 63; | |
1437 | mipspmu.read_counter = mipsxx_pmu_read_counter_64; | |
1438 | mipspmu.write_counter = mipsxx_pmu_write_counter_64; | |
1439 | counter_bits = 64; | |
1440 | } else { | |
1441 | mipspmu.max_period = (1ULL << 31) - 1; | |
1442 | mipspmu.valid_count = (1ULL << 31) - 1; | |
1443 | mipspmu.overflow = 1ULL << 31; | |
1444 | mipspmu.read_counter = mipsxx_pmu_read_counter; | |
1445 | mipspmu.write_counter = mipsxx_pmu_write_counter; | |
1446 | counter_bits = 32; | |
1447 | } | |
1448 | ||
1449 | on_each_cpu(reset_counters, (void *)(long)counters, 1); | |
1450 | ||
1451 | pr_cont("%s PMU enabled, %d %d-bit counters available to each " | |
1452 | "CPU, irq %d%s\n", mipspmu.name, counters, counter_bits, irq, | |
1453 | irq < 0 ? " (share with timer interrupt)" : ""); | |
3a9ab99e | 1454 | |
404ff638 DCZ |
1455 | perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); |
1456 | ||
3a9ab99e DCZ |
1457 | return 0; |
1458 | } | |
004417a6 | 1459 | early_initcall(init_hw_perf_events); |