[linux-2.6-block.git] / arch / mips / kernel / mips-cm.c

/*
 * Copyright (C) 2013 Imagination Technologies
 * Author: Paul Burton <paul.burton@imgtec.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <linux/errno.h>
#include <linux/percpu.h>
#include <linux/spinlock.h>

#include <asm/mips-cm.h>
#include <asm/mipsregs.h>

void __iomem *mips_gcr_base;
void __iomem *mips_cm_l2sync_base;
int mips_cm_is64;

static char *cm2_tr[8] = {
	"mem",	"gcr",	"gic",	"mmio",
	"0x04", "cpc", "0x06", "0x07"
};

/* CM3 Tag ECC transaction type */
static char *cm3_tr[16] = {
	[0x0] = "ReqNoData",
	[0x1] = "0x1",
	[0x2] = "ReqWData",
	[0x3] = "0x3",
	[0x4] = "IReqNoResp",
	[0x5] = "IReqWResp",
	[0x6] = "IReqNoRespDat",
	[0x7] = "IReqWRespDat",
	[0x8] = "RespNoData",
	[0x9] = "RespDataFol",
	[0xa] = "RespWData",
	[0xb] = "RespDataOnly",
	[0xc] = "IRespNoData",
	[0xd] = "IRespDataFol",
	[0xe] = "IRespWData",
	[0xf] = "IRespDataOnly"
};

static char *cm2_cmd[32] = {
	[0x00] = "0x00",
	[0x01] = "Legacy Write",
	[0x02] = "Legacy Read",
	[0x03] = "0x03",
	[0x04] = "0x04",
	[0x05] = "0x05",
	[0x06] = "0x06",
	[0x07] = "0x07",
	[0x08] = "Coherent Read Own",
	[0x09] = "Coherent Read Share",
	[0x0a] = "Coherent Read Discard",
	[0x0b] = "Coherent Ready Share Always",
	[0x0c] = "Coherent Upgrade",
	[0x0d] = "Coherent Writeback",
	[0x0e] = "0x0e",
	[0x0f] = "0x0f",
	[0x10] = "Coherent Copyback",
	[0x11] = "Coherent Copyback Invalidate",
	[0x12] = "Coherent Invalidate",
	[0x13] = "Coherent Write Invalidate",
	[0x14] = "Coherent Completion Sync",
	[0x15] = "0x15",
	[0x16] = "0x16",
	[0x17] = "0x17",
	[0x18] = "0x18",
	[0x19] = "0x19",
	[0x1a] = "0x1a",
	[0x1b] = "0x1b",
	[0x1c] = "0x1c",
	[0x1d] = "0x1d",
	[0x1e] = "0x1e",
	[0x1f] = "0x1f"
};

/* CM3 Tag ECC command type */
static char *cm3_cmd[16] = {
	[0x0] = "Legacy Read",
	[0x1] = "Legacy Write",
	[0x2] = "Coherent Read Own",
	[0x3] = "Coherent Read Share",
	[0x4] = "Coherent Read Discard",
	[0x5] = "Coherent Evicted",
	[0x6] = "Coherent Upgrade",
	[0x7] = "Coherent Upgrade for Store Conditional",
	[0x8] = "Coherent Writeback",
	[0x9] = "Coherent Write Invalidate",
	[0xa] = "0xa",
	[0xb] = "0xb",
	[0xc] = "0xc",
	[0xd] = "0xd",
	[0xe] = "0xe",
	[0xf] = "0xf"
};

/* CM3 Tag ECC command group */
static char *cm3_cmd_group[8] = {
	[0x0] = "Normal",
	[0x1] = "Registers",
	[0x2] = "TLB",
	[0x3] = "0x3",
	[0x4] = "L1I",
	[0x5] = "L1D",
	[0x6] = "L3",
	[0x7] = "L2"
};

static char *cm2_core[8] = {
	"Invalid/OK",	"Invalid/Data",
	"Shared/OK",	"Shared/Data",
	"Modified/OK",	"Modified/Data",
	"Exclusive/OK", "Exclusive/Data"
};

static char *cm2_causes[32] = {
	"None", "GC_WR_ERR", "GC_RD_ERR", "COH_WR_ERR",
	"COH_RD_ERR", "MMIO_WR_ERR", "MMIO_RD_ERR", "0x07",
	"0x08", "0x09", "0x0a", "0x0b",
	"0x0c", "0x0d", "0x0e", "0x0f",
	"0x10", "0x11", "0x12", "0x13",
	"0x14", "0x15", "0x16", "INTVN_WR_ERR",
	"INTVN_RD_ERR", "0x19", "0x1a", "0x1b",
	"0x1c", "0x1d", "0x1e", "0x1f"
};

static char *cm3_causes[32] = {
	"0x0", "MP_CORRECTABLE_ECC_ERR", "MP_REQUEST_DECODE_ERR",
	"MP_UNCORRECTABLE_ECC_ERR", "MP_PARITY_ERR", "MP_COHERENCE_ERR",
	"CMBIU_REQUEST_DECODE_ERR", "CMBIU_PARITY_ERR", "CMBIU_AXI_RESP_ERR",
	"0x9", "RBI_BUS_ERR", "0xb", "0xc", "0xd", "0xe", "0xf", "0x10",
	"0x11", "0x12", "0x13", "0x14", "0x15", "0x16", "0x17", "0x18",
	"0x19", "0x1a", "0x1b", "0x1c", "0x1d", "0x1e", "0x1f"
};

static DEFINE_PER_CPU_ALIGNED(spinlock_t, cm_core_lock);
static DEFINE_PER_CPU_ALIGNED(unsigned long, cm_core_lock_flags);

phys_addr_t __mips_cm_phys_base(void)
{
	u32 config3 = read_c0_config3();
	unsigned long cmgcr;

	/* Check the CMGCRBase register is implemented */
	if (!(config3 & MIPS_CONF3_CMGCR))
		return 0;

	/* Read the address from CMGCRBase */
	cmgcr = read_c0_cmgcrbase();
	return (cmgcr & MIPS_CMGCRF_BASE) << (36 - 32);
}

phys_addr_t mips_cm_phys_base(void)
	__attribute__((weak, alias("__mips_cm_phys_base")));

phys_addr_t __mips_cm_l2sync_phys_base(void)
{
	u32 base_reg;

	/*
	 * If the L2-only sync region is already enabled then leave it at it's
	 * current location.
	 */
	base_reg = read_gcr_l2_only_sync_base();
	if (base_reg & CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN_MSK)
		return base_reg & CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE_MSK;

	/* Default to following the CM */
	return mips_cm_phys_base() + MIPS_CM_GCR_SIZE;
}

phys_addr_t mips_cm_l2sync_phys_base(void)
	__attribute__((weak, alias("__mips_cm_l2sync_phys_base")));

static void mips_cm_probe_l2sync(void)
{
	unsigned major_rev;
	phys_addr_t addr;

	/* L2-only sync was introduced with CM major revision 6 */
	major_rev = (read_gcr_rev() & CM_GCR_REV_MAJOR_MSK) >>
		CM_GCR_REV_MAJOR_SHF;
	if (major_rev < 6)
		return;

	/* Find a location for the L2 sync region */
	addr = mips_cm_l2sync_phys_base();
	BUG_ON((addr & CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE_MSK) != addr);
	if (!addr)
		return;

	/* Set the region base address & enable it */
	write_gcr_l2_only_sync_base(addr | CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN_MSK);

	/* Map the region */
	mips_cm_l2sync_base = ioremap_nocache(addr, MIPS_CM_L2SYNC_SIZE);
}

int mips_cm_probe(void)
{
	phys_addr_t addr;
	u32 base_reg;
	unsigned cpu;

	/*
	 * No need to probe again if we have already been
	 * here before.
	 */
	if (mips_gcr_base)
		return 0;

	addr = mips_cm_phys_base();
	BUG_ON((addr & CM_GCR_BASE_GCRBASE_MSK) != addr);
	if (!addr)
		return -ENODEV;

	mips_gcr_base = ioremap_nocache(addr, MIPS_CM_GCR_SIZE);
	if (!mips_gcr_base)
		return -ENXIO;

	/* sanity check that we're looking at a CM */
	base_reg = read_gcr_base();
	if ((base_reg & CM_GCR_BASE_GCRBASE_MSK) != addr) {
		pr_err("GCRs appear to have been moved (expected them at 0x%08lx)!\n",
		       (unsigned long)addr);
		mips_gcr_base = NULL;
		return -ENODEV;
	}

	/* set default target to memory */
	base_reg &= ~CM_GCR_BASE_CMDEFTGT_MSK;
	base_reg |= CM_GCR_BASE_CMDEFTGT_MEM;
	write_gcr_base(base_reg);

	/* disable CM regions */
	write_gcr_reg0_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
	write_gcr_reg0_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
	write_gcr_reg1_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
	write_gcr_reg1_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
	write_gcr_reg2_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
	write_gcr_reg2_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
	write_gcr_reg3_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
	write_gcr_reg3_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);

	/* probe for an L2-only sync region */
	mips_cm_probe_l2sync();

	/* determine register width for this CM */
	mips_cm_is64 = IS_ENABLED(CONFIG_64BIT) && (mips_cm_revision() >= CM_REV_CM3);

	for_each_possible_cpu(cpu)
		spin_lock_init(&per_cpu(cm_core_lock, cpu));

	return 0;
}

void mips_cm_lock_other(unsigned int core, unsigned int vp)
{
	unsigned curr_core;
	u32 val;

	preempt_disable();

	if (mips_cm_revision() >= CM_REV_CM3) {
		val = core << CM3_GCR_Cx_OTHER_CORE_SHF;
		val |= vp << CM3_GCR_Cx_OTHER_VP_SHF;

		/*
		 * We need to disable interrupts in SMP systems in order to
		 * ensure that we don't interrupt the caller with code which
		 * may modify the redirect register. We do so here in a
		 * slightly obscure way by using a spin lock, since this has
		 * the neat property of also catching any nested uses of
		 * mips_cm_lock_other() leading to a deadlock or a nice warning
		 * with lockdep enabled.
		 */
		spin_lock_irqsave(this_cpu_ptr(&cm_core_lock),
				  *this_cpu_ptr(&cm_core_lock_flags));
	} else {
		WARN_ON(vp != 0);

		/*
		 * We only have a GCR_CL_OTHER per core in systems with
		 * CM 2.5 & older, so have to ensure other VP(E)s don't
		 * race with us.
		 */
		curr_core = current_cpu_data.core;
		spin_lock_irqsave(&per_cpu(cm_core_lock, curr_core),
				  per_cpu(cm_core_lock_flags, curr_core));

		val = core << CM_GCR_Cx_OTHER_CORENUM_SHF;
	}

	write_gcr_cl_other(val);

	/*
	 * Ensure the core-other region reflects the appropriate core &
	 * VP before any accesses to it occur.
	 */
	mb();
}

void mips_cm_unlock_other(void)
{
	unsigned int curr_core;

	if (mips_cm_revision() < CM_REV_CM3) {
		curr_core = current_cpu_data.core;
		spin_unlock_irqrestore(&per_cpu(cm_core_lock, curr_core),
				       per_cpu(cm_core_lock_flags, curr_core));
	} else {
		spin_unlock_irqrestore(this_cpu_ptr(&cm_core_lock),
				       *this_cpu_ptr(&cm_core_lock_flags));
	}

	preempt_enable();
}

void mips_cm_error_report(void)
{
	u64 cm_error, cm_addr, cm_other;
	unsigned long revision;
	int ocause, cause;
	char buf[256];

	if (!mips_cm_present())
		return;

	revision = mips_cm_revision();
	cm_error = read_gcr_error_cause();
	cm_addr = read_gcr_error_addr();
	cm_other = read_gcr_error_mult();

	if (revision < CM_REV_CM3) { /* CM2 */
		cause = cm_error >> CM_GCR_ERROR_CAUSE_ERRTYPE_SHF;
		ocause = cm_other >> CM_GCR_ERROR_MULT_ERR2ND_SHF;

		if (!cause)
			return;

		if (cause < 16) {
			unsigned long cca_bits = (cm_error >> 15) & 7;
			unsigned long tr_bits = (cm_error >> 12) & 7;
			unsigned long cmd_bits = (cm_error >> 7) & 0x1f;
			unsigned long stag_bits = (cm_error >> 3) & 15;
			unsigned long sport_bits = (cm_error >> 0) & 7;

			snprintf(buf, sizeof(buf),
				 "CCA=%lu TR=%s MCmd=%s STag=%lu "
				 "SPort=%lu\n", cca_bits, cm2_tr[tr_bits],
				 cm2_cmd[cmd_bits], stag_bits, sport_bits);
		} else {
			/* glob state & sresp together */
			unsigned long c3_bits = (cm_error >> 18) & 7;
			unsigned long c2_bits = (cm_error >> 15) & 7;
			unsigned long c1_bits = (cm_error >> 12) & 7;
			unsigned long c0_bits = (cm_error >> 9) & 7;
			unsigned long sc_bit = (cm_error >> 8) & 1;
			unsigned long cmd_bits = (cm_error >> 3) & 0x1f;
			unsigned long sport_bits = (cm_error >> 0) & 7;

			snprintf(buf, sizeof(buf),
				 "C3=%s C2=%s C1=%s C0=%s SC=%s "
				 "MCmd=%s SPort=%lu\n",
				 cm2_core[c3_bits], cm2_core[c2_bits],
				 cm2_core[c1_bits], cm2_core[c0_bits],
				 sc_bit ? "True" : "False",
				 cm2_cmd[cmd_bits], sport_bits);
		}
			pr_err("CM_ERROR=%08llx %s <%s>\n", cm_error,
			       cm2_causes[cause], buf);
		pr_err("CM_ADDR =%08llx\n", cm_addr);
		pr_err("CM_OTHER=%08llx %s\n", cm_other, cm2_causes[ocause]);
	} else { /* CM3 */
		ulong core_id_bits, vp_id_bits, cmd_bits, cmd_group_bits;
		ulong cm3_cca_bits, mcp_bits, cm3_tr_bits, sched_bit;

		cause = cm_error >> CM3_GCR_ERROR_CAUSE_ERRTYPE_SHF;
		ocause = cm_other >> CM_GCR_ERROR_MULT_ERR2ND_SHF;

		if (!cause)
			return;

		/* Used by cause == {1,2,3} */
		core_id_bits = (cm_error >> 22) & 0xf;
		vp_id_bits = (cm_error >> 18) & 0xf;
		cmd_bits = (cm_error >> 14) & 0xf;
		cmd_group_bits = (cm_error >> 11) & 0xf;
		cm3_cca_bits = (cm_error >> 8) & 7;
		mcp_bits = (cm_error >> 5) & 0xf;
		cm3_tr_bits = (cm_error >> 1) & 0xf;
		sched_bit = cm_error & 0x1;

		if (cause == 1 || cause == 3) { /* Tag ECC */
			unsigned long tag_ecc = (cm_error >> 57) & 0x1;
			unsigned long tag_way_bits = (cm_error >> 29) & 0xffff;
			unsigned long dword_bits = (cm_error >> 49) & 0xff;
			unsigned long data_way_bits = (cm_error >> 45) & 0xf;
			unsigned long data_sets_bits = (cm_error >> 29) & 0xfff;
			unsigned long bank_bit = (cm_error >> 28) & 0x1;
			snprintf(buf, sizeof(buf),
				 "%s ECC Error: Way=%lu (DWORD=%lu, Sets=%lu)"
				 "Bank=%lu CoreID=%lu VPID=%lu Command=%s"
				 "Command Group=%s CCA=%lu MCP=%d"
				 "Transaction type=%s Scheduler=%lu\n",
				 tag_ecc ? "TAG" : "DATA",
				 tag_ecc ? (unsigned long)ffs(tag_way_bits) - 1 :
				 data_way_bits, bank_bit, dword_bits,
				 data_sets_bits,
				 core_id_bits, vp_id_bits,
				 cm3_cmd[cmd_bits],
				 cm3_cmd_group[cmd_group_bits],
				 cm3_cca_bits, 1 << mcp_bits,
				 cm3_tr[cm3_tr_bits], sched_bit);
		} else if (cause == 2) {
			unsigned long data_error_type = (cm_error >> 41) & 0xfff;
			unsigned long data_decode_cmd = (cm_error >> 37) & 0xf;
			unsigned long data_decode_group = (cm_error >> 34) & 0x7;
			unsigned long data_decode_destination_id = (cm_error >> 28) & 0x3f;

			snprintf(buf, sizeof(buf),
				 "Decode Request Error: Type=%lu, Command=%lu"
				 "Command Group=%lu Destination ID=%lu"
				 "CoreID=%lu VPID=%lu Command=%s"
				 "Command Group=%s CCA=%lu MCP=%d"
				 "Transaction type=%s Scheduler=%lu\n",
				 data_error_type, data_decode_cmd,
				 data_decode_group, data_decode_destination_id,
				 core_id_bits, vp_id_bits,
				 cm3_cmd[cmd_bits],
				 cm3_cmd_group[cmd_group_bits],
				 cm3_cca_bits, 1 << mcp_bits,
				 cm3_tr[cm3_tr_bits], sched_bit);
		} else {
			buf[0] = 0;
		}

		pr_err("CM_ERROR=%llx %s <%s>\n", cm_error,
		       cm3_causes[cause], buf);
		pr_err("CM_ADDR =%llx\n", cm_addr);
		pr_err("CM_OTHER=%llx %s\n", cm_other, cm3_causes[ocause]);
	}

	/* reprime cause register */
	write_gcr_error_cause(0);
}
Commit	Line	Data
9f98f3dd PB	1	/*
	2	* Copyright (C) 2013 Imagination Technologies
	3	* Author: Paul Burton <paul.burton@imgtec.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of the GNU General Public License as published by the
	7	* Free Software Foundation; either version 2 of the License, or (at your
	8	* option) any later version.
	9	*/
	10
	11	#include <linux/errno.h>
23d5de8e PB	12	#include <linux/percpu.h>
23d5de8e PB	13	#include <linux/spinlock.h>
9f98f3dd PB	14
	15	#include <asm/mips-cm.h>
	16	#include <asm/mipsregs.h>
	17
abe852ea	18	void __iomem *mips_gcr_base;
9f98f3dd	19	void __iomem *mips_cm_l2sync_base;
c0b584a2	20	int mips_cm_is64;
9f98f3dd	21
3885c2b4 MC	22	static char *cm2_tr[8] = {
	23	"mem", "gcr", "gic", "mmio",
	24	"0x04", "cpc", "0x06", "0x07"
	25	};
	26
92a76f6d	27	/* CM3 Tag ECC transaction type */
3885c2b4 MC	28	static char *cm3_tr[16] = {
	29	[0x0] = "ReqNoData",
	30	[0x1] = "0x1",
	31	[0x2] = "ReqWData",
	32	[0x3] = "0x3",
	33	[0x4] = "IReqNoResp",
	34	[0x5] = "IReqWResp",
	35	[0x6] = "IReqNoRespDat",
	36	[0x7] = "IReqWRespDat",
	37	[0x8] = "RespNoData",
	38	[0x9] = "RespDataFol",
	39	[0xa] = "RespWData",
	40	[0xb] = "RespDataOnly",
	41	[0xc] = "IRespNoData",
	42	[0xd] = "IRespDataFol",
	43	[0xe] = "IRespWData",
	44	[0xf] = "IRespDataOnly"
	45	};
	46
	47	static char *cm2_cmd[32] = {
	48	[0x00] = "0x00",
	49	[0x01] = "Legacy Write",
	50	[0x02] = "Legacy Read",
	51	[0x03] = "0x03",
	52	[0x04] = "0x04",
	53	[0x05] = "0x05",
	54	[0x06] = "0x06",
	55	[0x07] = "0x07",
	56	[0x08] = "Coherent Read Own",
	57	[0x09] = "Coherent Read Share",
	58	[0x0a] = "Coherent Read Discard",
	59	[0x0b] = "Coherent Ready Share Always",
	60	[0x0c] = "Coherent Upgrade",
	61	[0x0d] = "Coherent Writeback",
	62	[0x0e] = "0x0e",
	63	[0x0f] = "0x0f",
	64	[0x10] = "Coherent Copyback",
	65	[0x11] = "Coherent Copyback Invalidate",
	66	[0x12] = "Coherent Invalidate",
	67	[0x13] = "Coherent Write Invalidate",
	68	[0x14] = "Coherent Completion Sync",
	69	[0x15] = "0x15",
	70	[0x16] = "0x16",
	71	[0x17] = "0x17",
	72	[0x18] = "0x18",
	73	[0x19] = "0x19",
	74	[0x1a] = "0x1a",
	75	[0x1b] = "0x1b",
	76	[0x1c] = "0x1c",
	77	[0x1d] = "0x1d",
	78	[0x1e] = "0x1e",
	79	[0x1f] = "0x1f"
	80	};
	81
	82	/* CM3 Tag ECC command type */
	83	static char *cm3_cmd[16] = {
	84	[0x0] = "Legacy Read",
	85	[0x1] = "Legacy Write",
	86	[0x2] = "Coherent Read Own",
	87	[0x3] = "Coherent Read Share",
	88	[0x4] = "Coherent Read Discard",
	89	[0x5] = "Coherent Evicted",
	90	[0x6] = "Coherent Upgrade",
	91	[0x7] = "Coherent Upgrade for Store Conditional",
92	[0x8] = "Coherent Writeback",
93	[0x9] = "Coherent Write Invalidate",
94	[0xa] = "0xa",
95	[0xb] = "0xb",
96	[0xc] = "0xc",
97	[0xd] = "0xd",
98	[0xe] = "0xe",
99	[0xf] = "0xf"
100	};
101
102	/* CM3 Tag ECC command group */
103	static char *cm3_cmd_group[8] = {
104	[0x0] = "Normal",
105	[0x1] = "Registers",
106	[0x2] = "TLB",
107	[0x3] = "0x3",
108	[0x4] = "L1I",
109	[0x5] = "L1D",
110	[0x6] = "L3",
111	[0x7] = "L2"
112	};
113
114	static char *cm2_core[8] = {
115	"Invalid/OK", "Invalid/Data",
116	"Shared/OK", "Shared/Data",
117	"Modified/OK", "Modified/Data",
118	"Exclusive/OK", "Exclusive/Data"
119	};
120
121	static char *cm2_causes[32] = {
122	"None", "GC_WR_ERR", "GC_RD_ERR", "COH_WR_ERR",
123	"COH_RD_ERR", "MMIO_WR_ERR", "MMIO_RD_ERR", "0x07",
124	"0x08", "0x09", "0x0a", "0x0b",
125	"0x0c", "0x0d", "0x0e", "0x0f",
126	"0x10", "0x11", "0x12", "0x13",
127	"0x14", "0x15", "0x16", "INTVN_WR_ERR",
128	"INTVN_RD_ERR", "0x19", "0x1a", "0x1b",
129	"0x1c", "0x1d", "0x1e", "0x1f"
130	};
131
132	static char *cm3_causes[32] = {
133	"0x0", "MP_CORRECTABLE_ECC_ERR", "MP_REQUEST_DECODE_ERR",
134	"MP_UNCORRECTABLE_ECC_ERR", "MP_PARITY_ERR", "MP_COHERENCE_ERR",
135	"CMBIU_REQUEST_DECODE_ERR", "CMBIU_PARITY_ERR", "CMBIU_AXI_RESP_ERR",
136	"0x9", "RBI_BUS_ERR", "0xb", "0xc", "0xd", "0xe", "0xf", "0x10",
137	"0x11", "0x12", "0x13", "0x14", "0x15", "0x16", "0x17", "0x18",
138	"0x19", "0x1a", "0x1b", "0x1c", "0x1d", "0x1e", "0x1f"
139	};
140
23d5de8e PB	141	static DEFINE_PER_CPU_ALIGNED(spinlock_t, cm_core_lock);
	142	static DEFINE_PER_CPU_ALIGNED(unsigned long, cm_core_lock_flags);
	143
15d45cce	144	phys_addr_t __mips_cm_phys_base(void)
9f98f3dd PB	145	{
9f98f3dd PB	146	u32 config3 = read_c0_config3();
038b0f53	147	unsigned long cmgcr;
9f98f3dd PB	148
	149	/* Check the CMGCRBase register is implemented */
	150	if (!(config3 & MIPS_CONF3_CMGCR))
	151	return 0;
	152
	153	/* Read the address from CMGCRBase */
	154	cmgcr = read_c0_cmgcrbase();
	155	return (cmgcr & MIPS_CMGCRF_BASE) << (36 - 32);
	156	}
	157
15d45cce	158	phys_addr_t mips_cm_phys_base(void)
9f98f3dd PB	159	__attribute__((weak, alias("__mips_cm_phys_base")));
9f98f3dd PB	160
15d45cce	161	phys_addr_t __mips_cm_l2sync_phys_base(void)
9f98f3dd PB	162	{
	163	u32 base_reg;
	164
	165	/*
	166	* If the L2-only sync region is already enabled then leave it at it's
	167	* current location.
	168	*/
	169	base_reg = read_gcr_l2_only_sync_base();
	170	if (base_reg & CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN_MSK)
	171	return base_reg & CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE_MSK;
	172
	173	/* Default to following the CM */
	174	return mips_cm_phys_base() + MIPS_CM_GCR_SIZE;
	175	}
	176
15d45cce	177	phys_addr_t mips_cm_l2sync_phys_base(void)
9f98f3dd PB	178	__attribute__((weak, alias("__mips_cm_l2sync_phys_base")));
	179
	180	static void mips_cm_probe_l2sync(void)
	181	{
	182	unsigned major_rev;
15d45cce	183	phys_addr_t addr;
9f98f3dd PB	184
	185	/* L2-only sync was introduced with CM major revision 6 */
	186	major_rev = (read_gcr_rev() & CM_GCR_REV_MAJOR_MSK) >>
	187	CM_GCR_REV_MAJOR_SHF;
	188	if (major_rev < 6)
	189	return;
	190
	191	/* Find a location for the L2 sync region */
	192	addr = mips_cm_l2sync_phys_base();
	193	BUG_ON((addr & CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE_MSK) != addr);
	194	if (!addr)
	195	return;
	196
	197	/* Set the region base address & enable it */
	198	write_gcr_l2_only_sync_base(addr \| CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN_MSK);
	199
	200	/* Map the region */
	201	mips_cm_l2sync_base = ioremap_nocache(addr, MIPS_CM_L2SYNC_SIZE);
	202	}
	203
	204	int mips_cm_probe(void)
	205	{
15d45cce	206	phys_addr_t addr;
9f98f3dd	207	u32 base_reg;
23d5de8e	208	unsigned cpu;
9f98f3dd	209
c014d164 MC	210	/*
	211	* No need to probe again if we have already been
	212	* here before.
	213	*/
abe852ea	214	if (mips_gcr_base)
c014d164 MC	215	return 0;
c014d164 MC	216
9f98f3dd PB	217	addr = mips_cm_phys_base();
	218	BUG_ON((addr & CM_GCR_BASE_GCRBASE_MSK) != addr);
	219	if (!addr)
	220	return -ENODEV;
	221
abe852ea PB	222	mips_gcr_base = ioremap_nocache(addr, MIPS_CM_GCR_SIZE);
abe852ea PB	223	if (!mips_gcr_base)
9f98f3dd PB	224	return -ENXIO;
	225
	226	/* sanity check that we're looking at a CM */
	227	base_reg = read_gcr_base();
	228	if ((base_reg & CM_GCR_BASE_GCRBASE_MSK) != addr) {
	229	pr_err("GCRs appear to have been moved (expected them at 0x%08lx)!\n",
	230	(unsigned long)addr);
abe852ea	231	mips_gcr_base = NULL;
9f98f3dd PB	232	return -ENODEV;
	233	}
	234
	235	/* set default target to memory */
	236	base_reg &= ~CM_GCR_BASE_CMDEFTGT_MSK;
	237	base_reg \|= CM_GCR_BASE_CMDEFTGT_MEM;
	238	write_gcr_base(base_reg);
	239
	240	/* disable CM regions */
	241	write_gcr_reg0_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
	242	write_gcr_reg0_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
	243	write_gcr_reg1_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
	244	write_gcr_reg1_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
	245	write_gcr_reg2_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
	246	write_gcr_reg2_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
	247	write_gcr_reg3_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
	248	write_gcr_reg3_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
	249
	250	/* probe for an L2-only sync region */
	251	mips_cm_probe_l2sync();
	252
c0b584a2	253	/* determine register width for this CM */
97f2645f	254	mips_cm_is64 = IS_ENABLED(CONFIG_64BIT) && (mips_cm_revision() >= CM_REV_CM3);
c0b584a2	255
23d5de8e PB	256	for_each_possible_cpu(cpu)
	257	spin_lock_init(&per_cpu(cm_core_lock, cpu));
	258
9f98f3dd PB	259	return 0;
9f98f3dd PB	260	}
3885c2b4	261
23d5de8e PB	262	void mips_cm_lock_other(unsigned int core, unsigned int vp)
	263	{
	264	unsigned curr_core;
	265	u32 val;
	266
	267	preempt_disable();
23d5de8e PB	268
	269	if (mips_cm_revision() >= CM_REV_CM3) {
	270	val = core << CM3_GCR_Cx_OTHER_CORE_SHF;
	271	val \|= vp << CM3_GCR_Cx_OTHER_VP_SHF;
516db1c6 PB	272
	273	/*
	274	* We need to disable interrupts in SMP systems in order to
	275	* ensure that we don't interrupt the caller with code which
	276	* may modify the redirect register. We do so here in a
	277	* slightly obscure way by using a spin lock, since this has
	278	* the neat property of also catching any nested uses of
	279	* mips_cm_lock_other() leading to a deadlock or a nice warning
	280	* with lockdep enabled.
	281	*/
	282	spin_lock_irqsave(this_cpu_ptr(&cm_core_lock),
	283	*this_cpu_ptr(&cm_core_lock_flags));
23d5de8e	284	} else {
2f93a60c	285	WARN_ON(vp != 0);
516db1c6 PB	286
	287	/*
	288	* We only have a GCR_CL_OTHER per core in systems with
	289	* CM 2.5 & older, so have to ensure other VP(E)s don't
	290	* race with us.
	291	*/
	292	curr_core = current_cpu_data.core;
	293	spin_lock_irqsave(&per_cpu(cm_core_lock, curr_core),
	294	per_cpu(cm_core_lock_flags, curr_core));
	295
23d5de8e PB	296	val = core << CM_GCR_Cx_OTHER_CORENUM_SHF;
	297	}
	298
	299	write_gcr_cl_other(val);
78a54c4d PB	300
	301	/*
	302	* Ensure the core-other region reflects the appropriate core &
	303	* VP before any accesses to it occur.
	304	*/
	305	mb();
23d5de8e PB	306	}
	307
	308	void mips_cm_unlock_other(void)
	309	{
516db1c6 PB	310	unsigned int curr_core;
	311
	312	if (mips_cm_revision() < CM_REV_CM3) {
	313	curr_core = current_cpu_data.core;
	314	spin_unlock_irqrestore(&per_cpu(cm_core_lock, curr_core),
	315	per_cpu(cm_core_lock_flags, curr_core));
	316	} else {
	317	spin_unlock_irqrestore(this_cpu_ptr(&cm_core_lock),
	318	*this_cpu_ptr(&cm_core_lock_flags));
	319	}
23d5de8e	320
23d5de8e PB	321	preempt_enable();
	322	}
	323
3885c2b4 MC	324	void mips_cm_error_report(void)
3885c2b4 MC	325	{
47b26a46 PB	326	u64 cm_error, cm_addr, cm_other;
	327	unsigned long revision;
	328	int ocause, cause;
3885c2b4 MC	329	char buf[256];
	330
	331	if (!mips_cm_present())
	332	return;
	333
03b1b85d	334	revision = mips_cm_revision();
b025d518 PB	335	cm_error = read_gcr_error_cause();
	336	cm_addr = read_gcr_error_addr();
	337	cm_other = read_gcr_error_mult();
03b1b85d	338
47b26a46	339	if (revision < CM_REV_CM3) { /* CM2 */
47b26a46 PB	340	cause = cm_error >> CM_GCR_ERROR_CAUSE_ERRTYPE_SHF;
47b26a46 PB	341	ocause = cm_other >> CM_GCR_ERROR_MULT_ERR2ND_SHF;
3885c2b4	342
47b26a46 PB	343	if (!cause)
47b26a46 PB	344	return;
3885c2b4	345
3885c2b4 MC	346	if (cause < 16) {
	347	unsigned long cca_bits = (cm_error >> 15) & 7;
	348	unsigned long tr_bits = (cm_error >> 12) & 7;
	349	unsigned long cmd_bits = (cm_error >> 7) & 0x1f;
	350	unsigned long stag_bits = (cm_error >> 3) & 15;
	351	unsigned long sport_bits = (cm_error >> 0) & 7;
	352
	353	snprintf(buf, sizeof(buf),
	354	"CCA=%lu TR=%s MCmd=%s STag=%lu "
	355	"SPort=%lu\n", cca_bits, cm2_tr[tr_bits],
	356	cm2_cmd[cmd_bits], stag_bits, sport_bits);
	357	} else {
	358	/* glob state & sresp together */
	359	unsigned long c3_bits = (cm_error >> 18) & 7;
	360	unsigned long c2_bits = (cm_error >> 15) & 7;
	361	unsigned long c1_bits = (cm_error >> 12) & 7;
	362	unsigned long c0_bits = (cm_error >> 9) & 7;
	363	unsigned long sc_bit = (cm_error >> 8) & 1;
	364	unsigned long cmd_bits = (cm_error >> 3) & 0x1f;
	365	unsigned long sport_bits = (cm_error >> 0) & 7;
	366
	367	snprintf(buf, sizeof(buf),
	368	"C3=%s C2=%s C1=%s C0=%s SC=%s "
	369	"MCmd=%s SPort=%lu\n",
	370	cm2_core[c3_bits], cm2_core[c2_bits],
	371	cm2_core[c1_bits], cm2_core[c0_bits],
	372	sc_bit ? "True" : "False",
	373	cm2_cmd[cmd_bits], sport_bits);
	374	}
	375	pr_err("CM_ERROR=%08llx %s <%s>\n", cm_error,
	376	cm2_causes[cause], buf);
47b26a46 PB	377	pr_err("CM_ADDR =%08llx\n", cm_addr);
47b26a46 PB	378	pr_err("CM_OTHER=%08llx %s\n", cm_other, cm2_causes[ocause]);
3885c2b4	379	} else { /* CM3 */
47b26a46 PB	380	ulong core_id_bits, vp_id_bits, cmd_bits, cmd_group_bits;
	381	ulong cm3_cca_bits, mcp_bits, cm3_tr_bits, sched_bit;
	382
47b26a46 PB	383	cause = cm_error >> CM3_GCR_ERROR_CAUSE_ERRTYPE_SHF;
	384	ocause = cm_other >> CM_GCR_ERROR_MULT_ERR2ND_SHF;
	385
	386	if (!cause)
	387	return;
	388
	389	/* Used by cause == {1,2,3} */
	390	core_id_bits = (cm_error >> 22) & 0xf;
	391	vp_id_bits = (cm_error >> 18) & 0xf;
	392	cmd_bits = (cm_error >> 14) & 0xf;
	393	cmd_group_bits = (cm_error >> 11) & 0xf;
	394	cm3_cca_bits = (cm_error >> 8) & 7;
	395	mcp_bits = (cm_error >> 5) & 0xf;
	396	cm3_tr_bits = (cm_error >> 1) & 0xf;
	397	sched_bit = cm_error & 0x1;
3885c2b4 MC	398
	399	if (cause == 1 \|\| cause == 3) { /* Tag ECC */
	400	unsigned long tag_ecc = (cm_error >> 57) & 0x1;
	401	unsigned long tag_way_bits = (cm_error >> 29) & 0xffff;
	402	unsigned long dword_bits = (cm_error >> 49) & 0xff;
	403	unsigned long data_way_bits = (cm_error >> 45) & 0xf;
	404	unsigned long data_sets_bits = (cm_error >> 29) & 0xfff;
	405	unsigned long bank_bit = (cm_error >> 28) & 0x1;
	406	snprintf(buf, sizeof(buf),
	407	"%s ECC Error: Way=%lu (DWORD=%lu, Sets=%lu)"
	408	"Bank=%lu CoreID=%lu VPID=%lu Command=%s"
	409	"Command Group=%s CCA=%lu MCP=%d"
	410	"Transaction type=%s Scheduler=%lu\n",
	411	tag_ecc ? "TAG" : "DATA",
	412	tag_ecc ? (unsigned long)ffs(tag_way_bits) - 1 :
	413	data_way_bits, bank_bit, dword_bits,
	414	data_sets_bits,
	415	core_id_bits, vp_id_bits,
	416	cm3_cmd[cmd_bits],
	417	cm3_cmd_group[cmd_group_bits],
	418	cm3_cca_bits, 1 << mcp_bits,
	419	cm3_tr[cm3_tr_bits], sched_bit);
	420	} else if (cause == 2) {
	421	unsigned long data_error_type = (cm_error >> 41) & 0xfff;
	422	unsigned long data_decode_cmd = (cm_error >> 37) & 0xf;
	423	unsigned long data_decode_group = (cm_error >> 34) & 0x7;
	424	unsigned long data_decode_destination_id = (cm_error >> 28) & 0x3f;
	425
	426	snprintf(buf, sizeof(buf),
	427	"Decode Request Error: Type=%lu, Command=%lu"
	428	"Command Group=%lu Destination ID=%lu"
	429	"CoreID=%lu VPID=%lu Command=%s"
	430	"Command Group=%s CCA=%lu MCP=%d"
	431	"Transaction type=%s Scheduler=%lu\n",
	432	data_error_type, data_decode_cmd,
	433	data_decode_group, data_decode_destination_id,
	434	core_id_bits, vp_id_bits,
	435	cm3_cmd[cmd_bits],
	436	cm3_cmd_group[cmd_group_bits],
	437	cm3_cca_bits, 1 << mcp_bits,
	438	cm3_tr[cm3_tr_bits], sched_bit);
f88e6324 PB	439	} else {
f88e6324 PB	440	buf[0] = 0;
3885c2b4 MC	441	}
	442
	443	pr_err("CM_ERROR=%llx %s <%s>\n", cm_error,
	444	cm3_causes[cause], buf);
47b26a46 PB	445	pr_err("CM_ADDR =%llx\n", cm_addr);
47b26a46 PB	446	pr_err("CM_OTHER=%llx %s\n", cm_other, cm3_causes[ocause]);
3885c2b4 MC	447	}
	448
	449	/* reprime cause register */
	450	write_gcr_error_cause(0);
	451	}