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1 | /* |
2 | * Copyright 2001 MontaVista Software Inc. | |
3 | * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net | |
4 | * | |
5 | * Copyright (C) 2001 Ralf Baechle | |
925ddb04 MR |
6 | * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. |
7 | * Author: Maciej W. Rozycki <macro@mips.com> | |
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8 | * |
9 | * This file define the irq handler for MIPS CPU interrupts. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify it | |
12 | * under the terms of the GNU General Public License as published by the | |
13 | * Free Software Foundation; either version 2 of the License, or (at your | |
14 | * option) any later version. | |
15 | */ | |
16 | ||
17 | /* | |
18 | * Almost all MIPS CPUs define 8 interrupt sources. They are typically | |
19 | * level triggered (i.e., cannot be cleared from CPU; must be cleared from | |
20 | * device). The first two are software interrupts which we don't really | |
21 | * use or support. The last one is usually the CPU timer interrupt if | |
22 | * counter register is present or, for CPUs with an external FPU, by | |
23 | * convention it's the FPU exception interrupt. | |
24 | * | |
25 | * Don't even think about using this on SMP. You have been warned. | |
26 | * | |
27 | * This file exports one global function: | |
97dcb82d | 28 | * void mips_cpu_irq_init(void); |
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29 | */ |
30 | #include <linux/init.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/kernel.h> | |
ca4d3e67 | 33 | #include <linux/irq.h> |
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34 | |
35 | #include <asm/irq_cpu.h> | |
36 | #include <asm/mipsregs.h> | |
d03d0a57 | 37 | #include <asm/mipsmtregs.h> |
1da177e4 | 38 | |
a93951c4 | 39 | static inline void unmask_mips_irq(struct irq_data *d) |
1da177e4 | 40 | { |
a93951c4 | 41 | set_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); |
569f75bd | 42 | irq_enable_hazard(); |
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43 | } |
44 | ||
a93951c4 | 45 | static inline void mask_mips_irq(struct irq_data *d) |
1da177e4 | 46 | { |
a93951c4 | 47 | clear_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); |
569f75bd | 48 | irq_disable_hazard(); |
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49 | } |
50 | ||
94dee171 | 51 | static struct irq_chip mips_cpu_irq_controller = { |
70d21cde | 52 | .name = "MIPS", |
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53 | .irq_ack = mask_mips_irq, |
54 | .irq_mask = mask_mips_irq, | |
55 | .irq_mask_ack = mask_mips_irq, | |
56 | .irq_unmask = unmask_mips_irq, | |
57 | .irq_eoi = unmask_mips_irq, | |
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58 | }; |
59 | ||
d03d0a57 RB |
60 | /* |
61 | * Basically the same as above but taking care of all the MT stuff | |
62 | */ | |
63 | ||
a93951c4 | 64 | static unsigned int mips_mt_cpu_irq_startup(struct irq_data *d) |
d03d0a57 RB |
65 | { |
66 | unsigned int vpflags = dvpe(); | |
67 | ||
a93951c4 | 68 | clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); |
d03d0a57 | 69 | evpe(vpflags); |
a93951c4 | 70 | unmask_mips_irq(d); |
d03d0a57 RB |
71 | return 0; |
72 | } | |
73 | ||
d03d0a57 RB |
74 | /* |
75 | * While we ack the interrupt interrupts are disabled and thus we don't need | |
76 | * to deal with concurrency issues. Same for mips_cpu_irq_end. | |
77 | */ | |
a93951c4 | 78 | static void mips_mt_cpu_irq_ack(struct irq_data *d) |
d03d0a57 RB |
79 | { |
80 | unsigned int vpflags = dvpe(); | |
a93951c4 | 81 | clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); |
d03d0a57 | 82 | evpe(vpflags); |
a93951c4 | 83 | mask_mips_irq(d); |
d03d0a57 RB |
84 | } |
85 | ||
94dee171 | 86 | static struct irq_chip mips_mt_cpu_irq_controller = { |
70d21cde | 87 | .name = "MIPS", |
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88 | .irq_startup = mips_mt_cpu_irq_startup, |
89 | .irq_ack = mips_mt_cpu_irq_ack, | |
90 | .irq_mask = mask_mips_irq, | |
91 | .irq_mask_ack = mips_mt_cpu_irq_ack, | |
92 | .irq_unmask = unmask_mips_irq, | |
93 | .irq_eoi = unmask_mips_irq, | |
d03d0a57 | 94 | }; |
1da177e4 | 95 | |
97dcb82d | 96 | void __init mips_cpu_irq_init(void) |
1da177e4 | 97 | { |
97dcb82d | 98 | int irq_base = MIPS_CPU_IRQ_BASE; |
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99 | int i; |
100 | ||
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101 | /* Mask interrupts. */ |
102 | clear_c0_status(ST0_IM); | |
103 | clear_c0_cause(CAUSEF_IP); | |
104 | ||
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105 | /* Software interrupts are used for MT/CMT IPI */ |
106 | for (i = irq_base; i < irq_base + 2; i++) | |
107 | irq_set_chip_and_handler(i, cpu_has_mipsmt ? | |
108 | &mips_mt_cpu_irq_controller : | |
109 | &mips_cpu_irq_controller, | |
110 | handle_percpu_irq); | |
1603b5ac AN |
111 | |
112 | for (i = irq_base + 2; i < irq_base + 8; i++) | |
e4ec7989 | 113 | irq_set_chip_and_handler(i, &mips_cpu_irq_controller, |
30e748a5 | 114 | handle_percpu_irq); |
1da177e4 | 115 | } |