[linux-2.6-block.git] / arch / mips / kernel / genex.S

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1994 - 2000, 2001, 2003 Ralf Baechle
 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
 * Copyright (C) 2002, 2007  Maciej W. Rozycki
 * Copyright (C) 2001, 2012 MIPS Technologies, Inc.  All rights reserved.
 */
#include <linux/init.h>

#include <asm/asm.h>
#include <asm/asmmacro.h>
#include <asm/cacheops.h>
#include <asm/irqflags.h>
#include <asm/regdef.h>
#include <asm/fpregdef.h>
#include <asm/mipsregs.h>
#include <asm/stackframe.h>
#include <asm/sync.h>
#include <asm/thread_info.h>

	__INIT

/*
 * General exception vector for all other CPUs.
 *
 * Be careful when changing this, it has to be at most 128 bytes
 * to fit into space reserved for the exception handler.
 */
NESTED(except_vec3_generic, 0, sp)
	.set	push
	.set	noat
	mfc0	k1, CP0_CAUSE
	andi	k1, k1, 0x7c
#ifdef CONFIG_64BIT
	dsll	k1, k1, 1
#endif
	PTR_L	k0, exception_handlers(k1)
	jr	k0
	.set	pop
	END(except_vec3_generic)

/*
 * General exception handler for CPUs with virtual coherency exception.
 *
 * Be careful when changing this, it has to be at most 256 (as a special
 * exception) bytes to fit into space reserved for the exception handler.
 */
NESTED(except_vec3_r4000, 0, sp)
	.set	push
	.set	arch=r4000
	.set	noat
	mfc0	k1, CP0_CAUSE
	li	k0, 31<<2
	andi	k1, k1, 0x7c
	.set	push
	.set	noreorder
	.set	nomacro
	beq	k1, k0, handle_vced
	 li	k0, 14<<2
	beq	k1, k0, handle_vcei
#ifdef CONFIG_64BIT
	 dsll	k1, k1, 1
#endif
	.set	pop
	PTR_L	k0, exception_handlers(k1)
	jr	k0

	/*
	 * Big shit, we now may have two dirty primary cache lines for the same
	 * physical address.  We can safely invalidate the line pointed to by
	 * c0_badvaddr because after return from this exception handler the
	 * load / store will be re-executed.
	 */
handle_vced:
	MFC0	k0, CP0_BADVADDR
	li	k1, -4					# Is this ...
	and	k0, k1					# ... really needed?
	mtc0	zero, CP0_TAGLO
	cache	Index_Store_Tag_D, (k0)
	cache	Hit_Writeback_Inv_SD, (k0)
#ifdef CONFIG_PROC_FS
	PTR_LA	k0, vced_count
	lw	k1, (k0)
	addiu	k1, 1
	sw	k1, (k0)
#endif
	eret

handle_vcei:
	MFC0	k0, CP0_BADVADDR
	cache	Hit_Writeback_Inv_SD, (k0)		# also cleans pi
#ifdef CONFIG_PROC_FS
	PTR_LA	k0, vcei_count
	lw	k1, (k0)
	addiu	k1, 1
	sw	k1, (k0)
#endif
	eret
	.set	pop
	END(except_vec3_r4000)

	__FINIT

	.align	5	/* 32 byte rollback region */
LEAF(__r4k_wait)
	.set	push
	.set	noreorder
	/* start of rollback region */
	LONG_L	t0, TI_FLAGS($28)
	nop
	andi	t0, _TIF_NEED_RESCHED
	bnez	t0, 1f
	 nop
	nop
	nop
#ifdef CONFIG_CPU_MICROMIPS
	nop
	nop
	nop
	nop
#endif
	.set	MIPS_ISA_ARCH_LEVEL_RAW
	wait
	/* end of rollback region (the region size must be power of two) */
1:
	jr	ra
	 nop
	.set	pop
	END(__r4k_wait)

	.macro	BUILD_ROLLBACK_PROLOGUE handler
	FEXPORT(rollback_\handler)
	.set	push
	.set	noat
	MFC0	k0, CP0_EPC
	PTR_LA	k1, __r4k_wait
	ori	k0, 0x1f	/* 32 byte rollback region */
	xori	k0, 0x1f
	bne	k0, k1, \handler
	MTC0	k0, CP0_EPC
	.set pop
	.endm

	.align	5
BUILD_ROLLBACK_PROLOGUE handle_int
NESTED(handle_int, PT_SIZE, sp)
	.cfi_signal_frame
#ifdef CONFIG_TRACE_IRQFLAGS
	/*
	 * Check to see if the interrupted code has just disabled
	 * interrupts and ignore this interrupt for now if so.
	 *
	 * local_irq_disable() disables interrupts and then calls
	 * trace_hardirqs_off() to track the state. If an interrupt is taken
	 * after interrupts are disabled but before the state is updated
	 * it will appear to restore_all that it is incorrectly returning with
	 * interrupts disabled
	 */
	.set	push
	.set	noat
	mfc0	k0, CP0_STATUS
#if defined(CONFIG_CPU_R3000)
	and	k0, ST0_IEP
	bnez	k0, 1f

	mfc0	k0, CP0_EPC
	.set	noreorder
	j	k0
	 rfe
#else
	and	k0, ST0_IE
	bnez	k0, 1f

	eret
#endif
1:
	.set pop
#endif
	SAVE_ALL docfi=1
	CLI
	TRACE_IRQS_OFF

	LONG_L	s0, TI_REGS($28)
	LONG_S	sp, TI_REGS($28)

	/*
	 * SAVE_ALL ensures we are using a valid kernel stack for the thread.
	 * Check if we are already using the IRQ stack.
	 */
	move	s1, sp # Preserve the sp

	/* Get IRQ stack for this CPU */
	ASM_CPUID_MFC0	k0, ASM_SMP_CPUID_REG
#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
	lui	k1, %hi(irq_stack)
#else
	lui	k1, %highest(irq_stack)
	daddiu	k1, %higher(irq_stack)
	dsll	k1, 16
	daddiu	k1, %hi(irq_stack)
	dsll	k1, 16
#endif
	LONG_SRL	k0, SMP_CPUID_PTRSHIFT
	LONG_ADDU	k1, k0
	LONG_L	t0, %lo(irq_stack)(k1)

	# Check if already on IRQ stack
	PTR_LI	t1, ~(_THREAD_SIZE-1)
	and	t1, t1, sp
	beq	t0, t1, 2f

	/* Switch to IRQ stack */
	li	t1, _IRQ_STACK_START
	PTR_ADD sp, t0, t1

	/* Save task's sp on IRQ stack so that unwinding can follow it */
	LONG_S	s1, 0(sp)
2:
	jal	plat_irq_dispatch

	/* Restore sp */
	move	sp, s1

	j	ret_from_irq
#ifdef CONFIG_CPU_MICROMIPS
	nop
#endif
	END(handle_int)

	__INIT

/*
 * Special interrupt vector for MIPS64 ISA & embedded MIPS processors.
 * This is a dedicated interrupt exception vector which reduces the
 * interrupt processing overhead.  The jump instruction will be replaced
 * at the initialization time.
 *
 * Be careful when changing this, it has to be at most 128 bytes
 * to fit into space reserved for the exception handler.
 */
NESTED(except_vec4, 0, sp)
1:	j	1b			/* Dummy, will be replaced */
	END(except_vec4)

/*
 * EJTAG debug exception handler.
 * The EJTAG debug exception entry point is 0xbfc00480, which
 * normally is in the boot PROM, so the boot PROM must do an
 * unconditional jump to this vector.
 */
NESTED(except_vec_ejtag_debug, 0, sp)
	j	ejtag_debug_handler
#ifdef CONFIG_CPU_MICROMIPS
	 nop
#endif
	END(except_vec_ejtag_debug)

	__FINIT

/*
 * Vectored interrupt handler.
 * This prototype is copied to ebase + n*IntCtl.VS and patched
 * to invoke the handler
 */
BUILD_ROLLBACK_PROLOGUE except_vec_vi
NESTED(except_vec_vi, 0, sp)
	SAVE_SOME docfi=1
	SAVE_AT docfi=1
	.set	push
	.set	noreorder
	PTR_LA	v1, except_vec_vi_handler
	jr	v1
FEXPORT(except_vec_vi_ori)
	 ori	v0, zero, 0		/* Offset in vi_handlers[] */
	.set	pop
	END(except_vec_vi)
EXPORT(except_vec_vi_end)

/*
 * Common Vectored Interrupt code
 * Complete the register saves and invoke the handler, $v0 holds
 * offset into vi_handlers[]
 */
NESTED(except_vec_vi_handler, 0, sp)
	SAVE_TEMP
	SAVE_STATIC
	CLI
#ifdef CONFIG_TRACE_IRQFLAGS
	move	s0, v0
	TRACE_IRQS_OFF
	move	v0, s0
#endif

	LONG_L	s0, TI_REGS($28)
	LONG_S	sp, TI_REGS($28)

	/*
	 * SAVE_ALL ensures we are using a valid kernel stack for the thread.
	 * Check if we are already using the IRQ stack.
	 */
	move	s1, sp # Preserve the sp

	/* Get IRQ stack for this CPU */
	ASM_CPUID_MFC0	k0, ASM_SMP_CPUID_REG
#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
	lui	k1, %hi(irq_stack)
#else
	lui	k1, %highest(irq_stack)
	daddiu	k1, %higher(irq_stack)
	dsll	k1, 16
	daddiu	k1, %hi(irq_stack)
	dsll	k1, 16
#endif
	LONG_SRL	k0, SMP_CPUID_PTRSHIFT
	LONG_ADDU	k1, k0
	LONG_L	t0, %lo(irq_stack)(k1)

	# Check if already on IRQ stack
	PTR_LI	t1, ~(_THREAD_SIZE-1)
	and	t1, t1, sp
	beq	t0, t1, 2f

	/* Switch to IRQ stack */
	li	t1, _IRQ_STACK_START
	PTR_ADD sp, t0, t1

	/* Save task's sp on IRQ stack so that unwinding can follow it */
	LONG_S	s1, 0(sp)
2:
	PTR_L	v0, vi_handlers(v0)
	jalr	v0

	/* Restore sp */
	move	sp, s1

	j	ret_from_irq
	END(except_vec_vi_handler)

/*
 * EJTAG debug exception handler.
 */
NESTED(ejtag_debug_handler, PT_SIZE, sp)
	.set	push
	.set	noat
	MTC0	k0, CP0_DESAVE
	mfc0	k0, CP0_DEBUG

	andi	k0, k0, MIPS_DEBUG_DBP	# Check for SDBBP.
	beqz	k0, ejtag_return

#ifdef CONFIG_SMP
1:	PTR_LA	k0, ejtag_debug_buffer_spinlock
	__SYNC(full, loongson3_war)
2:	ll	k0, 0(k0)
	bnez	k0, 2b
	PTR_LA	k0, ejtag_debug_buffer_spinlock
	sc	k0, 0(k0)
	beqz	k0, 1b
# ifdef CONFIG_WEAK_REORDERING_BEYOND_LLSC
	sync
# endif

	PTR_LA	k0, ejtag_debug_buffer
	LONG_S	k1, 0(k0)

	ASM_CPUID_MFC0 k1, ASM_SMP_CPUID_REG
	PTR_SRL	k1, SMP_CPUID_PTRSHIFT
	PTR_SLL	k1, LONGLOG
	PTR_LA	k0, ejtag_debug_buffer_per_cpu
	PTR_ADDU k0, k1

	PTR_LA	k1, ejtag_debug_buffer
	LONG_L	k1, 0(k1)
	LONG_S	k1, 0(k0)

	PTR_LA	k0, ejtag_debug_buffer_spinlock
	sw	zero, 0(k0)
#else
	PTR_LA	k0, ejtag_debug_buffer
	LONG_S	k1, 0(k0)
#endif

	SAVE_ALL
	move	a0, sp
	jal	ejtag_exception_handler
	RESTORE_ALL

#ifdef CONFIG_SMP
	ASM_CPUID_MFC0 k1, ASM_SMP_CPUID_REG
	PTR_SRL	k1, SMP_CPUID_PTRSHIFT
	PTR_SLL	k1, LONGLOG
	PTR_LA	k0, ejtag_debug_buffer_per_cpu
	PTR_ADDU k0, k1
	LONG_L	k1, 0(k0)
#else
	PTR_LA	k0, ejtag_debug_buffer
	LONG_L	k1, 0(k0)
#endif

ejtag_return:
	back_to_back_c0_hazard
	MFC0	k0, CP0_DESAVE
	.set	mips32
	deret
	.set	pop
	END(ejtag_debug_handler)

/*
 * This buffer is reserved for the use of the EJTAG debug
 * handler.
 */
	.data
EXPORT(ejtag_debug_buffer)
	.fill	LONGSIZE
#ifdef CONFIG_SMP
EXPORT(ejtag_debug_buffer_spinlock)
	.fill	LONGSIZE
EXPORT(ejtag_debug_buffer_per_cpu)
	.fill	LONGSIZE * NR_CPUS
#endif
	.previous

	__INIT

/*
 * NMI debug exception handler for MIPS reference boards.
 * The NMI debug exception entry point is 0xbfc00000, which
 * normally is in the boot PROM, so the boot PROM must do a
 * unconditional jump to this vector.
 */
NESTED(except_vec_nmi, 0, sp)
	j	nmi_handler
#ifdef CONFIG_CPU_MICROMIPS
	 nop
#endif
	END(except_vec_nmi)

	__FINIT

NESTED(nmi_handler, PT_SIZE, sp)
	.cfi_signal_frame
	.set	push
	.set	noat
	/*
	 * Clear ERL - restore segment mapping
	 * Clear BEV - required for page fault exception handler to work
	 */
	mfc0	k0, CP0_STATUS
	ori	k0, k0, ST0_EXL
	li	k1, ~(ST0_BEV | ST0_ERL)
	and	k0, k0, k1
	mtc0	k0, CP0_STATUS
	_ehb
	SAVE_ALL
	move	a0, sp
	jal	nmi_exception_handler
	/* nmi_exception_handler never returns */
	.set	pop
	END(nmi_handler)

	.macro	__build_clear_none
	.endm

	.macro	__build_clear_sti
	TRACE_IRQS_ON
	STI
	.endm

	.macro	__build_clear_cli
	CLI
	TRACE_IRQS_OFF
	.endm

	.macro	__build_clear_fpe
	CLI
	TRACE_IRQS_OFF
	.set	push
	/* gas fails to assemble cfc1 for some archs (octeon).*/ \
	.set	mips1
	.set	hardfloat
	cfc1	a1, fcr31
	.set	pop
	.endm

	.macro	__build_clear_msa_fpe
	CLI
	TRACE_IRQS_OFF
	_cfcmsa	a1, MSA_CSR
	.endm

	.macro	__build_clear_ade
	MFC0	t0, CP0_BADVADDR
	PTR_S	t0, PT_BVADDR(sp)
	KMODE
	.endm

	.macro __build_clear_gsexc
	.set	push
	/*
	 * We need to specify a selector to access the CP0.Diag1 (GSCause)
	 * register. All GSExc-equipped processors have MIPS32.
	 */
	.set	mips32
	mfc0	a1, CP0_DIAGNOSTIC1
	.set	pop
	TRACE_IRQS_ON
	STI
	.endm

	.macro	__BUILD_silent exception
	.endm

	/* Gas tries to parse the ASM_PRINT argument as a string containing
	   string escapes and emits bogus warnings if it believes to
	   recognize an unknown escape code.  So make the arguments
	   start with an n and gas will believe \n is ok ...  */
	.macro	__BUILD_verbose nexception
	LONG_L	a1, PT_EPC(sp)
#ifdef CONFIG_32BIT
	ASM_PRINT("Got \nexception at %08lx\012")
#endif
#ifdef CONFIG_64BIT
	ASM_PRINT("Got \nexception at %016lx\012")
#endif
	.endm

	.macro	__BUILD_count exception
	LONG_L	t0,exception_count_\exception
	LONG_ADDIU	t0, 1
	LONG_S	t0,exception_count_\exception
	.comm	exception_count\exception, 8, 8
	.endm

	.macro	__BUILD_HANDLER exception handler clear verbose ext
	.align	5
	NESTED(handle_\exception, PT_SIZE, sp)
	.cfi_signal_frame
	.set	noat
	SAVE_ALL
	FEXPORT(handle_\exception\ext)
	__build_clear_\clear
	.set	at
	__BUILD_\verbose \exception
	move	a0, sp
	jal	do_\handler
	j	ret_from_exception
	END(handle_\exception)
	.endm

	.macro	BUILD_HANDLER exception handler clear verbose
	__BUILD_HANDLER \exception \handler \clear \verbose _int
	.endm

	BUILD_HANDLER adel ade ade silent		/* #4  */
	BUILD_HANDLER ades ade ade silent		/* #5  */
	BUILD_HANDLER ibe be cli silent			/* #6  */
	BUILD_HANDLER dbe be cli silent			/* #7  */
	BUILD_HANDLER bp bp sti silent			/* #9  */
	BUILD_HANDLER ri ri sti silent			/* #10 */
	BUILD_HANDLER cpu cpu sti silent		/* #11 */
	BUILD_HANDLER ov ov sti silent			/* #12 */
	BUILD_HANDLER tr tr sti silent			/* #13 */
	BUILD_HANDLER msa_fpe msa_fpe msa_fpe silent	/* #14 */
#ifdef CONFIG_MIPS_FP_SUPPORT
	BUILD_HANDLER fpe fpe fpe silent		/* #15 */
#endif
	BUILD_HANDLER ftlb ftlb none silent		/* #16 */
	BUILD_HANDLER gsexc gsexc gsexc silent		/* #16 */
	BUILD_HANDLER msa msa sti silent		/* #21 */
	BUILD_HANDLER mdmx mdmx sti silent		/* #22 */
#ifdef	CONFIG_HARDWARE_WATCHPOINTS
	/*
	 * For watch, interrupts will be enabled after the watch
	 * registers are read.
	 */
	BUILD_HANDLER watch watch cli silent		/* #23 */
#else
	BUILD_HANDLER watch watch sti verbose		/* #23 */
#endif
	BUILD_HANDLER mcheck mcheck cli verbose		/* #24 */
	BUILD_HANDLER mt mt sti silent			/* #25 */
	BUILD_HANDLER dsp dsp sti silent		/* #26 */
	BUILD_HANDLER reserved reserved sti verbose	/* others */

	.align	5
	LEAF(handle_ri_rdhwr_tlbp)
	.set	push
	.set	noat
	.set	noreorder
	/* check if TLB contains a entry for EPC */
	MFC0	k1, CP0_ENTRYHI
	andi	k1, MIPS_ENTRYHI_ASID | MIPS_ENTRYHI_ASIDX
	MFC0	k0, CP0_EPC
	PTR_SRL	k0, _PAGE_SHIFT + 1
	PTR_SLL	k0, _PAGE_SHIFT + 1
	or	k1, k0
	MTC0	k1, CP0_ENTRYHI
	mtc0_tlbw_hazard
	tlbp
	tlb_probe_hazard
	mfc0	k1, CP0_INDEX
	.set	pop
	bltz	k1, handle_ri	/* slow path */
	/* fall thru */
	END(handle_ri_rdhwr_tlbp)

	LEAF(handle_ri_rdhwr)
	.set	push
	.set	noat
	.set	noreorder
	/* MIPS32:    0x7c03e83b: rdhwr v1,$29 */
	/* microMIPS: 0x007d6b3c: rdhwr v1,$29 */
	MFC0	k1, CP0_EPC
#if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_CPU_MIPS64_R2)
	and	k0, k1, 1
	beqz	k0, 1f
	 xor	k1, k0
	lhu	k0, (k1)
	lhu	k1, 2(k1)
	ins	k1, k0, 16, 16
	lui	k0, 0x007d
	b	docheck
	 ori	k0, 0x6b3c
1:
	lui	k0, 0x7c03
	lw	k1, (k1)
	ori	k0, 0xe83b
#else
	andi	k0, k1, 1
	bnez	k0, handle_ri
	 lui	k0, 0x7c03
	lw	k1, (k1)
	ori	k0, 0xe83b
#endif
	.set	reorder
docheck:
	bne	k0, k1, handle_ri	/* if not ours */

isrdhwr:
	/* The insn is rdhwr.  No need to check CAUSE.BD here. */
	get_saved_sp	/* k1 := current_thread_info */
	.set	noreorder
	MFC0	k0, CP0_EPC
#if defined(CONFIG_CPU_R3000)
	ori	k1, _THREAD_MASK
	xori	k1, _THREAD_MASK
	LONG_L	v1, TI_TP_VALUE(k1)
	LONG_ADDIU	k0, 4
	jr	k0
	 rfe
#else
#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
	LONG_ADDIU	k0, 4		/* stall on $k0 */
#else
	.set	at=v1
	LONG_ADDIU	k0, 4
	.set	noat
#endif
	MTC0	k0, CP0_EPC
	/* I hope three instructions between MTC0 and ERET are enough... */
	ori	k1, _THREAD_MASK
	xori	k1, _THREAD_MASK
	LONG_L	v1, TI_TP_VALUE(k1)
	.set	push
	.set	arch=r4000
	eret
	.set	pop
#endif
	.set	pop
	END(handle_ri_rdhwr)

#ifdef CONFIG_CPU_R4X00_BUGS64
/* A temporary overflow handler used by check_daddi(). */

	__INIT

	BUILD_HANDLER  daddi_ov daddi_ov none silent	/* #12 */
#endif
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 1994 - 2000, 2001, 2003 Ralf Baechle
	7	* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
619b6e18	8	* Copyright (C) 2002, 2007 Maciej W. Rozycki
2a0b24f5	9	* Copyright (C) 2001, 2012 MIPS Technologies, Inc. All rights reserved.
1da177e4	10	*/
1da177e4 LT	11	#include <linux/init.h>
	12
	13	#include <asm/asm.h>
41c594ab	14	#include <asm/asmmacro.h>
1da177e4	15	#include <asm/cacheops.h>
192ef366	16	#include <asm/irqflags.h>
1da177e4 LT	17	#include <asm/regdef.h>
	18	#include <asm/fpregdef.h>
	19	#include <asm/mipsregs.h>
	20	#include <asm/stackframe.h>
12dbb04f	21	#include <asm/sync.h>
c65a5480	22	#include <asm/thread_info.h>
1da177e4	23
1da177e4 LT	24	__INIT
1da177e4 LT	25
1da177e4 LT	26	/*
	27	* General exception vector for all other CPUs.
	28	*
	29	* Be careful when changing this, it has to be at most 128 bytes
	30	* to fit into space reserved for the exception handler.
	31	*/
	32	NESTED(except_vec3_generic, 0, sp)
	33	.set push
	34	.set noat
1da177e4 LT	35	mfc0 k1, CP0_CAUSE
1da177e4 LT	36	andi k1, k1, 0x7c
875d43e7	37	#ifdef CONFIG_64BIT
1da177e4 LT	38	dsll k1, k1, 1
	39	#endif
	40	PTR_L k0, exception_handlers(k1)
	41	jr k0
	42	.set pop
	43	END(except_vec3_generic)
	44
	45	/*
	46	* General exception handler for CPUs with virtual coherency exception.
	47	*
	48	* Be careful when changing this, it has to be at most 256 (as a special
	49	* exception) bytes to fit into space reserved for the exception handler.
	50	*/
	51	NESTED(except_vec3_r4000, 0, sp)
	52	.set push
a809d460	53	.set arch=r4000
1da177e4 LT	54	.set noat
	55	mfc0 k1, CP0_CAUSE
	56	li k0, 31<<2
	57	andi k1, k1, 0x7c
	58	.set push
	59	.set noreorder
	60	.set nomacro
	61	beq k1, k0, handle_vced
	62	li k0, 14<<2
	63	beq k1, k0, handle_vcei
875d43e7	64	#ifdef CONFIG_64BIT
69903d65	65	dsll k1, k1, 1
1da177e4 LT	66	#endif
	67	.set pop
	68	PTR_L k0, exception_handlers(k1)
	69	jr k0
	70
	71	/*
	72	* Big shit, we now may have two dirty primary cache lines for the same
69903d65	73	* physical address. We can safely invalidate the line pointed to by
1da177e4 LT	74	* c0_badvaddr because after return from this exception handler the
	75	* load / store will be re-executed.
	76	*/
	77	handle_vced:
69903d65	78	MFC0 k0, CP0_BADVADDR
1da177e4 LT	79	li k1, -4 # Is this ...
	80	and k0, k1 # ... really needed?
	81	mtc0 zero, CP0_TAGLO
69903d65 TS	82	cache Index_Store_Tag_D, (k0)
69903d65 TS	83	cache Hit_Writeback_Inv_SD, (k0)
1da177e4 LT	84	#ifdef CONFIG_PROC_FS
	85	PTR_LA k0, vced_count
	86	lw k1, (k0)
	87	addiu k1, 1
	88	sw k1, (k0)
	89	#endif
	90	eret
	91
	92	handle_vcei:
	93	MFC0 k0, CP0_BADVADDR
	94	cache Hit_Writeback_Inv_SD, (k0) # also cleans pi
	95	#ifdef CONFIG_PROC_FS
	96	PTR_LA k0, vcei_count
	97	lw k1, (k0)
	98	addiu k1, 1
	99	sw k1, (k0)
	100	#endif
	101	eret
	102	.set pop
	103	END(except_vec3_r4000)
	104
e4ac58af RB	105	__FINIT
e4ac58af RB	106
c65a5480	107	.align 5 /* 32 byte rollback region */
087d990b	108	LEAF(__r4k_wait)
c65a5480 AN	109	.set push
	110	.set noreorder
	111	/* start of rollback region */
	112	LONG_L t0, TI_FLAGS($28)
	113	nop
	114	andi t0, _TIF_NEED_RESCHED
	115	bnez t0, 1f
	116	nop
	117	nop
	118	nop
2a0b24f5 SH	119	#ifdef CONFIG_CPU_MICROMIPS
	120	nop
	121	nop
	122	nop
	123	nop
	124	#endif
938c1282	125	.set MIPS_ISA_ARCH_LEVEL_RAW
c65a5480 AN	126	wait
c65a5480 AN	127	/* end of rollback region (the region size must be power of two) */
c65a5480 AN	128	1:
c65a5480 AN	129	jr ra
105c22c5	130	nop
2a0b24f5	131	.set pop
087d990b	132	END(__r4k_wait)
c65a5480 AN	133
	134	.macro BUILD_ROLLBACK_PROLOGUE handler
	135	FEXPORT(rollback_\handler)
	136	.set push
	137	.set noat
	138	MFC0 k0, CP0_EPC
087d990b	139	PTR_LA k1, __r4k_wait
c65a5480 AN	140	ori k0, 0x1f /* 32 byte rollback region */
c65a5480 AN	141	xori k0, 0x1f
1eefcbc8	142	bne k0, k1, \handler
c65a5480	143	MTC0 k0, CP0_EPC
c65a5480 AN	144	.set pop
	145	.endm
	146
70342287	147	.align 5
c65a5480	148	BUILD_ROLLBACK_PROLOGUE handle_int
e4ac58af	149	NESTED(handle_int, PT_SIZE, sp)
866b6a89	150	.cfi_signal_frame
fe99f1b1 CD	151	#ifdef CONFIG_TRACE_IRQFLAGS
	152	/*
	153	* Check to see if the interrupted code has just disabled
	154	* interrupts and ignore this interrupt for now if so.
	155	*
	156	* local_irq_disable() disables interrupts and then calls
	157	* trace_hardirqs_off() to track the state. If an interrupt is taken
	158	* after interrupts are disabled but before the state is updated
	159	* it will appear to restore_all that it is incorrectly returning with
	160	* interrupts disabled
	161	*/
	162	.set push
	163	.set noat
	164	mfc0 k0, CP0_STATUS
455481fc	165	#if defined(CONFIG_CPU_R3000)
fe99f1b1 CD	166	and k0, ST0_IEP
	167	bnez k0, 1f
	168
c6563e85	169	mfc0 k0, CP0_EPC
fe99f1b1 CD	170	.set noreorder
fe99f1b1 CD	171	j k0
105c22c5	172	rfe
fe99f1b1 CD	173	#else
	174	and k0, ST0_IE
	175	bnez k0, 1f
	176
	177	eret
	178	#endif
	179	1:
	180	.set pop
	181	#endif
866b6a89	182	SAVE_ALL docfi=1
e4ac58af	183	CLI
192ef366	184	TRACE_IRQS_OFF
e4ac58af	185
937a8015 RB	186	LONG_L s0, TI_REGS($28)
937a8015 RB	187	LONG_S sp, TI_REGS($28)
dda45f70 MR	188
	189	/*
	190	* SAVE_ALL ensures we are using a valid kernel stack for the thread.
	191	* Check if we are already using the IRQ stack.
	192	*/
	193	move s1, sp # Preserve the sp
	194
	195	/* Get IRQ stack for this CPU */
	196	ASM_CPUID_MFC0 k0, ASM_SMP_CPUID_REG
	197	#if defined(CONFIG_32BIT) \|\| defined(KBUILD_64BIT_SYM32)
	198	lui k1, %hi(irq_stack)
	199	#else
	200	lui k1, %highest(irq_stack)
	201	daddiu k1, %higher(irq_stack)
	202	dsll k1, 16
	203	daddiu k1, %hi(irq_stack)
	204	dsll k1, 16
	205	#endif
	206	LONG_SRL k0, SMP_CPUID_PTRSHIFT
	207	LONG_ADDU k1, k0
	208	LONG_L t0, %lo(irq_stack)(k1)
	209
	210	# Check if already on IRQ stack
	211	PTR_LI t1, ~(_THREAD_SIZE-1)
	212	and t1, t1, sp
	213	beq t0, t1, 2f
	214
	215	/* Switch to IRQ stack */
db8466c5	216	li t1, _IRQ_STACK_START
dda45f70 MR	217	PTR_ADD sp, t0, t1
dda45f70 MR	218
db8466c5 MR	219	/* Save task's sp on IRQ stack so that unwinding can follow it */
db8466c5 MR	220	LONG_S s1, 0(sp)
dda45f70 MR	221	2:
	222	jal plat_irq_dispatch
	223
	224	/* Restore sp */
	225	move sp, s1
	226
	227	j ret_from_irq
2a0b24f5 SH	228	#ifdef CONFIG_CPU_MICROMIPS
	229	nop
	230	#endif
e4ac58af RB	231	END(handle_int)
	232
	233	__INIT
	234
1da177e4 LT	235	/*
	236	* Special interrupt vector for MIPS64 ISA & embedded MIPS processors.
	237	* This is a dedicated interrupt exception vector which reduces the
	238	* interrupt processing overhead. The jump instruction will be replaced
	239	* at the initialization time.
	240	*
	241	* Be careful when changing this, it has to be at most 128 bytes
	242	* to fit into space reserved for the exception handler.
	243	*/
	244	NESTED(except_vec4, 0, sp)
	245	1: j 1b /* Dummy, will be replaced */
	246	END(except_vec4)
	247
	248	/*
	249	* EJTAG debug exception handler.
	250	* The EJTAG debug exception entry point is 0xbfc00480, which
2a0b24f5	251	* normally is in the boot PROM, so the boot PROM must do an
1da177e4 LT	252	* unconditional jump to this vector.
	253	*/
	254	NESTED(except_vec_ejtag_debug, 0, sp)
	255	j ejtag_debug_handler
2a0b24f5 SH	256	#ifdef CONFIG_CPU_MICROMIPS
	257	nop
	258	#endif
1da177e4 LT	259	END(except_vec_ejtag_debug)
	260
	261	__FINIT
	262
e01402b1 RB	263	/*
	264	* Vectored interrupt handler.
	265	* This prototype is copied to ebase + n*IntCtl.VS and patched
	266	* to invoke the handler
	267	*/
c65a5480	268	BUILD_ROLLBACK_PROLOGUE except_vec_vi
e01402b1	269	NESTED(except_vec_vi, 0, sp)
866b6a89 CM	270	SAVE_SOME docfi=1
866b6a89 CM	271	SAVE_AT docfi=1
e01402b1 RB	272	.set push
e01402b1 RB	273	.set noreorder
2a0b24f5	274	PTR_LA v1, except_vec_vi_handler
2a0b24f5	275	jr v1
7df42461	276	FEXPORT(except_vec_vi_ori)
682fb5be	277	ori v0, zero, 0 /* Offset in vi_handlers[] */
e01402b1 RB	278	.set pop
	279	END(except_vec_vi)
	280	EXPORT(except_vec_vi_end)
	281
	282	/*
	283	* Common Vectored Interrupt code
682fb5be TB	284	* Complete the register saves and invoke the handler, $v0 holds
682fb5be TB	285	* offset into vi_handlers[]
e01402b1 RB	286	*/
	287	NESTED(except_vec_vi_handler, 0, sp)
	288	SAVE_TEMP
	289	SAVE_STATIC
	290	CLI
8c364435 RB	291	#ifdef CONFIG_TRACE_IRQFLAGS
8c364435 RB	292	move s0, v0
192ef366	293	TRACE_IRQS_OFF
8c364435 RB	294	move v0, s0
8c364435 RB	295	#endif
937a8015 RB	296
	297	LONG_L s0, TI_REGS($28)
	298	LONG_S sp, TI_REGS($28)
dda45f70 MR	299
	300	/*
	301	* SAVE_ALL ensures we are using a valid kernel stack for the thread.
	302	* Check if we are already using the IRQ stack.
	303	*/
	304	move s1, sp # Preserve the sp
	305
	306	/* Get IRQ stack for this CPU */
	307	ASM_CPUID_MFC0 k0, ASM_SMP_CPUID_REG
	308	#if defined(CONFIG_32BIT) \|\| defined(KBUILD_64BIT_SYM32)
	309	lui k1, %hi(irq_stack)
	310	#else
	311	lui k1, %highest(irq_stack)
	312	daddiu k1, %higher(irq_stack)
	313	dsll k1, 16
	314	daddiu k1, %hi(irq_stack)
	315	dsll k1, 16
	316	#endif
	317	LONG_SRL k0, SMP_CPUID_PTRSHIFT
	318	LONG_ADDU k1, k0
	319	LONG_L t0, %lo(irq_stack)(k1)
	320
	321	# Check if already on IRQ stack
	322	PTR_LI t1, ~(_THREAD_SIZE-1)
	323	and t1, t1, sp
	324	beq t0, t1, 2f
	325
	326	/* Switch to IRQ stack */
db8466c5	327	li t1, _IRQ_STACK_START
dda45f70 MR	328	PTR_ADD sp, t0, t1
dda45f70 MR	329
db8466c5 MR	330	/* Save task's sp on IRQ stack so that unwinding can follow it */
db8466c5 MR	331	LONG_S s1, 0(sp)
dda45f70	332	2:
682fb5be	333	PTR_L v0, vi_handlers(v0)
c25f8064	334	jalr v0
dda45f70 MR	335
	336	/* Restore sp */
	337	move sp, s1
	338
	339	j ret_from_irq
e01402b1 RB	340	END(except_vec_vi_handler)
e01402b1 RB	341
1da177e4 LT	342	/*
	343	* EJTAG debug exception handler.
	344	*/
	345	NESTED(ejtag_debug_handler, PT_SIZE, sp)
	346	.set push
	347	.set noat
	348	MTC0 k0, CP0_DESAVE
	349	mfc0 k0, CP0_DEBUG
	350
ee54d379 TY	351	andi k0, k0, MIPS_DEBUG_DBP # Check for SDBBP.
ee54d379 TY	352	beqz k0, ejtag_return
1da177e4	353
c8bf3805 H	354	#ifdef CONFIG_SMP
c8bf3805 H	355	1: PTR_LA k0, ejtag_debug_buffer_spinlock
12dbb04f	356	__SYNC(full, loongson3_war)
4dee90d7 PB	357	2: ll k0, 0(k0)
4dee90d7 PB	358	bnez k0, 2b
c8bf3805 H	359	PTR_LA k0, ejtag_debug_buffer_spinlock
	360	sc k0, 0(k0)
	361	beqz k0, 1b
	362	# ifdef CONFIG_WEAK_REORDERING_BEYOND_LLSC
	363	sync
	364	# endif
	365
	366	PTR_LA k0, ejtag_debug_buffer
	367	LONG_S k1, 0(k0)
	368
	369	ASM_CPUID_MFC0 k1, ASM_SMP_CPUID_REG
	370	PTR_SRL k1, SMP_CPUID_PTRSHIFT
	371	PTR_SLL k1, LONGLOG
	372	PTR_LA k0, ejtag_debug_buffer_per_cpu
	373	PTR_ADDU k0, k1
	374
	375	PTR_LA k1, ejtag_debug_buffer
	376	LONG_L k1, 0(k1)
	377	LONG_S k1, 0(k0)
	378
	379	PTR_LA k0, ejtag_debug_buffer_spinlock
	380	sw zero, 0(k0)
	381	#else
1da177e4 LT	382	PTR_LA k0, ejtag_debug_buffer
1da177e4 LT	383	LONG_S k1, 0(k0)
c8bf3805 H	384	#endif
c8bf3805 H	385
1da177e4 LT	386	SAVE_ALL
	387	move a0, sp
	388	jal ejtag_exception_handler
	389	RESTORE_ALL
c8bf3805 H	390
	391	#ifdef CONFIG_SMP
	392	ASM_CPUID_MFC0 k1, ASM_SMP_CPUID_REG
	393	PTR_SRL k1, SMP_CPUID_PTRSHIFT
	394	PTR_SLL k1, LONGLOG
	395	PTR_LA k0, ejtag_debug_buffer_per_cpu
	396	PTR_ADDU k0, k1
	397	LONG_L k1, 0(k0)
	398	#else
1da177e4 LT	399	PTR_LA k0, ejtag_debug_buffer
1da177e4 LT	400	LONG_L k1, 0(k0)
c8bf3805	401	#endif
1da177e4 LT	402
1da177e4 LT	403	ejtag_return:
c8bf3805	404	back_to_back_c0_hazard
1da177e4 LT	405	MFC0 k0, CP0_DESAVE
	406	.set mips32
	407	deret
105c22c5	408	.set pop
1da177e4 LT	409	END(ejtag_debug_handler)
	410
	411	/*
	412	* This buffer is reserved for the use of the EJTAG debug
	413	* handler.
	414	*/
	415	.data
	416	EXPORT(ejtag_debug_buffer)
	417	.fill LONGSIZE
c8bf3805 H	418	#ifdef CONFIG_SMP
	419	EXPORT(ejtag_debug_buffer_spinlock)
	420	.fill LONGSIZE
	421	EXPORT(ejtag_debug_buffer_per_cpu)
	422	.fill LONGSIZE * NR_CPUS
	423	#endif
1da177e4 LT	424	.previous
	425
	426	__INIT
	427
	428	/*
	429	* NMI debug exception handler for MIPS reference boards.
	430	* The NMI debug exception entry point is 0xbfc00000, which
	431	* normally is in the boot PROM, so the boot PROM must do a
	432	* unconditional jump to this vector.
	433	*/
	434	NESTED(except_vec_nmi, 0, sp)
	435	j nmi_handler
2a0b24f5 SH	436	#ifdef CONFIG_CPU_MICROMIPS
	437	nop
	438	#endif
1da177e4 LT	439	END(except_vec_nmi)
	440
	441	__FINIT
	442
	443	NESTED(nmi_handler, PT_SIZE, sp)
866b6a89	444	.cfi_signal_frame
1da177e4 LT	445	.set push
1da177e4 LT	446	.set noat
83e4da1e LY	447	/*
	448	* Clear ERL - restore segment mapping
	449	* Clear BEV - required for page fault exception handler to work
	450	*/
	451	mfc0 k0, CP0_STATUS
105c22c5	452	ori k0, k0, ST0_EXL
83e4da1e	453	li k1, ~(ST0_BEV \| ST0_ERL)
105c22c5 JH	454	and k0, k0, k1
105c22c5 JH	455	mtc0 k0, CP0_STATUS
83e4da1e	456	_ehb
1da177e4	457	SAVE_ALL
70342287	458	move a0, sp
1da177e4	459	jal nmi_exception_handler
83e4da1e	460	/* nmi_exception_handler never returns */
1da177e4 LT	461	.set pop
	462	END(nmi_handler)
	463
	464	.macro __build_clear_none
	465	.endm
	466
	467	.macro __build_clear_sti
192ef366	468	TRACE_IRQS_ON
1da177e4 LT	469	STI
	470	.endm
	471
	472	.macro __build_clear_cli
	473	CLI
192ef366	474	TRACE_IRQS_OFF
1da177e4 LT	475	.endm
	476
	477	.macro __build_clear_fpe
31e1b3ef Y	478	CLI
31e1b3ef Y	479	TRACE_IRQS_OFF
25c30003 DD	480	.set push
	481	/* gas fails to assemble cfc1 for some archs (octeon).*/ \
	482	.set mips1
80a20d2f	483	.set hardfloat
1da177e4	484	cfc1 a1, fcr31
25c30003	485	.set pop
1da177e4 LT	486	.endm
1da177e4 LT	487
091be550	488	.macro __build_clear_msa_fpe
64bedffe JH	489	CLI
64bedffe JH	490	TRACE_IRQS_OFF
31e1b3ef	491	_cfcmsa a1, MSA_CSR
091be550 PB	492	.endm
091be550 PB	493
1da177e4 LT	494	.macro __build_clear_ade
	495	MFC0 t0, CP0_BADVADDR
	496	PTR_S t0, PT_BVADDR(sp)
	497	KMODE
	498	.endm
	499
bc6e8dc1 WX	500	.macro __build_clear_gsexc
	501	.set push
	502	/*
	503	* We need to specify a selector to access the CP0.Diag1 (GSCause)
	504	* register. All GSExc-equipped processors have MIPS32.
	505	*/
	506	.set mips32
	507	mfc0 a1, CP0_DIAGNOSTIC1
	508	.set pop
	509	TRACE_IRQS_ON
	510	STI
	511	.endm
	512
1da177e4 LT	513	.macro __BUILD_silent exception
	514	.endm
	515
da706e50	516	/* Gas tries to parse the ASM_PRINT argument as a string containing
1da177e4 LT	517	string escapes and emits bogus warnings if it believes to
	518	recognize an unknown escape code. So make the arguments
	519	start with an n and gas will believe \n is ok ... */
70342287	520	.macro __BUILD_verbose nexception
1da177e4	521	LONG_L a1, PT_EPC(sp)
766160c2	522	#ifdef CONFIG_32BIT
da706e50	523	ASM_PRINT("Got \nexception at %08lx\012")
42a3b4f2	524	#endif
766160c2	525	#ifdef CONFIG_64BIT
da706e50	526	ASM_PRINT("Got \nexception at %016lx\012")
42a3b4f2	527	#endif
1da177e4 LT	528	.endm
	529
	530	.macro __BUILD_count exception
	531	LONG_L t0,exception_count_\exception
105c22c5	532	LONG_ADDIU t0, 1
1da177e4 LT	533	LONG_S t0,exception_count_\exception
	534	.comm exception_count\exception, 8, 8
	535	.endm
	536
	537	.macro __BUILD_HANDLER exception handler clear verbose ext
	538	.align 5
	539	NESTED(handle_\exception, PT_SIZE, sp)
866b6a89	540	.cfi_signal_frame
1da177e4 LT	541	.set noat
	542	SAVE_ALL
	543	FEXPORT(handle_\exception\ext)
158d3b2a	544	__build_clear_\clear
1da177e4 LT	545	.set at
	546	__BUILD_\verbose \exception
	547	move a0, sp
866b6a89 CM	548	jal do_\handler
866b6a89 CM	549	j ret_from_exception
1da177e4 LT	550	END(handle_\exception)
	551	.endm
	552
	553	.macro BUILD_HANDLER exception handler clear verbose
70342287	554	__BUILD_HANDLER \exception \handler \clear \verbose _int
1da177e4 LT	555	.endm
	556
	557	BUILD_HANDLER adel ade ade silent /* #4 */
	558	BUILD_HANDLER ades ade ade silent /* #5 */
	559	BUILD_HANDLER ibe be cli silent /* #6 */
	560	BUILD_HANDLER dbe be cli silent /* #7 */
	561	BUILD_HANDLER bp bp sti silent /* #9 */
	562	BUILD_HANDLER ri ri sti silent /* #10 */
	563	BUILD_HANDLER cpu cpu sti silent /* #11 */
	564	BUILD_HANDLER ov ov sti silent /* #12 */
	565	BUILD_HANDLER tr tr sti silent /* #13 */
091be550	566	BUILD_HANDLER msa_fpe msa_fpe msa_fpe silent /* #14 */
5328f742	567	#ifdef CONFIG_MIPS_FP_SUPPORT
1da177e4	568	BUILD_HANDLER fpe fpe fpe silent /* #15 */
5328f742	569	#endif
75b5b5e0	570	BUILD_HANDLER ftlb ftlb none silent /* #16 */
bc6e8dc1	571	BUILD_HANDLER gsexc gsexc gsexc silent /* #16 */
1db1af84	572	BUILD_HANDLER msa msa sti silent /* #21 */
1da177e4	573	BUILD_HANDLER mdmx mdmx sti silent /* #22 */
70342287	574	#ifdef CONFIG_HARDWARE_WATCHPOINTS
8bc6d05b DD	575	/*
	576	* For watch, interrupts will be enabled after the watch
	577	* registers are read.
	578	*/
	579	BUILD_HANDLER watch watch cli silent /* #23 */
b67b2b70	580	#else
1da177e4	581	BUILD_HANDLER watch watch sti verbose /* #23 */
b67b2b70	582	#endif
1da177e4	583	BUILD_HANDLER mcheck mcheck cli verbose /* #24 */
e35a5e35	584	BUILD_HANDLER mt mt sti silent /* #25 */
e50c0a8f	585	BUILD_HANDLER dsp dsp sti silent /* #26 */
1da177e4 LT	586	BUILD_HANDLER reserved reserved sti verbose /* others */
1da177e4 LT	587
5b10496b	588	.align 5
5a341331	589	LEAF(handle_ri_rdhwr_tlbp)
5b10496b AN	590	.set push
	591	.set noat
	592	.set noreorder
	593	/* check if TLB contains a entry for EPC */
	594	MFC0 k1, CP0_ENTRYHI
2db003a5	595	andi k1, MIPS_ENTRYHI_ASID \| MIPS_ENTRYHI_ASIDX
5b10496b	596	MFC0 k0, CP0_EPC
105c22c5 JH	597	PTR_SRL k0, _PAGE_SHIFT + 1
105c22c5 JH	598	PTR_SLL k0, _PAGE_SHIFT + 1
5b10496b AN	599	or k1, k0
	600	MTC0 k1, CP0_ENTRYHI
	601	mtc0_tlbw_hazard
	602	tlbp
	603	tlb_probe_hazard
	604	mfc0 k1, CP0_INDEX
	605	.set pop
	606	bltz k1, handle_ri /* slow path */
	607	/* fall thru */
5a341331	608	END(handle_ri_rdhwr_tlbp)
5b10496b AN	609
	610	LEAF(handle_ri_rdhwr)
	611	.set push
	612	.set noat
	613	.set noreorder
2a0b24f5 SH	614	/* MIPS32: 0x7c03e83b: rdhwr v1,$29 */
2a0b24f5 SH	615	/* microMIPS: 0x007d6b3c: rdhwr v1,$29 */
5b10496b	616	MFC0 k1, CP0_EPC
2a0b24f5	617	#if defined(CONFIG_CPU_MICROMIPS) \|\| defined(CONFIG_CPU_MIPS32_R2) \|\| defined(CONFIG_CPU_MIPS64_R2)
105c22c5 JH	618	and k0, k1, 1
	619	beqz k0, 1f
	620	xor k1, k0
	621	lhu k0, (k1)
	622	lhu k1, 2(k1)
	623	ins k1, k0, 16, 16
	624	lui k0, 0x007d
	625	b docheck
	626	ori k0, 0x6b3c
2a0b24f5	627	1:
105c22c5 JH	628	lui k0, 0x7c03
	629	lw k1, (k1)
	630	ori k0, 0xe83b
2a0b24f5	631	#else
105c22c5 JH	632	andi k0, k1, 1
	633	bnez k0, handle_ri
	634	lui k0, 0x7c03
	635	lw k1, (k1)
	636	ori k0, 0xe83b
2a0b24f5	637	#endif
105c22c5	638	.set reorder
2a0b24f5	639	docheck:
5b10496b	640	bne k0, k1, handle_ri /* if not ours */
2a0b24f5 SH	641
2a0b24f5 SH	642	isrdhwr:
5b10496b AN	643	/* The insn is rdhwr. No need to check CAUSE.BD here. */
	644	get_saved_sp /* k1 := current_thread_info */
	645	.set noreorder
	646	MFC0 k0, CP0_EPC
455481fc	647	#if defined(CONFIG_CPU_R3000)
5b10496b AN	648	ori k1, _THREAD_MASK
	649	xori k1, _THREAD_MASK
	650	LONG_L v1, TI_TP_VALUE(k1)
	651	LONG_ADDIU k0, 4
	652	jr k0
	653	rfe
	654	#else
619b6e18	655	#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
5b10496b	656	LONG_ADDIU k0, 4 /* stall on $k0 */
619b6e18 MR	657	#else
	658	.set at=v1
	659	LONG_ADDIU k0, 4
	660	.set noat
	661	#endif
5b10496b AN	662	MTC0 k0, CP0_EPC
	663	/* I hope three instructions between MTC0 and ERET are enough... */
	664	ori k1, _THREAD_MASK
	665	xori k1, _THREAD_MASK
	666	LONG_L v1, TI_TP_VALUE(k1)
378ed6f0	667	.set push
a809d460	668	.set arch=r4000
5b10496b	669	eret
378ed6f0	670	.set pop
5b10496b AN	671	#endif
	672	.set pop
	673	END(handle_ri_rdhwr)
	674
071d2f0b	675	#ifdef CONFIG_CPU_R4X00_BUGS64
1da177e4 LT	676	/* A temporary overflow handler used by check_daddi(). */
	677
	678	__INIT
	679
	680	BUILD_HANDLER daddi_ov daddi_ov none silent /* #12 */
	681	#endif