[linux-2.6-block.git] / arch / mips / kernel / genex.S

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1994 - 2000, 2001, 2003 Ralf Baechle
 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
 * Copyright (C) 2001 MIPS Technologies, Inc.
 * Copyright (C) 2002, 2007  Maciej W. Rozycki
 */
#include <linux/init.h>

#include <asm/asm.h>
#include <asm/asmmacro.h>
#include <asm/cacheops.h>
#include <asm/irqflags.h>
#include <asm/regdef.h>
#include <asm/fpregdef.h>
#include <asm/mipsregs.h>
#include <asm/stackframe.h>
#include <asm/war.h>
#include <asm/page.h>
#include <asm/thread_info.h>

#define PANIC_PIC(msg)					\
		.set push;				\
		.set	reorder;			\
		PTR_LA	a0,8f;				\
		.set	noat;				\
		PTR_LA	AT, panic;			\
		jr	AT;				\
9:		b	9b;				\
		.set	pop;				\
		TEXT(msg)

	__INIT

NESTED(except_vec0_generic, 0, sp)
	PANIC_PIC("Exception vector 0 called")
	END(except_vec0_generic)

NESTED(except_vec1_generic, 0, sp)
	PANIC_PIC("Exception vector 1 called")
	END(except_vec1_generic)

/*
 * General exception vector for all other CPUs.
 *
 * Be careful when changing this, it has to be at most 128 bytes
 * to fit into space reserved for the exception handler.
 */
NESTED(except_vec3_generic, 0, sp)
	.set	push
	.set	noat
#if R5432_CP0_INTERRUPT_WAR
	mfc0	k0, CP0_INDEX
#endif
	mfc0	k1, CP0_CAUSE
	andi	k1, k1, 0x7c
#ifdef CONFIG_64BIT
	dsll	k1, k1, 1
#endif
	PTR_L	k0, exception_handlers(k1)
	jr	k0
	.set	pop
	END(except_vec3_generic)

/*
 * General exception handler for CPUs with virtual coherency exception.
 *
 * Be careful when changing this, it has to be at most 256 (as a special
 * exception) bytes to fit into space reserved for the exception handler.
 */
NESTED(except_vec3_r4000, 0, sp)
	.set	push
	.set	mips3
	.set	noat
	mfc0	k1, CP0_CAUSE
	li	k0, 31<<2
	andi	k1, k1, 0x7c
	.set	push
	.set	noreorder
	.set	nomacro
	beq	k1, k0, handle_vced
	 li	k0, 14<<2
	beq	k1, k0, handle_vcei
#ifdef CONFIG_64BIT
	 dsll	k1, k1, 1
#endif
	.set	pop
	PTR_L	k0, exception_handlers(k1)
	jr	k0

	/*
	 * Big shit, we now may have two dirty primary cache lines for the same
	 * physical address.  We can safely invalidate the line pointed to by
	 * c0_badvaddr because after return from this exception handler the
	 * load / store will be re-executed.
	 */
handle_vced:
	MFC0	k0, CP0_BADVADDR
	li	k1, -4					# Is this ...
	and	k0, k1					# ... really needed?
	mtc0	zero, CP0_TAGLO
	cache	Index_Store_Tag_D, (k0)
	cache	Hit_Writeback_Inv_SD, (k0)
#ifdef CONFIG_PROC_FS
	PTR_LA	k0, vced_count
	lw	k1, (k0)
	addiu	k1, 1
	sw	k1, (k0)
#endif
	eret

handle_vcei:
	MFC0	k0, CP0_BADVADDR
	cache	Hit_Writeback_Inv_SD, (k0)		# also cleans pi
#ifdef CONFIG_PROC_FS
	PTR_LA	k0, vcei_count
	lw	k1, (k0)
	addiu	k1, 1
	sw	k1, (k0)
#endif
	eret
	.set	pop
	END(except_vec3_r4000)

	__FINIT

	.align	5	/* 32 byte rollback region */
LEAF(r4k_wait)
	.set	push
	.set	noreorder
	/* start of rollback region */
	LONG_L	t0, TI_FLAGS($28)
	nop
	andi	t0, _TIF_NEED_RESCHED
	bnez	t0, 1f
	 nop
	nop
	nop
	.set	mips3
	wait
	/* end of rollback region (the region size must be power of two) */
	.set	pop
1:
	jr	ra
	END(r4k_wait)

	.macro	BUILD_ROLLBACK_PROLOGUE handler
	FEXPORT(rollback_\handler)
	.set	push
	.set	noat
	MFC0	k0, CP0_EPC
	PTR_LA	k1, r4k_wait
	ori	k0, 0x1f	/* 32 byte rollback region */
	xori	k0, 0x1f
	bne	k0, k1, 9f
	MTC0	k0, CP0_EPC
9:
	.set pop
	.endm

	.align  5
BUILD_ROLLBACK_PROLOGUE handle_int
NESTED(handle_int, PT_SIZE, sp)
#ifdef CONFIG_TRACE_IRQFLAGS
	/*
	 * Check to see if the interrupted code has just disabled
	 * interrupts and ignore this interrupt for now if so.
	 *
	 * local_irq_disable() disables interrupts and then calls
	 * trace_hardirqs_off() to track the state. If an interrupt is taken
	 * after interrupts are disabled but before the state is updated
	 * it will appear to restore_all that it is incorrectly returning with
	 * interrupts disabled
	 */
	.set	push
	.set	noat
	mfc0	k0, CP0_STATUS
#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
	and	k0, ST0_IEP
	bnez	k0, 1f

	mfc0	k0, CP0_EPC
	.set	noreorder
	j	k0
	rfe
#else
	and	k0, ST0_IE
	bnez	k0, 1f

	eret
#endif
1:
	.set pop
#endif
	SAVE_ALL
	CLI
	TRACE_IRQS_OFF

	LONG_L	s0, TI_REGS($28)
	LONG_S	sp, TI_REGS($28)
	PTR_LA	ra, ret_from_irq
	j	plat_irq_dispatch
	END(handle_int)

	__INIT

/*
 * Special interrupt vector for MIPS64 ISA & embedded MIPS processors.
 * This is a dedicated interrupt exception vector which reduces the
 * interrupt processing overhead.  The jump instruction will be replaced
 * at the initialization time.
 *
 * Be careful when changing this, it has to be at most 128 bytes
 * to fit into space reserved for the exception handler.
 */
NESTED(except_vec4, 0, sp)
1:	j	1b			/* Dummy, will be replaced */
	END(except_vec4)

/*
 * EJTAG debug exception handler.
 * The EJTAG debug exception entry point is 0xbfc00480, which
 * normally is in the boot PROM, so the boot PROM must do a
 * unconditional jump to this vector.
 */
NESTED(except_vec_ejtag_debug, 0, sp)
	j	ejtag_debug_handler
	END(except_vec_ejtag_debug)

	__FINIT

/*
 * Vectored interrupt handler.
 * This prototype is copied to ebase + n*IntCtl.VS and patched
 * to invoke the handler
 */
BUILD_ROLLBACK_PROLOGUE except_vec_vi
NESTED(except_vec_vi, 0, sp)
	SAVE_SOME
	SAVE_AT
	.set	push
	.set	noreorder
#ifdef CONFIG_MIPS_MT_SMTC
	/*
	 * To keep from blindly blocking *all* interrupts
	 * during service by SMTC kernel, we also want to
	 * pass the IM value to be cleared.
	 */
FEXPORT(except_vec_vi_mori)
	ori	a0, $0, 0
#endif /* CONFIG_MIPS_MT_SMTC */
FEXPORT(except_vec_vi_lui)
	lui	v0, 0		/* Patched */
	j	except_vec_vi_handler
FEXPORT(except_vec_vi_ori)
	 ori	v0, 0		/* Patched */
	.set	pop
	END(except_vec_vi)
EXPORT(except_vec_vi_end)

/*
 * Common Vectored Interrupt code
 * Complete the register saves and invoke the handler which is passed in $v0
 */
NESTED(except_vec_vi_handler, 0, sp)
	SAVE_TEMP
	SAVE_STATIC
#ifdef CONFIG_MIPS_MT_SMTC
	/*
	 * SMTC has an interesting problem that interrupts are level-triggered,
	 * and the CLI macro will clear EXL, potentially causing a duplicate
	 * interrupt service invocation. So we need to clear the associated
	 * IM bit of Status prior to doing CLI, and restore it after the
	 * service routine has been invoked - we must assume that the
	 * service routine will have cleared the state, and any active
	 * level represents a new or otherwised unserviced event...
	 */
	mfc0	t1, CP0_STATUS
	and	t0, a0, t1
#ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP
	mfc0	t2, CP0_TCCONTEXT
	or	t2, t0, t2
	mtc0	t2, CP0_TCCONTEXT
#endif /* CONFIG_MIPS_MT_SMTC_IM_BACKSTOP */
	xor	t1, t1, t0
	mtc0	t1, CP0_STATUS
	_ehb
#endif /* CONFIG_MIPS_MT_SMTC */
	CLI
#ifdef CONFIG_TRACE_IRQFLAGS
	move	s0, v0
#ifdef CONFIG_MIPS_MT_SMTC
	move	s1, a0
#endif
	TRACE_IRQS_OFF
#ifdef CONFIG_MIPS_MT_SMTC
	move	a0, s1
#endif
	move	v0, s0
#endif

	LONG_L	s0, TI_REGS($28)
	LONG_S	sp, TI_REGS($28)
	PTR_LA	ra, ret_from_irq
	jr	v0
	END(except_vec_vi_handler)

/*
 * EJTAG debug exception handler.
 */
NESTED(ejtag_debug_handler, PT_SIZE, sp)
	.set	push
	.set	noat
	MTC0	k0, CP0_DESAVE
	mfc0	k0, CP0_DEBUG

	sll	k0, k0, 30	# Check for SDBBP.
	bgez	k0, ejtag_return

	PTR_LA	k0, ejtag_debug_buffer
	LONG_S	k1, 0(k0)
	SAVE_ALL
	move	a0, sp
	jal	ejtag_exception_handler
	RESTORE_ALL
	PTR_LA	k0, ejtag_debug_buffer
	LONG_L	k1, 0(k0)

ejtag_return:
	MFC0	k0, CP0_DESAVE
	.set	mips32
	deret
	.set pop
	END(ejtag_debug_handler)

/*
 * This buffer is reserved for the use of the EJTAG debug
 * handler.
 */
	.data
EXPORT(ejtag_debug_buffer)
	.fill	LONGSIZE
	.previous

	__INIT

/*
 * NMI debug exception handler for MIPS reference boards.
 * The NMI debug exception entry point is 0xbfc00000, which
 * normally is in the boot PROM, so the boot PROM must do a
 * unconditional jump to this vector.
 */
NESTED(except_vec_nmi, 0, sp)
	j	nmi_handler
	END(except_vec_nmi)

	__FINIT

NESTED(nmi_handler, PT_SIZE, sp)
	.set	push
	.set	noat
	SAVE_ALL
 	move	a0, sp
	jal	nmi_exception_handler
	RESTORE_ALL
	.set	mips3
	eret
	.set	pop
	END(nmi_handler)

	.macro	__build_clear_none
	.endm

	.macro	__build_clear_sti
	TRACE_IRQS_ON
	STI
	.endm

	.macro	__build_clear_cli
	CLI
	TRACE_IRQS_OFF
	.endm

	.macro	__build_clear_fpe
	.set	push
	/* gas fails to assemble cfc1 for some archs (octeon).*/ \
	.set	mips1
	cfc1	a1, fcr31
	li	a2, ~(0x3f << 12)
	and	a2, a1
	ctc1	a2, fcr31
	.set	pop
	TRACE_IRQS_ON
	STI
	.endm

	.macro	__build_clear_ade
	MFC0	t0, CP0_BADVADDR
	PTR_S	t0, PT_BVADDR(sp)
	KMODE
	.endm

	.macro	__BUILD_silent exception
	.endm

	/* Gas tries to parse the PRINT argument as a string containing
	   string escapes and emits bogus warnings if it believes to
	   recognize an unknown escape code.  So make the arguments
	   start with an n and gas will believe \n is ok ...  */
	.macro	__BUILD_verbose	nexception
	LONG_L	a1, PT_EPC(sp)
#ifdef CONFIG_32BIT
	PRINT("Got \nexception at %08lx\012")
#endif
#ifdef CONFIG_64BIT
	PRINT("Got \nexception at %016lx\012")
#endif
	.endm

	.macro	__BUILD_count exception
	LONG_L	t0,exception_count_\exception
	LONG_ADDIU t0, 1
	LONG_S	t0,exception_count_\exception
	.comm	exception_count\exception, 8, 8
	.endm

	.macro	__BUILD_HANDLER exception handler clear verbose ext
	.align	5
	NESTED(handle_\exception, PT_SIZE, sp)
	.set	noat
	SAVE_ALL
	FEXPORT(handle_\exception\ext)
	__BUILD_clear_\clear
	.set	at
	__BUILD_\verbose \exception
	move	a0, sp
	PTR_LA	ra, ret_from_exception
	j	do_\handler
	END(handle_\exception)
	.endm

	.macro	BUILD_HANDLER exception handler clear verbose
	__BUILD_HANDLER	\exception \handler \clear \verbose _int
	.endm

	BUILD_HANDLER adel ade ade silent		/* #4  */
	BUILD_HANDLER ades ade ade silent		/* #5  */
	BUILD_HANDLER ibe be cli silent			/* #6  */
	BUILD_HANDLER dbe be cli silent			/* #7  */
	BUILD_HANDLER bp bp sti silent			/* #9  */
	BUILD_HANDLER ri ri sti silent			/* #10 */
	BUILD_HANDLER cpu cpu sti silent		/* #11 */
	BUILD_HANDLER ov ov sti silent			/* #12 */
	BUILD_HANDLER tr tr sti silent			/* #13 */
	BUILD_HANDLER fpe fpe fpe silent		/* #15 */
	BUILD_HANDLER mdmx mdmx sti silent		/* #22 */
#ifdef 	CONFIG_HARDWARE_WATCHPOINTS
	/*
	 * For watch, interrupts will be enabled after the watch
	 * registers are read.
	 */
	BUILD_HANDLER watch watch cli silent		/* #23 */
#else
	BUILD_HANDLER watch watch sti verbose		/* #23 */
#endif
	BUILD_HANDLER mcheck mcheck cli verbose		/* #24 */
	BUILD_HANDLER mt mt sti silent			/* #25 */
	BUILD_HANDLER dsp dsp sti silent		/* #26 */
	BUILD_HANDLER reserved reserved sti verbose	/* others */

	.align	5
	LEAF(handle_ri_rdhwr_vivt)
#ifdef CONFIG_MIPS_MT_SMTC
	PANIC_PIC("handle_ri_rdhwr_vivt called")
#else
	.set	push
	.set	noat
	.set	noreorder
	/* check if TLB contains a entry for EPC */
	MFC0	k1, CP0_ENTRYHI
	andi	k1, 0xff	/* ASID_MASK */
	MFC0	k0, CP0_EPC
	PTR_SRL	k0, PAGE_SHIFT + 1
	PTR_SLL	k0, PAGE_SHIFT + 1
	or	k1, k0
	MTC0	k1, CP0_ENTRYHI
	mtc0_tlbw_hazard
	tlbp
	tlb_probe_hazard
	mfc0	k1, CP0_INDEX
	.set	pop
	bltz	k1, handle_ri	/* slow path */
	/* fall thru */
#endif
	END(handle_ri_rdhwr_vivt)

	LEAF(handle_ri_rdhwr)
	.set	push
	.set	noat
	.set	noreorder
	/* 0x7c03e83b: rdhwr v1,$29 */
	MFC0	k1, CP0_EPC
	lui	k0, 0x7c03
	lw	k1, (k1)
	ori	k0, 0xe83b
	.set	reorder
	bne	k0, k1, handle_ri	/* if not ours */
	/* The insn is rdhwr.  No need to check CAUSE.BD here. */
	get_saved_sp	/* k1 := current_thread_info */
	.set	noreorder
	MFC0	k0, CP0_EPC
#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
	ori	k1, _THREAD_MASK
	xori	k1, _THREAD_MASK
	LONG_L	v1, TI_TP_VALUE(k1)
	LONG_ADDIU	k0, 4
	jr	k0
	 rfe
#else
#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
	LONG_ADDIU	k0, 4		/* stall on $k0 */
#else
	.set	at=v1
	LONG_ADDIU	k0, 4
	.set	noat
#endif
	MTC0	k0, CP0_EPC
	/* I hope three instructions between MTC0 and ERET are enough... */
	ori	k1, _THREAD_MASK
	xori	k1, _THREAD_MASK
	LONG_L	v1, TI_TP_VALUE(k1)
	.set	mips3
	eret
	.set	mips0
#endif
	.set	pop
	END(handle_ri_rdhwr)

#ifdef CONFIG_64BIT
/* A temporary overflow handler used by check_daddi(). */

	__INIT

	BUILD_HANDLER  daddi_ov daddi_ov none silent	/* #12 */
#endif
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 1994 - 2000, 2001, 2003 Ralf Baechle
	7	* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
	8	* Copyright (C) 2001 MIPS Technologies, Inc.
619b6e18	9	* Copyright (C) 2002, 2007 Maciej W. Rozycki
1da177e4	10	*/
1da177e4 LT	11	#include <linux/init.h>
	12
	13	#include <asm/asm.h>
41c594ab	14	#include <asm/asmmacro.h>
1da177e4	15	#include <asm/cacheops.h>
192ef366	16	#include <asm/irqflags.h>
1da177e4 LT	17	#include <asm/regdef.h>
	18	#include <asm/fpregdef.h>
	19	#include <asm/mipsregs.h>
	20	#include <asm/stackframe.h>
	21	#include <asm/war.h>
5b10496b	22	#include <asm/page.h>
c65a5480	23	#include <asm/thread_info.h>
1da177e4 LT	24
	25	#define PANIC_PIC(msg) \
	26	.set push; \
	27	.set reorder; \
	28	PTR_LA a0,8f; \
	29	.set noat; \
	30	PTR_LA AT, panic; \
	31	jr AT; \
	32	9: b 9b; \
	33	.set pop; \
	34	TEXT(msg)
	35
	36	__INIT
	37
	38	NESTED(except_vec0_generic, 0, sp)
	39	PANIC_PIC("Exception vector 0 called")
	40	END(except_vec0_generic)
	41
	42	NESTED(except_vec1_generic, 0, sp)
	43	PANIC_PIC("Exception vector 1 called")
	44	END(except_vec1_generic)
	45
	46	/*
	47	* General exception vector for all other CPUs.
	48	*
	49	* Be careful when changing this, it has to be at most 128 bytes
	50	* to fit into space reserved for the exception handler.
	51	*/
	52	NESTED(except_vec3_generic, 0, sp)
	53	.set push
	54	.set noat
	55	#if R5432_CP0_INTERRUPT_WAR
	56	mfc0 k0, CP0_INDEX
	57	#endif
	58	mfc0 k1, CP0_CAUSE
	59	andi k1, k1, 0x7c
875d43e7	60	#ifdef CONFIG_64BIT
1da177e4 LT	61	dsll k1, k1, 1
	62	#endif
	63	PTR_L k0, exception_handlers(k1)
	64	jr k0
	65	.set pop
	66	END(except_vec3_generic)
	67
	68	/*
	69	* General exception handler for CPUs with virtual coherency exception.
	70	*
	71	* Be careful when changing this, it has to be at most 256 (as a special
	72	* exception) bytes to fit into space reserved for the exception handler.
	73	*/
	74	NESTED(except_vec3_r4000, 0, sp)
	75	.set push
	76	.set mips3
	77	.set noat
	78	mfc0 k1, CP0_CAUSE
	79	li k0, 31<<2
	80	andi k1, k1, 0x7c
	81	.set push
	82	.set noreorder
	83	.set nomacro
	84	beq k1, k0, handle_vced
	85	li k0, 14<<2
	86	beq k1, k0, handle_vcei
875d43e7	87	#ifdef CONFIG_64BIT
69903d65	88	dsll k1, k1, 1
1da177e4 LT	89	#endif
	90	.set pop
	91	PTR_L k0, exception_handlers(k1)
	92	jr k0
	93
	94	/*
	95	* Big shit, we now may have two dirty primary cache lines for the same
69903d65	96	* physical address. We can safely invalidate the line pointed to by
1da177e4 LT	97	* c0_badvaddr because after return from this exception handler the
	98	* load / store will be re-executed.
	99	*/
	100	handle_vced:
69903d65	101	MFC0 k0, CP0_BADVADDR
1da177e4 LT	102	li k1, -4 # Is this ...
	103	and k0, k1 # ... really needed?
	104	mtc0 zero, CP0_TAGLO
69903d65 TS	105	cache Index_Store_Tag_D, (k0)
69903d65 TS	106	cache Hit_Writeback_Inv_SD, (k0)
1da177e4 LT	107	#ifdef CONFIG_PROC_FS
	108	PTR_LA k0, vced_count
	109	lw k1, (k0)
	110	addiu k1, 1
	111	sw k1, (k0)
	112	#endif
	113	eret
	114
	115	handle_vcei:
	116	MFC0 k0, CP0_BADVADDR
	117	cache Hit_Writeback_Inv_SD, (k0) # also cleans pi
	118	#ifdef CONFIG_PROC_FS
	119	PTR_LA k0, vcei_count
	120	lw k1, (k0)
	121	addiu k1, 1
	122	sw k1, (k0)
	123	#endif
	124	eret
	125	.set pop
	126	END(except_vec3_r4000)
	127
e4ac58af RB	128	__FINIT
e4ac58af RB	129
c65a5480 AN	130	.align 5 /* 32 byte rollback region */
	131	LEAF(r4k_wait)
	132	.set push
	133	.set noreorder
	134	/* start of rollback region */
	135	LONG_L t0, TI_FLAGS($28)
	136	nop
	137	andi t0, _TIF_NEED_RESCHED
	138	bnez t0, 1f
	139	nop
	140	nop
	141	nop
	142	.set mips3
	143	wait
	144	/* end of rollback region (the region size must be power of two) */
	145	.set pop
	146	1:
	147	jr ra
	148	END(r4k_wait)
	149
	150	.macro BUILD_ROLLBACK_PROLOGUE handler
	151	FEXPORT(rollback_\handler)
	152	.set push
	153	.set noat
	154	MFC0 k0, CP0_EPC
	155	PTR_LA k1, r4k_wait
	156	ori k0, 0x1f /* 32 byte rollback region */
	157	xori k0, 0x1f
	158	bne k0, k1, 9f
	159	MTC0 k0, CP0_EPC
	160	9:
	161	.set pop
	162	.endm
	163
e4ac58af	164	.align 5
c65a5480	165	BUILD_ROLLBACK_PROLOGUE handle_int
e4ac58af	166	NESTED(handle_int, PT_SIZE, sp)
fe99f1b1 CD	167	#ifdef CONFIG_TRACE_IRQFLAGS
	168	/*
	169	* Check to see if the interrupted code has just disabled
	170	* interrupts and ignore this interrupt for now if so.
	171	*
	172	* local_irq_disable() disables interrupts and then calls
	173	* trace_hardirqs_off() to track the state. If an interrupt is taken
	174	* after interrupts are disabled but before the state is updated
	175	* it will appear to restore_all that it is incorrectly returning with
	176	* interrupts disabled
	177	*/
	178	.set push
	179	.set noat
	180	mfc0 k0, CP0_STATUS
	181	#if defined(CONFIG_CPU_R3000) \|\| defined(CONFIG_CPU_TX39XX)
	182	and k0, ST0_IEP
	183	bnez k0, 1f
	184
c6563e85	185	mfc0 k0, CP0_EPC
fe99f1b1 CD	186	.set noreorder
	187	j k0
	188	rfe
	189	#else
	190	and k0, ST0_IE
	191	bnez k0, 1f
	192
	193	eret
	194	#endif
	195	1:
	196	.set pop
	197	#endif
e4ac58af RB	198	SAVE_ALL
e4ac58af RB	199	CLI
192ef366	200	TRACE_IRQS_OFF
e4ac58af	201
937a8015 RB	202	LONG_L s0, TI_REGS($28)
937a8015 RB	203	LONG_S sp, TI_REGS($28)
f431baa5 AN	204	PTR_LA ra, ret_from_irq
f431baa5 AN	205	j plat_irq_dispatch
e4ac58af RB	206	END(handle_int)
	207
	208	__INIT
	209
1da177e4 LT	210	/*
	211	* Special interrupt vector for MIPS64 ISA & embedded MIPS processors.
	212	* This is a dedicated interrupt exception vector which reduces the
	213	* interrupt processing overhead. The jump instruction will be replaced
	214	* at the initialization time.
	215	*
	216	* Be careful when changing this, it has to be at most 128 bytes
	217	* to fit into space reserved for the exception handler.
	218	*/
	219	NESTED(except_vec4, 0, sp)
	220	1: j 1b /* Dummy, will be replaced */
	221	END(except_vec4)
	222
	223	/*
	224	* EJTAG debug exception handler.
	225	* The EJTAG debug exception entry point is 0xbfc00480, which
	226	* normally is in the boot PROM, so the boot PROM must do a
	227	* unconditional jump to this vector.
	228	*/
	229	NESTED(except_vec_ejtag_debug, 0, sp)
	230	j ejtag_debug_handler
	231	END(except_vec_ejtag_debug)
	232
	233	__FINIT
	234
e01402b1 RB	235	/*
	236	* Vectored interrupt handler.
	237	* This prototype is copied to ebase + n*IntCtl.VS and patched
	238	* to invoke the handler
	239	*/
c65a5480	240	BUILD_ROLLBACK_PROLOGUE except_vec_vi
e01402b1 RB	241	NESTED(except_vec_vi, 0, sp)
	242	SAVE_SOME
	243	SAVE_AT
	244	.set push
	245	.set noreorder
41c594ab RB	246	#ifdef CONFIG_MIPS_MT_SMTC
	247	/*
	248	* To keep from blindly blocking all interrupts
	249	* during service by SMTC kernel, we also want to
	250	* pass the IM value to be cleared.
	251	*/
7df42461	252	FEXPORT(except_vec_vi_mori)
41c594ab RB	253	ori a0, $0, 0
41c594ab RB	254	#endif /* CONFIG_MIPS_MT_SMTC */
7df42461	255	FEXPORT(except_vec_vi_lui)
e01402b1 RB	256	lui v0, 0 /* Patched */
e01402b1 RB	257	j except_vec_vi_handler
7df42461	258	FEXPORT(except_vec_vi_ori)
e01402b1 RB	259	ori v0, 0 /* Patched */
	260	.set pop
	261	END(except_vec_vi)
	262	EXPORT(except_vec_vi_end)
	263
	264	/*
	265	* Common Vectored Interrupt code
	266	* Complete the register saves and invoke the handler which is passed in $v0
	267	*/
	268	NESTED(except_vec_vi_handler, 0, sp)
	269	SAVE_TEMP
	270	SAVE_STATIC
41c594ab RB	271	#ifdef CONFIG_MIPS_MT_SMTC
	272	/*
	273	* SMTC has an interesting problem that interrupts are level-triggered,
	274	* and the CLI macro will clear EXL, potentially causing a duplicate
	275	* interrupt service invocation. So we need to clear the associated
	276	* IM bit of Status prior to doing CLI, and restore it after the
	277	* service routine has been invoked - we must assume that the
	278	* service routine will have cleared the state, and any active
	279	* level represents a new or otherwised unserviced event...
	280	*/
	281	mfc0 t1, CP0_STATUS
	282	and t0, a0, t1
0db34215	283	#ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP
41c594ab	284	mfc0 t2, CP0_TCCONTEXT
8531a35e KK	285	or t2, t0, t2
8531a35e KK	286	mtc0 t2, CP0_TCCONTEXT
0db34215	287	#endif /* CONFIG_MIPS_MT_SMTC_IM_BACKSTOP */
41c594ab RB	288	xor t1, t1, t0
41c594ab RB	289	mtc0 t1, CP0_STATUS
4277ff5e	290	_ehb
41c594ab	291	#endif /* CONFIG_MIPS_MT_SMTC */
e01402b1	292	CLI
8c364435 RB	293	#ifdef CONFIG_TRACE_IRQFLAGS
	294	move s0, v0
	295	#ifdef CONFIG_MIPS_MT_SMTC
	296	move s1, a0
	297	#endif
192ef366	298	TRACE_IRQS_OFF
8c364435 RB	299	#ifdef CONFIG_MIPS_MT_SMTC
	300	move a0, s1
	301	#endif
	302	move v0, s0
	303	#endif
937a8015 RB	304
	305	LONG_L s0, TI_REGS($28)
	306	LONG_S sp, TI_REGS($28)
23126692	307	PTR_LA ra, ret_from_irq
f431baa5	308	jr v0
e01402b1 RB	309	END(except_vec_vi_handler)
e01402b1 RB	310
1da177e4 LT	311	/*
	312	* EJTAG debug exception handler.
	313	*/
	314	NESTED(ejtag_debug_handler, PT_SIZE, sp)
	315	.set push
	316	.set noat
	317	MTC0 k0, CP0_DESAVE
	318	mfc0 k0, CP0_DEBUG
	319
	320	sll k0, k0, 30 # Check for SDBBP.
	321	bgez k0, ejtag_return
	322
	323	PTR_LA k0, ejtag_debug_buffer
	324	LONG_S k1, 0(k0)
	325	SAVE_ALL
	326	move a0, sp
	327	jal ejtag_exception_handler
	328	RESTORE_ALL
	329	PTR_LA k0, ejtag_debug_buffer
	330	LONG_L k1, 0(k0)
	331
	332	ejtag_return:
	333	MFC0 k0, CP0_DESAVE
	334	.set mips32
	335	deret
	336	.set pop
	337	END(ejtag_debug_handler)
	338
	339	/*
	340	* This buffer is reserved for the use of the EJTAG debug
	341	* handler.
	342	*/
	343	.data
	344	EXPORT(ejtag_debug_buffer)
	345	.fill LONGSIZE
	346	.previous
	347
	348	__INIT
	349
	350	/*
	351	* NMI debug exception handler for MIPS reference boards.
	352	* The NMI debug exception entry point is 0xbfc00000, which
	353	* normally is in the boot PROM, so the boot PROM must do a
	354	* unconditional jump to this vector.
	355	*/
	356	NESTED(except_vec_nmi, 0, sp)
	357	j nmi_handler
	358	END(except_vec_nmi)
	359
	360	__FINIT
	361
	362	NESTED(nmi_handler, PT_SIZE, sp)
	363	.set push
	364	.set noat
1da177e4 LT	365	SAVE_ALL
	366	move a0, sp
	367	jal nmi_exception_handler
	368	RESTORE_ALL
4f0638ba	369	.set mips3
1da177e4 LT	370	eret
	371	.set pop
	372	END(nmi_handler)
	373
	374	.macro __build_clear_none
	375	.endm
	376
	377	.macro __build_clear_sti
192ef366	378	TRACE_IRQS_ON
1da177e4 LT	379	STI
	380	.endm
	381
	382	.macro __build_clear_cli
	383	CLI
192ef366	384	TRACE_IRQS_OFF
1da177e4 LT	385	.endm
	386
	387	.macro __build_clear_fpe
25c30003 DD	388	.set push
	389	/* gas fails to assemble cfc1 for some archs (octeon).*/ \
	390	.set mips1
1da177e4 LT	391	cfc1 a1, fcr31
	392	li a2, ~(0x3f << 12)
	393	and a2, a1
	394	ctc1 a2, fcr31
25c30003	395	.set pop
192ef366	396	TRACE_IRQS_ON
1da177e4 LT	397	STI
	398	.endm
	399
	400	.macro __build_clear_ade
	401	MFC0 t0, CP0_BADVADDR
	402	PTR_S t0, PT_BVADDR(sp)
	403	KMODE
	404	.endm
	405
	406	.macro __BUILD_silent exception
	407	.endm
	408
	409	/* Gas tries to parse the PRINT argument as a string containing
	410	string escapes and emits bogus warnings if it believes to
	411	recognize an unknown escape code. So make the arguments
	412	start with an n and gas will believe \n is ok ... */
	413	.macro __BUILD_verbose nexception
	414	LONG_L a1, PT_EPC(sp)
766160c2	415	#ifdef CONFIG_32BIT
1da177e4	416	PRINT("Got \nexception at %08lx\012")
42a3b4f2	417	#endif
766160c2	418	#ifdef CONFIG_64BIT
1da177e4	419	PRINT("Got \nexception at %016lx\012")
42a3b4f2	420	#endif
1da177e4 LT	421	.endm
	422
	423	.macro __BUILD_count exception
	424	LONG_L t0,exception_count_\exception
	425	LONG_ADDIU t0, 1
	426	LONG_S t0,exception_count_\exception
	427	.comm exception_count\exception, 8, 8
	428	.endm
	429
	430	.macro __BUILD_HANDLER exception handler clear verbose ext
	431	.align 5
	432	NESTED(handle_\exception, PT_SIZE, sp)
	433	.set noat
	434	SAVE_ALL
	435	FEXPORT(handle_\exception\ext)
	436	__BUILD_clear_\clear
	437	.set at
	438	__BUILD_\verbose \exception
	439	move a0, sp
23126692 AN	440	PTR_LA ra, ret_from_exception
23126692 AN	441	j do_\handler
1da177e4 LT	442	END(handle_\exception)
	443	.endm
	444
	445	.macro BUILD_HANDLER exception handler clear verbose
	446	__BUILD_HANDLER \exception \handler \clear \verbose _int
	447	.endm
	448
	449	BUILD_HANDLER adel ade ade silent /* #4 */
	450	BUILD_HANDLER ades ade ade silent /* #5 */
	451	BUILD_HANDLER ibe be cli silent /* #6 */
	452	BUILD_HANDLER dbe be cli silent /* #7 */
	453	BUILD_HANDLER bp bp sti silent /* #9 */
	454	BUILD_HANDLER ri ri sti silent /* #10 */
	455	BUILD_HANDLER cpu cpu sti silent /* #11 */
	456	BUILD_HANDLER ov ov sti silent /* #12 */
	457	BUILD_HANDLER tr tr sti silent /* #13 */
	458	BUILD_HANDLER fpe fpe fpe silent /* #15 */
	459	BUILD_HANDLER mdmx mdmx sti silent /* #22 */
b67b2b70	460	#ifdef CONFIG_HARDWARE_WATCHPOINTS
8bc6d05b DD	461	/*
	462	* For watch, interrupts will be enabled after the watch
	463	* registers are read.
	464	*/
	465	BUILD_HANDLER watch watch cli silent /* #23 */
b67b2b70	466	#else
1da177e4	467	BUILD_HANDLER watch watch sti verbose /* #23 */
b67b2b70	468	#endif
1da177e4	469	BUILD_HANDLER mcheck mcheck cli verbose /* #24 */
e35a5e35	470	BUILD_HANDLER mt mt sti silent /* #25 */
e50c0a8f	471	BUILD_HANDLER dsp dsp sti silent /* #26 */
1da177e4 LT	472	BUILD_HANDLER reserved reserved sti verbose /* others */
1da177e4 LT	473
5b10496b AN	474	.align 5
	475	LEAF(handle_ri_rdhwr_vivt)
	476	#ifdef CONFIG_MIPS_MT_SMTC
	477	PANIC_PIC("handle_ri_rdhwr_vivt called")
	478	#else
	479	.set push
	480	.set noat
	481	.set noreorder
	482	/* check if TLB contains a entry for EPC */
	483	MFC0 k1, CP0_ENTRYHI
	484	andi k1, 0xff /* ASID_MASK */
	485	MFC0 k0, CP0_EPC
	486	PTR_SRL k0, PAGE_SHIFT + 1
	487	PTR_SLL k0, PAGE_SHIFT + 1
	488	or k1, k0
	489	MTC0 k1, CP0_ENTRYHI
	490	mtc0_tlbw_hazard
	491	tlbp
	492	tlb_probe_hazard
	493	mfc0 k1, CP0_INDEX
	494	.set pop
	495	bltz k1, handle_ri /* slow path */
	496	/* fall thru */
	497	#endif
	498	END(handle_ri_rdhwr_vivt)
	499
	500	LEAF(handle_ri_rdhwr)
	501	.set push
	502	.set noat
	503	.set noreorder
	504	/* 0x7c03e83b: rdhwr v1,$29 */
	505	MFC0 k1, CP0_EPC
	506	lui k0, 0x7c03
	507	lw k1, (k1)
	508	ori k0, 0xe83b
	509	.set reorder
	510	bne k0, k1, handle_ri /* if not ours */
	511	/* The insn is rdhwr. No need to check CAUSE.BD here. */
	512	get_saved_sp /* k1 := current_thread_info */
	513	.set noreorder
	514	MFC0 k0, CP0_EPC
	515	#if defined(CONFIG_CPU_R3000) \|\| defined(CONFIG_CPU_TX39XX)
	516	ori k1, _THREAD_MASK
	517	xori k1, _THREAD_MASK
	518	LONG_L v1, TI_TP_VALUE(k1)
	519	LONG_ADDIU k0, 4
	520	jr k0
	521	rfe
	522	#else
619b6e18	523	#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
5b10496b	524	LONG_ADDIU k0, 4 /* stall on $k0 */
619b6e18 MR	525	#else
	526	.set at=v1
	527	LONG_ADDIU k0, 4
	528	.set noat
	529	#endif
5b10496b AN	530	MTC0 k0, CP0_EPC
	531	/* I hope three instructions between MTC0 and ERET are enough... */
	532	ori k1, _THREAD_MASK
	533	xori k1, _THREAD_MASK
	534	LONG_L v1, TI_TP_VALUE(k1)
	535	.set mips3
	536	eret
	537	.set mips0
	538	#endif
	539	.set pop
	540	END(handle_ri_rdhwr)
	541
875d43e7	542	#ifdef CONFIG_64BIT
1da177e4 LT	543	/* A temporary overflow handler used by check_daddi(). */
	544
	545	__INIT
	546
	547	BUILD_HANDLER daddi_ov daddi_ov none silent /* #12 */
	548	#endif