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MIPS: Probe for small (1KiB) page support
[linux-2.6-block.git] / arch / mips / kernel / cpu-probe.c
CommitLineData
1da177e4
LT		 1/*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
010b853b 5 * Copyright (C) 1994 - 2006 Ralf Baechle
4194318c 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
70342287 7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
1da177e4
LT		 8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
1da177e4
LT		 14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/ptrace.h>
631330f5 17#include <linux/smp.h>
1da177e4 18#include <linux/stddef.h>
73bc256d 19#include <linux/export.h>
1da177e4 20
5759906c 21#include <asm/bugs.h>
1da177e4 22#include <asm/cpu.h>
f6843626 23#include <asm/cpu-features.h>
69f24d17 24#include <asm/cpu-type.h>
1da177e4
LT		 25#include <asm/fpu.h>
26#include <asm/mipsregs.h>
30ee615b 27#include <asm/mipsmtregs.h>
a5e9a69e 28#include <asm/msa.h>
654f57bf 29#include <asm/watch.h>
06372a63 30#include <asm/elf.h>
4f12b91d 31#include <asm/pgtable-bits.h>
a074f0e8 32#include <asm/spram.h>
949e51be
DD		 33#include <asm/uaccess.h>
34
7aecd5ca
MR		 35/*
36 * Get the FPU Implementation/Revision.
37 */
38static inline unsigned long cpu_get_fpu_id(void)
39{
40 unsigned long tmp, fpu_id;
41
42 tmp = read_c0_status();
43 __enable_fpu(FPU_AS_IS);
44 fpu_id = read_32bit_cp1_register(CP1_REVISION);
45 write_c0_status(tmp);
46 return fpu_id;
47}
48
49/*
50 * Check if the CPU has an external FPU.
51 */
52static inline int __cpu_has_fpu(void)
53{
54 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
55}
56
57static inline unsigned long cpu_get_msa_id(void)
58{
59 unsigned long status, msa_id;
60
61 status = read_c0_status();
62 __enable_fpu(FPU_64BIT);
63 enable_msa();
64 msa_id = read_msa_ir();
65 disable_msa();
66 write_c0_status(status);
67 return msa_id;
68}
69
9b26616c
MR		 70/*
71 * Determine the FCSR mask for FPU hardware.
72 */
73static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c)
74{
75 unsigned long sr, mask, fcsr, fcsr0, fcsr1;
76
90b712dd 77 fcsr = c->fpu_csr31;
9b26616c
MR		 78 mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
79
80 sr = read_c0_status();
81 __enable_fpu(FPU_AS_IS);
82
9b26616c
MR		 83 fcsr0 = fcsr & mask;
84 write_32bit_cp1_register(CP1_STATUS, fcsr0);
85 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
86
87 fcsr1 = fcsr | ~mask;
88 write_32bit_cp1_register(CP1_STATUS, fcsr1);
89 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
90
91 write_32bit_cp1_register(CP1_STATUS, fcsr);
92
93 write_c0_status(sr);
94
95 c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask;
96}
97
f6843626
MR		 98/*
99 * Set the FIR feature flags for the FPU emulator.
100 */
101static void cpu_set_nofpu_id(struct cpuinfo_mips *c)
102{
103 u32 value;
104
105 value = 0;
106 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
107 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
108 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
109 value |= MIPS_FPIR_D | MIPS_FPIR_S;
110 if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
111 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
112 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W;
113 c->fpu_id = value;
114}
115
9b26616c
MR		 116/* Determined FPU emulator mask to use for the boot CPU with "nofpu". */
117static unsigned int mips_nofpu_msk31;
118
7aecd5ca
MR		 119/*
120 * Set options for FPU hardware.
121 */
122static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
123{
124 c->fpu_id = cpu_get_fpu_id();
125 mips_nofpu_msk31 = c->fpu_msk31;
126
127 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
128 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
129 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
130 if (c->fpu_id & MIPS_FPIR_3D)
131 c->ases |= MIPS_ASE_MIPS3D;
132 if (c->fpu_id & MIPS_FPIR_FREP)
133 c->options |= MIPS_CPU_FRE;
134 }
135
136 cpu_set_fpu_fcsr_mask(c);
137}
138
139/*
140 * Set options for the FPU emulator.
141 */
142static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
143{
144 c->options &= ~MIPS_CPU_FPU;
145 c->fpu_msk31 = mips_nofpu_msk31;
146
147 cpu_set_nofpu_id(c);
148}
149
078a55fc 150static int mips_fpu_disabled;
0103d23f
KC		 151
152static int __init fpu_disable(char *s)
153{
7aecd5ca 154 cpu_set_nofpu_opts(&boot_cpu_data);
0103d23f
KC		 155 mips_fpu_disabled = 1;
156
157 return 1;
158}
159
160__setup("nofpu", fpu_disable);
161
078a55fc 162int mips_dsp_disabled;
0103d23f
KC		 163
164static int __init dsp_disable(char *s)
165{
ee80f7c7 166 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
0103d23f
KC		 167 mips_dsp_disabled = 1;
168
169 return 1;
170}
171
172__setup("nodsp", dsp_disable);
173
3d528b32
MC		 174static int mips_htw_disabled;
175
176static int __init htw_disable(char *s)
177{
178 mips_htw_disabled = 1;
179 cpu_data[0].options &= ~MIPS_CPU_HTW;
180 write_c0_pwctl(read_c0_pwctl() &
181 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
182
183 return 1;
184}
185
186__setup("nohtw", htw_disable);
187
97f4ad29
MC		 188static int mips_ftlb_disabled;
189static int mips_has_ftlb_configured;
190
912708c2 191static int set_ftlb_enable(struct cpuinfo_mips *c, int enable);
97f4ad29
MC		 192
193static int __init ftlb_disable(char *s)
194{
195 unsigned int config4, mmuextdef;
196
197 /*
198 * If the core hasn't done any FTLB configuration, there is nothing
199 * for us to do here.
200 */
201 if (!mips_has_ftlb_configured)
202 return 1;
203
204 /* Disable it in the boot cpu */
912708c2
MC		 205 if (set_ftlb_enable(&cpu_data[0], 0)) {
206 pr_warn("Can't turn FTLB off\n");
207 return 1;
208 }
97f4ad29
MC		 209
210 back_to_back_c0_hazard();
211
212 config4 = read_c0_config4();
213
214 /* Check that FTLB has been disabled */
215 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
216 /* MMUSIZEEXT == VTLB ON, FTLB OFF */
217 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
218 /* This should never happen */
219 pr_warn("FTLB could not be disabled!\n");
220 return 1;
221 }
222
223 mips_ftlb_disabled = 1;
224 mips_has_ftlb_configured = 0;
225
226 /*
227 * noftlb is mainly used for debug purposes so print
228 * an informative message instead of using pr_debug()
229 */
230 pr_info("FTLB has been disabled\n");
231
232 /*
233 * Some of these bits are duplicated in the decode_config4.
234 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
235 * once FTLB has been disabled so undo what decode_config4 did.
236 */
237 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
238 cpu_data[0].tlbsizeftlbsets;
239 cpu_data[0].tlbsizeftlbsets = 0;
240 cpu_data[0].tlbsizeftlbways = 0;
241
242 return 1;
243}
244
245__setup("noftlb", ftlb_disable);
246
247
9267a30d
MSJ		 248static inline void check_errata(void)
249{
250 struct cpuinfo_mips *c = &current_cpu_data;
251
69f24d17 252 switch (current_cpu_type()) {
9267a30d
MSJ		 253 case CPU_34K:
254 /*
255 * Erratum "RPS May Cause Incorrect Instruction Execution"
b633648c 256 * This code only handles VPE0, any SMP/RTOS code
9267a30d
MSJ		 257 * making use of VPE1 will be responsable for that VPE.
258 */
259 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
260 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
261 break;
262 default:
263 break;
264 }
265}
266
1da177e4
LT		 267void __init check_bugs32(void)
268{
9267a30d 269 check_errata();
1da177e4
LT		 270}
271
272/*
273 * Probe whether cpu has config register by trying to play with
274 * alternate cache bit and see whether it matters.
275 * It's used by cpu_probe to distinguish between R3000A and R3081.
276 */
277static inline int cpu_has_confreg(void)
278{
279#ifdef CONFIG_CPU_R3000
280 extern unsigned long r3k_cache_size(unsigned long);
281 unsigned long size1, size2;
282 unsigned long cfg = read_c0_conf();
283
284 size1 = r3k_cache_size(ST0_ISC);
285 write_c0_conf(cfg ^ R30XX_CONF_AC);
286 size2 = r3k_cache_size(ST0_ISC);
287 write_c0_conf(cfg);
288 return size1 != size2;
289#else
290 return 0;
291#endif
292}
293
c094c99e
RM		 294static inline void set_elf_platform(int cpu, const char *plat)
295{
296 if (cpu == 0)
297 __elf_platform = plat;
298}
299
91dfc423
GR		 300static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
301{
302#ifdef __NEED_VMBITS_PROBE
5b7efa89 303 write_c0_entryhi(0x3fffffffffffe000ULL);
91dfc423 304 back_to_back_c0_hazard();
5b7efa89 305 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
91dfc423
GR		 306#endif
307}
308
078a55fc 309static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
a96102be
SH		 310{
311 switch (isa) {
312 case MIPS_CPU_ISA_M64R2:
313 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
314 case MIPS_CPU_ISA_M64R1:
315 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
316 case MIPS_CPU_ISA_V:
317 c->isa_level |= MIPS_CPU_ISA_V;
318 case MIPS_CPU_ISA_IV:
319 c->isa_level |= MIPS_CPU_ISA_IV;
320 case MIPS_CPU_ISA_III:
1990e542 321 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
a96102be
SH		 322 break;
323
8b8aa636
LY		 324 /* R6 incompatible with everything else */
325 case MIPS_CPU_ISA_M64R6:
326 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
327 case MIPS_CPU_ISA_M32R6:
328 c->isa_level |= MIPS_CPU_ISA_M32R6;
329 /* Break here so we don't add incompatible ISAs */
330 break;
a96102be
SH		 331 case MIPS_CPU_ISA_M32R2:
332 c->isa_level |= MIPS_CPU_ISA_M32R2;
333 case MIPS_CPU_ISA_M32R1:
334 c->isa_level |= MIPS_CPU_ISA_M32R1;
335 case MIPS_CPU_ISA_II:
336 c->isa_level |= MIPS_CPU_ISA_II;
a96102be
SH		 337 break;
338 }
339}
340
078a55fc 341static char unknown_isa[] = KERN_ERR \
2fa36399
KC		 342 "Unsupported ISA type, c0.config0: %d.";
343
cf0a8aa0
MC		 344static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
345{
346
347 unsigned int probability = c->tlbsize / c->tlbsizevtlb;
348
349 /*
350 * 0 = All TLBWR instructions go to FTLB
351 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
352 * FTLB and 1 goes to the VTLB.
353 * 2 = 7:1: As above with 7:1 ratio.
354 * 3 = 3:1: As above with 3:1 ratio.
355 *
356 * Use the linear midpoint as the probability threshold.
357 */
358 if (probability >= 12)
359 return 1;
360 else if (probability >= 6)
361 return 2;
362 else
363 /*
364 * So FTLB is less than 4 times bigger than VTLB.
365 * A 3:1 ratio can still be useful though.
366 */
367 return 3;
368}
369
912708c2 370static int set_ftlb_enable(struct cpuinfo_mips *c, int enable)
75b5b5e0 371{
20a7f7e5 372 unsigned int config;
d83b0e82
JH		 373
374 /* It's implementation dependent how the FTLB can be enabled */
375 switch (c->cputype) {
376 case CPU_PROAPTIV:
377 case CPU_P5600:
378 /* proAptiv & related cores use Config6 to enable the FTLB */
20a7f7e5 379 config = read_c0_config6();
cf0a8aa0 380 /* Clear the old probability value */
20a7f7e5 381 config &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
75b5b5e0
LY		 382 if (enable)
383 /* Enable FTLB */
20a7f7e5 384 write_c0_config6(config |
cf0a8aa0
MC		 385 (calculate_ftlb_probability(c)
386 << MIPS_CONF6_FTLBP_SHIFT)
387 | MIPS_CONF6_FTLBEN);
75b5b5e0
LY		 388 else
389 /* Disable FTLB */
20a7f7e5
MC		 390 write_c0_config6(config & ~MIPS_CONF6_FTLBEN);
391 break;
392 case CPU_I6400:
393 /* I6400 & related cores use Config7 to configure FTLB */
394 config = read_c0_config7();
395 /* Clear the old probability value */
396 config &= ~(3 << MIPS_CONF7_FTLBP_SHIFT);
397 write_c0_config7(config | (calculate_ftlb_probability(c)
398 << MIPS_CONF7_FTLBP_SHIFT));
d83b0e82 399 break;
912708c2
MC		 400 default:
401 return 1;
75b5b5e0 402 }
912708c2
MC		 403
404 return 0;
75b5b5e0
LY		 405}
406
2fa36399
KC		 407static inline unsigned int decode_config0(struct cpuinfo_mips *c)
408{
409 unsigned int config0;
410 int isa;
411
412 config0 = read_c0_config();
413
75b5b5e0
LY		 414 /*
415 * Look for Standard TLB or Dual VTLB and FTLB
416 */
417 if ((((config0 & MIPS_CONF_MT) >> 7) == 1) ||
418 (((config0 & MIPS_CONF_MT) >> 7) == 4))
2fa36399 419 c->options |= MIPS_CPU_TLB;
75b5b5e0 420
2fa36399
KC		 421 isa = (config0 & MIPS_CONF_AT) >> 13;
422 switch (isa) {
423 case 0:
424 switch ((config0 & MIPS_CONF_AR) >> 10) {
425 case 0:
a96102be 426 set_isa(c, MIPS_CPU_ISA_M32R1);
2fa36399
KC		 427 break;
428 case 1:
a96102be 429 set_isa(c, MIPS_CPU_ISA_M32R2);
2fa36399 430 break;
8b8aa636
LY		 431 case 2:
432 set_isa(c, MIPS_CPU_ISA_M32R6);
433 break;
2fa36399
KC		 434 default:
435 goto unknown;
436 }
437 break;
438 case 2:
439 switch ((config0 & MIPS_CONF_AR) >> 10) {
440 case 0:
a96102be 441 set_isa(c, MIPS_CPU_ISA_M64R1);
2fa36399
KC		 442 break;
443 case 1:
a96102be 444 set_isa(c, MIPS_CPU_ISA_M64R2);
2fa36399 445 break;
8b8aa636
LY		 446 case 2:
447 set_isa(c, MIPS_CPU_ISA_M64R6);
448 break;
2fa36399
KC		 449 default:
450 goto unknown;
451 }
452 break;
453 default:
454 goto unknown;
455 }
456
457 return config0 & MIPS_CONF_M;
458
459unknown:
460 panic(unknown_isa, config0);
461}
462
463static inline unsigned int decode_config1(struct cpuinfo_mips *c)
464{
465 unsigned int config1;
466
467 config1 = read_c0_config1();
468
469 if (config1 & MIPS_CONF1_MD)
470 c->ases |= MIPS_ASE_MDMX;
471 if (config1 & MIPS_CONF1_WR)
472 c->options |= MIPS_CPU_WATCH;
473 if (config1 & MIPS_CONF1_CA)
474 c->ases |= MIPS_ASE_MIPS16;
475 if (config1 & MIPS_CONF1_EP)
476 c->options |= MIPS_CPU_EJTAG;
477 if (config1 & MIPS_CONF1_FP) {
478 c->options |= MIPS_CPU_FPU;
479 c->options |= MIPS_CPU_32FPR;
480 }
75b5b5e0 481 if (cpu_has_tlb) {
2fa36399 482 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
75b5b5e0
LY		 483 c->tlbsizevtlb = c->tlbsize;
484 c->tlbsizeftlbsets = 0;
485 }
2fa36399
KC		 486
487 return config1 & MIPS_CONF_M;
488}
489
490static inline unsigned int decode_config2(struct cpuinfo_mips *c)
491{
492 unsigned int config2;
493
494 config2 = read_c0_config2();
495
496 if (config2 & MIPS_CONF2_SL)
497 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
498
499 return config2 & MIPS_CONF_M;
500}
501
502static inline unsigned int decode_config3(struct cpuinfo_mips *c)
503{
504 unsigned int config3;
505
506 config3 = read_c0_config3();
507
b2ab4f08 508 if (config3 & MIPS_CONF3_SM) {
2fa36399 509 c->ases |= MIPS_ASE_SMARTMIPS;
b2ab4f08
SH		 510 c->options |= MIPS_CPU_RIXI;
511 }
512 if (config3 & MIPS_CONF3_RXI)
513 c->options |= MIPS_CPU_RIXI;
2fa36399
KC		 514 if (config3 & MIPS_CONF3_DSP)
515 c->ases |= MIPS_ASE_DSP;
ee80f7c7
SH		 516 if (config3 & MIPS_CONF3_DSP2P)
517 c->ases |= MIPS_ASE_DSP2P;
2fa36399
KC		 518 if (config3 & MIPS_CONF3_VINT)
519 c->options |= MIPS_CPU_VINT;
520 if (config3 & MIPS_CONF3_VEIC)
521 c->options |= MIPS_CPU_VEIC;
522 if (config3 & MIPS_CONF3_MT)
523 c->ases |= MIPS_ASE_MIPSMT;
524 if (config3 & MIPS_CONF3_ULRI)
525 c->options |= MIPS_CPU_ULRI;
f8fa4811
SH		 526 if (config3 & MIPS_CONF3_ISA)
527 c->options |= MIPS_CPU_MICROMIPS;
1e7decdb
DD		 528 if (config3 & MIPS_CONF3_VZ)
529 c->ases |= MIPS_ASE_VZ;
4a0156fb
SH		 530 if (config3 & MIPS_CONF3_SC)
531 c->options |= MIPS_CPU_SEGMENTS;
a5e9a69e
PB		 532 if (config3 & MIPS_CONF3_MSA)
533 c->ases |= MIPS_ASE_MSA;
3d528b32 534 /* Only tested on 32-bit cores */
ed4cbc81
MC		 535 if ((config3 & MIPS_CONF3_PW) && config_enabled(CONFIG_32BIT)) {
536 c->htw_seq = 0;
3d528b32 537 c->options |= MIPS_CPU_HTW;
ed4cbc81 538 }
9b3274bd
JH		 539 if (config3 & MIPS_CONF3_CDMM)
540 c->options |= MIPS_CPU_CDMM;
aaa7be48
JH		 541 if (config3 & MIPS_CONF3_SP)
542 c->options |= MIPS_CPU_SP;
2fa36399
KC		 543
544 return config3 & MIPS_CONF_M;
545}
546
547static inline unsigned int decode_config4(struct cpuinfo_mips *c)
548{
549 unsigned int config4;
75b5b5e0
LY		 550 unsigned int newcf4;
551 unsigned int mmuextdef;
552 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
2fa36399
KC		 553
554 config4 = read_c0_config4();
555
1745c1ef
LY		 556 if (cpu_has_tlb) {
557 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
558 c->options |= MIPS_CPU_TLBINV;
e87569cd
MC		 559 /*
560 * This is a bit ugly. R6 has dropped that field from
561 * config4 and the only valid configuration is VTLB+FTLB so
562 * set a good value for mmuextdef for that case.
563 */
564 if (cpu_has_mips_r6)
565 mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT;
566 else
567 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
568
75b5b5e0
LY		 569 switch (mmuextdef) {
570 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
571 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
572 c->tlbsizevtlb = c->tlbsize;
573 break;
574 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
575 c->tlbsizevtlb +=
576 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
577 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
578 c->tlbsize = c->tlbsizevtlb;
579 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
580 /* fall through */
581 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
97f4ad29
MC		 582 if (mips_ftlb_disabled)
583 break;
75b5b5e0
LY		 584 newcf4 = (config4 & ~ftlb_page) |
585 (page_size_ftlb(mmuextdef) <<
586 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
587 write_c0_config4(newcf4);
588 back_to_back_c0_hazard();
589 config4 = read_c0_config4();
590 if (config4 != newcf4) {
591 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
592 PAGE_SIZE, config4);
593 /* Switch FTLB off */
594 set_ftlb_enable(c, 0);
595 break;
596 }
597 c->tlbsizeftlbsets = 1 <<
598 ((config4 & MIPS_CONF4_FTLBSETS) >>
599 MIPS_CONF4_FTLBSETS_SHIFT);
600 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
601 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
602 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
97f4ad29 603 mips_has_ftlb_configured = 1;
75b5b5e0
LY		 604 break;
605 }
1745c1ef
LY		 606 }
607
2fa36399
KC		 608 c->kscratch_mask = (config4 >> 16) & 0xff;
609
610 return config4 & MIPS_CONF_M;
611}
612
8b8a7634
RB		 613static inline unsigned int decode_config5(struct cpuinfo_mips *c)
614{
615 unsigned int config5;
616
617 config5 = read_c0_config5();
d175ed2b 618 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
8b8a7634
RB		 619 write_c0_config5(config5);
620
49016748
MC		 621 if (config5 & MIPS_CONF5_EVA)
622 c->options |= MIPS_CPU_EVA;
1f6c52ff
PB		 623 if (config5 & MIPS_CONF5_MRP)
624 c->options |= MIPS_CPU_MAAR;
5aed9da1
MC		 625 if (config5 & MIPS_CONF5_LLB)
626 c->options |= MIPS_CPU_RW_LLB;
c5b36783
SH		 627#ifdef CONFIG_XPA
628 if (config5 & MIPS_CONF5_MVH)
629 c->options |= MIPS_CPU_XPA;
630#endif
49016748 631
8b8a7634
RB		 632 return config5 & MIPS_CONF_M;
633}
634
078a55fc 635static void decode_configs(struct cpuinfo_mips *c)
2fa36399
KC		 636{
637 int ok;
638
639 /* MIPS32 or MIPS64 compliant CPU. */
640 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
641 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
642
643 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
644
97f4ad29
MC		 645 /* Enable FTLB if present and not disabled */
646 set_ftlb_enable(c, !mips_ftlb_disabled);
75b5b5e0 647
2fa36399 648 ok = decode_config0(c); /* Read Config registers. */
70342287 649 BUG_ON(!ok); /* Arch spec violation! */
2fa36399
KC		 650 if (ok)
651 ok = decode_config1(c);
652 if (ok)
653 ok = decode_config2(c);
654 if (ok)
655 ok = decode_config3(c);
656 if (ok)
657 ok = decode_config4(c);
8b8a7634
RB		 658 if (ok)
659 ok = decode_config5(c);
2fa36399
KC		 660
661 mips_probe_watch_registers(c);
662
6575b1d4
LY		 663 if (cpu_has_rixi) {
664 /* Enable the RIXI exceptions */
a5770df0 665 set_c0_pagegrain(PG_IEC);
6575b1d4
LY		 666 back_to_back_c0_hazard();
667 /* Verify the IEC bit is set */
668 if (read_c0_pagegrain() & PG_IEC)
669 c->options |= MIPS_CPU_RIXIEX;
670 }
671
0ee958e1 672#ifndef CONFIG_MIPS_CPS
8b8aa636 673 if (cpu_has_mips_r2_r6) {
45b585c8 674 c->core = get_ebase_cpunum();
30ee615b
PB		 675 if (cpu_has_mipsmt)
676 c->core >>= fls(core_nvpes()) - 1;
677 }
0ee958e1 678#endif
2fa36399
KC		 679}
680
02cf2119 681#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1da177e4
LT		 682 | MIPS_CPU_COUNTER)
683
cea7e2df 684static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 685{
8ff374b9 686 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 687 case PRID_IMP_R2000:
688 c->cputype = CPU_R2000;
cea7e2df 689 __cpu_name[cpu] = "R2000";
9b26616c 690 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
02cf2119 691 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 692 MIPS_CPU_NOFPUEX;
1da177e4
LT		 693 if (__cpu_has_fpu())
694 c->options |= MIPS_CPU_FPU;
695 c->tlbsize = 64;
696 break;
697 case PRID_IMP_R3000:
8ff374b9 698 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
cea7e2df 699 if (cpu_has_confreg()) {
1da177e4 700 c->cputype = CPU_R3081E;
cea7e2df
RB		 701 __cpu_name[cpu] = "R3081";
702 } else {
1da177e4 703 c->cputype = CPU_R3000A;
cea7e2df
RB		 704 __cpu_name[cpu] = "R3000A";
705 }
cea7e2df 706 } else {
1da177e4 707 c->cputype = CPU_R3000;
cea7e2df
RB		 708 __cpu_name[cpu] = "R3000";
709 }
9b26616c 710 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
02cf2119 711 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 712 MIPS_CPU_NOFPUEX;
1da177e4
LT		 713 if (__cpu_has_fpu())
714 c->options |= MIPS_CPU_FPU;
715 c->tlbsize = 64;
716 break;
717 case PRID_IMP_R4000:
718 if (read_c0_config() & CONF_SC) {
8ff374b9
MR		 719 if ((c->processor_id & PRID_REV_MASK) >=
720 PRID_REV_R4400) {
1da177e4 721 c->cputype = CPU_R4400PC;
cea7e2df
RB		 722 __cpu_name[cpu] = "R4400PC";
723 } else {
1da177e4 724 c->cputype = CPU_R4000PC;
cea7e2df
RB		 725 __cpu_name[cpu] = "R4000PC";
726 }
1da177e4 727 } else {
7f177a52
MR		 728 int cca = read_c0_config() & CONF_CM_CMASK;
729 int mc;
730
731 /*
732 * SC and MC versions can't be reliably told apart,
733 * but only the latter support coherent caching
734 * modes so assume the firmware has set the KSEG0
735 * coherency attribute reasonably (if uncached, we
736 * assume SC).
737 */
738 switch (cca) {
739 case CONF_CM_CACHABLE_CE:
740 case CONF_CM_CACHABLE_COW:
741 case CONF_CM_CACHABLE_CUW:
742 mc = 1;
743 break;
744 default:
745 mc = 0;
746 break;
747 }
8ff374b9
MR		 748 if ((c->processor_id & PRID_REV_MASK) >=
749 PRID_REV_R4400) {
7f177a52
MR		 750 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
751 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
cea7e2df 752 } else {
7f177a52
MR		 753 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
754 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
cea7e2df 755 }
1da177e4
LT		 756 }
757
a96102be 758 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 759 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4 760 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79
SH		 761 MIPS_CPU_WATCH | MIPS_CPU_VCE |
762 MIPS_CPU_LLSC;
1da177e4
LT		 763 c->tlbsize = 48;
764 break;
765 case PRID_IMP_VR41XX:
9f91e506 766 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 767 c->fpu_msk31 |= FPU_CSR_CONDX;
9f91e506
YY		 768 c->options = R4K_OPTS;
769 c->tlbsize = 32;
1da177e4 770 switch (c->processor_id & 0xf0) {
1da177e4
LT		 771 case PRID_REV_VR4111:
772 c->cputype = CPU_VR4111;
cea7e2df 773 __cpu_name[cpu] = "NEC VR4111";
1da177e4 774 break;
1da177e4
LT		 775 case PRID_REV_VR4121:
776 c->cputype = CPU_VR4121;
cea7e2df 777 __cpu_name[cpu] = "NEC VR4121";
1da177e4
LT		 778 break;
779 case PRID_REV_VR4122:
cea7e2df 780 if ((c->processor_id & 0xf) < 0x3) {
1da177e4 781 c->cputype = CPU_VR4122;
cea7e2df
RB		 782 __cpu_name[cpu] = "NEC VR4122";
783 } else {
1da177e4 784 c->cputype = CPU_VR4181A;
cea7e2df
RB		 785 __cpu_name[cpu] = "NEC VR4181A";
786 }
1da177e4
LT		 787 break;
788 case PRID_REV_VR4130:
cea7e2df 789 if ((c->processor_id & 0xf) < 0x4) {
1da177e4 790 c->cputype = CPU_VR4131;
cea7e2df
RB		 791 __cpu_name[cpu] = "NEC VR4131";
792 } else {
1da177e4 793 c->cputype = CPU_VR4133;
9f91e506 794 c->options |= MIPS_CPU_LLSC;
cea7e2df
RB		 795 __cpu_name[cpu] = "NEC VR4133";
796 }
1da177e4
LT		 797 break;
798 default:
799 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
800 c->cputype = CPU_VR41XX;
cea7e2df 801 __cpu_name[cpu] = "NEC Vr41xx";
1da177e4
LT		 802 break;
803 }
1da177e4
LT		 804 break;
805 case PRID_IMP_R4300:
806 c->cputype = CPU_R4300;
cea7e2df 807 __cpu_name[cpu] = "R4300";
a96102be 808 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 809 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4 810 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 811 MIPS_CPU_LLSC;
1da177e4
LT		 812 c->tlbsize = 32;
813 break;
814 case PRID_IMP_R4600:
815 c->cputype = CPU_R4600;
cea7e2df 816 __cpu_name[cpu] = "R4600";
a96102be 817 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 818 c->fpu_msk31 |= FPU_CSR_CONDX;
075e7502
TS		 819 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
820 MIPS_CPU_LLSC;
1da177e4
LT		 821 c->tlbsize = 48;
822 break;
823 #if 0
03751e79 824 case PRID_IMP_R4650:
1da177e4
LT		 825 /*
826 * This processor doesn't have an MMU, so it's not
827 * "real easy" to run Linux on it. It is left purely
828 * for documentation. Commented out because it shares
829 * it's c0_prid id number with the TX3900.
830 */
a3dddd56 831 c->cputype = CPU_R4650;
cea7e2df 832 __cpu_name[cpu] = "R4650";
a96102be 833 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 834 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4 835 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
03751e79 836 c->tlbsize = 48;
1da177e4
LT		 837 break;
838 #endif
839 case PRID_IMP_TX39:
9b26616c 840 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
02cf2119 841 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1da177e4
LT		 842
843 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
844 c->cputype = CPU_TX3927;
cea7e2df 845 __cpu_name[cpu] = "TX3927";
1da177e4
LT		 846 c->tlbsize = 64;
847 } else {
8ff374b9 848 switch (c->processor_id & PRID_REV_MASK) {
1da177e4
LT		 849 case PRID_REV_TX3912:
850 c->cputype = CPU_TX3912;
cea7e2df 851 __cpu_name[cpu] = "TX3912";
1da177e4
LT		 852 c->tlbsize = 32;
853 break;
854 case PRID_REV_TX3922:
855 c->cputype = CPU_TX3922;
cea7e2df 856 __cpu_name[cpu] = "TX3922";
1da177e4
LT		 857 c->tlbsize = 64;
858 break;
1da177e4
LT		 859 }
860 }
861 break;
862 case PRID_IMP_R4700:
863 c->cputype = CPU_R4700;
cea7e2df 864 __cpu_name[cpu] = "R4700";
a96102be 865 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 866 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4 867 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 868 MIPS_CPU_LLSC;
1da177e4
LT		 869 c->tlbsize = 48;
870 break;
871 case PRID_IMP_TX49:
872 c->cputype = CPU_TX49XX;
cea7e2df 873 __cpu_name[cpu] = "R49XX";
a96102be 874 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 875 c->fpu_msk31 |= FPU_CSR_CONDX;
1da177e4
LT		 876 c->options = R4K_OPTS | MIPS_CPU_LLSC;
877 if (!(c->processor_id & 0x08))
878 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
879 c->tlbsize = 48;
880 break;
881 case PRID_IMP_R5000:
882 c->cputype = CPU_R5000;
cea7e2df 883 __cpu_name[cpu] = "R5000";
a96102be 884 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 885 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 886 MIPS_CPU_LLSC;
1da177e4
LT		 887 c->tlbsize = 48;
888 break;
889 case PRID_IMP_R5432:
890 c->cputype = CPU_R5432;
cea7e2df 891 __cpu_name[cpu] = "R5432";
a96102be 892 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 893 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 894 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 895 c->tlbsize = 48;
896 break;
897 case PRID_IMP_R5500:
898 c->cputype = CPU_R5500;
cea7e2df 899 __cpu_name[cpu] = "R5500";
a96102be 900 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 901 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 902 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 903 c->tlbsize = 48;
904 break;
905 case PRID_IMP_NEVADA:
906 c->cputype = CPU_NEVADA;
cea7e2df 907 __cpu_name[cpu] = "Nevada";
a96102be 908 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 909 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 910 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
1da177e4
LT		 911 c->tlbsize = 48;
912 break;
913 case PRID_IMP_R6000:
914 c->cputype = CPU_R6000;
cea7e2df 915 __cpu_name[cpu] = "R6000";
a96102be 916 set_isa(c, MIPS_CPU_ISA_II);
9b26616c 917 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1da177e4 918 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 919 MIPS_CPU_LLSC;
1da177e4
LT		 920 c->tlbsize = 32;
921 break;
922 case PRID_IMP_R6000A:
923 c->cputype = CPU_R6000A;
cea7e2df 924 __cpu_name[cpu] = "R6000A";
a96102be 925 set_isa(c, MIPS_CPU_ISA_II);
9b26616c 926 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1da177e4 927 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 928 MIPS_CPU_LLSC;
1da177e4
LT		 929 c->tlbsize = 32;
930 break;
931 case PRID_IMP_RM7000:
932 c->cputype = CPU_RM7000;
cea7e2df 933 __cpu_name[cpu] = "RM7000";
a96102be 934 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 935 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 936 MIPS_CPU_LLSC;
1da177e4 937 /*
70342287 938 * Undocumented RM7000: Bit 29 in the info register of
1da177e4
LT		 939 * the RM7000 v2.0 indicates if the TLB has 48 or 64
940 * entries.
941 *
70342287
RB		 942 * 29 1 => 64 entry JTLB
943 * 0 => 48 entry JTLB
1da177e4
LT		 944 */
945 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
1da177e4
LT		 946 break;
947 case PRID_IMP_R8000:
948 c->cputype = CPU_R8000;
cea7e2df 949 __cpu_name[cpu] = "RM8000";
a96102be 950 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 951 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
03751e79
SH		 952 MIPS_CPU_FPU | MIPS_CPU_32FPR |
953 MIPS_CPU_LLSC;
1da177e4
LT		 954 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
955 break;
956 case PRID_IMP_R10000:
957 c->cputype = CPU_R10000;
cea7e2df 958 __cpu_name[cpu] = "R10000";
a96102be 959 set_isa(c, MIPS_CPU_ISA_IV);
8b36612a 960 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 961 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 962 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 963 MIPS_CPU_LLSC;
1da177e4
LT		 964 c->tlbsize = 64;
965 break;
966 case PRID_IMP_R12000:
967 c->cputype = CPU_R12000;
cea7e2df 968 __cpu_name[cpu] = "R12000";
a96102be 969 set_isa(c, MIPS_CPU_ISA_IV);
8b36612a 970 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 971 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 972 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
8d5ded16 973 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
1da177e4
LT		 974 c->tlbsize = 64;
975 break;
44d921b2 976 case PRID_IMP_R14000:
30577391
JK		 977 if (((c->processor_id >> 4) & 0x0f) > 2) {
978 c->cputype = CPU_R16000;
979 __cpu_name[cpu] = "R16000";
980 } else {
981 c->cputype = CPU_R14000;
982 __cpu_name[cpu] = "R14000";
983 }
a96102be 984 set_isa(c, MIPS_CPU_ISA_IV);
44d921b2 985 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 986 MIPS_CPU_FPU | MIPS_CPU_32FPR |
44d921b2 987 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
8d5ded16 988 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
44d921b2
K		 989 c->tlbsize = 64;
990 break;
26859198 991 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
5aac1e8a
RM		 992 switch (c->processor_id & PRID_REV_MASK) {
993 case PRID_REV_LOONGSON2E:
c579d310
HC		 994 c->cputype = CPU_LOONGSON2;
995 __cpu_name[cpu] = "ICT Loongson-2";
5aac1e8a 996 set_elf_platform(cpu, "loongson2e");
7352c8b1 997 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 998 c->fpu_msk31 |= FPU_CSR_CONDX;
5aac1e8a
RM		 999 break;
1000 case PRID_REV_LOONGSON2F:
c579d310
HC		 1001 c->cputype = CPU_LOONGSON2;
1002 __cpu_name[cpu] = "ICT Loongson-2";
5aac1e8a 1003 set_elf_platform(cpu, "loongson2f");
7352c8b1 1004 set_isa(c, MIPS_CPU_ISA_III);
9b26616c 1005 c->fpu_msk31 |= FPU_CSR_CONDX;
5aac1e8a 1006 break;
c579d310
HC		 1007 case PRID_REV_LOONGSON3A:
1008 c->cputype = CPU_LOONGSON3;
1009 __cpu_name[cpu] = "ICT Loongson-3";
1010 set_elf_platform(cpu, "loongson3a");
7352c8b1 1011 set_isa(c, MIPS_CPU_ISA_M64R1);
c579d310 1012 break;
e7841be5
HC		 1013 case PRID_REV_LOONGSON3B_R1:
1014 case PRID_REV_LOONGSON3B_R2:
1015 c->cputype = CPU_LOONGSON3;
1016 __cpu_name[cpu] = "ICT Loongson-3";
1017 set_elf_platform(cpu, "loongson3b");
7352c8b1 1018 set_isa(c, MIPS_CPU_ISA_M64R1);
e7841be5 1019 break;
5aac1e8a
RM		 1020 }
1021
2a21c730
FZ		 1022 c->options = R4K_OPTS |
1023 MIPS_CPU_FPU | MIPS_CPU_LLSC |
1024 MIPS_CPU_32FPR;
1025 c->tlbsize = 64;
cc94ea31 1026 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
2a21c730 1027 break;
26859198 1028 case PRID_IMP_LOONGSON_32: /* Loongson-1 */
2fa36399 1029 decode_configs(c);
b4672d37 1030
2fa36399 1031 c->cputype = CPU_LOONGSON1;
1da177e4 1032
2fa36399
KC		 1033 switch (c->processor_id & PRID_REV_MASK) {
1034 case PRID_REV_LOONGSON1B:
1035 __cpu_name[cpu] = "Loongson 1B";
b4672d37 1036 break;
b4672d37 1037 }
4194318c 1038
2fa36399 1039 break;
1da177e4 1040 }
1da177e4
LT		 1041}
1042
cea7e2df 1043static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1044{
4f12b91d 1045 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
8ff374b9 1046 switch (c->processor_id & PRID_IMP_MASK) {
b2498af5
LY		 1047 case PRID_IMP_QEMU_GENERIC:
1048 c->writecombine = _CACHE_UNCACHED;
1049 c->cputype = CPU_QEMU_GENERIC;
1050 __cpu_name[cpu] = "MIPS GENERIC QEMU";
1051 break;
1da177e4
LT		 1052 case PRID_IMP_4KC:
1053 c->cputype = CPU_4KC;
4f12b91d 1054 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1055 __cpu_name[cpu] = "MIPS 4Kc";
1da177e4
LT		 1056 break;
1057 case PRID_IMP_4KEC:
2b07bd02
RB		 1058 case PRID_IMP_4KECR2:
1059 c->cputype = CPU_4KEC;
4f12b91d 1060 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1061 __cpu_name[cpu] = "MIPS 4KEc";
2b07bd02 1062 break;
1da177e4 1063 case PRID_IMP_4KSC:
8afcb5d8 1064 case PRID_IMP_4KSD:
1da177e4 1065 c->cputype = CPU_4KSC;
4f12b91d 1066 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1067 __cpu_name[cpu] = "MIPS 4KSc";
1da177e4
LT		 1068 break;
1069 case PRID_IMP_5KC:
1070 c->cputype = CPU_5KC;
4f12b91d 1071 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1072 __cpu_name[cpu] = "MIPS 5Kc";
1da177e4 1073 break;
78d4803f
LY		 1074 case PRID_IMP_5KE:
1075 c->cputype = CPU_5KE;
4f12b91d 1076 c->writecombine = _CACHE_UNCACHED;
78d4803f
LY		 1077 __cpu_name[cpu] = "MIPS 5KE";
1078 break;
1da177e4
LT		 1079 case PRID_IMP_20KC:
1080 c->cputype = CPU_20KC;
4f12b91d 1081 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1082 __cpu_name[cpu] = "MIPS 20Kc";
1da177e4
LT		 1083 break;
1084 case PRID_IMP_24K:
1085 c->cputype = CPU_24K;
4f12b91d 1086 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1087 __cpu_name[cpu] = "MIPS 24Kc";
1da177e4 1088 break;
42f3caef
JC		 1089 case PRID_IMP_24KE:
1090 c->cputype = CPU_24K;
4f12b91d 1091 c->writecombine = _CACHE_UNCACHED;
42f3caef
JC		 1092 __cpu_name[cpu] = "MIPS 24KEc";
1093 break;
1da177e4
LT		 1094 case PRID_IMP_25KF:
1095 c->cputype = CPU_25KF;
4f12b91d 1096 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1097 __cpu_name[cpu] = "MIPS 25Kc";
1da177e4 1098 break;
bbc7f22f
RB		 1099 case PRID_IMP_34K:
1100 c->cputype = CPU_34K;
4f12b91d 1101 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1102 __cpu_name[cpu] = "MIPS 34Kc";
bbc7f22f 1103 break;
c620953c
CD		 1104 case PRID_IMP_74K:
1105 c->cputype = CPU_74K;
4f12b91d 1106 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1107 __cpu_name[cpu] = "MIPS 74Kc";
c620953c 1108 break;
113c62d9
SH		 1109 case PRID_IMP_M14KC:
1110 c->cputype = CPU_M14KC;
4f12b91d 1111 c->writecombine = _CACHE_UNCACHED;
113c62d9
SH		 1112 __cpu_name[cpu] = "MIPS M14Kc";
1113 break;
f8fa4811
SH		 1114 case PRID_IMP_M14KEC:
1115 c->cputype = CPU_M14KEC;
4f12b91d 1116 c->writecombine = _CACHE_UNCACHED;
f8fa4811
SH		 1117 __cpu_name[cpu] = "MIPS M14KEc";
1118 break;
39b8d525
RB		 1119 case PRID_IMP_1004K:
1120 c->cputype = CPU_1004K;
4f12b91d 1121 c->writecombine = _CACHE_UNCACHED;
cea7e2df 1122 __cpu_name[cpu] = "MIPS 1004Kc";
39b8d525 1123 break;
006a851b 1124 case PRID_IMP_1074K:
442e14a2 1125 c->cputype = CPU_1074K;
4f12b91d 1126 c->writecombine = _CACHE_UNCACHED;
006a851b
SH		 1127 __cpu_name[cpu] = "MIPS 1074Kc";
1128 break;
b5f065e7
LY		 1129 case PRID_IMP_INTERAPTIV_UP:
1130 c->cputype = CPU_INTERAPTIV;
1131 __cpu_name[cpu] = "MIPS interAptiv";
1132 break;
1133 case PRID_IMP_INTERAPTIV_MP:
1134 c->cputype = CPU_INTERAPTIV;
1135 __cpu_name[cpu] = "MIPS interAptiv (multi)";
1136 break;
b0d4d300
LY		 1137 case PRID_IMP_PROAPTIV_UP:
1138 c->cputype = CPU_PROAPTIV;
1139 __cpu_name[cpu] = "MIPS proAptiv";
1140 break;
1141 case PRID_IMP_PROAPTIV_MP:
1142 c->cputype = CPU_PROAPTIV;
1143 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1144 break;
829dcc0a
JH		 1145 case PRID_IMP_P5600:
1146 c->cputype = CPU_P5600;
1147 __cpu_name[cpu] = "MIPS P5600";
1148 break;
e57f9a2d
MC		 1149 case PRID_IMP_I6400:
1150 c->cputype = CPU_I6400;
1151 __cpu_name[cpu] = "MIPS I6400";
1152 break;
9943ed92
LY		 1153 case PRID_IMP_M5150:
1154 c->cputype = CPU_M5150;
1155 __cpu_name[cpu] = "MIPS M5150";
1156 break;
1da177e4 1157 }
0b6d497f 1158
75b5b5e0
LY		 1159 decode_configs(c);
1160
0b6d497f 1161 spram_config();
1da177e4
LT		 1162}
1163
cea7e2df 1164static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1165{
4194318c 1166 decode_configs(c);
8ff374b9 1167 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 1168 case PRID_IMP_AU1_REV1:
1169 case PRID_IMP_AU1_REV2:
270717a8 1170 c->cputype = CPU_ALCHEMY;
1da177e4
LT		 1171 switch ((c->processor_id >> 24) & 0xff) {
1172 case 0:
cea7e2df 1173 __cpu_name[cpu] = "Au1000";
1da177e4
LT		 1174 break;
1175 case 1:
cea7e2df 1176 __cpu_name[cpu] = "Au1500";
1da177e4
LT		 1177 break;
1178 case 2:
cea7e2df 1179 __cpu_name[cpu] = "Au1100";
1da177e4
LT		 1180 break;
1181 case 3:
cea7e2df 1182 __cpu_name[cpu] = "Au1550";
1da177e4 1183 break;
e3ad1c23 1184 case 4:
cea7e2df 1185 __cpu_name[cpu] = "Au1200";
8ff374b9 1186 if ((c->processor_id & PRID_REV_MASK) == 2)
cea7e2df 1187 __cpu_name[cpu] = "Au1250";
237cfee1
ML		 1188 break;
1189 case 5:
cea7e2df 1190 __cpu_name[cpu] = "Au1210";
e3ad1c23 1191 break;
1da177e4 1192 default:
270717a8 1193 __cpu_name[cpu] = "Au1xxx";
1da177e4
LT		 1194 break;
1195 }
1da177e4
LT		 1196 break;
1197 }
1198}
1199
cea7e2df 1200static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1201{
4194318c 1202 decode_configs(c);
02cf2119 1203
4f12b91d 1204 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
8ff374b9 1205 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 1206 case PRID_IMP_SB1:
1207 c->cputype = CPU_SB1;
cea7e2df 1208 __cpu_name[cpu] = "SiByte SB1";
1da177e4 1209 /* FPU in pass1 is known to have issues. */
8ff374b9 1210 if ((c->processor_id & PRID_REV_MASK) < 0x02)
010b853b 1211 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1da177e4 1212 break;
93ce2f52
AI		 1213 case PRID_IMP_SB1A:
1214 c->cputype = CPU_SB1A;
cea7e2df 1215 __cpu_name[cpu] = "SiByte SB1A";
93ce2f52 1216 break;
1da177e4
LT		 1217 }
1218}
1219
cea7e2df 1220static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1221{
4194318c 1222 decode_configs(c);
8ff374b9 1223 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 1224 case PRID_IMP_SR71000:
1225 c->cputype = CPU_SR71000;
cea7e2df 1226 __cpu_name[cpu] = "Sandcraft SR71000";
1da177e4
LT		 1227 c->scache.ways = 8;
1228 c->tlbsize = 64;
1229 break;
1230 }
1231}
1232
cea7e2df 1233static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
bdf21b18
PP		 1234{
1235 decode_configs(c);
8ff374b9 1236 switch (c->processor_id & PRID_IMP_MASK) {
bdf21b18
PP		 1237 case PRID_IMP_PR4450:
1238 c->cputype = CPU_PR4450;
cea7e2df 1239 __cpu_name[cpu] = "Philips PR4450";
a96102be 1240 set_isa(c, MIPS_CPU_ISA_M32R1);
bdf21b18 1241 break;
bdf21b18
PP		 1242 }
1243}
1244
cea7e2df 1245static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1c0c13eb
AJ		 1246{
1247 decode_configs(c);
8ff374b9 1248 switch (c->processor_id & PRID_IMP_MASK) {
190fca3e
KC		 1249 case PRID_IMP_BMIPS32_REV4:
1250 case PRID_IMP_BMIPS32_REV8:
602977b0
KC		 1251 c->cputype = CPU_BMIPS32;
1252 __cpu_name[cpu] = "Broadcom BMIPS32";
06785df0 1253 set_elf_platform(cpu, "bmips32");
602977b0
KC		 1254 break;
1255 case PRID_IMP_BMIPS3300:
1256 case PRID_IMP_BMIPS3300_ALT:
1257 case PRID_IMP_BMIPS3300_BUG:
1258 c->cputype = CPU_BMIPS3300;
1259 __cpu_name[cpu] = "Broadcom BMIPS3300";
06785df0 1260 set_elf_platform(cpu, "bmips3300");
602977b0
KC		 1261 break;
1262 case PRID_IMP_BMIPS43XX: {
8ff374b9 1263 int rev = c->processor_id & PRID_REV_MASK;
602977b0
KC		 1264
1265 if (rev >= PRID_REV_BMIPS4380_LO &&
1266 rev <= PRID_REV_BMIPS4380_HI) {
1267 c->cputype = CPU_BMIPS4380;
1268 __cpu_name[cpu] = "Broadcom BMIPS4380";
06785df0 1269 set_elf_platform(cpu, "bmips4380");
602977b0
KC		 1270 } else {
1271 c->cputype = CPU_BMIPS4350;
1272 __cpu_name[cpu] = "Broadcom BMIPS4350";
06785df0 1273 set_elf_platform(cpu, "bmips4350");
602977b0 1274 }
0de663ef 1275 break;
602977b0
KC		 1276 }
1277 case PRID_IMP_BMIPS5000:
68e6a783 1278 case PRID_IMP_BMIPS5200:
602977b0
KC		 1279 c->cputype = CPU_BMIPS5000;
1280 __cpu_name[cpu] = "Broadcom BMIPS5000";
06785df0 1281 set_elf_platform(cpu, "bmips5000");
602977b0 1282 c->options |= MIPS_CPU_ULRI;
0de663ef 1283 break;
1c0c13eb
AJ		 1284 }
1285}
1286
0dd4781b
DD		 1287static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1288{
1289 decode_configs(c);
8ff374b9 1290 switch (c->processor_id & PRID_IMP_MASK) {
0dd4781b
DD		 1291 case PRID_IMP_CAVIUM_CN38XX:
1292 case PRID_IMP_CAVIUM_CN31XX:
1293 case PRID_IMP_CAVIUM_CN30XX:
6f329468
DD		 1294 c->cputype = CPU_CAVIUM_OCTEON;
1295 __cpu_name[cpu] = "Cavium Octeon";
1296 goto platform;
0dd4781b
DD		 1297 case PRID_IMP_CAVIUM_CN58XX:
1298 case PRID_IMP_CAVIUM_CN56XX:
1299 case PRID_IMP_CAVIUM_CN50XX:
1300 case PRID_IMP_CAVIUM_CN52XX:
6f329468
DD		 1301 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1302 __cpu_name[cpu] = "Cavium Octeon+";
1303platform:
c094c99e 1304 set_elf_platform(cpu, "octeon");
0dd4781b 1305 break;
a1431b61 1306 case PRID_IMP_CAVIUM_CN61XX:
0e56b385 1307 case PRID_IMP_CAVIUM_CN63XX:
a1431b61
DD		 1308 case PRID_IMP_CAVIUM_CN66XX:
1309 case PRID_IMP_CAVIUM_CN68XX:
af04bb85 1310 case PRID_IMP_CAVIUM_CNF71XX:
0e56b385
DD		 1311 c->cputype = CPU_CAVIUM_OCTEON2;
1312 __cpu_name[cpu] = "Cavium Octeon II";
c094c99e 1313 set_elf_platform(cpu, "octeon2");
0e56b385 1314 break;
af04bb85
DD		 1315 case PRID_IMP_CAVIUM_CN70XX:
1316 case PRID_IMP_CAVIUM_CN78XX:
1317 c->cputype = CPU_CAVIUM_OCTEON3;
1318 __cpu_name[cpu] = "Cavium Octeon III";
1319 set_elf_platform(cpu, "octeon3");
1320 break;
0dd4781b
DD		 1321 default:
1322 printk(KERN_INFO "Unknown Octeon chip!\n");
1323 c->cputype = CPU_UNKNOWN;
1324 break;
1325 }
1326}
1327
83ccf69d
LPC		 1328static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1329{
1330 decode_configs(c);
1331 /* JZRISC does not implement the CP0 counter. */
1332 c->options &= ~MIPS_CPU_COUNTER;
06947aaa 1333 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
8ff374b9 1334 switch (c->processor_id & PRID_IMP_MASK) {
83ccf69d
LPC		 1335 case PRID_IMP_JZRISC:
1336 c->cputype = CPU_JZRISC;
4f12b91d 1337 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
83ccf69d
LPC		 1338 __cpu_name[cpu] = "Ingenic JZRISC";
1339 break;
1340 default:
1341 panic("Unknown Ingenic Processor ID!");
1342 break;
1343 }
1344}
1345
a7117c6b
J		 1346static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1347{
1348 decode_configs(c);
1349
8ff374b9 1350 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
809f36c6
ML		 1351 c->cputype = CPU_ALCHEMY;
1352 __cpu_name[cpu] = "Au1300";
1353 /* following stuff is not for Alchemy */
1354 return;
1355 }
1356
70342287
RB		 1357 c->options = (MIPS_CPU_TLB |
1358 MIPS_CPU_4KEX |
a7117c6b 1359 MIPS_CPU_COUNTER |
70342287
RB		 1360 MIPS_CPU_DIVEC |
1361 MIPS_CPU_WATCH |
1362 MIPS_CPU_EJTAG |
a7117c6b
J		 1363 MIPS_CPU_LLSC);
1364
8ff374b9 1365 switch (c->processor_id & PRID_IMP_MASK) {
4ca86a2f 1366 case PRID_IMP_NETLOGIC_XLP2XX:
8907c55e 1367 case PRID_IMP_NETLOGIC_XLP9XX:
1c983986 1368 case PRID_IMP_NETLOGIC_XLP5XX:
4ca86a2f
J		 1369 c->cputype = CPU_XLP;
1370 __cpu_name[cpu] = "Broadcom XLPII";
1371 break;
1372
2aa54b20
J		 1373 case PRID_IMP_NETLOGIC_XLP8XX:
1374 case PRID_IMP_NETLOGIC_XLP3XX:
a3d4fb2d
J		 1375 c->cputype = CPU_XLP;
1376 __cpu_name[cpu] = "Netlogic XLP";
1377 break;
1378
a7117c6b
J		 1379 case PRID_IMP_NETLOGIC_XLR732:
1380 case PRID_IMP_NETLOGIC_XLR716:
1381 case PRID_IMP_NETLOGIC_XLR532:
1382 case PRID_IMP_NETLOGIC_XLR308:
1383 case PRID_IMP_NETLOGIC_XLR532C:
1384 case PRID_IMP_NETLOGIC_XLR516C:
1385 case PRID_IMP_NETLOGIC_XLR508C:
1386 case PRID_IMP_NETLOGIC_XLR308C:
1387 c->cputype = CPU_XLR;
1388 __cpu_name[cpu] = "Netlogic XLR";
1389 break;
1390
1391 case PRID_IMP_NETLOGIC_XLS608:
1392 case PRID_IMP_NETLOGIC_XLS408:
1393 case PRID_IMP_NETLOGIC_XLS404:
1394 case PRID_IMP_NETLOGIC_XLS208:
1395 case PRID_IMP_NETLOGIC_XLS204:
1396 case PRID_IMP_NETLOGIC_XLS108:
1397 case PRID_IMP_NETLOGIC_XLS104:
1398 case PRID_IMP_NETLOGIC_XLS616B:
1399 case PRID_IMP_NETLOGIC_XLS608B:
1400 case PRID_IMP_NETLOGIC_XLS416B:
1401 case PRID_IMP_NETLOGIC_XLS412B:
1402 case PRID_IMP_NETLOGIC_XLS408B:
1403 case PRID_IMP_NETLOGIC_XLS404B:
1404 c->cputype = CPU_XLR;
1405 __cpu_name[cpu] = "Netlogic XLS";
1406 break;
1407
1408 default:
a3d4fb2d 1409 pr_info("Unknown Netlogic chip id [%02x]!\n",
a7117c6b
J		 1410 c->processor_id);
1411 c->cputype = CPU_XLR;
1412 break;
1413 }
1414
a3d4fb2d 1415 if (c->cputype == CPU_XLP) {
a96102be 1416 set_isa(c, MIPS_CPU_ISA_M64R2);
a3d4fb2d
J		 1417 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1418 /* This will be updated again after all threads are woken up */
1419 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1420 } else {
a96102be 1421 set_isa(c, MIPS_CPU_ISA_M64R1);
a3d4fb2d
J		 1422 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1423 }
7777b939 1424 c->kscratch_mask = 0xf;
a7117c6b
J		 1425}
1426
949e51be
DD		 1427#ifdef CONFIG_64BIT
1428/* For use by uaccess.h */
1429u64 __ua_limit;
1430EXPORT_SYMBOL(__ua_limit);
1431#endif
1432
9966db25 1433const char *__cpu_name[NR_CPUS];
874fd3b5 1434const char *__elf_platform;
9966db25 1435
078a55fc 1436void cpu_probe(void)
1da177e4
LT		 1437{
1438 struct cpuinfo_mips *c = &current_cpu_data;
9966db25 1439 unsigned int cpu = smp_processor_id();
1da177e4 1440
70342287 1441 c->processor_id = PRID_IMP_UNKNOWN;
1da177e4
LT		 1442 c->fpu_id = FPIR_IMP_NONE;
1443 c->cputype = CPU_UNKNOWN;
4f12b91d 1444 c->writecombine = _CACHE_UNCACHED;
1da177e4 1445
9b26616c
MR		 1446 c->fpu_csr31 = FPU_CSR_RN;
1447 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
1448
1da177e4 1449 c->processor_id = read_c0_prid();
8ff374b9 1450 switch (c->processor_id & PRID_COMP_MASK) {
1da177e4 1451 case PRID_COMP_LEGACY:
cea7e2df 1452 cpu_probe_legacy(c, cpu);
1da177e4
LT		 1453 break;
1454 case PRID_COMP_MIPS:
cea7e2df 1455 cpu_probe_mips(c, cpu);
1da177e4
LT		 1456 break;
1457 case PRID_COMP_ALCHEMY:
cea7e2df 1458 cpu_probe_alchemy(c, cpu);
1da177e4
LT		 1459 break;
1460 case PRID_COMP_SIBYTE:
cea7e2df 1461 cpu_probe_sibyte(c, cpu);
1da177e4 1462 break;
1c0c13eb 1463 case PRID_COMP_BROADCOM:
cea7e2df 1464 cpu_probe_broadcom(c, cpu);
1c0c13eb 1465 break;
1da177e4 1466 case PRID_COMP_SANDCRAFT:
cea7e2df 1467 cpu_probe_sandcraft(c, cpu);
1da177e4 1468 break;
a92b0588 1469 case PRID_COMP_NXP:
cea7e2df 1470 cpu_probe_nxp(c, cpu);
a3dddd56 1471 break;
0dd4781b
DD		 1472 case PRID_COMP_CAVIUM:
1473 cpu_probe_cavium(c, cpu);
1474 break;
252617a4
PB		 1475 case PRID_COMP_INGENIC_D0:
1476 case PRID_COMP_INGENIC_D1:
1477 case PRID_COMP_INGENIC_E1:
83ccf69d
LPC		 1478 cpu_probe_ingenic(c, cpu);
1479 break;
a7117c6b
J		 1480 case PRID_COMP_NETLOGIC:
1481 cpu_probe_netlogic(c, cpu);
1482 break;
1da177e4 1483 }
dec8b1ca 1484
cea7e2df
RB		 1485 BUG_ON(!__cpu_name[cpu]);
1486 BUG_ON(c->cputype == CPU_UNKNOWN);
1487
dec8b1ca
FBH		 1488 /*
1489 * Platform code can force the cpu type to optimize code
1490 * generation. In that case be sure the cpu type is correctly
1491 * manually setup otherwise it could trigger some nasty bugs.
1492 */
1493 BUG_ON(current_cpu_type() != c->cputype);
1494
0103d23f
KC		 1495 if (mips_fpu_disabled)
1496 c->options &= ~MIPS_CPU_FPU;
1497
1498 if (mips_dsp_disabled)
ee80f7c7 1499 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
0103d23f 1500
3d528b32
MC		 1501 if (mips_htw_disabled) {
1502 c->options &= ~MIPS_CPU_HTW;
1503 write_c0_pwctl(read_c0_pwctl() &
1504 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
1505 }
1506
7aecd5ca
MR		 1507 if (c->options & MIPS_CPU_FPU)
1508 cpu_set_fpu_opts(c);
1509 else
1510 cpu_set_nofpu_opts(c);
9966db25 1511
8d5ded16
JK		 1512 if (cpu_has_bp_ghist)
1513 write_c0_r10k_diag(read_c0_r10k_diag() |
1514 R10K_DIAG_E_GHIST);
1515
8b8aa636 1516 if (cpu_has_mips_r2_r6) {
f6771dbb 1517 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
da4b62cd
AC		 1518 /* R2 has Performance Counter Interrupt indicator */
1519 c->options |= MIPS_CPU_PCI;
1520 }
f6771dbb
RB		 1521 else
1522 c->srsets = 1;
91dfc423 1523
a8ad1367 1524 if (cpu_has_msa) {
a5e9a69e 1525 c->msa_id = cpu_get_msa_id();
a8ad1367
PB		 1526 WARN(c->msa_id & MSA_IR_WRPF,
1527 "Vector register partitioning unimplemented!");
1528 }
a5e9a69e 1529
91dfc423 1530 cpu_probe_vmbits(c);
949e51be
DD		 1531
1532#ifdef CONFIG_64BIT
1533 if (cpu == 0)
1534 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1535#endif
1da177e4
LT		 1536}
1537
078a55fc 1538void cpu_report(void)
1da177e4
LT		 1539{
1540 struct cpuinfo_mips *c = &current_cpu_data;
1541
d9f897c9
LY		 1542 pr_info("CPU%d revision is: %08x (%s)\n",
1543 smp_processor_id(), c->processor_id, cpu_name_string());
1da177e4 1544 if (c->options & MIPS_CPU_FPU)
9966db25 1545 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
a5e9a69e
PB		 1546 if (cpu_has_msa)
1547 pr_info("MSA revision is: %08x\n", c->msa_id);
1da177e4 1548}
Linux 6.x block layer and io_uring tree(s)