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MIPS: Add arch CDMM definitions and probing
[linux-2.6-block.git] / arch / mips / kernel / cpu-probe.c
CommitLineData
1da177e4
LT		 1/*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
010b853b 5 * Copyright (C) 1994 - 2006 Ralf Baechle
4194318c 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
70342287 7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
1da177e4
LT		 8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
1da177e4
LT		 14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/ptrace.h>
631330f5 17#include <linux/smp.h>
1da177e4 18#include <linux/stddef.h>
73bc256d 19#include <linux/export.h>
1da177e4 20
5759906c 21#include <asm/bugs.h>
1da177e4 22#include <asm/cpu.h>
69f24d17 23#include <asm/cpu-type.h>
1da177e4
LT		 24#include <asm/fpu.h>
25#include <asm/mipsregs.h>
30ee615b 26#include <asm/mipsmtregs.h>
a5e9a69e 27#include <asm/msa.h>
654f57bf 28#include <asm/watch.h>
06372a63 29#include <asm/elf.h>
4f12b91d 30#include <asm/pgtable-bits.h>
a074f0e8 31#include <asm/spram.h>
949e51be
DD		 32#include <asm/uaccess.h>
33
078a55fc 34static int mips_fpu_disabled;
0103d23f
KC		 35
36static int __init fpu_disable(char *s)
37{
38 cpu_data[0].options &= ~MIPS_CPU_FPU;
39 mips_fpu_disabled = 1;
40
41 return 1;
42}
43
44__setup("nofpu", fpu_disable);
45
078a55fc 46int mips_dsp_disabled;
0103d23f
KC		 47
48static int __init dsp_disable(char *s)
49{
ee80f7c7 50 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
0103d23f
KC		 51 mips_dsp_disabled = 1;
52
53 return 1;
54}
55
56__setup("nodsp", dsp_disable);
57
3d528b32
MC		 58static int mips_htw_disabled;
59
60static int __init htw_disable(char *s)
61{
62 mips_htw_disabled = 1;
63 cpu_data[0].options &= ~MIPS_CPU_HTW;
64 write_c0_pwctl(read_c0_pwctl() &
65 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
66
67 return 1;
68}
69
70__setup("nohtw", htw_disable);
71
97f4ad29
MC		 72static int mips_ftlb_disabled;
73static int mips_has_ftlb_configured;
74
75static void set_ftlb_enable(struct cpuinfo_mips *c, int enable);
76
77static int __init ftlb_disable(char *s)
78{
79 unsigned int config4, mmuextdef;
80
81 /*
82 * If the core hasn't done any FTLB configuration, there is nothing
83 * for us to do here.
84 */
85 if (!mips_has_ftlb_configured)
86 return 1;
87
88 /* Disable it in the boot cpu */
89 set_ftlb_enable(&cpu_data[0], 0);
90
91 back_to_back_c0_hazard();
92
93 config4 = read_c0_config4();
94
95 /* Check that FTLB has been disabled */
96 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
97 /* MMUSIZEEXT == VTLB ON, FTLB OFF */
98 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
99 /* This should never happen */
100 pr_warn("FTLB could not be disabled!\n");
101 return 1;
102 }
103
104 mips_ftlb_disabled = 1;
105 mips_has_ftlb_configured = 0;
106
107 /*
108 * noftlb is mainly used for debug purposes so print
109 * an informative message instead of using pr_debug()
110 */
111 pr_info("FTLB has been disabled\n");
112
113 /*
114 * Some of these bits are duplicated in the decode_config4.
115 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
116 * once FTLB has been disabled so undo what decode_config4 did.
117 */
118 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
119 cpu_data[0].tlbsizeftlbsets;
120 cpu_data[0].tlbsizeftlbsets = 0;
121 cpu_data[0].tlbsizeftlbways = 0;
122
123 return 1;
124}
125
126__setup("noftlb", ftlb_disable);
127
128
9267a30d
MSJ		 129static inline void check_errata(void)
130{
131 struct cpuinfo_mips *c = &current_cpu_data;
132
69f24d17 133 switch (current_cpu_type()) {
9267a30d
MSJ		 134 case CPU_34K:
135 /*
136 * Erratum "RPS May Cause Incorrect Instruction Execution"
b633648c 137 * This code only handles VPE0, any SMP/RTOS code
9267a30d
MSJ		 138 * making use of VPE1 will be responsable for that VPE.
139 */
140 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
141 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
142 break;
143 default:
144 break;
145 }
146}
147
1da177e4
LT		 148void __init check_bugs32(void)
149{
9267a30d 150 check_errata();
1da177e4
LT		 151}
152
153/*
154 * Probe whether cpu has config register by trying to play with
155 * alternate cache bit and see whether it matters.
156 * It's used by cpu_probe to distinguish between R3000A and R3081.
157 */
158static inline int cpu_has_confreg(void)
159{
160#ifdef CONFIG_CPU_R3000
161 extern unsigned long r3k_cache_size(unsigned long);
162 unsigned long size1, size2;
163 unsigned long cfg = read_c0_conf();
164
165 size1 = r3k_cache_size(ST0_ISC);
166 write_c0_conf(cfg ^ R30XX_CONF_AC);
167 size2 = r3k_cache_size(ST0_ISC);
168 write_c0_conf(cfg);
169 return size1 != size2;
170#else
171 return 0;
172#endif
173}
174
c094c99e
RM		 175static inline void set_elf_platform(int cpu, const char *plat)
176{
177 if (cpu == 0)
178 __elf_platform = plat;
179}
180
1da177e4
LT		 181/*
182 * Get the FPU Implementation/Revision.
183 */
184static inline unsigned long cpu_get_fpu_id(void)
185{
186 unsigned long tmp, fpu_id;
187
188 tmp = read_c0_status();
597ce172 189 __enable_fpu(FPU_AS_IS);
1da177e4
LT		 190 fpu_id = read_32bit_cp1_register(CP1_REVISION);
191 write_c0_status(tmp);
192 return fpu_id;
193}
194
195/*
196 * Check the CPU has an FPU the official way.
197 */
198static inline int __cpu_has_fpu(void)
199{
635c9907 200 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
1da177e4
LT		 201}
202
a5e9a69e
PB		 203static inline unsigned long cpu_get_msa_id(void)
204{
3587ea88 205 unsigned long status, msa_id;
a5e9a69e
PB		 206
207 status = read_c0_status();
208 __enable_fpu(FPU_64BIT);
a5e9a69e
PB		 209 enable_msa();
210 msa_id = read_msa_ir();
3587ea88 211 disable_msa();
a5e9a69e
PB		 212 write_c0_status(status);
213 return msa_id;
214}
215
91dfc423
GR		 216static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
217{
218#ifdef __NEED_VMBITS_PROBE
5b7efa89 219 write_c0_entryhi(0x3fffffffffffe000ULL);
91dfc423 220 back_to_back_c0_hazard();
5b7efa89 221 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
91dfc423
GR		 222#endif
223}
224
078a55fc 225static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
a96102be
SH		 226{
227 switch (isa) {
228 case MIPS_CPU_ISA_M64R2:
229 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
230 case MIPS_CPU_ISA_M64R1:
231 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
232 case MIPS_CPU_ISA_V:
233 c->isa_level |= MIPS_CPU_ISA_V;
234 case MIPS_CPU_ISA_IV:
235 c->isa_level |= MIPS_CPU_ISA_IV;
236 case MIPS_CPU_ISA_III:
1990e542 237 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
a96102be
SH		 238 break;
239
8b8aa636
LY		 240 /* R6 incompatible with everything else */
241 case MIPS_CPU_ISA_M64R6:
242 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
243 case MIPS_CPU_ISA_M32R6:
244 c->isa_level |= MIPS_CPU_ISA_M32R6;
245 /* Break here so we don't add incompatible ISAs */
246 break;
a96102be
SH		 247 case MIPS_CPU_ISA_M32R2:
248 c->isa_level |= MIPS_CPU_ISA_M32R2;
249 case MIPS_CPU_ISA_M32R1:
250 c->isa_level |= MIPS_CPU_ISA_M32R1;
251 case MIPS_CPU_ISA_II:
252 c->isa_level |= MIPS_CPU_ISA_II;
a96102be
SH		 253 break;
254 }
255}
256
078a55fc 257static char unknown_isa[] = KERN_ERR \
2fa36399
KC		 258 "Unsupported ISA type, c0.config0: %d.";
259
cf0a8aa0
MC		 260static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
261{
262
263 unsigned int probability = c->tlbsize / c->tlbsizevtlb;
264
265 /*
266 * 0 = All TLBWR instructions go to FTLB
267 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
268 * FTLB and 1 goes to the VTLB.
269 * 2 = 7:1: As above with 7:1 ratio.
270 * 3 = 3:1: As above with 3:1 ratio.
271 *
272 * Use the linear midpoint as the probability threshold.
273 */
274 if (probability >= 12)
275 return 1;
276 else if (probability >= 6)
277 return 2;
278 else
279 /*
280 * So FTLB is less than 4 times bigger than VTLB.
281 * A 3:1 ratio can still be useful though.
282 */
283 return 3;
284}
285
75b5b5e0
LY		 286static void set_ftlb_enable(struct cpuinfo_mips *c, int enable)
287{
288 unsigned int config6;
d83b0e82
JH		 289
290 /* It's implementation dependent how the FTLB can be enabled */
291 switch (c->cputype) {
292 case CPU_PROAPTIV:
293 case CPU_P5600:
294 /* proAptiv & related cores use Config6 to enable the FTLB */
75b5b5e0 295 config6 = read_c0_config6();
cf0a8aa0
MC		 296 /* Clear the old probability value */
297 config6 &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
75b5b5e0
LY		 298 if (enable)
299 /* Enable FTLB */
cf0a8aa0
MC		 300 write_c0_config6(config6 |
301 (calculate_ftlb_probability(c)
302 << MIPS_CONF6_FTLBP_SHIFT)
303 | MIPS_CONF6_FTLBEN);
75b5b5e0
LY		 304 else
305 /* Disable FTLB */
306 write_c0_config6(config6 & ~MIPS_CONF6_FTLBEN);
307 back_to_back_c0_hazard();
d83b0e82 308 break;
75b5b5e0
LY		 309 }
310}
311
2fa36399
KC		 312static inline unsigned int decode_config0(struct cpuinfo_mips *c)
313{
314 unsigned int config0;
315 int isa;
316
317 config0 = read_c0_config();
318
75b5b5e0
LY		 319 /*
320 * Look for Standard TLB or Dual VTLB and FTLB
321 */
322 if ((((config0 & MIPS_CONF_MT) >> 7) == 1) ||
323 (((config0 & MIPS_CONF_MT) >> 7) == 4))
2fa36399 324 c->options |= MIPS_CPU_TLB;
75b5b5e0 325
2fa36399
KC		 326 isa = (config0 & MIPS_CONF_AT) >> 13;
327 switch (isa) {
328 case 0:
329 switch ((config0 & MIPS_CONF_AR) >> 10) {
330 case 0:
a96102be 331 set_isa(c, MIPS_CPU_ISA_M32R1);
2fa36399
KC		 332 break;
333 case 1:
a96102be 334 set_isa(c, MIPS_CPU_ISA_M32R2);
2fa36399 335 break;
8b8aa636
LY		 336 case 2:
337 set_isa(c, MIPS_CPU_ISA_M32R6);
338 break;
2fa36399
KC		 339 default:
340 goto unknown;
341 }
342 break;
343 case 2:
344 switch ((config0 & MIPS_CONF_AR) >> 10) {
345 case 0:
a96102be 346 set_isa(c, MIPS_CPU_ISA_M64R1);
2fa36399
KC		 347 break;
348 case 1:
a96102be 349 set_isa(c, MIPS_CPU_ISA_M64R2);
2fa36399 350 break;
8b8aa636
LY		 351 case 2:
352 set_isa(c, MIPS_CPU_ISA_M64R6);
353 break;
2fa36399
KC		 354 default:
355 goto unknown;
356 }
357 break;
358 default:
359 goto unknown;
360 }
361
362 return config0 & MIPS_CONF_M;
363
364unknown:
365 panic(unknown_isa, config0);
366}
367
368static inline unsigned int decode_config1(struct cpuinfo_mips *c)
369{
370 unsigned int config1;
371
372 config1 = read_c0_config1();
373
374 if (config1 & MIPS_CONF1_MD)
375 c->ases |= MIPS_ASE_MDMX;
376 if (config1 & MIPS_CONF1_WR)
377 c->options |= MIPS_CPU_WATCH;
378 if (config1 & MIPS_CONF1_CA)
379 c->ases |= MIPS_ASE_MIPS16;
380 if (config1 & MIPS_CONF1_EP)
381 c->options |= MIPS_CPU_EJTAG;
382 if (config1 & MIPS_CONF1_FP) {
383 c->options |= MIPS_CPU_FPU;
384 c->options |= MIPS_CPU_32FPR;
385 }
75b5b5e0 386 if (cpu_has_tlb) {
2fa36399 387 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
75b5b5e0
LY		 388 c->tlbsizevtlb = c->tlbsize;
389 c->tlbsizeftlbsets = 0;
390 }
2fa36399
KC		 391
392 return config1 & MIPS_CONF_M;
393}
394
395static inline unsigned int decode_config2(struct cpuinfo_mips *c)
396{
397 unsigned int config2;
398
399 config2 = read_c0_config2();
400
401 if (config2 & MIPS_CONF2_SL)
402 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
403
404 return config2 & MIPS_CONF_M;
405}
406
407static inline unsigned int decode_config3(struct cpuinfo_mips *c)
408{
409 unsigned int config3;
410
411 config3 = read_c0_config3();
412
b2ab4f08 413 if (config3 & MIPS_CONF3_SM) {
2fa36399 414 c->ases |= MIPS_ASE_SMARTMIPS;
b2ab4f08
SH		 415 c->options |= MIPS_CPU_RIXI;
416 }
417 if (config3 & MIPS_CONF3_RXI)
418 c->options |= MIPS_CPU_RIXI;
2fa36399
KC		 419 if (config3 & MIPS_CONF3_DSP)
420 c->ases |= MIPS_ASE_DSP;
ee80f7c7
SH		 421 if (config3 & MIPS_CONF3_DSP2P)
422 c->ases |= MIPS_ASE_DSP2P;
2fa36399
KC		 423 if (config3 & MIPS_CONF3_VINT)
424 c->options |= MIPS_CPU_VINT;
425 if (config3 & MIPS_CONF3_VEIC)
426 c->options |= MIPS_CPU_VEIC;
427 if (config3 & MIPS_CONF3_MT)
428 c->ases |= MIPS_ASE_MIPSMT;
429 if (config3 & MIPS_CONF3_ULRI)
430 c->options |= MIPS_CPU_ULRI;
f8fa4811
SH		 431 if (config3 & MIPS_CONF3_ISA)
432 c->options |= MIPS_CPU_MICROMIPS;
1e7decdb
DD		 433 if (config3 & MIPS_CONF3_VZ)
434 c->ases |= MIPS_ASE_VZ;
4a0156fb
SH		 435 if (config3 & MIPS_CONF3_SC)
436 c->options |= MIPS_CPU_SEGMENTS;
a5e9a69e
PB		 437 if (config3 & MIPS_CONF3_MSA)
438 c->ases |= MIPS_ASE_MSA;
3d528b32 439 /* Only tested on 32-bit cores */
ed4cbc81
MC		 440 if ((config3 & MIPS_CONF3_PW) && config_enabled(CONFIG_32BIT)) {
441 c->htw_seq = 0;
3d528b32 442 c->options |= MIPS_CPU_HTW;
ed4cbc81 443 }
9b3274bd
JH		 444 if (config3 & MIPS_CONF3_CDMM)
445 c->options |= MIPS_CPU_CDMM;
2fa36399
KC		 446
447 return config3 & MIPS_CONF_M;
448}
449
450static inline unsigned int decode_config4(struct cpuinfo_mips *c)
451{
452 unsigned int config4;
75b5b5e0
LY		 453 unsigned int newcf4;
454 unsigned int mmuextdef;
455 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
2fa36399
KC		 456
457 config4 = read_c0_config4();
458
1745c1ef
LY		 459 if (cpu_has_tlb) {
460 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
461 c->options |= MIPS_CPU_TLBINV;
75b5b5e0
LY		 462 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
463 switch (mmuextdef) {
464 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
465 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
466 c->tlbsizevtlb = c->tlbsize;
467 break;
468 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
469 c->tlbsizevtlb +=
470 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
471 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
472 c->tlbsize = c->tlbsizevtlb;
473 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
474 /* fall through */
475 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
97f4ad29
MC		 476 if (mips_ftlb_disabled)
477 break;
75b5b5e0
LY		 478 newcf4 = (config4 & ~ftlb_page) |
479 (page_size_ftlb(mmuextdef) <<
480 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
481 write_c0_config4(newcf4);
482 back_to_back_c0_hazard();
483 config4 = read_c0_config4();
484 if (config4 != newcf4) {
485 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
486 PAGE_SIZE, config4);
487 /* Switch FTLB off */
488 set_ftlb_enable(c, 0);
489 break;
490 }
491 c->tlbsizeftlbsets = 1 <<
492 ((config4 & MIPS_CONF4_FTLBSETS) >>
493 MIPS_CONF4_FTLBSETS_SHIFT);
494 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
495 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
496 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
97f4ad29 497 mips_has_ftlb_configured = 1;
75b5b5e0
LY		 498 break;
499 }
1745c1ef
LY		 500 }
501
2fa36399
KC		 502 c->kscratch_mask = (config4 >> 16) & 0xff;
503
504 return config4 & MIPS_CONF_M;
505}
506
8b8a7634
RB		 507static inline unsigned int decode_config5(struct cpuinfo_mips *c)
508{
509 unsigned int config5;
510
511 config5 = read_c0_config5();
d175ed2b 512 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
8b8a7634
RB		 513 write_c0_config5(config5);
514
49016748
MC		 515 if (config5 & MIPS_CONF5_EVA)
516 c->options |= MIPS_CPU_EVA;
1f6c52ff
PB		 517 if (config5 & MIPS_CONF5_MRP)
518 c->options |= MIPS_CPU_MAAR;
5aed9da1
MC		 519 if (config5 & MIPS_CONF5_LLB)
520 c->options |= MIPS_CPU_RW_LLB;
49016748 521
8b8a7634
RB		 522 return config5 & MIPS_CONF_M;
523}
524
078a55fc 525static void decode_configs(struct cpuinfo_mips *c)
2fa36399
KC		 526{
527 int ok;
528
529 /* MIPS32 or MIPS64 compliant CPU. */
530 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
531 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
532
533 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
534
97f4ad29
MC		 535 /* Enable FTLB if present and not disabled */
536 set_ftlb_enable(c, !mips_ftlb_disabled);
75b5b5e0 537
2fa36399 538 ok = decode_config0(c); /* Read Config registers. */
70342287 539 BUG_ON(!ok); /* Arch spec violation! */
2fa36399
KC		 540 if (ok)
541 ok = decode_config1(c);
542 if (ok)
543 ok = decode_config2(c);
544 if (ok)
545 ok = decode_config3(c);
546 if (ok)
547 ok = decode_config4(c);
8b8a7634
RB		 548 if (ok)
549 ok = decode_config5(c);
2fa36399
KC		 550
551 mips_probe_watch_registers(c);
552
6575b1d4
LY		 553 if (cpu_has_rixi) {
554 /* Enable the RIXI exceptions */
a5770df0 555 set_c0_pagegrain(PG_IEC);
6575b1d4
LY		 556 back_to_back_c0_hazard();
557 /* Verify the IEC bit is set */
558 if (read_c0_pagegrain() & PG_IEC)
559 c->options |= MIPS_CPU_RIXIEX;
560 }
561
0ee958e1 562#ifndef CONFIG_MIPS_CPS
8b8aa636 563 if (cpu_has_mips_r2_r6) {
45b585c8 564 c->core = get_ebase_cpunum();
30ee615b
PB		 565 if (cpu_has_mipsmt)
566 c->core >>= fls(core_nvpes()) - 1;
567 }
0ee958e1 568#endif
2fa36399
KC		 569}
570
02cf2119 571#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1da177e4
LT		 572 | MIPS_CPU_COUNTER)
573
cea7e2df 574static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 575{
8ff374b9 576 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 577 case PRID_IMP_R2000:
578 c->cputype = CPU_R2000;
cea7e2df 579 __cpu_name[cpu] = "R2000";
02cf2119 580 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 581 MIPS_CPU_NOFPUEX;
1da177e4
LT		 582 if (__cpu_has_fpu())
583 c->options |= MIPS_CPU_FPU;
584 c->tlbsize = 64;
585 break;
586 case PRID_IMP_R3000:
8ff374b9 587 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
cea7e2df 588 if (cpu_has_confreg()) {
1da177e4 589 c->cputype = CPU_R3081E;
cea7e2df
RB		 590 __cpu_name[cpu] = "R3081";
591 } else {
1da177e4 592 c->cputype = CPU_R3000A;
cea7e2df
RB		 593 __cpu_name[cpu] = "R3000A";
594 }
cea7e2df 595 } else {
1da177e4 596 c->cputype = CPU_R3000;
cea7e2df
RB		 597 __cpu_name[cpu] = "R3000";
598 }
02cf2119 599 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
03751e79 600 MIPS_CPU_NOFPUEX;
1da177e4
LT		 601 if (__cpu_has_fpu())
602 c->options |= MIPS_CPU_FPU;
603 c->tlbsize = 64;
604 break;
605 case PRID_IMP_R4000:
606 if (read_c0_config() & CONF_SC) {
8ff374b9
MR		 607 if ((c->processor_id & PRID_REV_MASK) >=
608 PRID_REV_R4400) {
1da177e4 609 c->cputype = CPU_R4400PC;
cea7e2df
RB		 610 __cpu_name[cpu] = "R4400PC";
611 } else {
1da177e4 612 c->cputype = CPU_R4000PC;
cea7e2df
RB		 613 __cpu_name[cpu] = "R4000PC";
614 }
1da177e4 615 } else {
7f177a52
MR		 616 int cca = read_c0_config() & CONF_CM_CMASK;
617 int mc;
618
619 /*
620 * SC and MC versions can't be reliably told apart,
621 * but only the latter support coherent caching
622 * modes so assume the firmware has set the KSEG0
623 * coherency attribute reasonably (if uncached, we
624 * assume SC).
625 */
626 switch (cca) {
627 case CONF_CM_CACHABLE_CE:
628 case CONF_CM_CACHABLE_COW:
629 case CONF_CM_CACHABLE_CUW:
630 mc = 1;
631 break;
632 default:
633 mc = 0;
634 break;
635 }
8ff374b9
MR		 636 if ((c->processor_id & PRID_REV_MASK) >=
637 PRID_REV_R4400) {
7f177a52
MR		 638 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
639 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
cea7e2df 640 } else {
7f177a52
MR		 641 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
642 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
cea7e2df 643 }
1da177e4
LT		 644 }
645
a96102be 646 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 647 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79
SH		 648 MIPS_CPU_WATCH | MIPS_CPU_VCE |
649 MIPS_CPU_LLSC;
1da177e4
LT		 650 c->tlbsize = 48;
651 break;
652 case PRID_IMP_VR41XX:
9f91e506
YY		 653 set_isa(c, MIPS_CPU_ISA_III);
654 c->options = R4K_OPTS;
655 c->tlbsize = 32;
1da177e4 656 switch (c->processor_id & 0xf0) {
1da177e4
LT		 657 case PRID_REV_VR4111:
658 c->cputype = CPU_VR4111;
cea7e2df 659 __cpu_name[cpu] = "NEC VR4111";
1da177e4 660 break;
1da177e4
LT		 661 case PRID_REV_VR4121:
662 c->cputype = CPU_VR4121;
cea7e2df 663 __cpu_name[cpu] = "NEC VR4121";
1da177e4
LT		 664 break;
665 case PRID_REV_VR4122:
cea7e2df 666 if ((c->processor_id & 0xf) < 0x3) {
1da177e4 667 c->cputype = CPU_VR4122;
cea7e2df
RB		 668 __cpu_name[cpu] = "NEC VR4122";
669 } else {
1da177e4 670 c->cputype = CPU_VR4181A;
cea7e2df
RB		 671 __cpu_name[cpu] = "NEC VR4181A";
672 }
1da177e4
LT		 673 break;
674 case PRID_REV_VR4130:
cea7e2df 675 if ((c->processor_id & 0xf) < 0x4) {
1da177e4 676 c->cputype = CPU_VR4131;
cea7e2df
RB		 677 __cpu_name[cpu] = "NEC VR4131";
678 } else {
1da177e4 679 c->cputype = CPU_VR4133;
9f91e506 680 c->options |= MIPS_CPU_LLSC;
cea7e2df
RB		 681 __cpu_name[cpu] = "NEC VR4133";
682 }
1da177e4
LT		 683 break;
684 default:
685 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
686 c->cputype = CPU_VR41XX;
cea7e2df 687 __cpu_name[cpu] = "NEC Vr41xx";
1da177e4
LT		 688 break;
689 }
1da177e4
LT		 690 break;
691 case PRID_IMP_R4300:
692 c->cputype = CPU_R4300;
cea7e2df 693 __cpu_name[cpu] = "R4300";
a96102be 694 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 695 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 696 MIPS_CPU_LLSC;
1da177e4
LT		 697 c->tlbsize = 32;
698 break;
699 case PRID_IMP_R4600:
700 c->cputype = CPU_R4600;
cea7e2df 701 __cpu_name[cpu] = "R4600";
a96102be 702 set_isa(c, MIPS_CPU_ISA_III);
075e7502
TS		 703 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
704 MIPS_CPU_LLSC;
1da177e4
LT		 705 c->tlbsize = 48;
706 break;
707 #if 0
03751e79 708 case PRID_IMP_R4650:
1da177e4
LT		 709 /*
710 * This processor doesn't have an MMU, so it's not
711 * "real easy" to run Linux on it. It is left purely
712 * for documentation. Commented out because it shares
713 * it's c0_prid id number with the TX3900.
714 */
a3dddd56 715 c->cputype = CPU_R4650;
cea7e2df 716 __cpu_name[cpu] = "R4650";
a96102be 717 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 718 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
03751e79 719 c->tlbsize = 48;
1da177e4
LT		 720 break;
721 #endif
722 case PRID_IMP_TX39:
02cf2119 723 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1da177e4
LT		 724
725 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
726 c->cputype = CPU_TX3927;
cea7e2df 727 __cpu_name[cpu] = "TX3927";
1da177e4
LT		 728 c->tlbsize = 64;
729 } else {
8ff374b9 730 switch (c->processor_id & PRID_REV_MASK) {
1da177e4
LT		 731 case PRID_REV_TX3912:
732 c->cputype = CPU_TX3912;
cea7e2df 733 __cpu_name[cpu] = "TX3912";
1da177e4
LT		 734 c->tlbsize = 32;
735 break;
736 case PRID_REV_TX3922:
737 c->cputype = CPU_TX3922;
cea7e2df 738 __cpu_name[cpu] = "TX3922";
1da177e4
LT		 739 c->tlbsize = 64;
740 break;
1da177e4
LT		 741 }
742 }
743 break;
744 case PRID_IMP_R4700:
745 c->cputype = CPU_R4700;
cea7e2df 746 __cpu_name[cpu] = "R4700";
a96102be 747 set_isa(c, MIPS_CPU_ISA_III);
1da177e4 748 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 749 MIPS_CPU_LLSC;
1da177e4
LT		 750 c->tlbsize = 48;
751 break;
752 case PRID_IMP_TX49:
753 c->cputype = CPU_TX49XX;
cea7e2df 754 __cpu_name[cpu] = "R49XX";
a96102be 755 set_isa(c, MIPS_CPU_ISA_III);
1da177e4
LT		 756 c->options = R4K_OPTS | MIPS_CPU_LLSC;
757 if (!(c->processor_id & 0x08))
758 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
759 c->tlbsize = 48;
760 break;
761 case PRID_IMP_R5000:
762 c->cputype = CPU_R5000;
cea7e2df 763 __cpu_name[cpu] = "R5000";
a96102be 764 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 765 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 766 MIPS_CPU_LLSC;
1da177e4
LT		 767 c->tlbsize = 48;
768 break;
769 case PRID_IMP_R5432:
770 c->cputype = CPU_R5432;
cea7e2df 771 __cpu_name[cpu] = "R5432";
a96102be 772 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 773 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 774 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 775 c->tlbsize = 48;
776 break;
777 case PRID_IMP_R5500:
778 c->cputype = CPU_R5500;
cea7e2df 779 __cpu_name[cpu] = "R5500";
a96102be 780 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 781 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 782 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1da177e4
LT		 783 c->tlbsize = 48;
784 break;
785 case PRID_IMP_NEVADA:
786 c->cputype = CPU_NEVADA;
cea7e2df 787 __cpu_name[cpu] = "Nevada";
a96102be 788 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 789 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 790 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
1da177e4
LT		 791 c->tlbsize = 48;
792 break;
793 case PRID_IMP_R6000:
794 c->cputype = CPU_R6000;
cea7e2df 795 __cpu_name[cpu] = "R6000";
a96102be 796 set_isa(c, MIPS_CPU_ISA_II);
1da177e4 797 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 798 MIPS_CPU_LLSC;
1da177e4
LT		 799 c->tlbsize = 32;
800 break;
801 case PRID_IMP_R6000A:
802 c->cputype = CPU_R6000A;
cea7e2df 803 __cpu_name[cpu] = "R6000A";
a96102be 804 set_isa(c, MIPS_CPU_ISA_II);
1da177e4 805 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
03751e79 806 MIPS_CPU_LLSC;
1da177e4
LT		 807 c->tlbsize = 32;
808 break;
809 case PRID_IMP_RM7000:
810 c->cputype = CPU_RM7000;
cea7e2df 811 __cpu_name[cpu] = "RM7000";
a96102be 812 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 813 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
03751e79 814 MIPS_CPU_LLSC;
1da177e4 815 /*
70342287 816 * Undocumented RM7000: Bit 29 in the info register of
1da177e4
LT		 817 * the RM7000 v2.0 indicates if the TLB has 48 or 64
818 * entries.
819 *
70342287
RB		 820 * 29 1 => 64 entry JTLB
821 * 0 => 48 entry JTLB
1da177e4
LT		 822 */
823 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
1da177e4
LT		 824 break;
825 case PRID_IMP_R8000:
826 c->cputype = CPU_R8000;
cea7e2df 827 __cpu_name[cpu] = "RM8000";
a96102be 828 set_isa(c, MIPS_CPU_ISA_IV);
1da177e4 829 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
03751e79
SH		 830 MIPS_CPU_FPU | MIPS_CPU_32FPR |
831 MIPS_CPU_LLSC;
1da177e4
LT		 832 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
833 break;
834 case PRID_IMP_R10000:
835 c->cputype = CPU_R10000;
cea7e2df 836 __cpu_name[cpu] = "R10000";
a96102be 837 set_isa(c, MIPS_CPU_ISA_IV);
8b36612a 838 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 839 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 840 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 841 MIPS_CPU_LLSC;
1da177e4
LT		 842 c->tlbsize = 64;
843 break;
844 case PRID_IMP_R12000:
845 c->cputype = CPU_R12000;
cea7e2df 846 __cpu_name[cpu] = "R12000";
a96102be 847 set_isa(c, MIPS_CPU_ISA_IV);
8b36612a 848 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 849 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1da177e4 850 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 851 MIPS_CPU_LLSC;
1da177e4
LT		 852 c->tlbsize = 64;
853 break;
44d921b2
K		 854 case PRID_IMP_R14000:
855 c->cputype = CPU_R14000;
cea7e2df 856 __cpu_name[cpu] = "R14000";
a96102be 857 set_isa(c, MIPS_CPU_ISA_IV);
44d921b2 858 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
03751e79 859 MIPS_CPU_FPU | MIPS_CPU_32FPR |
44d921b2 860 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
03751e79 861 MIPS_CPU_LLSC;
44d921b2
K		 862 c->tlbsize = 64;
863 break;
26859198 864 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
5aac1e8a
RM		 865 switch (c->processor_id & PRID_REV_MASK) {
866 case PRID_REV_LOONGSON2E:
c579d310
HC		 867 c->cputype = CPU_LOONGSON2;
868 __cpu_name[cpu] = "ICT Loongson-2";
5aac1e8a 869 set_elf_platform(cpu, "loongson2e");
7352c8b1 870 set_isa(c, MIPS_CPU_ISA_III);
5aac1e8a
RM		 871 break;
872 case PRID_REV_LOONGSON2F:
c579d310
HC		 873 c->cputype = CPU_LOONGSON2;
874 __cpu_name[cpu] = "ICT Loongson-2";
5aac1e8a 875 set_elf_platform(cpu, "loongson2f");
7352c8b1 876 set_isa(c, MIPS_CPU_ISA_III);
5aac1e8a 877 break;
c579d310
HC		 878 case PRID_REV_LOONGSON3A:
879 c->cputype = CPU_LOONGSON3;
880 __cpu_name[cpu] = "ICT Loongson-3";
881 set_elf_platform(cpu, "loongson3a");
7352c8b1 882 set_isa(c, MIPS_CPU_ISA_M64R1);
c579d310 883 break;
e7841be5
HC		 884 case PRID_REV_LOONGSON3B_R1:
885 case PRID_REV_LOONGSON3B_R2:
886 c->cputype = CPU_LOONGSON3;
887 __cpu_name[cpu] = "ICT Loongson-3";
888 set_elf_platform(cpu, "loongson3b");
7352c8b1 889 set_isa(c, MIPS_CPU_ISA_M64R1);
e7841be5 890 break;
5aac1e8a
RM		 891 }
892
2a21c730
FZ		 893 c->options = R4K_OPTS |
894 MIPS_CPU_FPU | MIPS_CPU_LLSC |
895 MIPS_CPU_32FPR;
896 c->tlbsize = 64;
cc94ea31 897 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
2a21c730 898 break;
26859198 899 case PRID_IMP_LOONGSON_32: /* Loongson-1 */
2fa36399 900 decode_configs(c);
b4672d37 901
2fa36399 902 c->cputype = CPU_LOONGSON1;
1da177e4 903
2fa36399
KC		 904 switch (c->processor_id & PRID_REV_MASK) {
905 case PRID_REV_LOONGSON1B:
906 __cpu_name[cpu] = "Loongson 1B";
b4672d37 907 break;
b4672d37 908 }
4194318c 909
2fa36399 910 break;
1da177e4 911 }
1da177e4
LT		 912}
913
cea7e2df 914static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 915{
4f12b91d 916 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
8ff374b9 917 switch (c->processor_id & PRID_IMP_MASK) {
b2498af5
LY		 918 case PRID_IMP_QEMU_GENERIC:
919 c->writecombine = _CACHE_UNCACHED;
920 c->cputype = CPU_QEMU_GENERIC;
921 __cpu_name[cpu] = "MIPS GENERIC QEMU";
922 break;
1da177e4
LT		 923 case PRID_IMP_4KC:
924 c->cputype = CPU_4KC;
4f12b91d 925 c->writecombine = _CACHE_UNCACHED;
cea7e2df 926 __cpu_name[cpu] = "MIPS 4Kc";
1da177e4
LT		 927 break;
928 case PRID_IMP_4KEC:
2b07bd02
RB		 929 case PRID_IMP_4KECR2:
930 c->cputype = CPU_4KEC;
4f12b91d 931 c->writecombine = _CACHE_UNCACHED;
cea7e2df 932 __cpu_name[cpu] = "MIPS 4KEc";
2b07bd02 933 break;
1da177e4 934 case PRID_IMP_4KSC:
8afcb5d8 935 case PRID_IMP_4KSD:
1da177e4 936 c->cputype = CPU_4KSC;
4f12b91d 937 c->writecombine = _CACHE_UNCACHED;
cea7e2df 938 __cpu_name[cpu] = "MIPS 4KSc";
1da177e4
LT		 939 break;
940 case PRID_IMP_5KC:
941 c->cputype = CPU_5KC;
4f12b91d 942 c->writecombine = _CACHE_UNCACHED;
cea7e2df 943 __cpu_name[cpu] = "MIPS 5Kc";
1da177e4 944 break;
78d4803f
LY		 945 case PRID_IMP_5KE:
946 c->cputype = CPU_5KE;
4f12b91d 947 c->writecombine = _CACHE_UNCACHED;
78d4803f
LY		 948 __cpu_name[cpu] = "MIPS 5KE";
949 break;
1da177e4
LT		 950 case PRID_IMP_20KC:
951 c->cputype = CPU_20KC;
4f12b91d 952 c->writecombine = _CACHE_UNCACHED;
cea7e2df 953 __cpu_name[cpu] = "MIPS 20Kc";
1da177e4
LT		 954 break;
955 case PRID_IMP_24K:
956 c->cputype = CPU_24K;
4f12b91d 957 c->writecombine = _CACHE_UNCACHED;
cea7e2df 958 __cpu_name[cpu] = "MIPS 24Kc";
1da177e4 959 break;
42f3caef
JC		 960 case PRID_IMP_24KE:
961 c->cputype = CPU_24K;
4f12b91d 962 c->writecombine = _CACHE_UNCACHED;
42f3caef
JC		 963 __cpu_name[cpu] = "MIPS 24KEc";
964 break;
1da177e4
LT		 965 case PRID_IMP_25KF:
966 c->cputype = CPU_25KF;
4f12b91d 967 c->writecombine = _CACHE_UNCACHED;
cea7e2df 968 __cpu_name[cpu] = "MIPS 25Kc";
1da177e4 969 break;
bbc7f22f
RB		 970 case PRID_IMP_34K:
971 c->cputype = CPU_34K;
4f12b91d 972 c->writecombine = _CACHE_UNCACHED;
cea7e2df 973 __cpu_name[cpu] = "MIPS 34Kc";
bbc7f22f 974 break;
c620953c
CD		 975 case PRID_IMP_74K:
976 c->cputype = CPU_74K;
4f12b91d 977 c->writecombine = _CACHE_UNCACHED;
cea7e2df 978 __cpu_name[cpu] = "MIPS 74Kc";
c620953c 979 break;
113c62d9
SH		 980 case PRID_IMP_M14KC:
981 c->cputype = CPU_M14KC;
4f12b91d 982 c->writecombine = _CACHE_UNCACHED;
113c62d9
SH		 983 __cpu_name[cpu] = "MIPS M14Kc";
984 break;
f8fa4811
SH		 985 case PRID_IMP_M14KEC:
986 c->cputype = CPU_M14KEC;
4f12b91d 987 c->writecombine = _CACHE_UNCACHED;
f8fa4811
SH		 988 __cpu_name[cpu] = "MIPS M14KEc";
989 break;
39b8d525
RB		 990 case PRID_IMP_1004K:
991 c->cputype = CPU_1004K;
4f12b91d 992 c->writecombine = _CACHE_UNCACHED;
cea7e2df 993 __cpu_name[cpu] = "MIPS 1004Kc";
39b8d525 994 break;
006a851b 995 case PRID_IMP_1074K:
442e14a2 996 c->cputype = CPU_1074K;
4f12b91d 997 c->writecombine = _CACHE_UNCACHED;
006a851b
SH		 998 __cpu_name[cpu] = "MIPS 1074Kc";
999 break;
b5f065e7
LY		 1000 case PRID_IMP_INTERAPTIV_UP:
1001 c->cputype = CPU_INTERAPTIV;
1002 __cpu_name[cpu] = "MIPS interAptiv";
1003 break;
1004 case PRID_IMP_INTERAPTIV_MP:
1005 c->cputype = CPU_INTERAPTIV;
1006 __cpu_name[cpu] = "MIPS interAptiv (multi)";
1007 break;
b0d4d300
LY		 1008 case PRID_IMP_PROAPTIV_UP:
1009 c->cputype = CPU_PROAPTIV;
1010 __cpu_name[cpu] = "MIPS proAptiv";
1011 break;
1012 case PRID_IMP_PROAPTIV_MP:
1013 c->cputype = CPU_PROAPTIV;
1014 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1015 break;
829dcc0a
JH		 1016 case PRID_IMP_P5600:
1017 c->cputype = CPU_P5600;
1018 __cpu_name[cpu] = "MIPS P5600";
1019 break;
9943ed92
LY		 1020 case PRID_IMP_M5150:
1021 c->cputype = CPU_M5150;
1022 __cpu_name[cpu] = "MIPS M5150";
1023 break;
1da177e4 1024 }
0b6d497f 1025
75b5b5e0
LY		 1026 decode_configs(c);
1027
0b6d497f 1028 spram_config();
1da177e4
LT		 1029}
1030
cea7e2df 1031static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1032{
4194318c 1033 decode_configs(c);
8ff374b9 1034 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 1035 case PRID_IMP_AU1_REV1:
1036 case PRID_IMP_AU1_REV2:
270717a8 1037 c->cputype = CPU_ALCHEMY;
1da177e4
LT		 1038 switch ((c->processor_id >> 24) & 0xff) {
1039 case 0:
cea7e2df 1040 __cpu_name[cpu] = "Au1000";
1da177e4
LT		 1041 break;
1042 case 1:
cea7e2df 1043 __cpu_name[cpu] = "Au1500";
1da177e4
LT		 1044 break;
1045 case 2:
cea7e2df 1046 __cpu_name[cpu] = "Au1100";
1da177e4
LT		 1047 break;
1048 case 3:
cea7e2df 1049 __cpu_name[cpu] = "Au1550";
1da177e4 1050 break;
e3ad1c23 1051 case 4:
cea7e2df 1052 __cpu_name[cpu] = "Au1200";
8ff374b9 1053 if ((c->processor_id & PRID_REV_MASK) == 2)
cea7e2df 1054 __cpu_name[cpu] = "Au1250";
237cfee1
ML		 1055 break;
1056 case 5:
cea7e2df 1057 __cpu_name[cpu] = "Au1210";
e3ad1c23 1058 break;
1da177e4 1059 default:
270717a8 1060 __cpu_name[cpu] = "Au1xxx";
1da177e4
LT		 1061 break;
1062 }
1da177e4
LT		 1063 break;
1064 }
1065}
1066
cea7e2df 1067static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1068{
4194318c 1069 decode_configs(c);
02cf2119 1070
4f12b91d 1071 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
8ff374b9 1072 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 1073 case PRID_IMP_SB1:
1074 c->cputype = CPU_SB1;
cea7e2df 1075 __cpu_name[cpu] = "SiByte SB1";
1da177e4 1076 /* FPU in pass1 is known to have issues. */
8ff374b9 1077 if ((c->processor_id & PRID_REV_MASK) < 0x02)
010b853b 1078 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1da177e4 1079 break;
93ce2f52
AI		 1080 case PRID_IMP_SB1A:
1081 c->cputype = CPU_SB1A;
cea7e2df 1082 __cpu_name[cpu] = "SiByte SB1A";
93ce2f52 1083 break;
1da177e4
LT		 1084 }
1085}
1086
cea7e2df 1087static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 1088{
4194318c 1089 decode_configs(c);
8ff374b9 1090 switch (c->processor_id & PRID_IMP_MASK) {
1da177e4
LT		 1091 case PRID_IMP_SR71000:
1092 c->cputype = CPU_SR71000;
cea7e2df 1093 __cpu_name[cpu] = "Sandcraft SR71000";
1da177e4
LT		 1094 c->scache.ways = 8;
1095 c->tlbsize = 64;
1096 break;
1097 }
1098}
1099
cea7e2df 1100static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
bdf21b18
PP		 1101{
1102 decode_configs(c);
8ff374b9 1103 switch (c->processor_id & PRID_IMP_MASK) {
bdf21b18
PP		 1104 case PRID_IMP_PR4450:
1105 c->cputype = CPU_PR4450;
cea7e2df 1106 __cpu_name[cpu] = "Philips PR4450";
a96102be 1107 set_isa(c, MIPS_CPU_ISA_M32R1);
bdf21b18 1108 break;
bdf21b18
PP		 1109 }
1110}
1111
cea7e2df 1112static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1c0c13eb
AJ		 1113{
1114 decode_configs(c);
8ff374b9 1115 switch (c->processor_id & PRID_IMP_MASK) {
190fca3e
KC		 1116 case PRID_IMP_BMIPS32_REV4:
1117 case PRID_IMP_BMIPS32_REV8:
602977b0
KC		 1118 c->cputype = CPU_BMIPS32;
1119 __cpu_name[cpu] = "Broadcom BMIPS32";
06785df0 1120 set_elf_platform(cpu, "bmips32");
602977b0
KC		 1121 break;
1122 case PRID_IMP_BMIPS3300:
1123 case PRID_IMP_BMIPS3300_ALT:
1124 case PRID_IMP_BMIPS3300_BUG:
1125 c->cputype = CPU_BMIPS3300;
1126 __cpu_name[cpu] = "Broadcom BMIPS3300";
06785df0 1127 set_elf_platform(cpu, "bmips3300");
602977b0
KC		 1128 break;
1129 case PRID_IMP_BMIPS43XX: {
8ff374b9 1130 int rev = c->processor_id & PRID_REV_MASK;
602977b0
KC		 1131
1132 if (rev >= PRID_REV_BMIPS4380_LO &&
1133 rev <= PRID_REV_BMIPS4380_HI) {
1134 c->cputype = CPU_BMIPS4380;
1135 __cpu_name[cpu] = "Broadcom BMIPS4380";
06785df0 1136 set_elf_platform(cpu, "bmips4380");
602977b0
KC		 1137 } else {
1138 c->cputype = CPU_BMIPS4350;
1139 __cpu_name[cpu] = "Broadcom BMIPS4350";
06785df0 1140 set_elf_platform(cpu, "bmips4350");
602977b0 1141 }
0de663ef 1142 break;
602977b0
KC		 1143 }
1144 case PRID_IMP_BMIPS5000:
68e6a783 1145 case PRID_IMP_BMIPS5200:
602977b0
KC		 1146 c->cputype = CPU_BMIPS5000;
1147 __cpu_name[cpu] = "Broadcom BMIPS5000";
06785df0 1148 set_elf_platform(cpu, "bmips5000");
602977b0 1149 c->options |= MIPS_CPU_ULRI;
0de663ef 1150 break;
1c0c13eb
AJ		 1151 }
1152}
1153
0dd4781b
DD		 1154static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1155{
1156 decode_configs(c);
8ff374b9 1157 switch (c->processor_id & PRID_IMP_MASK) {
0dd4781b
DD		 1158 case PRID_IMP_CAVIUM_CN38XX:
1159 case PRID_IMP_CAVIUM_CN31XX:
1160 case PRID_IMP_CAVIUM_CN30XX:
6f329468
DD		 1161 c->cputype = CPU_CAVIUM_OCTEON;
1162 __cpu_name[cpu] = "Cavium Octeon";
1163 goto platform;
0dd4781b
DD		 1164 case PRID_IMP_CAVIUM_CN58XX:
1165 case PRID_IMP_CAVIUM_CN56XX:
1166 case PRID_IMP_CAVIUM_CN50XX:
1167 case PRID_IMP_CAVIUM_CN52XX:
6f329468
DD		 1168 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1169 __cpu_name[cpu] = "Cavium Octeon+";
1170platform:
c094c99e 1171 set_elf_platform(cpu, "octeon");
0dd4781b 1172 break;
a1431b61 1173 case PRID_IMP_CAVIUM_CN61XX:
0e56b385 1174 case PRID_IMP_CAVIUM_CN63XX:
a1431b61
DD		 1175 case PRID_IMP_CAVIUM_CN66XX:
1176 case PRID_IMP_CAVIUM_CN68XX:
af04bb85 1177 case PRID_IMP_CAVIUM_CNF71XX:
0e56b385
DD		 1178 c->cputype = CPU_CAVIUM_OCTEON2;
1179 __cpu_name[cpu] = "Cavium Octeon II";
c094c99e 1180 set_elf_platform(cpu, "octeon2");
0e56b385 1181 break;
af04bb85
DD		 1182 case PRID_IMP_CAVIUM_CN70XX:
1183 case PRID_IMP_CAVIUM_CN78XX:
1184 c->cputype = CPU_CAVIUM_OCTEON3;
1185 __cpu_name[cpu] = "Cavium Octeon III";
1186 set_elf_platform(cpu, "octeon3");
1187 break;
0dd4781b
DD		 1188 default:
1189 printk(KERN_INFO "Unknown Octeon chip!\n");
1190 c->cputype = CPU_UNKNOWN;
1191 break;
1192 }
1193}
1194
83ccf69d
LPC		 1195static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1196{
1197 decode_configs(c);
1198 /* JZRISC does not implement the CP0 counter. */
1199 c->options &= ~MIPS_CPU_COUNTER;
06947aaa 1200 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
8ff374b9 1201 switch (c->processor_id & PRID_IMP_MASK) {
83ccf69d
LPC		 1202 case PRID_IMP_JZRISC:
1203 c->cputype = CPU_JZRISC;
4f12b91d 1204 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
83ccf69d
LPC		 1205 __cpu_name[cpu] = "Ingenic JZRISC";
1206 break;
1207 default:
1208 panic("Unknown Ingenic Processor ID!");
1209 break;
1210 }
1211}
1212
a7117c6b
J		 1213static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1214{
1215 decode_configs(c);
1216
8ff374b9 1217 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
809f36c6
ML		 1218 c->cputype = CPU_ALCHEMY;
1219 __cpu_name[cpu] = "Au1300";
1220 /* following stuff is not for Alchemy */
1221 return;
1222 }
1223
70342287
RB		 1224 c->options = (MIPS_CPU_TLB |
1225 MIPS_CPU_4KEX |
a7117c6b 1226 MIPS_CPU_COUNTER |
70342287
RB		 1227 MIPS_CPU_DIVEC |
1228 MIPS_CPU_WATCH |
1229 MIPS_CPU_EJTAG |
a7117c6b
J		 1230 MIPS_CPU_LLSC);
1231
8ff374b9 1232 switch (c->processor_id & PRID_IMP_MASK) {
4ca86a2f 1233 case PRID_IMP_NETLOGIC_XLP2XX:
8907c55e 1234 case PRID_IMP_NETLOGIC_XLP9XX:
1c983986 1235 case PRID_IMP_NETLOGIC_XLP5XX:
4ca86a2f
J		 1236 c->cputype = CPU_XLP;
1237 __cpu_name[cpu] = "Broadcom XLPII";
1238 break;
1239
2aa54b20
J		 1240 case PRID_IMP_NETLOGIC_XLP8XX:
1241 case PRID_IMP_NETLOGIC_XLP3XX:
a3d4fb2d
J		 1242 c->cputype = CPU_XLP;
1243 __cpu_name[cpu] = "Netlogic XLP";
1244 break;
1245
a7117c6b
J		 1246 case PRID_IMP_NETLOGIC_XLR732:
1247 case PRID_IMP_NETLOGIC_XLR716:
1248 case PRID_IMP_NETLOGIC_XLR532:
1249 case PRID_IMP_NETLOGIC_XLR308:
1250 case PRID_IMP_NETLOGIC_XLR532C:
1251 case PRID_IMP_NETLOGIC_XLR516C:
1252 case PRID_IMP_NETLOGIC_XLR508C:
1253 case PRID_IMP_NETLOGIC_XLR308C:
1254 c->cputype = CPU_XLR;
1255 __cpu_name[cpu] = "Netlogic XLR";
1256 break;
1257
1258 case PRID_IMP_NETLOGIC_XLS608:
1259 case PRID_IMP_NETLOGIC_XLS408:
1260 case PRID_IMP_NETLOGIC_XLS404:
1261 case PRID_IMP_NETLOGIC_XLS208:
1262 case PRID_IMP_NETLOGIC_XLS204:
1263 case PRID_IMP_NETLOGIC_XLS108:
1264 case PRID_IMP_NETLOGIC_XLS104:
1265 case PRID_IMP_NETLOGIC_XLS616B:
1266 case PRID_IMP_NETLOGIC_XLS608B:
1267 case PRID_IMP_NETLOGIC_XLS416B:
1268 case PRID_IMP_NETLOGIC_XLS412B:
1269 case PRID_IMP_NETLOGIC_XLS408B:
1270 case PRID_IMP_NETLOGIC_XLS404B:
1271 c->cputype = CPU_XLR;
1272 __cpu_name[cpu] = "Netlogic XLS";
1273 break;
1274
1275 default:
a3d4fb2d 1276 pr_info("Unknown Netlogic chip id [%02x]!\n",
a7117c6b
J		 1277 c->processor_id);
1278 c->cputype = CPU_XLR;
1279 break;
1280 }
1281
a3d4fb2d 1282 if (c->cputype == CPU_XLP) {
a96102be 1283 set_isa(c, MIPS_CPU_ISA_M64R2);
a3d4fb2d
J		 1284 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1285 /* This will be updated again after all threads are woken up */
1286 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1287 } else {
a96102be 1288 set_isa(c, MIPS_CPU_ISA_M64R1);
a3d4fb2d
J		 1289 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1290 }
7777b939 1291 c->kscratch_mask = 0xf;
a7117c6b
J		 1292}
1293
949e51be
DD		 1294#ifdef CONFIG_64BIT
1295/* For use by uaccess.h */
1296u64 __ua_limit;
1297EXPORT_SYMBOL(__ua_limit);
1298#endif
1299
9966db25 1300const char *__cpu_name[NR_CPUS];
874fd3b5 1301const char *__elf_platform;
9966db25 1302
078a55fc 1303void cpu_probe(void)
1da177e4
LT		 1304{
1305 struct cpuinfo_mips *c = &current_cpu_data;
9966db25 1306 unsigned int cpu = smp_processor_id();
1da177e4 1307
70342287 1308 c->processor_id = PRID_IMP_UNKNOWN;
1da177e4
LT		 1309 c->fpu_id = FPIR_IMP_NONE;
1310 c->cputype = CPU_UNKNOWN;
4f12b91d 1311 c->writecombine = _CACHE_UNCACHED;
1da177e4
LT		 1312
1313 c->processor_id = read_c0_prid();
8ff374b9 1314 switch (c->processor_id & PRID_COMP_MASK) {
1da177e4 1315 case PRID_COMP_LEGACY:
cea7e2df 1316 cpu_probe_legacy(c, cpu);
1da177e4
LT		 1317 break;
1318 case PRID_COMP_MIPS:
cea7e2df 1319 cpu_probe_mips(c, cpu);
1da177e4
LT		 1320 break;
1321 case PRID_COMP_ALCHEMY:
cea7e2df 1322 cpu_probe_alchemy(c, cpu);
1da177e4
LT		 1323 break;
1324 case PRID_COMP_SIBYTE:
cea7e2df 1325 cpu_probe_sibyte(c, cpu);
1da177e4 1326 break;
1c0c13eb 1327 case PRID_COMP_BROADCOM:
cea7e2df 1328 cpu_probe_broadcom(c, cpu);
1c0c13eb 1329 break;
1da177e4 1330 case PRID_COMP_SANDCRAFT:
cea7e2df 1331 cpu_probe_sandcraft(c, cpu);
1da177e4 1332 break;
a92b0588 1333 case PRID_COMP_NXP:
cea7e2df 1334 cpu_probe_nxp(c, cpu);
a3dddd56 1335 break;
0dd4781b
DD		 1336 case PRID_COMP_CAVIUM:
1337 cpu_probe_cavium(c, cpu);
1338 break;
83ccf69d
LPC		 1339 case PRID_COMP_INGENIC:
1340 cpu_probe_ingenic(c, cpu);
1341 break;
a7117c6b
J		 1342 case PRID_COMP_NETLOGIC:
1343 cpu_probe_netlogic(c, cpu);
1344 break;
1da177e4 1345 }
dec8b1ca 1346
cea7e2df
RB		 1347 BUG_ON(!__cpu_name[cpu]);
1348 BUG_ON(c->cputype == CPU_UNKNOWN);
1349
dec8b1ca
FBH		 1350 /*
1351 * Platform code can force the cpu type to optimize code
1352 * generation. In that case be sure the cpu type is correctly
1353 * manually setup otherwise it could trigger some nasty bugs.
1354 */
1355 BUG_ON(current_cpu_type() != c->cputype);
1356
0103d23f
KC		 1357 if (mips_fpu_disabled)
1358 c->options &= ~MIPS_CPU_FPU;
1359
1360 if (mips_dsp_disabled)
ee80f7c7 1361 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
0103d23f 1362
3d528b32
MC		 1363 if (mips_htw_disabled) {
1364 c->options &= ~MIPS_CPU_HTW;
1365 write_c0_pwctl(read_c0_pwctl() &
1366 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
1367 }
1368
4194318c 1369 if (c->options & MIPS_CPU_FPU) {
1da177e4 1370 c->fpu_id = cpu_get_fpu_id();
4194318c 1371
8b8aa636 1372 if (c->isa_level & cpu_has_mips_r) {
4194318c
RB		 1373 if (c->fpu_id & MIPS_FPIR_3D)
1374 c->ases |= MIPS_ASE_MIPS3D;
adac5d53
PB		 1375 if (c->fpu_id & MIPS_FPIR_FREP)
1376 c->options |= MIPS_CPU_FRE;
4194318c
RB		 1377 }
1378 }
9966db25 1379
8b8aa636 1380 if (cpu_has_mips_r2_r6) {
f6771dbb 1381 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
da4b62cd
AC		 1382 /* R2 has Performance Counter Interrupt indicator */
1383 c->options |= MIPS_CPU_PCI;
1384 }
f6771dbb
RB		 1385 else
1386 c->srsets = 1;
91dfc423 1387
a8ad1367 1388 if (cpu_has_msa) {
a5e9a69e 1389 c->msa_id = cpu_get_msa_id();
a8ad1367
PB		 1390 WARN(c->msa_id & MSA_IR_WRPF,
1391 "Vector register partitioning unimplemented!");
1392 }
a5e9a69e 1393
91dfc423 1394 cpu_probe_vmbits(c);
949e51be
DD		 1395
1396#ifdef CONFIG_64BIT
1397 if (cpu == 0)
1398 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1399#endif
1da177e4
LT		 1400}
1401
078a55fc 1402void cpu_report(void)
1da177e4
LT		 1403{
1404 struct cpuinfo_mips *c = &current_cpu_data;
1405
d9f897c9
LY		 1406 pr_info("CPU%d revision is: %08x (%s)\n",
1407 smp_processor_id(), c->processor_id, cpu_name_string());
1da177e4 1408 if (c->options & MIPS_CPU_FPU)
9966db25 1409 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
a5e9a69e
PB		 1410 if (cpu_has_msa)
1411 pr_info("MSA revision is: %08x\n", c->msa_id);
1da177e4 1412}
Linux 6.x block layer and io_uring tree(s)