Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Processor capabilities determination functions. | |
3 | * | |
4 | * Copyright (C) xxxx the Anonymous | |
010b853b | 5 | * Copyright (C) 1994 - 2006 Ralf Baechle |
4194318c | 6 | * Copyright (C) 2003, 2004 Maciej W. Rozycki |
4194318c | 7 | * Copyright (C) 2001, 2004 MIPS Inc. |
1da177e4 LT |
8 | * |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * as published by the Free Software Foundation; either version | |
12 | * 2 of the License, or (at your option) any later version. | |
13 | */ | |
1da177e4 LT |
14 | #include <linux/init.h> |
15 | #include <linux/kernel.h> | |
16 | #include <linux/ptrace.h> | |
17 | #include <linux/stddef.h> | |
18 | ||
1da177e4 LT |
19 | #include <asm/cpu.h> |
20 | #include <asm/fpu.h> | |
21 | #include <asm/mipsregs.h> | |
22 | #include <asm/system.h> | |
23 | ||
24 | /* | |
25 | * Not all of the MIPS CPUs have the "wait" instruction available. Moreover, | |
26 | * the implementation of the "wait" feature differs between CPU families. This | |
27 | * points to the function that implements CPU specific wait. | |
28 | * The wait instruction stops the pipeline and reduces the power consumption of | |
29 | * the CPU very much. | |
30 | */ | |
31 | void (*cpu_wait)(void) = NULL; | |
32 | ||
33 | static void r3081_wait(void) | |
34 | { | |
35 | unsigned long cfg = read_c0_conf(); | |
36 | write_c0_conf(cfg | R30XX_CONF_HALT); | |
37 | } | |
38 | ||
39 | static void r39xx_wait(void) | |
40 | { | |
60a6c377 AN |
41 | local_irq_disable(); |
42 | if (!need_resched()) | |
43 | write_c0_conf(read_c0_conf() | TX39_CONF_HALT); | |
44 | local_irq_enable(); | |
1da177e4 LT |
45 | } |
46 | ||
60a6c377 AN |
47 | /* |
48 | * There is a race when WAIT instruction executed with interrupt | |
49 | * enabled. | |
50 | * But it is implementation-dependent wheter the pipelie restarts when | |
51 | * a non-enabled interrupt is requested. | |
52 | */ | |
1da177e4 LT |
53 | static void r4k_wait(void) |
54 | { | |
60a6c377 AN |
55 | __asm__(" .set mips3 \n" |
56 | " wait \n" | |
57 | " .set mips0 \n"); | |
58 | } | |
59 | ||
60 | /* | |
61 | * This variant is preferable as it allows testing need_resched and going to | |
62 | * sleep depending on the outcome atomically. Unfortunately the "It is | |
63 | * implementation-dependent whether the pipeline restarts when a non-enabled | |
64 | * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes | |
65 | * using this version a gamble. | |
66 | */ | |
67 | static void r4k_wait_irqoff(void) | |
68 | { | |
69 | local_irq_disable(); | |
70 | if (!need_resched()) | |
71 | __asm__(" .set mips3 \n" | |
72 | " wait \n" | |
73 | " .set mips0 \n"); | |
74 | local_irq_enable(); | |
1da177e4 LT |
75 | } |
76 | ||
494900af PP |
77 | /* The Au1xxx wait is available only if using 32khz counter or |
78 | * external timer source, but specifically not CP0 Counter. */ | |
fe359bf5 | 79 | int allow_au1k_wait; |
10f650db | 80 | |
494900af | 81 | static void au1k_wait(void) |
1da177e4 | 82 | { |
1da177e4 | 83 | /* using the wait instruction makes CP0 counter unusable */ |
60a6c377 AN |
84 | __asm__(" .set mips3 \n" |
85 | " cache 0x14, 0(%0) \n" | |
86 | " cache 0x14, 32(%0) \n" | |
87 | " sync \n" | |
88 | " nop \n" | |
89 | " wait \n" | |
90 | " nop \n" | |
91 | " nop \n" | |
92 | " nop \n" | |
93 | " nop \n" | |
94 | " .set mips0 \n" | |
10f650db | 95 | : : "r" (au1k_wait)); |
1da177e4 LT |
96 | } |
97 | ||
55d04dff RB |
98 | static int __initdata nowait = 0; |
99 | ||
100 | int __init wait_disable(char *s) | |
101 | { | |
102 | nowait = 1; | |
103 | ||
104 | return 1; | |
105 | } | |
106 | ||
107 | __setup("nowait", wait_disable); | |
108 | ||
1da177e4 LT |
109 | static inline void check_wait(void) |
110 | { | |
111 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
112 | ||
113 | printk("Checking for 'wait' instruction... "); | |
55d04dff RB |
114 | if (nowait) { |
115 | printk (" disabled.\n"); | |
116 | return; | |
117 | } | |
118 | ||
1da177e4 LT |
119 | switch (c->cputype) { |
120 | case CPU_R3081: | |
121 | case CPU_R3081E: | |
122 | cpu_wait = r3081_wait; | |
123 | printk(" available.\n"); | |
124 | break; | |
125 | case CPU_TX3927: | |
126 | cpu_wait = r39xx_wait; | |
127 | printk(" available.\n"); | |
128 | break; | |
129 | case CPU_R4200: | |
130 | /* case CPU_R4300: */ | |
131 | case CPU_R4600: | |
132 | case CPU_R4640: | |
133 | case CPU_R4650: | |
134 | case CPU_R4700: | |
135 | case CPU_R5000: | |
136 | case CPU_NEVADA: | |
137 | case CPU_RM7000: | |
1da177e4 LT |
138 | case CPU_4KC: |
139 | case CPU_4KEC: | |
140 | case CPU_4KSC: | |
141 | case CPU_5KC: | |
142 | /* case CPU_20KC:*/ | |
143 | case CPU_24K: | |
144 | case CPU_25KF: | |
bbc7f22f | 145 | case CPU_34K: |
c620953c | 146 | case CPU_74K: |
bdf21b18 | 147 | case CPU_PR4450: |
1da177e4 LT |
148 | cpu_wait = r4k_wait; |
149 | printk(" available.\n"); | |
150 | break; | |
60a6c377 AN |
151 | case CPU_TX49XX: |
152 | cpu_wait = r4k_wait_irqoff; | |
153 | printk(" available.\n"); | |
154 | break; | |
1da177e4 LT |
155 | case CPU_AU1000: |
156 | case CPU_AU1100: | |
157 | case CPU_AU1500: | |
e3ad1c23 PP |
158 | case CPU_AU1550: |
159 | case CPU_AU1200: | |
fe359bf5 PP |
160 | if (allow_au1k_wait) { |
161 | cpu_wait = au1k_wait; | |
162 | printk(" available.\n"); | |
163 | } else | |
164 | printk(" unavailable.\n"); | |
1da177e4 | 165 | break; |
441ee341 RB |
166 | case CPU_RM9000: |
167 | if ((c->processor_id & 0x00ff) >= 0x40) { | |
168 | cpu_wait = r4k_wait; | |
169 | printk(" available.\n"); | |
170 | } else { | |
171 | printk(" unavailable.\n"); | |
172 | } | |
173 | break; | |
1da177e4 LT |
174 | default: |
175 | printk(" unavailable.\n"); | |
176 | break; | |
177 | } | |
178 | } | |
179 | ||
180 | void __init check_bugs32(void) | |
181 | { | |
182 | check_wait(); | |
183 | } | |
184 | ||
185 | /* | |
186 | * Probe whether cpu has config register by trying to play with | |
187 | * alternate cache bit and see whether it matters. | |
188 | * It's used by cpu_probe to distinguish between R3000A and R3081. | |
189 | */ | |
190 | static inline int cpu_has_confreg(void) | |
191 | { | |
192 | #ifdef CONFIG_CPU_R3000 | |
193 | extern unsigned long r3k_cache_size(unsigned long); | |
194 | unsigned long size1, size2; | |
195 | unsigned long cfg = read_c0_conf(); | |
196 | ||
197 | size1 = r3k_cache_size(ST0_ISC); | |
198 | write_c0_conf(cfg ^ R30XX_CONF_AC); | |
199 | size2 = r3k_cache_size(ST0_ISC); | |
200 | write_c0_conf(cfg); | |
201 | return size1 != size2; | |
202 | #else | |
203 | return 0; | |
204 | #endif | |
205 | } | |
206 | ||
207 | /* | |
208 | * Get the FPU Implementation/Revision. | |
209 | */ | |
210 | static inline unsigned long cpu_get_fpu_id(void) | |
211 | { | |
212 | unsigned long tmp, fpu_id; | |
213 | ||
214 | tmp = read_c0_status(); | |
215 | __enable_fpu(); | |
216 | fpu_id = read_32bit_cp1_register(CP1_REVISION); | |
217 | write_c0_status(tmp); | |
218 | return fpu_id; | |
219 | } | |
220 | ||
221 | /* | |
222 | * Check the CPU has an FPU the official way. | |
223 | */ | |
224 | static inline int __cpu_has_fpu(void) | |
225 | { | |
226 | return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE); | |
227 | } | |
228 | ||
02cf2119 | 229 | #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ |
1da177e4 LT |
230 | | MIPS_CPU_COUNTER) |
231 | ||
232 | static inline void cpu_probe_legacy(struct cpuinfo_mips *c) | |
233 | { | |
234 | switch (c->processor_id & 0xff00) { | |
235 | case PRID_IMP_R2000: | |
236 | c->cputype = CPU_R2000; | |
237 | c->isa_level = MIPS_CPU_ISA_I; | |
02cf2119 RB |
238 | c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | |
239 | MIPS_CPU_NOFPUEX; | |
1da177e4 LT |
240 | if (__cpu_has_fpu()) |
241 | c->options |= MIPS_CPU_FPU; | |
242 | c->tlbsize = 64; | |
243 | break; | |
244 | case PRID_IMP_R3000: | |
245 | if ((c->processor_id & 0xff) == PRID_REV_R3000A) | |
246 | if (cpu_has_confreg()) | |
247 | c->cputype = CPU_R3081E; | |
248 | else | |
249 | c->cputype = CPU_R3000A; | |
250 | else | |
251 | c->cputype = CPU_R3000; | |
252 | c->isa_level = MIPS_CPU_ISA_I; | |
02cf2119 RB |
253 | c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | |
254 | MIPS_CPU_NOFPUEX; | |
1da177e4 LT |
255 | if (__cpu_has_fpu()) |
256 | c->options |= MIPS_CPU_FPU; | |
257 | c->tlbsize = 64; | |
258 | break; | |
259 | case PRID_IMP_R4000: | |
260 | if (read_c0_config() & CONF_SC) { | |
261 | if ((c->processor_id & 0xff) >= PRID_REV_R4400) | |
262 | c->cputype = CPU_R4400PC; | |
263 | else | |
264 | c->cputype = CPU_R4000PC; | |
265 | } else { | |
266 | if ((c->processor_id & 0xff) >= PRID_REV_R4400) | |
267 | c->cputype = CPU_R4400SC; | |
268 | else | |
269 | c->cputype = CPU_R4000SC; | |
270 | } | |
271 | ||
272 | c->isa_level = MIPS_CPU_ISA_III; | |
273 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
274 | MIPS_CPU_WATCH | MIPS_CPU_VCE | | |
275 | MIPS_CPU_LLSC; | |
276 | c->tlbsize = 48; | |
277 | break; | |
278 | case PRID_IMP_VR41XX: | |
279 | switch (c->processor_id & 0xf0) { | |
1da177e4 LT |
280 | case PRID_REV_VR4111: |
281 | c->cputype = CPU_VR4111; | |
282 | break; | |
1da177e4 LT |
283 | case PRID_REV_VR4121: |
284 | c->cputype = CPU_VR4121; | |
285 | break; | |
286 | case PRID_REV_VR4122: | |
287 | if ((c->processor_id & 0xf) < 0x3) | |
288 | c->cputype = CPU_VR4122; | |
289 | else | |
290 | c->cputype = CPU_VR4181A; | |
291 | break; | |
292 | case PRID_REV_VR4130: | |
293 | if ((c->processor_id & 0xf) < 0x4) | |
294 | c->cputype = CPU_VR4131; | |
295 | else | |
296 | c->cputype = CPU_VR4133; | |
297 | break; | |
298 | default: | |
299 | printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); | |
300 | c->cputype = CPU_VR41XX; | |
301 | break; | |
302 | } | |
303 | c->isa_level = MIPS_CPU_ISA_III; | |
304 | c->options = R4K_OPTS; | |
305 | c->tlbsize = 32; | |
306 | break; | |
307 | case PRID_IMP_R4300: | |
308 | c->cputype = CPU_R4300; | |
309 | c->isa_level = MIPS_CPU_ISA_III; | |
310 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
311 | MIPS_CPU_LLSC; | |
312 | c->tlbsize = 32; | |
313 | break; | |
314 | case PRID_IMP_R4600: | |
315 | c->cputype = CPU_R4600; | |
316 | c->isa_level = MIPS_CPU_ISA_III; | |
075e7502 TS |
317 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
318 | MIPS_CPU_LLSC; | |
1da177e4 LT |
319 | c->tlbsize = 48; |
320 | break; | |
321 | #if 0 | |
322 | case PRID_IMP_R4650: | |
323 | /* | |
324 | * This processor doesn't have an MMU, so it's not | |
325 | * "real easy" to run Linux on it. It is left purely | |
326 | * for documentation. Commented out because it shares | |
327 | * it's c0_prid id number with the TX3900. | |
328 | */ | |
a3dddd56 | 329 | c->cputype = CPU_R4650; |
1da177e4 LT |
330 | c->isa_level = MIPS_CPU_ISA_III; |
331 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; | |
332 | c->tlbsize = 48; | |
333 | break; | |
334 | #endif | |
335 | case PRID_IMP_TX39: | |
336 | c->isa_level = MIPS_CPU_ISA_I; | |
02cf2119 | 337 | c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; |
1da177e4 LT |
338 | |
339 | if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { | |
340 | c->cputype = CPU_TX3927; | |
341 | c->tlbsize = 64; | |
342 | } else { | |
343 | switch (c->processor_id & 0xff) { | |
344 | case PRID_REV_TX3912: | |
345 | c->cputype = CPU_TX3912; | |
346 | c->tlbsize = 32; | |
347 | break; | |
348 | case PRID_REV_TX3922: | |
349 | c->cputype = CPU_TX3922; | |
350 | c->tlbsize = 64; | |
351 | break; | |
352 | default: | |
353 | c->cputype = CPU_UNKNOWN; | |
354 | break; | |
355 | } | |
356 | } | |
357 | break; | |
358 | case PRID_IMP_R4700: | |
359 | c->cputype = CPU_R4700; | |
360 | c->isa_level = MIPS_CPU_ISA_III; | |
361 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
362 | MIPS_CPU_LLSC; | |
363 | c->tlbsize = 48; | |
364 | break; | |
365 | case PRID_IMP_TX49: | |
366 | c->cputype = CPU_TX49XX; | |
367 | c->isa_level = MIPS_CPU_ISA_III; | |
368 | c->options = R4K_OPTS | MIPS_CPU_LLSC; | |
369 | if (!(c->processor_id & 0x08)) | |
370 | c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; | |
371 | c->tlbsize = 48; | |
372 | break; | |
373 | case PRID_IMP_R5000: | |
374 | c->cputype = CPU_R5000; | |
375 | c->isa_level = MIPS_CPU_ISA_IV; | |
376 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
377 | MIPS_CPU_LLSC; | |
378 | c->tlbsize = 48; | |
379 | break; | |
380 | case PRID_IMP_R5432: | |
381 | c->cputype = CPU_R5432; | |
382 | c->isa_level = MIPS_CPU_ISA_IV; | |
383 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
384 | MIPS_CPU_WATCH | MIPS_CPU_LLSC; | |
385 | c->tlbsize = 48; | |
386 | break; | |
387 | case PRID_IMP_R5500: | |
388 | c->cputype = CPU_R5500; | |
389 | c->isa_level = MIPS_CPU_ISA_IV; | |
390 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
391 | MIPS_CPU_WATCH | MIPS_CPU_LLSC; | |
392 | c->tlbsize = 48; | |
393 | break; | |
394 | case PRID_IMP_NEVADA: | |
395 | c->cputype = CPU_NEVADA; | |
396 | c->isa_level = MIPS_CPU_ISA_IV; | |
397 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
398 | MIPS_CPU_DIVEC | MIPS_CPU_LLSC; | |
399 | c->tlbsize = 48; | |
400 | break; | |
401 | case PRID_IMP_R6000: | |
402 | c->cputype = CPU_R6000; | |
403 | c->isa_level = MIPS_CPU_ISA_II; | |
404 | c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | | |
405 | MIPS_CPU_LLSC; | |
406 | c->tlbsize = 32; | |
407 | break; | |
408 | case PRID_IMP_R6000A: | |
409 | c->cputype = CPU_R6000A; | |
410 | c->isa_level = MIPS_CPU_ISA_II; | |
411 | c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | | |
412 | MIPS_CPU_LLSC; | |
413 | c->tlbsize = 32; | |
414 | break; | |
415 | case PRID_IMP_RM7000: | |
416 | c->cputype = CPU_RM7000; | |
417 | c->isa_level = MIPS_CPU_ISA_IV; | |
418 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
419 | MIPS_CPU_LLSC; | |
420 | /* | |
421 | * Undocumented RM7000: Bit 29 in the info register of | |
422 | * the RM7000 v2.0 indicates if the TLB has 48 or 64 | |
423 | * entries. | |
424 | * | |
425 | * 29 1 => 64 entry JTLB | |
426 | * 0 => 48 entry JTLB | |
427 | */ | |
428 | c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; | |
429 | break; | |
430 | case PRID_IMP_RM9000: | |
431 | c->cputype = CPU_RM9000; | |
432 | c->isa_level = MIPS_CPU_ISA_IV; | |
433 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
434 | MIPS_CPU_LLSC; | |
435 | /* | |
436 | * Bit 29 in the info register of the RM9000 | |
437 | * indicates if the TLB has 48 or 64 entries. | |
438 | * | |
439 | * 29 1 => 64 entry JTLB | |
440 | * 0 => 48 entry JTLB | |
441 | */ | |
442 | c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; | |
443 | break; | |
444 | case PRID_IMP_R8000: | |
445 | c->cputype = CPU_R8000; | |
446 | c->isa_level = MIPS_CPU_ISA_IV; | |
447 | c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | | |
448 | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
449 | MIPS_CPU_LLSC; | |
450 | c->tlbsize = 384; /* has weird TLB: 3-way x 128 */ | |
451 | break; | |
452 | case PRID_IMP_R10000: | |
453 | c->cputype = CPU_R10000; | |
454 | c->isa_level = MIPS_CPU_ISA_IV; | |
8b36612a | 455 | c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | |
1da177e4 LT |
456 | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
457 | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | | |
458 | MIPS_CPU_LLSC; | |
459 | c->tlbsize = 64; | |
460 | break; | |
461 | case PRID_IMP_R12000: | |
462 | c->cputype = CPU_R12000; | |
463 | c->isa_level = MIPS_CPU_ISA_IV; | |
8b36612a | 464 | c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | |
1da177e4 LT |
465 | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
466 | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | | |
467 | MIPS_CPU_LLSC; | |
468 | c->tlbsize = 64; | |
469 | break; | |
44d921b2 K |
470 | case PRID_IMP_R14000: |
471 | c->cputype = CPU_R14000; | |
472 | c->isa_level = MIPS_CPU_ISA_IV; | |
473 | c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | | |
474 | MIPS_CPU_FPU | MIPS_CPU_32FPR | | |
475 | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | | |
476 | MIPS_CPU_LLSC; | |
477 | c->tlbsize = 64; | |
478 | break; | |
1da177e4 LT |
479 | } |
480 | } | |
481 | ||
b4672d37 RB |
482 | static char unknown_isa[] __initdata = KERN_ERR \ |
483 | "Unsupported ISA type, c0.config0: %d."; | |
484 | ||
4194318c | 485 | static inline unsigned int decode_config0(struct cpuinfo_mips *c) |
1da177e4 | 486 | { |
4194318c RB |
487 | unsigned int config0; |
488 | int isa; | |
1da177e4 | 489 | |
4194318c RB |
490 | config0 = read_c0_config(); |
491 | ||
492 | if (((config0 & MIPS_CONF_MT) >> 7) == 1) | |
02cf2119 | 493 | c->options |= MIPS_CPU_TLB; |
4194318c RB |
494 | isa = (config0 & MIPS_CONF_AT) >> 13; |
495 | switch (isa) { | |
496 | case 0: | |
3a01c49a | 497 | switch ((config0 & MIPS_CONF_AR) >> 10) { |
b4672d37 RB |
498 | case 0: |
499 | c->isa_level = MIPS_CPU_ISA_M32R1; | |
500 | break; | |
501 | case 1: | |
502 | c->isa_level = MIPS_CPU_ISA_M32R2; | |
503 | break; | |
504 | default: | |
505 | goto unknown; | |
506 | } | |
4194318c RB |
507 | break; |
508 | case 2: | |
3a01c49a | 509 | switch ((config0 & MIPS_CONF_AR) >> 10) { |
b4672d37 RB |
510 | case 0: |
511 | c->isa_level = MIPS_CPU_ISA_M64R1; | |
512 | break; | |
513 | case 1: | |
514 | c->isa_level = MIPS_CPU_ISA_M64R2; | |
515 | break; | |
516 | default: | |
517 | goto unknown; | |
518 | } | |
4194318c RB |
519 | break; |
520 | default: | |
b4672d37 | 521 | goto unknown; |
4194318c RB |
522 | } |
523 | ||
524 | return config0 & MIPS_CONF_M; | |
b4672d37 RB |
525 | |
526 | unknown: | |
527 | panic(unknown_isa, config0); | |
4194318c RB |
528 | } |
529 | ||
530 | static inline unsigned int decode_config1(struct cpuinfo_mips *c) | |
531 | { | |
532 | unsigned int config1; | |
1da177e4 | 533 | |
1da177e4 | 534 | config1 = read_c0_config1(); |
4194318c RB |
535 | |
536 | if (config1 & MIPS_CONF1_MD) | |
537 | c->ases |= MIPS_ASE_MDMX; | |
538 | if (config1 & MIPS_CONF1_WR) | |
1da177e4 | 539 | c->options |= MIPS_CPU_WATCH; |
4194318c RB |
540 | if (config1 & MIPS_CONF1_CA) |
541 | c->ases |= MIPS_ASE_MIPS16; | |
542 | if (config1 & MIPS_CONF1_EP) | |
1da177e4 | 543 | c->options |= MIPS_CPU_EJTAG; |
4194318c | 544 | if (config1 & MIPS_CONF1_FP) { |
1da177e4 LT |
545 | c->options |= MIPS_CPU_FPU; |
546 | c->options |= MIPS_CPU_32FPR; | |
547 | } | |
4194318c RB |
548 | if (cpu_has_tlb) |
549 | c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; | |
550 | ||
551 | return config1 & MIPS_CONF_M; | |
552 | } | |
553 | ||
554 | static inline unsigned int decode_config2(struct cpuinfo_mips *c) | |
555 | { | |
556 | unsigned int config2; | |
557 | ||
558 | config2 = read_c0_config2(); | |
559 | ||
560 | if (config2 & MIPS_CONF2_SL) | |
561 | c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; | |
562 | ||
563 | return config2 & MIPS_CONF_M; | |
564 | } | |
565 | ||
566 | static inline unsigned int decode_config3(struct cpuinfo_mips *c) | |
567 | { | |
568 | unsigned int config3; | |
569 | ||
570 | config3 = read_c0_config3(); | |
571 | ||
572 | if (config3 & MIPS_CONF3_SM) | |
573 | c->ases |= MIPS_ASE_SMARTMIPS; | |
e50c0a8f RB |
574 | if (config3 & MIPS_CONF3_DSP) |
575 | c->ases |= MIPS_ASE_DSP; | |
8f40611d RB |
576 | if (config3 & MIPS_CONF3_VINT) |
577 | c->options |= MIPS_CPU_VINT; | |
578 | if (config3 & MIPS_CONF3_VEIC) | |
579 | c->options |= MIPS_CPU_VEIC; | |
580 | if (config3 & MIPS_CONF3_MT) | |
581 | c->ases |= MIPS_ASE_MIPSMT; | |
4194318c RB |
582 | |
583 | return config3 & MIPS_CONF_M; | |
584 | } | |
585 | ||
c36cd4ba | 586 | static void __init decode_configs(struct cpuinfo_mips *c) |
4194318c RB |
587 | { |
588 | /* MIPS32 or MIPS64 compliant CPU. */ | |
02cf2119 RB |
589 | c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | |
590 | MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; | |
4194318c | 591 | |
1da177e4 LT |
592 | c->scache.flags = MIPS_CACHE_NOT_PRESENT; |
593 | ||
4194318c RB |
594 | /* Read Config registers. */ |
595 | if (!decode_config0(c)) | |
596 | return; /* actually worth a panic() */ | |
597 | if (!decode_config1(c)) | |
598 | return; | |
599 | if (!decode_config2(c)) | |
600 | return; | |
601 | if (!decode_config3(c)) | |
602 | return; | |
1da177e4 LT |
603 | } |
604 | ||
605 | static inline void cpu_probe_mips(struct cpuinfo_mips *c) | |
606 | { | |
4194318c | 607 | decode_configs(c); |
1da177e4 LT |
608 | switch (c->processor_id & 0xff00) { |
609 | case PRID_IMP_4KC: | |
610 | c->cputype = CPU_4KC; | |
1da177e4 LT |
611 | break; |
612 | case PRID_IMP_4KEC: | |
613 | c->cputype = CPU_4KEC; | |
1da177e4 | 614 | break; |
2b07bd02 RB |
615 | case PRID_IMP_4KECR2: |
616 | c->cputype = CPU_4KEC; | |
2b07bd02 | 617 | break; |
1da177e4 | 618 | case PRID_IMP_4KSC: |
8afcb5d8 | 619 | case PRID_IMP_4KSD: |
1da177e4 | 620 | c->cputype = CPU_4KSC; |
1da177e4 LT |
621 | break; |
622 | case PRID_IMP_5KC: | |
623 | c->cputype = CPU_5KC; | |
1da177e4 LT |
624 | break; |
625 | case PRID_IMP_20KC: | |
626 | c->cputype = CPU_20KC; | |
1da177e4 LT |
627 | break; |
628 | case PRID_IMP_24K: | |
e50c0a8f | 629 | case PRID_IMP_24KE: |
1da177e4 | 630 | c->cputype = CPU_24K; |
1da177e4 LT |
631 | break; |
632 | case PRID_IMP_25KF: | |
633 | c->cputype = CPU_25KF; | |
1da177e4 | 634 | break; |
bbc7f22f RB |
635 | case PRID_IMP_34K: |
636 | c->cputype = CPU_34K; | |
bbc7f22f | 637 | break; |
c620953c CD |
638 | case PRID_IMP_74K: |
639 | c->cputype = CPU_74K; | |
640 | break; | |
1da177e4 LT |
641 | } |
642 | } | |
643 | ||
644 | static inline void cpu_probe_alchemy(struct cpuinfo_mips *c) | |
645 | { | |
4194318c | 646 | decode_configs(c); |
1da177e4 LT |
647 | switch (c->processor_id & 0xff00) { |
648 | case PRID_IMP_AU1_REV1: | |
649 | case PRID_IMP_AU1_REV2: | |
650 | switch ((c->processor_id >> 24) & 0xff) { | |
651 | case 0: | |
a3dddd56 | 652 | c->cputype = CPU_AU1000; |
1da177e4 LT |
653 | break; |
654 | case 1: | |
655 | c->cputype = CPU_AU1500; | |
656 | break; | |
657 | case 2: | |
658 | c->cputype = CPU_AU1100; | |
659 | break; | |
660 | case 3: | |
661 | c->cputype = CPU_AU1550; | |
662 | break; | |
e3ad1c23 PP |
663 | case 4: |
664 | c->cputype = CPU_AU1200; | |
665 | break; | |
1da177e4 LT |
666 | default: |
667 | panic("Unknown Au Core!"); | |
668 | break; | |
669 | } | |
1da177e4 LT |
670 | break; |
671 | } | |
672 | } | |
673 | ||
674 | static inline void cpu_probe_sibyte(struct cpuinfo_mips *c) | |
675 | { | |
4194318c | 676 | decode_configs(c); |
02cf2119 RB |
677 | |
678 | /* | |
679 | * For historical reasons the SB1 comes with it's own variant of | |
680 | * cache code which eventually will be folded into c-r4k.c. Until | |
681 | * then we pretend it's got it's own cache architecture. | |
682 | */ | |
d121ced2 | 683 | c->options &= ~MIPS_CPU_4K_CACHE; |
02cf2119 RB |
684 | c->options |= MIPS_CPU_SB1_CACHE; |
685 | ||
1da177e4 LT |
686 | switch (c->processor_id & 0xff00) { |
687 | case PRID_IMP_SB1: | |
688 | c->cputype = CPU_SB1; | |
1da177e4 | 689 | /* FPU in pass1 is known to have issues. */ |
aa32374a | 690 | if ((c->processor_id & 0xff) < 0x02) |
010b853b | 691 | c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); |
1da177e4 | 692 | break; |
93ce2f52 AI |
693 | case PRID_IMP_SB1A: |
694 | c->cputype = CPU_SB1A; | |
695 | break; | |
1da177e4 LT |
696 | } |
697 | } | |
698 | ||
699 | static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c) | |
700 | { | |
4194318c | 701 | decode_configs(c); |
1da177e4 LT |
702 | switch (c->processor_id & 0xff00) { |
703 | case PRID_IMP_SR71000: | |
704 | c->cputype = CPU_SR71000; | |
1da177e4 LT |
705 | c->scache.ways = 8; |
706 | c->tlbsize = 64; | |
707 | break; | |
708 | } | |
709 | } | |
710 | ||
bdf21b18 PP |
711 | static inline void cpu_probe_philips(struct cpuinfo_mips *c) |
712 | { | |
713 | decode_configs(c); | |
714 | switch (c->processor_id & 0xff00) { | |
715 | case PRID_IMP_PR4450: | |
716 | c->cputype = CPU_PR4450; | |
e7958bb9 | 717 | c->isa_level = MIPS_CPU_ISA_M32R1; |
bdf21b18 PP |
718 | break; |
719 | default: | |
720 | panic("Unknown Philips Core!"); /* REVISIT: die? */ | |
721 | break; | |
722 | } | |
723 | } | |
724 | ||
725 | ||
1da177e4 LT |
726 | __init void cpu_probe(void) |
727 | { | |
728 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
729 | ||
730 | c->processor_id = PRID_IMP_UNKNOWN; | |
731 | c->fpu_id = FPIR_IMP_NONE; | |
732 | c->cputype = CPU_UNKNOWN; | |
733 | ||
734 | c->processor_id = read_c0_prid(); | |
735 | switch (c->processor_id & 0xff0000) { | |
736 | case PRID_COMP_LEGACY: | |
737 | cpu_probe_legacy(c); | |
738 | break; | |
739 | case PRID_COMP_MIPS: | |
740 | cpu_probe_mips(c); | |
741 | break; | |
742 | case PRID_COMP_ALCHEMY: | |
743 | cpu_probe_alchemy(c); | |
744 | break; | |
745 | case PRID_COMP_SIBYTE: | |
746 | cpu_probe_sibyte(c); | |
747 | break; | |
1da177e4 LT |
748 | case PRID_COMP_SANDCRAFT: |
749 | cpu_probe_sandcraft(c); | |
750 | break; | |
bdf21b18 PP |
751 | case PRID_COMP_PHILIPS: |
752 | cpu_probe_philips(c); | |
a3dddd56 | 753 | break; |
1da177e4 LT |
754 | default: |
755 | c->cputype = CPU_UNKNOWN; | |
756 | } | |
4194318c | 757 | if (c->options & MIPS_CPU_FPU) { |
1da177e4 | 758 | c->fpu_id = cpu_get_fpu_id(); |
4194318c | 759 | |
e7958bb9 | 760 | if (c->isa_level == MIPS_CPU_ISA_M32R1 || |
b4672d37 RB |
761 | c->isa_level == MIPS_CPU_ISA_M32R2 || |
762 | c->isa_level == MIPS_CPU_ISA_M64R1 || | |
763 | c->isa_level == MIPS_CPU_ISA_M64R2) { | |
4194318c RB |
764 | if (c->fpu_id & MIPS_FPIR_3D) |
765 | c->ases |= MIPS_ASE_MIPS3D; | |
766 | } | |
767 | } | |
1da177e4 LT |
768 | } |
769 | ||
770 | __init void cpu_report(void) | |
771 | { | |
772 | struct cpuinfo_mips *c = ¤t_cpu_data; | |
773 | ||
774 | printk("CPU revision is: %08x\n", c->processor_id); | |
775 | if (c->options & MIPS_CPU_FPU) | |
776 | printk("FPU revision is: %08x\n", c->fpu_id); | |
777 | } |