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MIPS: Alchemy: get rid of allow_au1k_wait
[linux-2.6-block.git] / arch / mips / kernel / cpu-probe.c
CommitLineData
1da177e4
LT		 1/*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
010b853b 5 * Copyright (C) 1994 - 2006 Ralf Baechle
4194318c 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
4194318c 7 * Copyright (C) 2001, 2004 MIPS Inc.
1da177e4
LT		 8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
1da177e4
LT		 14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/ptrace.h>
631330f5 17#include <linux/smp.h>
1da177e4
LT		 18#include <linux/stddef.h>
19
5759906c 20#include <asm/bugs.h>
1da177e4
LT		 21#include <asm/cpu.h>
22#include <asm/fpu.h>
23#include <asm/mipsregs.h>
24#include <asm/system.h>
654f57bf 25#include <asm/watch.h>
1da177e4
LT		 26
27/*
28 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
29 * the implementation of the "wait" feature differs between CPU families. This
30 * points to the function that implements CPU specific wait.
31 * The wait instruction stops the pipeline and reduces the power consumption of
32 * the CPU very much.
33 */
34void (*cpu_wait)(void) = NULL;
35
36static void r3081_wait(void)
37{
38 unsigned long cfg = read_c0_conf();
39 write_c0_conf(cfg | R30XX_CONF_HALT);
40}
41
42static void r39xx_wait(void)
43{
60a6c377
AN		 44 local_irq_disable();
45 if (!need_resched())
46 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
47 local_irq_enable();
1da177e4
LT		 48}
49
c65a5480 50extern void r4k_wait(void);
60a6c377
AN		 51
52/*
53 * This variant is preferable as it allows testing need_resched and going to
54 * sleep depending on the outcome atomically. Unfortunately the "It is
55 * implementation-dependent whether the pipeline restarts when a non-enabled
56 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
57 * using this version a gamble.
58 */
8531a35e 59void r4k_wait_irqoff(void)
60a6c377
AN		 60{
61 local_irq_disable();
62 if (!need_resched())
8531a35e
KK		 63 __asm__(" .set push \n"
64 " .set mips3 \n"
60a6c377 65 " wait \n"
8531a35e 66 " .set pop \n");
60a6c377 67 local_irq_enable();
8531a35e
KK		 68 __asm__(" .globl __pastwait \n"
69 "__pastwait: \n");
70 return;
1da177e4
LT		 71}
72
5a812999
RB		 73/*
74 * The RM7000 variant has to handle erratum 38. The workaround is to not
75 * have any pending stores when the WAIT instruction is executed.
76 */
77static void rm7k_wait_irqoff(void)
78{
79 local_irq_disable();
80 if (!need_resched())
81 __asm__(
82 " .set push \n"
83 " .set mips3 \n"
84 " .set noat \n"
85 " mfc0 $1, $12 \n"
86 " sync \n"
87 " mtc0 $1, $12 # stalls until W stage \n"
88 " wait \n"
89 " mtc0 $1, $12 # stalls until W stage \n"
90 " .set pop \n");
91 local_irq_enable();
92}
93
2882b0c6
ML		 94/*
95 * The Au1xxx wait is available only if using 32khz counter or
96 * external timer source, but specifically not CP0 Counter.
97 * alchemy/common/time.c may override cpu_wait!
98 */
494900af 99static void au1k_wait(void)
1da177e4 100{
60a6c377
AN		 101 __asm__(" .set mips3 \n"
102 " cache 0x14, 0(%0) \n"
103 " cache 0x14, 32(%0) \n"
104 " sync \n"
105 " nop \n"
106 " wait \n"
107 " nop \n"
108 " nop \n"
109 " nop \n"
110 " nop \n"
111 " .set mips0 \n"
10f650db 112 : : "r" (au1k_wait));
1da177e4
LT		 113}
114
55d04dff
RB		 115static int __initdata nowait = 0;
116
f49a747c 117static int __init wait_disable(char *s)
55d04dff
RB		 118{
119 nowait = 1;
120
121 return 1;
122}
123
124__setup("nowait", wait_disable);
125
c65a5480 126void __init check_wait(void)
1da177e4
LT		 127{
128 struct cpuinfo_mips *c = &current_cpu_data;
129
55d04dff 130 if (nowait) {
c2379230 131 printk("Wait instruction disabled.\n");
55d04dff
RB		 132 return;
133 }
134
1da177e4
LT		 135 switch (c->cputype) {
136 case CPU_R3081:
137 case CPU_R3081E:
138 cpu_wait = r3081_wait;
1da177e4
LT		 139 break;
140 case CPU_TX3927:
141 cpu_wait = r39xx_wait;
1da177e4
LT		 142 break;
143 case CPU_R4200:
144/* case CPU_R4300: */
145 case CPU_R4600:
146 case CPU_R4640:
147 case CPU_R4650:
148 case CPU_R4700:
149 case CPU_R5000:
a644b277 150 case CPU_R5500:
1da177e4 151 case CPU_NEVADA:
1da177e4
LT		 152 case CPU_4KC:
153 case CPU_4KEC:
154 case CPU_4KSC:
155 case CPU_5KC:
1da177e4 156 case CPU_25KF:
4b3e975e 157 case CPU_PR4450:
1c0c13eb 158 case CPU_BCM3302:
0dd4781b 159 case CPU_CAVIUM_OCTEON:
4b3e975e
RB		 160 cpu_wait = r4k_wait;
161 break;
162
5a812999
RB		 163 case CPU_RM7000:
164 cpu_wait = rm7k_wait_irqoff;
165 break;
166
4b3e975e 167 case CPU_24K:
bbc7f22f 168 case CPU_34K:
39b8d525 169 case CPU_1004K:
4b3e975e
RB		 170 cpu_wait = r4k_wait;
171 if (read_c0_config7() & MIPS_CONF7_WII)
172 cpu_wait = r4k_wait_irqoff;
173 break;
174
c620953c 175 case CPU_74K:
1da177e4 176 cpu_wait = r4k_wait;
4b3e975e
RB		 177 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
178 cpu_wait = r4k_wait_irqoff;
1da177e4 179 break;
4b3e975e 180
60a6c377
AN		 181 case CPU_TX49XX:
182 cpu_wait = r4k_wait_irqoff;
60a6c377 183 break;
270717a8 184 case CPU_ALCHEMY:
0c694de1 185 cpu_wait = au1k_wait;
1da177e4 186 break;
c8eae71d
RB		 187 case CPU_20KC:
188 /*
189 * WAIT on Rev1.0 has E1, E2, E3 and E16.
190 * WAIT on Rev2.0 and Rev3.0 has E16.
191 * Rev3.1 WAIT is nop, why bother
192 */
193 if ((c->processor_id & 0xff) <= 0x64)
194 break;
195
50da469a
RB		 196 /*
197 * Another rev is incremeting c0_count at a reduced clock
198 * rate while in WAIT mode. So we basically have the choice
199 * between using the cp0 timer as clocksource or avoiding
200 * the WAIT instruction. Until more details are known,
201 * disable the use of WAIT for 20Kc entirely.
202 cpu_wait = r4k_wait;
203 */
c8eae71d 204 break;
441ee341 205 case CPU_RM9000:
c2379230 206 if ((c->processor_id & 0x00ff) >= 0x40)
441ee341 207 cpu_wait = r4k_wait;
441ee341 208 break;
1da177e4 209 default:
1da177e4
LT		 210 break;
211 }
212}
213
9267a30d
MSJ		 214static inline void check_errata(void)
215{
216 struct cpuinfo_mips *c = &current_cpu_data;
217
218 switch (c->cputype) {
219 case CPU_34K:
220 /*
221 * Erratum "RPS May Cause Incorrect Instruction Execution"
222 * This code only handles VPE0, any SMP/SMTC/RTOS code
223 * making use of VPE1 will be responsable for that VPE.
224 */
225 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
226 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
227 break;
228 default:
229 break;
230 }
231}
232
1da177e4
LT		 233void __init check_bugs32(void)
234{
9267a30d 235 check_errata();
1da177e4
LT		 236}
237
238/*
239 * Probe whether cpu has config register by trying to play with
240 * alternate cache bit and see whether it matters.
241 * It's used by cpu_probe to distinguish between R3000A and R3081.
242 */
243static inline int cpu_has_confreg(void)
244{
245#ifdef CONFIG_CPU_R3000
246 extern unsigned long r3k_cache_size(unsigned long);
247 unsigned long size1, size2;
248 unsigned long cfg = read_c0_conf();
249
250 size1 = r3k_cache_size(ST0_ISC);
251 write_c0_conf(cfg ^ R30XX_CONF_AC);
252 size2 = r3k_cache_size(ST0_ISC);
253 write_c0_conf(cfg);
254 return size1 != size2;
255#else
256 return 0;
257#endif
258}
259
260/*
261 * Get the FPU Implementation/Revision.
262 */
263static inline unsigned long cpu_get_fpu_id(void)
264{
265 unsigned long tmp, fpu_id;
266
267 tmp = read_c0_status();
268 __enable_fpu();
269 fpu_id = read_32bit_cp1_register(CP1_REVISION);
270 write_c0_status(tmp);
271 return fpu_id;
272}
273
274/*
275 * Check the CPU has an FPU the official way.
276 */
277static inline int __cpu_has_fpu(void)
278{
279 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
280}
281
02cf2119 282#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1da177e4
LT		 283 | MIPS_CPU_COUNTER)
284
cea7e2df 285static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4
LT		 286{
287 switch (c->processor_id & 0xff00) {
288 case PRID_IMP_R2000:
289 c->cputype = CPU_R2000;
cea7e2df 290 __cpu_name[cpu] = "R2000";
1da177e4 291 c->isa_level = MIPS_CPU_ISA_I;
02cf2119
RB		 292 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
293 MIPS_CPU_NOFPUEX;
1da177e4
LT		 294 if (__cpu_has_fpu())
295 c->options |= MIPS_CPU_FPU;
296 c->tlbsize = 64;
297 break;
298 case PRID_IMP_R3000:
cea7e2df
RB		 299 if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
300 if (cpu_has_confreg()) {
1da177e4 301 c->cputype = CPU_R3081E;
cea7e2df
RB		 302 __cpu_name[cpu] = "R3081";
303 } else {
1da177e4 304 c->cputype = CPU_R3000A;
cea7e2df
RB		 305 __cpu_name[cpu] = "R3000A";
306 }
307 break;
308 } else {
1da177e4 309 c->cputype = CPU_R3000;
cea7e2df
RB		 310 __cpu_name[cpu] = "R3000";
311 }
1da177e4 312 c->isa_level = MIPS_CPU_ISA_I;
02cf2119
RB		 313 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
314 MIPS_CPU_NOFPUEX;
1da177e4
LT		 315 if (__cpu_has_fpu())
316 c->options |= MIPS_CPU_FPU;
317 c->tlbsize = 64;
318 break;
319 case PRID_IMP_R4000:
320 if (read_c0_config() & CONF_SC) {
cea7e2df 321 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
1da177e4 322 c->cputype = CPU_R4400PC;
cea7e2df
RB		 323 __cpu_name[cpu] = "R4400PC";
324 } else {
1da177e4 325 c->cputype = CPU_R4000PC;
cea7e2df
RB		 326 __cpu_name[cpu] = "R4000PC";
327 }
1da177e4 328 } else {
cea7e2df 329 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
1da177e4 330 c->cputype = CPU_R4400SC;
cea7e2df
RB		 331 __cpu_name[cpu] = "R4400SC";
332 } else {
1da177e4 333 c->cputype = CPU_R4000SC;
cea7e2df
RB		 334 __cpu_name[cpu] = "R4000SC";
335 }
1da177e4
LT		 336 }
337
338 c->isa_level = MIPS_CPU_ISA_III;
339 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
340 MIPS_CPU_WATCH | MIPS_CPU_VCE |
341 MIPS_CPU_LLSC;
342 c->tlbsize = 48;
343 break;
344 case PRID_IMP_VR41XX:
345 switch (c->processor_id & 0xf0) {
1da177e4
LT		 346 case PRID_REV_VR4111:
347 c->cputype = CPU_VR4111;
cea7e2df 348 __cpu_name[cpu] = "NEC VR4111";
1da177e4 349 break;
1da177e4
LT		 350 case PRID_REV_VR4121:
351 c->cputype = CPU_VR4121;
cea7e2df 352 __cpu_name[cpu] = "NEC VR4121";
1da177e4
LT		 353 break;
354 case PRID_REV_VR4122:
cea7e2df 355 if ((c->processor_id & 0xf) < 0x3) {
1da177e4 356 c->cputype = CPU_VR4122;
cea7e2df
RB		 357 __cpu_name[cpu] = "NEC VR4122";
358 } else {
1da177e4 359 c->cputype = CPU_VR4181A;
cea7e2df
RB		 360 __cpu_name[cpu] = "NEC VR4181A";
361 }
1da177e4
LT		 362 break;
363 case PRID_REV_VR4130:
cea7e2df 364 if ((c->processor_id & 0xf) < 0x4) {
1da177e4 365 c->cputype = CPU_VR4131;
cea7e2df
RB		 366 __cpu_name[cpu] = "NEC VR4131";
367 } else {
1da177e4 368 c->cputype = CPU_VR4133;
cea7e2df
RB		 369 __cpu_name[cpu] = "NEC VR4133";
370 }
1da177e4
LT		 371 break;
372 default:
373 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
374 c->cputype = CPU_VR41XX;
cea7e2df 375 __cpu_name[cpu] = "NEC Vr41xx";
1da177e4
LT		 376 break;
377 }
378 c->isa_level = MIPS_CPU_ISA_III;
379 c->options = R4K_OPTS;
380 c->tlbsize = 32;
381 break;
382 case PRID_IMP_R4300:
383 c->cputype = CPU_R4300;
cea7e2df 384 __cpu_name[cpu] = "R4300";
1da177e4
LT		 385 c->isa_level = MIPS_CPU_ISA_III;
386 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
387 MIPS_CPU_LLSC;
388 c->tlbsize = 32;
389 break;
390 case PRID_IMP_R4600:
391 c->cputype = CPU_R4600;
cea7e2df 392 __cpu_name[cpu] = "R4600";
1da177e4 393 c->isa_level = MIPS_CPU_ISA_III;
075e7502
TS		 394 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
395 MIPS_CPU_LLSC;
1da177e4
LT		 396 c->tlbsize = 48;
397 break;
398 #if 0
399 case PRID_IMP_R4650:
400 /*
401 * This processor doesn't have an MMU, so it's not
402 * "real easy" to run Linux on it. It is left purely
403 * for documentation. Commented out because it shares
404 * it's c0_prid id number with the TX3900.
405 */
a3dddd56 406 c->cputype = CPU_R4650;
cea7e2df 407 __cpu_name[cpu] = "R4650";
1da177e4
LT		 408 c->isa_level = MIPS_CPU_ISA_III;
409 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
410 c->tlbsize = 48;
411 break;
412 #endif
413 case PRID_IMP_TX39:
414 c->isa_level = MIPS_CPU_ISA_I;
02cf2119 415 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1da177e4
LT		 416
417 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
418 c->cputype = CPU_TX3927;
cea7e2df 419 __cpu_name[cpu] = "TX3927";
1da177e4
LT		 420 c->tlbsize = 64;
421 } else {
422 switch (c->processor_id & 0xff) {
423 case PRID_REV_TX3912:
424 c->cputype = CPU_TX3912;
cea7e2df 425 __cpu_name[cpu] = "TX3912";
1da177e4
LT		 426 c->tlbsize = 32;
427 break;
428 case PRID_REV_TX3922:
429 c->cputype = CPU_TX3922;
cea7e2df 430 __cpu_name[cpu] = "TX3922";
1da177e4
LT		 431 c->tlbsize = 64;
432 break;
1da177e4
LT		 433 }
434 }
435 break;
436 case PRID_IMP_R4700:
437 c->cputype = CPU_R4700;
cea7e2df 438 __cpu_name[cpu] = "R4700";
1da177e4
LT		 439 c->isa_level = MIPS_CPU_ISA_III;
440 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
441 MIPS_CPU_LLSC;
442 c->tlbsize = 48;
443 break;
444 case PRID_IMP_TX49:
445 c->cputype = CPU_TX49XX;
cea7e2df 446 __cpu_name[cpu] = "R49XX";
1da177e4
LT		 447 c->isa_level = MIPS_CPU_ISA_III;
448 c->options = R4K_OPTS | MIPS_CPU_LLSC;
449 if (!(c->processor_id & 0x08))
450 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
451 c->tlbsize = 48;
452 break;
453 case PRID_IMP_R5000:
454 c->cputype = CPU_R5000;
cea7e2df 455 __cpu_name[cpu] = "R5000";
1da177e4
LT		 456 c->isa_level = MIPS_CPU_ISA_IV;
457 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
458 MIPS_CPU_LLSC;
459 c->tlbsize = 48;
460 break;
461 case PRID_IMP_R5432:
462 c->cputype = CPU_R5432;
cea7e2df 463 __cpu_name[cpu] = "R5432";
1da177e4
LT		 464 c->isa_level = MIPS_CPU_ISA_IV;
465 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
466 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
467 c->tlbsize = 48;
468 break;
469 case PRID_IMP_R5500:
470 c->cputype = CPU_R5500;
cea7e2df 471 __cpu_name[cpu] = "R5500";
1da177e4
LT		 472 c->isa_level = MIPS_CPU_ISA_IV;
473 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
474 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
475 c->tlbsize = 48;
476 break;
477 case PRID_IMP_NEVADA:
478 c->cputype = CPU_NEVADA;
cea7e2df 479 __cpu_name[cpu] = "Nevada";
1da177e4
LT		 480 c->isa_level = MIPS_CPU_ISA_IV;
481 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
482 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
483 c->tlbsize = 48;
484 break;
485 case PRID_IMP_R6000:
486 c->cputype = CPU_R6000;
cea7e2df 487 __cpu_name[cpu] = "R6000";
1da177e4
LT		 488 c->isa_level = MIPS_CPU_ISA_II;
489 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
490 MIPS_CPU_LLSC;
491 c->tlbsize = 32;
492 break;
493 case PRID_IMP_R6000A:
494 c->cputype = CPU_R6000A;
cea7e2df 495 __cpu_name[cpu] = "R6000A";
1da177e4
LT		 496 c->isa_level = MIPS_CPU_ISA_II;
497 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
498 MIPS_CPU_LLSC;
499 c->tlbsize = 32;
500 break;
501 case PRID_IMP_RM7000:
502 c->cputype = CPU_RM7000;
cea7e2df 503 __cpu_name[cpu] = "RM7000";
1da177e4
LT		 504 c->isa_level = MIPS_CPU_ISA_IV;
505 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
506 MIPS_CPU_LLSC;
507 /*
508 * Undocumented RM7000: Bit 29 in the info register of
509 * the RM7000 v2.0 indicates if the TLB has 48 or 64
510 * entries.
511 *
512 * 29 1 => 64 entry JTLB
513 * 0 => 48 entry JTLB
514 */
515 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
516 break;
517 case PRID_IMP_RM9000:
518 c->cputype = CPU_RM9000;
cea7e2df 519 __cpu_name[cpu] = "RM9000";
1da177e4
LT		 520 c->isa_level = MIPS_CPU_ISA_IV;
521 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
522 MIPS_CPU_LLSC;
523 /*
524 * Bit 29 in the info register of the RM9000
525 * indicates if the TLB has 48 or 64 entries.
526 *
527 * 29 1 => 64 entry JTLB
528 * 0 => 48 entry JTLB
529 */
530 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
531 break;
532 case PRID_IMP_R8000:
533 c->cputype = CPU_R8000;
cea7e2df 534 __cpu_name[cpu] = "RM8000";
1da177e4
LT		 535 c->isa_level = MIPS_CPU_ISA_IV;
536 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
537 MIPS_CPU_FPU | MIPS_CPU_32FPR |
538 MIPS_CPU_LLSC;
539 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
540 break;
541 case PRID_IMP_R10000:
542 c->cputype = CPU_R10000;
cea7e2df 543 __cpu_name[cpu] = "R10000";
1da177e4 544 c->isa_level = MIPS_CPU_ISA_IV;
8b36612a 545 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1da177e4
LT		 546 MIPS_CPU_FPU | MIPS_CPU_32FPR |
547 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
548 MIPS_CPU_LLSC;
549 c->tlbsize = 64;
550 break;
551 case PRID_IMP_R12000:
552 c->cputype = CPU_R12000;
cea7e2df 553 __cpu_name[cpu] = "R12000";
1da177e4 554 c->isa_level = MIPS_CPU_ISA_IV;
8b36612a 555 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1da177e4
LT		 556 MIPS_CPU_FPU | MIPS_CPU_32FPR |
557 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
558 MIPS_CPU_LLSC;
559 c->tlbsize = 64;
560 break;
44d921b2
K		 561 case PRID_IMP_R14000:
562 c->cputype = CPU_R14000;
cea7e2df 563 __cpu_name[cpu] = "R14000";
44d921b2
K		 564 c->isa_level = MIPS_CPU_ISA_IV;
565 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
566 MIPS_CPU_FPU | MIPS_CPU_32FPR |
567 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
568 MIPS_CPU_LLSC;
569 c->tlbsize = 64;
570 break;
2a21c730
FZ		 571 case PRID_IMP_LOONGSON2:
572 c->cputype = CPU_LOONGSON2;
cea7e2df 573 __cpu_name[cpu] = "ICT Loongson-2";
2a21c730
FZ		 574 c->isa_level = MIPS_CPU_ISA_III;
575 c->options = R4K_OPTS |
576 MIPS_CPU_FPU | MIPS_CPU_LLSC |
577 MIPS_CPU_32FPR;
578 c->tlbsize = 64;
579 break;
1da177e4
LT		 580 }
581}
582
234fcd14 583static char unknown_isa[] __cpuinitdata = KERN_ERR \
b4672d37
RB		 584 "Unsupported ISA type, c0.config0: %d.";
585
4194318c 586static inline unsigned int decode_config0(struct cpuinfo_mips *c)
1da177e4 587{
4194318c
RB		 588 unsigned int config0;
589 int isa;
1da177e4 590
4194318c
RB		 591 config0 = read_c0_config();
592
593 if (((config0 & MIPS_CONF_MT) >> 7) == 1)
02cf2119 594 c->options |= MIPS_CPU_TLB;
4194318c
RB		 595 isa = (config0 & MIPS_CONF_AT) >> 13;
596 switch (isa) {
597 case 0:
3a01c49a 598 switch ((config0 & MIPS_CONF_AR) >> 10) {
b4672d37
RB		 599 case 0:
600 c->isa_level = MIPS_CPU_ISA_M32R1;
601 break;
602 case 1:
603 c->isa_level = MIPS_CPU_ISA_M32R2;
604 break;
605 default:
606 goto unknown;
607 }
4194318c
RB		 608 break;
609 case 2:
3a01c49a 610 switch ((config0 & MIPS_CONF_AR) >> 10) {
b4672d37
RB		 611 case 0:
612 c->isa_level = MIPS_CPU_ISA_M64R1;
613 break;
614 case 1:
615 c->isa_level = MIPS_CPU_ISA_M64R2;
616 break;
617 default:
618 goto unknown;
619 }
4194318c
RB		 620 break;
621 default:
b4672d37 622 goto unknown;
4194318c
RB		 623 }
624
625 return config0 & MIPS_CONF_M;
b4672d37
RB		 626
627unknown:
628 panic(unknown_isa, config0);
4194318c
RB		 629}
630
631static inline unsigned int decode_config1(struct cpuinfo_mips *c)
632{
633 unsigned int config1;
1da177e4 634
1da177e4 635 config1 = read_c0_config1();
4194318c
RB		 636
637 if (config1 & MIPS_CONF1_MD)
638 c->ases |= MIPS_ASE_MDMX;
639 if (config1 & MIPS_CONF1_WR)
1da177e4 640 c->options |= MIPS_CPU_WATCH;
4194318c
RB		 641 if (config1 & MIPS_CONF1_CA)
642 c->ases |= MIPS_ASE_MIPS16;
643 if (config1 & MIPS_CONF1_EP)
1da177e4 644 c->options |= MIPS_CPU_EJTAG;
4194318c 645 if (config1 & MIPS_CONF1_FP) {
1da177e4
LT		 646 c->options |= MIPS_CPU_FPU;
647 c->options |= MIPS_CPU_32FPR;
648 }
4194318c
RB		 649 if (cpu_has_tlb)
650 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
651
652 return config1 & MIPS_CONF_M;
653}
654
655static inline unsigned int decode_config2(struct cpuinfo_mips *c)
656{
657 unsigned int config2;
658
659 config2 = read_c0_config2();
660
661 if (config2 & MIPS_CONF2_SL)
662 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
663
664 return config2 & MIPS_CONF_M;
665}
666
667static inline unsigned int decode_config3(struct cpuinfo_mips *c)
668{
669 unsigned int config3;
670
671 config3 = read_c0_config3();
672
673 if (config3 & MIPS_CONF3_SM)
674 c->ases |= MIPS_ASE_SMARTMIPS;
e50c0a8f
RB		 675 if (config3 & MIPS_CONF3_DSP)
676 c->ases |= MIPS_ASE_DSP;
8f40611d
RB		 677 if (config3 & MIPS_CONF3_VINT)
678 c->options |= MIPS_CPU_VINT;
679 if (config3 & MIPS_CONF3_VEIC)
680 c->options |= MIPS_CPU_VEIC;
681 if (config3 & MIPS_CONF3_MT)
e0daad44 682 c->ases |= MIPS_ASE_MIPSMT;
a3692020
RB		 683 if (config3 & MIPS_CONF3_ULRI)
684 c->options |= MIPS_CPU_ULRI;
4194318c
RB		 685
686 return config3 & MIPS_CONF_M;
687}
688
234fcd14 689static void __cpuinit decode_configs(struct cpuinfo_mips *c)
4194318c 690{
558ce124
RB		 691 int ok;
692
4194318c 693 /* MIPS32 or MIPS64 compliant CPU. */
02cf2119
RB		 694 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
695 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
4194318c 696
1da177e4
LT		 697 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
698
558ce124
RB		 699 ok = decode_config0(c); /* Read Config registers. */
700 BUG_ON(!ok); /* Arch spec violation! */
701 if (ok)
702 ok = decode_config1(c);
703 if (ok)
704 ok = decode_config2(c);
705 if (ok)
706 ok = decode_config3(c);
707
708 mips_probe_watch_registers(c);
1da177e4
LT		 709}
710
0b6d497f
CD		 711#ifdef CONFIG_CPU_MIPSR2
712extern void spram_config(void);
713#else
714static inline void spram_config(void) {}
715#endif
716
cea7e2df 717static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 718{
4194318c 719 decode_configs(c);
1da177e4
LT		 720 switch (c->processor_id & 0xff00) {
721 case PRID_IMP_4KC:
722 c->cputype = CPU_4KC;
cea7e2df 723 __cpu_name[cpu] = "MIPS 4Kc";
1da177e4
LT		 724 break;
725 case PRID_IMP_4KEC:
726 c->cputype = CPU_4KEC;
cea7e2df 727 __cpu_name[cpu] = "MIPS 4KEc";
1da177e4 728 break;
2b07bd02
RB		 729 case PRID_IMP_4KECR2:
730 c->cputype = CPU_4KEC;
cea7e2df 731 __cpu_name[cpu] = "MIPS 4KEc";
2b07bd02 732 break;
1da177e4 733 case PRID_IMP_4KSC:
8afcb5d8 734 case PRID_IMP_4KSD:
1da177e4 735 c->cputype = CPU_4KSC;
cea7e2df 736 __cpu_name[cpu] = "MIPS 4KSc";
1da177e4
LT		 737 break;
738 case PRID_IMP_5KC:
739 c->cputype = CPU_5KC;
cea7e2df 740 __cpu_name[cpu] = "MIPS 5Kc";
1da177e4
LT		 741 break;
742 case PRID_IMP_20KC:
743 c->cputype = CPU_20KC;
cea7e2df 744 __cpu_name[cpu] = "MIPS 20Kc";
1da177e4
LT		 745 break;
746 case PRID_IMP_24K:
e50c0a8f 747 case PRID_IMP_24KE:
1da177e4 748 c->cputype = CPU_24K;
cea7e2df 749 __cpu_name[cpu] = "MIPS 24Kc";
1da177e4
LT		 750 break;
751 case PRID_IMP_25KF:
752 c->cputype = CPU_25KF;
cea7e2df 753 __cpu_name[cpu] = "MIPS 25Kc";
1da177e4 754 break;
bbc7f22f
RB		 755 case PRID_IMP_34K:
756 c->cputype = CPU_34K;
cea7e2df 757 __cpu_name[cpu] = "MIPS 34Kc";
bbc7f22f 758 break;
c620953c
CD		 759 case PRID_IMP_74K:
760 c->cputype = CPU_74K;
cea7e2df 761 __cpu_name[cpu] = "MIPS 74Kc";
c620953c 762 break;
39b8d525
RB		 763 case PRID_IMP_1004K:
764 c->cputype = CPU_1004K;
cea7e2df 765 __cpu_name[cpu] = "MIPS 1004Kc";
39b8d525 766 break;
1da177e4 767 }
0b6d497f
CD		 768
769 spram_config();
1da177e4
LT		 770}
771
cea7e2df 772static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 773{
4194318c 774 decode_configs(c);
1da177e4
LT		 775 switch (c->processor_id & 0xff00) {
776 case PRID_IMP_AU1_REV1:
777 case PRID_IMP_AU1_REV2:
270717a8 778 c->cputype = CPU_ALCHEMY;
1da177e4
LT		 779 switch ((c->processor_id >> 24) & 0xff) {
780 case 0:
cea7e2df 781 __cpu_name[cpu] = "Au1000";
1da177e4
LT		 782 break;
783 case 1:
cea7e2df 784 __cpu_name[cpu] = "Au1500";
1da177e4
LT		 785 break;
786 case 2:
cea7e2df 787 __cpu_name[cpu] = "Au1100";
1da177e4
LT		 788 break;
789 case 3:
cea7e2df 790 __cpu_name[cpu] = "Au1550";
1da177e4 791 break;
e3ad1c23 792 case 4:
cea7e2df 793 __cpu_name[cpu] = "Au1200";
270717a8 794 if ((c->processor_id & 0xff) == 2)
cea7e2df 795 __cpu_name[cpu] = "Au1250";
237cfee1
ML		 796 break;
797 case 5:
cea7e2df 798 __cpu_name[cpu] = "Au1210";
e3ad1c23 799 break;
1da177e4 800 default:
270717a8 801 __cpu_name[cpu] = "Au1xxx";
1da177e4
LT		 802 break;
803 }
1da177e4
LT		 804 break;
805 }
806}
807
cea7e2df 808static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 809{
4194318c 810 decode_configs(c);
02cf2119 811
1da177e4
LT		 812 switch (c->processor_id & 0xff00) {
813 case PRID_IMP_SB1:
814 c->cputype = CPU_SB1;
cea7e2df 815 __cpu_name[cpu] = "SiByte SB1";
1da177e4 816 /* FPU in pass1 is known to have issues. */
aa32374a 817 if ((c->processor_id & 0xff) < 0x02)
010b853b 818 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1da177e4 819 break;
93ce2f52
AI		 820 case PRID_IMP_SB1A:
821 c->cputype = CPU_SB1A;
cea7e2df 822 __cpu_name[cpu] = "SiByte SB1A";
93ce2f52 823 break;
1da177e4
LT		 824 }
825}
826
cea7e2df 827static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 828{
4194318c 829 decode_configs(c);
1da177e4
LT		 830 switch (c->processor_id & 0xff00) {
831 case PRID_IMP_SR71000:
832 c->cputype = CPU_SR71000;
cea7e2df 833 __cpu_name[cpu] = "Sandcraft SR71000";
1da177e4
LT		 834 c->scache.ways = 8;
835 c->tlbsize = 64;
836 break;
837 }
838}
839
cea7e2df 840static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
bdf21b18
PP		 841{
842 decode_configs(c);
843 switch (c->processor_id & 0xff00) {
844 case PRID_IMP_PR4450:
845 c->cputype = CPU_PR4450;
cea7e2df 846 __cpu_name[cpu] = "Philips PR4450";
e7958bb9 847 c->isa_level = MIPS_CPU_ISA_M32R1;
bdf21b18 848 break;
bdf21b18
PP		 849 }
850}
851
cea7e2df 852static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1c0c13eb
AJ		 853{
854 decode_configs(c);
855 switch (c->processor_id & 0xff00) {
856 case PRID_IMP_BCM3302:
857 c->cputype = CPU_BCM3302;
cea7e2df 858 __cpu_name[cpu] = "Broadcom BCM3302";
1c0c13eb
AJ		 859 break;
860 case PRID_IMP_BCM4710:
861 c->cputype = CPU_BCM4710;
cea7e2df 862 __cpu_name[cpu] = "Broadcom BCM4710";
1c0c13eb
AJ		 863 break;
864 }
865}
866
0dd4781b
DD		 867static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
868{
869 decode_configs(c);
870 switch (c->processor_id & 0xff00) {
871 case PRID_IMP_CAVIUM_CN38XX:
872 case PRID_IMP_CAVIUM_CN31XX:
873 case PRID_IMP_CAVIUM_CN30XX:
874 case PRID_IMP_CAVIUM_CN58XX:
875 case PRID_IMP_CAVIUM_CN56XX:
876 case PRID_IMP_CAVIUM_CN50XX:
877 case PRID_IMP_CAVIUM_CN52XX:
878 c->cputype = CPU_CAVIUM_OCTEON;
879 __cpu_name[cpu] = "Cavium Octeon";
880 break;
881 default:
882 printk(KERN_INFO "Unknown Octeon chip!\n");
883 c->cputype = CPU_UNKNOWN;
884 break;
885 }
886}
887
9966db25
RB		 888const char *__cpu_name[NR_CPUS];
889
234fcd14 890__cpuinit void cpu_probe(void)
1da177e4
LT		 891{
892 struct cpuinfo_mips *c = &current_cpu_data;
9966db25 893 unsigned int cpu = smp_processor_id();
1da177e4
LT		 894
895 c->processor_id = PRID_IMP_UNKNOWN;
896 c->fpu_id = FPIR_IMP_NONE;
897 c->cputype = CPU_UNKNOWN;
898
899 c->processor_id = read_c0_prid();
900 switch (c->processor_id & 0xff0000) {
901 case PRID_COMP_LEGACY:
cea7e2df 902 cpu_probe_legacy(c, cpu);
1da177e4
LT		 903 break;
904 case PRID_COMP_MIPS:
cea7e2df 905 cpu_probe_mips(c, cpu);
1da177e4
LT		 906 break;
907 case PRID_COMP_ALCHEMY:
cea7e2df 908 cpu_probe_alchemy(c, cpu);
1da177e4
LT		 909 break;
910 case PRID_COMP_SIBYTE:
cea7e2df 911 cpu_probe_sibyte(c, cpu);
1da177e4 912 break;
1c0c13eb 913 case PRID_COMP_BROADCOM:
cea7e2df 914 cpu_probe_broadcom(c, cpu);
1c0c13eb 915 break;
1da177e4 916 case PRID_COMP_SANDCRAFT:
cea7e2df 917 cpu_probe_sandcraft(c, cpu);
1da177e4 918 break;
a92b0588 919 case PRID_COMP_NXP:
cea7e2df 920 cpu_probe_nxp(c, cpu);
a3dddd56 921 break;
0dd4781b
DD		 922 case PRID_COMP_CAVIUM:
923 cpu_probe_cavium(c, cpu);
924 break;
1da177e4 925 }
dec8b1ca 926
cea7e2df
RB		 927 BUG_ON(!__cpu_name[cpu]);
928 BUG_ON(c->cputype == CPU_UNKNOWN);
929
dec8b1ca
FBH		 930 /*
931 * Platform code can force the cpu type to optimize code
932 * generation. In that case be sure the cpu type is correctly
933 * manually setup otherwise it could trigger some nasty bugs.
934 */
935 BUG_ON(current_cpu_type() != c->cputype);
936
4194318c 937 if (c->options & MIPS_CPU_FPU) {
1da177e4 938 c->fpu_id = cpu_get_fpu_id();
4194318c 939
e7958bb9 940 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
b4672d37
RB		 941 c->isa_level == MIPS_CPU_ISA_M32R2 ||
942 c->isa_level == MIPS_CPU_ISA_M64R1 ||
943 c->isa_level == MIPS_CPU_ISA_M64R2) {
4194318c
RB		 944 if (c->fpu_id & MIPS_FPIR_3D)
945 c->ases |= MIPS_ASE_MIPS3D;
946 }
947 }
9966db25 948
f6771dbb
RB		 949 if (cpu_has_mips_r2)
950 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
951 else
952 c->srsets = 1;
1da177e4
LT		 953}
954
234fcd14 955__cpuinit void cpu_report(void)
1da177e4
LT		 956{
957 struct cpuinfo_mips *c = &current_cpu_data;
958
9966db25
RB		 959 printk(KERN_INFO "CPU revision is: %08x (%s)\n",
960 c->processor_id, cpu_name_string());
1da177e4 961 if (c->options & MIPS_CPU_FPU)
9966db25 962 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1da177e4 963}
Linux 6.x block layer and io_uring tree(s)