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Merge branch 'next' into for-linus
[linux-2.6-block.git] / arch / mips / kernel / cpu-probe.c
CommitLineData
1da177e4
LT		 1/*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
010b853b 5 * Copyright (C) 1994 - 2006 Ralf Baechle
4194318c 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
4194318c 7 * Copyright (C) 2001, 2004 MIPS Inc.
1da177e4
LT		 8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
1da177e4
LT		 14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/ptrace.h>
17#include <linux/stddef.h>
18
5759906c 19#include <asm/bugs.h>
1da177e4
LT		 20#include <asm/cpu.h>
21#include <asm/fpu.h>
22#include <asm/mipsregs.h>
23#include <asm/system.h>
654f57bf 24#include <asm/watch.h>
1da177e4
LT		 25
26/*
27 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
28 * the implementation of the "wait" feature differs between CPU families. This
29 * points to the function that implements CPU specific wait.
30 * The wait instruction stops the pipeline and reduces the power consumption of
31 * the CPU very much.
32 */
33void (*cpu_wait)(void) = NULL;
34
35static void r3081_wait(void)
36{
37 unsigned long cfg = read_c0_conf();
38 write_c0_conf(cfg | R30XX_CONF_HALT);
39}
40
41static void r39xx_wait(void)
42{
60a6c377
AN		 43 local_irq_disable();
44 if (!need_resched())
45 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
46 local_irq_enable();
1da177e4
LT		 47}
48
c65a5480 49extern void r4k_wait(void);
60a6c377
AN		 50
51/*
52 * This variant is preferable as it allows testing need_resched and going to
53 * sleep depending on the outcome atomically. Unfortunately the "It is
54 * implementation-dependent whether the pipeline restarts when a non-enabled
55 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
56 * using this version a gamble.
57 */
8531a35e 58void r4k_wait_irqoff(void)
60a6c377
AN		 59{
60 local_irq_disable();
61 if (!need_resched())
8531a35e
KK		 62 __asm__(" .set push \n"
63 " .set mips3 \n"
60a6c377 64 " wait \n"
8531a35e 65 " .set pop \n");
60a6c377 66 local_irq_enable();
8531a35e
KK		 67 __asm__(" .globl __pastwait \n"
68 "__pastwait: \n");
69 return;
1da177e4
LT		 70}
71
5a812999
RB		 72/*
73 * The RM7000 variant has to handle erratum 38. The workaround is to not
74 * have any pending stores when the WAIT instruction is executed.
75 */
76static void rm7k_wait_irqoff(void)
77{
78 local_irq_disable();
79 if (!need_resched())
80 __asm__(
81 " .set push \n"
82 " .set mips3 \n"
83 " .set noat \n"
84 " mfc0 $1, $12 \n"
85 " sync \n"
86 " mtc0 $1, $12 # stalls until W stage \n"
87 " wait \n"
88 " mtc0 $1, $12 # stalls until W stage \n"
89 " .set pop \n");
90 local_irq_enable();
91}
92
494900af
PP		 93/* The Au1xxx wait is available only if using 32khz counter or
94 * external timer source, but specifically not CP0 Counter. */
fe359bf5 95int allow_au1k_wait;
10f650db 96
494900af 97static void au1k_wait(void)
1da177e4 98{
0c694de1
ML		 99 if (!allow_au1k_wait)
100 return;
101
1da177e4 102 /* using the wait instruction makes CP0 counter unusable */
60a6c377
AN		 103 __asm__(" .set mips3 \n"
104 " cache 0x14, 0(%0) \n"
105 " cache 0x14, 32(%0) \n"
106 " sync \n"
107 " nop \n"
108 " wait \n"
109 " nop \n"
110 " nop \n"
111 " nop \n"
112 " nop \n"
113 " .set mips0 \n"
10f650db 114 : : "r" (au1k_wait));
1da177e4
LT		 115}
116
55d04dff
RB		 117static int __initdata nowait = 0;
118
f49a747c 119static int __init wait_disable(char *s)
55d04dff
RB		 120{
121 nowait = 1;
122
123 return 1;
124}
125
126__setup("nowait", wait_disable);
127
c65a5480 128void __init check_wait(void)
1da177e4
LT		 129{
130 struct cpuinfo_mips *c = &current_cpu_data;
131
55d04dff 132 if (nowait) {
c2379230 133 printk("Wait instruction disabled.\n");
55d04dff
RB		 134 return;
135 }
136
1da177e4
LT		 137 switch (c->cputype) {
138 case CPU_R3081:
139 case CPU_R3081E:
140 cpu_wait = r3081_wait;
1da177e4
LT		 141 break;
142 case CPU_TX3927:
143 cpu_wait = r39xx_wait;
1da177e4
LT		 144 break;
145 case CPU_R4200:
146/* case CPU_R4300: */
147 case CPU_R4600:
148 case CPU_R4640:
149 case CPU_R4650:
150 case CPU_R4700:
151 case CPU_R5000:
a644b277 152 case CPU_R5500:
1da177e4 153 case CPU_NEVADA:
1da177e4
LT		 154 case CPU_4KC:
155 case CPU_4KEC:
156 case CPU_4KSC:
157 case CPU_5KC:
1da177e4 158 case CPU_25KF:
4b3e975e 159 case CPU_PR4450:
1c0c13eb 160 case CPU_BCM3302:
0dd4781b 161 case CPU_CAVIUM_OCTEON:
4b3e975e
RB		 162 cpu_wait = r4k_wait;
163 break;
164
5a812999
RB		 165 case CPU_RM7000:
166 cpu_wait = rm7k_wait_irqoff;
167 break;
168
4b3e975e 169 case CPU_24K:
bbc7f22f 170 case CPU_34K:
39b8d525 171 case CPU_1004K:
4b3e975e
RB		 172 cpu_wait = r4k_wait;
173 if (read_c0_config7() & MIPS_CONF7_WII)
174 cpu_wait = r4k_wait_irqoff;
175 break;
176
c620953c 177 case CPU_74K:
1da177e4 178 cpu_wait = r4k_wait;
4b3e975e
RB		 179 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
180 cpu_wait = r4k_wait_irqoff;
1da177e4 181 break;
4b3e975e 182
60a6c377
AN		 183 case CPU_TX49XX:
184 cpu_wait = r4k_wait_irqoff;
60a6c377 185 break;
270717a8 186 case CPU_ALCHEMY:
0c694de1 187 cpu_wait = au1k_wait;
1da177e4 188 break;
c8eae71d
RB		 189 case CPU_20KC:
190 /*
191 * WAIT on Rev1.0 has E1, E2, E3 and E16.
192 * WAIT on Rev2.0 and Rev3.0 has E16.
193 * Rev3.1 WAIT is nop, why bother
194 */
195 if ((c->processor_id & 0xff) <= 0x64)
196 break;
197
50da469a
RB		 198 /*
199 * Another rev is incremeting c0_count at a reduced clock
200 * rate while in WAIT mode. So we basically have the choice
201 * between using the cp0 timer as clocksource or avoiding
202 * the WAIT instruction. Until more details are known,
203 * disable the use of WAIT for 20Kc entirely.
204 cpu_wait = r4k_wait;
205 */
c8eae71d 206 break;
441ee341 207 case CPU_RM9000:
c2379230 208 if ((c->processor_id & 0x00ff) >= 0x40)
441ee341 209 cpu_wait = r4k_wait;
441ee341 210 break;
1da177e4 211 default:
1da177e4
LT		 212 break;
213 }
214}
215
9267a30d
MSJ		 216static inline void check_errata(void)
217{
218 struct cpuinfo_mips *c = &current_cpu_data;
219
220 switch (c->cputype) {
221 case CPU_34K:
222 /*
223 * Erratum "RPS May Cause Incorrect Instruction Execution"
224 * This code only handles VPE0, any SMP/SMTC/RTOS code
225 * making use of VPE1 will be responsable for that VPE.
226 */
227 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
228 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
229 break;
230 default:
231 break;
232 }
233}
234
1da177e4
LT		 235void __init check_bugs32(void)
236{
9267a30d 237 check_errata();
1da177e4
LT		 238}
239
240/*
241 * Probe whether cpu has config register by trying to play with
242 * alternate cache bit and see whether it matters.
243 * It's used by cpu_probe to distinguish between R3000A and R3081.
244 */
245static inline int cpu_has_confreg(void)
246{
247#ifdef CONFIG_CPU_R3000
248 extern unsigned long r3k_cache_size(unsigned long);
249 unsigned long size1, size2;
250 unsigned long cfg = read_c0_conf();
251
252 size1 = r3k_cache_size(ST0_ISC);
253 write_c0_conf(cfg ^ R30XX_CONF_AC);
254 size2 = r3k_cache_size(ST0_ISC);
255 write_c0_conf(cfg);
256 return size1 != size2;
257#else
258 return 0;
259#endif
260}
261
262/*
263 * Get the FPU Implementation/Revision.
264 */
265static inline unsigned long cpu_get_fpu_id(void)
266{
267 unsigned long tmp, fpu_id;
268
269 tmp = read_c0_status();
270 __enable_fpu();
271 fpu_id = read_32bit_cp1_register(CP1_REVISION);
272 write_c0_status(tmp);
273 return fpu_id;
274}
275
276/*
277 * Check the CPU has an FPU the official way.
278 */
279static inline int __cpu_has_fpu(void)
280{
281 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
282}
283
02cf2119 284#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1da177e4
LT		 285 | MIPS_CPU_COUNTER)
286
cea7e2df 287static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4
LT		 288{
289 switch (c->processor_id & 0xff00) {
290 case PRID_IMP_R2000:
291 c->cputype = CPU_R2000;
cea7e2df 292 __cpu_name[cpu] = "R2000";
1da177e4 293 c->isa_level = MIPS_CPU_ISA_I;
02cf2119
RB		 294 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
295 MIPS_CPU_NOFPUEX;
1da177e4
LT		 296 if (__cpu_has_fpu())
297 c->options |= MIPS_CPU_FPU;
298 c->tlbsize = 64;
299 break;
300 case PRID_IMP_R3000:
cea7e2df
RB		 301 if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
302 if (cpu_has_confreg()) {
1da177e4 303 c->cputype = CPU_R3081E;
cea7e2df
RB		 304 __cpu_name[cpu] = "R3081";
305 } else {
1da177e4 306 c->cputype = CPU_R3000A;
cea7e2df
RB		 307 __cpu_name[cpu] = "R3000A";
308 }
309 break;
310 } else {
1da177e4 311 c->cputype = CPU_R3000;
cea7e2df
RB		 312 __cpu_name[cpu] = "R3000";
313 }
1da177e4 314 c->isa_level = MIPS_CPU_ISA_I;
02cf2119
RB		 315 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
316 MIPS_CPU_NOFPUEX;
1da177e4
LT		 317 if (__cpu_has_fpu())
318 c->options |= MIPS_CPU_FPU;
319 c->tlbsize = 64;
320 break;
321 case PRID_IMP_R4000:
322 if (read_c0_config() & CONF_SC) {
cea7e2df 323 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
1da177e4 324 c->cputype = CPU_R4400PC;
cea7e2df
RB		 325 __cpu_name[cpu] = "R4400PC";
326 } else {
1da177e4 327 c->cputype = CPU_R4000PC;
cea7e2df
RB		 328 __cpu_name[cpu] = "R4000PC";
329 }
1da177e4 330 } else {
cea7e2df 331 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
1da177e4 332 c->cputype = CPU_R4400SC;
cea7e2df
RB		 333 __cpu_name[cpu] = "R4400SC";
334 } else {
1da177e4 335 c->cputype = CPU_R4000SC;
cea7e2df
RB		 336 __cpu_name[cpu] = "R4000SC";
337 }
1da177e4
LT		 338 }
339
340 c->isa_level = MIPS_CPU_ISA_III;
341 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
342 MIPS_CPU_WATCH | MIPS_CPU_VCE |
343 MIPS_CPU_LLSC;
344 c->tlbsize = 48;
345 break;
346 case PRID_IMP_VR41XX:
347 switch (c->processor_id & 0xf0) {
1da177e4
LT		 348 case PRID_REV_VR4111:
349 c->cputype = CPU_VR4111;
cea7e2df 350 __cpu_name[cpu] = "NEC VR4111";
1da177e4 351 break;
1da177e4
LT		 352 case PRID_REV_VR4121:
353 c->cputype = CPU_VR4121;
cea7e2df 354 __cpu_name[cpu] = "NEC VR4121";
1da177e4
LT		 355 break;
356 case PRID_REV_VR4122:
cea7e2df 357 if ((c->processor_id & 0xf) < 0x3) {
1da177e4 358 c->cputype = CPU_VR4122;
cea7e2df
RB		 359 __cpu_name[cpu] = "NEC VR4122";
360 } else {
1da177e4 361 c->cputype = CPU_VR4181A;
cea7e2df
RB		 362 __cpu_name[cpu] = "NEC VR4181A";
363 }
1da177e4
LT		 364 break;
365 case PRID_REV_VR4130:
cea7e2df 366 if ((c->processor_id & 0xf) < 0x4) {
1da177e4 367 c->cputype = CPU_VR4131;
cea7e2df
RB		 368 __cpu_name[cpu] = "NEC VR4131";
369 } else {
1da177e4 370 c->cputype = CPU_VR4133;
cea7e2df
RB		 371 __cpu_name[cpu] = "NEC VR4133";
372 }
1da177e4
LT		 373 break;
374 default:
375 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
376 c->cputype = CPU_VR41XX;
cea7e2df 377 __cpu_name[cpu] = "NEC Vr41xx";
1da177e4
LT		 378 break;
379 }
380 c->isa_level = MIPS_CPU_ISA_III;
381 c->options = R4K_OPTS;
382 c->tlbsize = 32;
383 break;
384 case PRID_IMP_R4300:
385 c->cputype = CPU_R4300;
cea7e2df 386 __cpu_name[cpu] = "R4300";
1da177e4
LT		 387 c->isa_level = MIPS_CPU_ISA_III;
388 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
389 MIPS_CPU_LLSC;
390 c->tlbsize = 32;
391 break;
392 case PRID_IMP_R4600:
393 c->cputype = CPU_R4600;
cea7e2df 394 __cpu_name[cpu] = "R4600";
1da177e4 395 c->isa_level = MIPS_CPU_ISA_III;
075e7502
TS		 396 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
397 MIPS_CPU_LLSC;
1da177e4
LT		 398 c->tlbsize = 48;
399 break;
400 #if 0
401 case PRID_IMP_R4650:
402 /*
403 * This processor doesn't have an MMU, so it's not
404 * "real easy" to run Linux on it. It is left purely
405 * for documentation. Commented out because it shares
406 * it's c0_prid id number with the TX3900.
407 */
a3dddd56 408 c->cputype = CPU_R4650;
cea7e2df 409 __cpu_name[cpu] = "R4650";
1da177e4
LT		 410 c->isa_level = MIPS_CPU_ISA_III;
411 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
412 c->tlbsize = 48;
413 break;
414 #endif
415 case PRID_IMP_TX39:
416 c->isa_level = MIPS_CPU_ISA_I;
02cf2119 417 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1da177e4
LT		 418
419 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
420 c->cputype = CPU_TX3927;
cea7e2df 421 __cpu_name[cpu] = "TX3927";
1da177e4
LT		 422 c->tlbsize = 64;
423 } else {
424 switch (c->processor_id & 0xff) {
425 case PRID_REV_TX3912:
426 c->cputype = CPU_TX3912;
cea7e2df 427 __cpu_name[cpu] = "TX3912";
1da177e4
LT		 428 c->tlbsize = 32;
429 break;
430 case PRID_REV_TX3922:
431 c->cputype = CPU_TX3922;
cea7e2df 432 __cpu_name[cpu] = "TX3922";
1da177e4
LT		 433 c->tlbsize = 64;
434 break;
1da177e4
LT		 435 }
436 }
437 break;
438 case PRID_IMP_R4700:
439 c->cputype = CPU_R4700;
cea7e2df 440 __cpu_name[cpu] = "R4700";
1da177e4
LT		 441 c->isa_level = MIPS_CPU_ISA_III;
442 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
443 MIPS_CPU_LLSC;
444 c->tlbsize = 48;
445 break;
446 case PRID_IMP_TX49:
447 c->cputype = CPU_TX49XX;
cea7e2df 448 __cpu_name[cpu] = "R49XX";
1da177e4
LT		 449 c->isa_level = MIPS_CPU_ISA_III;
450 c->options = R4K_OPTS | MIPS_CPU_LLSC;
451 if (!(c->processor_id & 0x08))
452 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
453 c->tlbsize = 48;
454 break;
455 case PRID_IMP_R5000:
456 c->cputype = CPU_R5000;
cea7e2df 457 __cpu_name[cpu] = "R5000";
1da177e4
LT		 458 c->isa_level = MIPS_CPU_ISA_IV;
459 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
460 MIPS_CPU_LLSC;
461 c->tlbsize = 48;
462 break;
463 case PRID_IMP_R5432:
464 c->cputype = CPU_R5432;
cea7e2df 465 __cpu_name[cpu] = "R5432";
1da177e4
LT		 466 c->isa_level = MIPS_CPU_ISA_IV;
467 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
468 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
469 c->tlbsize = 48;
470 break;
471 case PRID_IMP_R5500:
472 c->cputype = CPU_R5500;
cea7e2df 473 __cpu_name[cpu] = "R5500";
1da177e4
LT		 474 c->isa_level = MIPS_CPU_ISA_IV;
475 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
476 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
477 c->tlbsize = 48;
478 break;
479 case PRID_IMP_NEVADA:
480 c->cputype = CPU_NEVADA;
cea7e2df 481 __cpu_name[cpu] = "Nevada";
1da177e4
LT		 482 c->isa_level = MIPS_CPU_ISA_IV;
483 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
484 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
485 c->tlbsize = 48;
486 break;
487 case PRID_IMP_R6000:
488 c->cputype = CPU_R6000;
cea7e2df 489 __cpu_name[cpu] = "R6000";
1da177e4
LT		 490 c->isa_level = MIPS_CPU_ISA_II;
491 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
492 MIPS_CPU_LLSC;
493 c->tlbsize = 32;
494 break;
495 case PRID_IMP_R6000A:
496 c->cputype = CPU_R6000A;
cea7e2df 497 __cpu_name[cpu] = "R6000A";
1da177e4
LT		 498 c->isa_level = MIPS_CPU_ISA_II;
499 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
500 MIPS_CPU_LLSC;
501 c->tlbsize = 32;
502 break;
503 case PRID_IMP_RM7000:
504 c->cputype = CPU_RM7000;
cea7e2df 505 __cpu_name[cpu] = "RM7000";
1da177e4
LT		 506 c->isa_level = MIPS_CPU_ISA_IV;
507 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
508 MIPS_CPU_LLSC;
509 /*
510 * Undocumented RM7000: Bit 29 in the info register of
511 * the RM7000 v2.0 indicates if the TLB has 48 or 64
512 * entries.
513 *
514 * 29 1 => 64 entry JTLB
515 * 0 => 48 entry JTLB
516 */
517 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
518 break;
519 case PRID_IMP_RM9000:
520 c->cputype = CPU_RM9000;
cea7e2df 521 __cpu_name[cpu] = "RM9000";
1da177e4
LT		 522 c->isa_level = MIPS_CPU_ISA_IV;
523 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
524 MIPS_CPU_LLSC;
525 /*
526 * Bit 29 in the info register of the RM9000
527 * indicates if the TLB has 48 or 64 entries.
528 *
529 * 29 1 => 64 entry JTLB
530 * 0 => 48 entry JTLB
531 */
532 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
533 break;
534 case PRID_IMP_R8000:
535 c->cputype = CPU_R8000;
cea7e2df 536 __cpu_name[cpu] = "RM8000";
1da177e4
LT		 537 c->isa_level = MIPS_CPU_ISA_IV;
538 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
539 MIPS_CPU_FPU | MIPS_CPU_32FPR |
540 MIPS_CPU_LLSC;
541 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
542 break;
543 case PRID_IMP_R10000:
544 c->cputype = CPU_R10000;
cea7e2df 545 __cpu_name[cpu] = "R10000";
1da177e4 546 c->isa_level = MIPS_CPU_ISA_IV;
8b36612a 547 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1da177e4
LT		 548 MIPS_CPU_FPU | MIPS_CPU_32FPR |
549 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
550 MIPS_CPU_LLSC;
551 c->tlbsize = 64;
552 break;
553 case PRID_IMP_R12000:
554 c->cputype = CPU_R12000;
cea7e2df 555 __cpu_name[cpu] = "R12000";
1da177e4 556 c->isa_level = MIPS_CPU_ISA_IV;
8b36612a 557 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1da177e4
LT		 558 MIPS_CPU_FPU | MIPS_CPU_32FPR |
559 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
560 MIPS_CPU_LLSC;
561 c->tlbsize = 64;
562 break;
44d921b2
K		 563 case PRID_IMP_R14000:
564 c->cputype = CPU_R14000;
cea7e2df 565 __cpu_name[cpu] = "R14000";
44d921b2
K		 566 c->isa_level = MIPS_CPU_ISA_IV;
567 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
568 MIPS_CPU_FPU | MIPS_CPU_32FPR |
569 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
570 MIPS_CPU_LLSC;
571 c->tlbsize = 64;
572 break;
2a21c730
FZ		 573 case PRID_IMP_LOONGSON2:
574 c->cputype = CPU_LOONGSON2;
cea7e2df 575 __cpu_name[cpu] = "ICT Loongson-2";
2a21c730
FZ		 576 c->isa_level = MIPS_CPU_ISA_III;
577 c->options = R4K_OPTS |
578 MIPS_CPU_FPU | MIPS_CPU_LLSC |
579 MIPS_CPU_32FPR;
580 c->tlbsize = 64;
581 break;
1da177e4
LT		 582 }
583}
584
234fcd14 585static char unknown_isa[] __cpuinitdata = KERN_ERR \
b4672d37
RB		 586 "Unsupported ISA type, c0.config0: %d.";
587
4194318c 588static inline unsigned int decode_config0(struct cpuinfo_mips *c)
1da177e4 589{
4194318c
RB		 590 unsigned int config0;
591 int isa;
1da177e4 592
4194318c
RB		 593 config0 = read_c0_config();
594
595 if (((config0 & MIPS_CONF_MT) >> 7) == 1)
02cf2119 596 c->options |= MIPS_CPU_TLB;
4194318c
RB		 597 isa = (config0 & MIPS_CONF_AT) >> 13;
598 switch (isa) {
599 case 0:
3a01c49a 600 switch ((config0 & MIPS_CONF_AR) >> 10) {
b4672d37
RB		 601 case 0:
602 c->isa_level = MIPS_CPU_ISA_M32R1;
603 break;
604 case 1:
605 c->isa_level = MIPS_CPU_ISA_M32R2;
606 break;
607 default:
608 goto unknown;
609 }
4194318c
RB		 610 break;
611 case 2:
3a01c49a 612 switch ((config0 & MIPS_CONF_AR) >> 10) {
b4672d37
RB		 613 case 0:
614 c->isa_level = MIPS_CPU_ISA_M64R1;
615 break;
616 case 1:
617 c->isa_level = MIPS_CPU_ISA_M64R2;
618 break;
619 default:
620 goto unknown;
621 }
4194318c
RB		 622 break;
623 default:
b4672d37 624 goto unknown;
4194318c
RB		 625 }
626
627 return config0 & MIPS_CONF_M;
b4672d37
RB		 628
629unknown:
630 panic(unknown_isa, config0);
4194318c
RB		 631}
632
633static inline unsigned int decode_config1(struct cpuinfo_mips *c)
634{
635 unsigned int config1;
1da177e4 636
1da177e4 637 config1 = read_c0_config1();
4194318c
RB		 638
639 if (config1 & MIPS_CONF1_MD)
640 c->ases |= MIPS_ASE_MDMX;
641 if (config1 & MIPS_CONF1_WR)
1da177e4 642 c->options |= MIPS_CPU_WATCH;
4194318c
RB		 643 if (config1 & MIPS_CONF1_CA)
644 c->ases |= MIPS_ASE_MIPS16;
645 if (config1 & MIPS_CONF1_EP)
1da177e4 646 c->options |= MIPS_CPU_EJTAG;
4194318c 647 if (config1 & MIPS_CONF1_FP) {
1da177e4
LT		 648 c->options |= MIPS_CPU_FPU;
649 c->options |= MIPS_CPU_32FPR;
650 }
4194318c
RB		 651 if (cpu_has_tlb)
652 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
653
654 return config1 & MIPS_CONF_M;
655}
656
657static inline unsigned int decode_config2(struct cpuinfo_mips *c)
658{
659 unsigned int config2;
660
661 config2 = read_c0_config2();
662
663 if (config2 & MIPS_CONF2_SL)
664 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
665
666 return config2 & MIPS_CONF_M;
667}
668
669static inline unsigned int decode_config3(struct cpuinfo_mips *c)
670{
671 unsigned int config3;
672
673 config3 = read_c0_config3();
674
675 if (config3 & MIPS_CONF3_SM)
676 c->ases |= MIPS_ASE_SMARTMIPS;
e50c0a8f
RB		 677 if (config3 & MIPS_CONF3_DSP)
678 c->ases |= MIPS_ASE_DSP;
8f40611d
RB		 679 if (config3 & MIPS_CONF3_VINT)
680 c->options |= MIPS_CPU_VINT;
681 if (config3 & MIPS_CONF3_VEIC)
682 c->options |= MIPS_CPU_VEIC;
683 if (config3 & MIPS_CONF3_MT)
e0daad44 684 c->ases |= MIPS_ASE_MIPSMT;
a3692020
RB		 685 if (config3 & MIPS_CONF3_ULRI)
686 c->options |= MIPS_CPU_ULRI;
4194318c
RB		 687
688 return config3 & MIPS_CONF_M;
689}
690
234fcd14 691static void __cpuinit decode_configs(struct cpuinfo_mips *c)
4194318c 692{
558ce124
RB		 693 int ok;
694
4194318c 695 /* MIPS32 or MIPS64 compliant CPU. */
02cf2119
RB		 696 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
697 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
4194318c 698
1da177e4
LT		 699 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
700
558ce124
RB		 701 ok = decode_config0(c); /* Read Config registers. */
702 BUG_ON(!ok); /* Arch spec violation! */
703 if (ok)
704 ok = decode_config1(c);
705 if (ok)
706 ok = decode_config2(c);
707 if (ok)
708 ok = decode_config3(c);
709
710 mips_probe_watch_registers(c);
1da177e4
LT		 711}
712
0b6d497f
CD		 713#ifdef CONFIG_CPU_MIPSR2
714extern void spram_config(void);
715#else
716static inline void spram_config(void) {}
717#endif
718
cea7e2df 719static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 720{
4194318c 721 decode_configs(c);
1da177e4
LT		 722 switch (c->processor_id & 0xff00) {
723 case PRID_IMP_4KC:
724 c->cputype = CPU_4KC;
cea7e2df 725 __cpu_name[cpu] = "MIPS 4Kc";
1da177e4
LT		 726 break;
727 case PRID_IMP_4KEC:
728 c->cputype = CPU_4KEC;
cea7e2df 729 __cpu_name[cpu] = "MIPS 4KEc";
1da177e4 730 break;
2b07bd02
RB		 731 case PRID_IMP_4KECR2:
732 c->cputype = CPU_4KEC;
cea7e2df 733 __cpu_name[cpu] = "MIPS 4KEc";
2b07bd02 734 break;
1da177e4 735 case PRID_IMP_4KSC:
8afcb5d8 736 case PRID_IMP_4KSD:
1da177e4 737 c->cputype = CPU_4KSC;
cea7e2df 738 __cpu_name[cpu] = "MIPS 4KSc";
1da177e4
LT		 739 break;
740 case PRID_IMP_5KC:
741 c->cputype = CPU_5KC;
cea7e2df 742 __cpu_name[cpu] = "MIPS 5Kc";
1da177e4
LT		 743 break;
744 case PRID_IMP_20KC:
745 c->cputype = CPU_20KC;
cea7e2df 746 __cpu_name[cpu] = "MIPS 20Kc";
1da177e4
LT		 747 break;
748 case PRID_IMP_24K:
e50c0a8f 749 case PRID_IMP_24KE:
1da177e4 750 c->cputype = CPU_24K;
cea7e2df 751 __cpu_name[cpu] = "MIPS 24Kc";
1da177e4
LT		 752 break;
753 case PRID_IMP_25KF:
754 c->cputype = CPU_25KF;
cea7e2df 755 __cpu_name[cpu] = "MIPS 25Kc";
1da177e4 756 break;
bbc7f22f
RB		 757 case PRID_IMP_34K:
758 c->cputype = CPU_34K;
cea7e2df 759 __cpu_name[cpu] = "MIPS 34Kc";
bbc7f22f 760 break;
c620953c
CD		 761 case PRID_IMP_74K:
762 c->cputype = CPU_74K;
cea7e2df 763 __cpu_name[cpu] = "MIPS 74Kc";
c620953c 764 break;
39b8d525
RB		 765 case PRID_IMP_1004K:
766 c->cputype = CPU_1004K;
cea7e2df 767 __cpu_name[cpu] = "MIPS 1004Kc";
39b8d525 768 break;
1da177e4 769 }
0b6d497f
CD		 770
771 spram_config();
1da177e4
LT		 772}
773
cea7e2df 774static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 775{
4194318c 776 decode_configs(c);
1da177e4
LT		 777 switch (c->processor_id & 0xff00) {
778 case PRID_IMP_AU1_REV1:
779 case PRID_IMP_AU1_REV2:
270717a8 780 c->cputype = CPU_ALCHEMY;
1da177e4
LT		 781 switch ((c->processor_id >> 24) & 0xff) {
782 case 0:
cea7e2df 783 __cpu_name[cpu] = "Au1000";
1da177e4
LT		 784 break;
785 case 1:
cea7e2df 786 __cpu_name[cpu] = "Au1500";
1da177e4
LT		 787 break;
788 case 2:
cea7e2df 789 __cpu_name[cpu] = "Au1100";
1da177e4
LT		 790 break;
791 case 3:
cea7e2df 792 __cpu_name[cpu] = "Au1550";
1da177e4 793 break;
e3ad1c23 794 case 4:
cea7e2df 795 __cpu_name[cpu] = "Au1200";
270717a8 796 if ((c->processor_id & 0xff) == 2)
cea7e2df 797 __cpu_name[cpu] = "Au1250";
237cfee1
ML		 798 break;
799 case 5:
cea7e2df 800 __cpu_name[cpu] = "Au1210";
e3ad1c23 801 break;
1da177e4 802 default:
270717a8 803 __cpu_name[cpu] = "Au1xxx";
1da177e4
LT		 804 break;
805 }
1da177e4
LT		 806 break;
807 }
808}
809
cea7e2df 810static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 811{
4194318c 812 decode_configs(c);
02cf2119 813
1da177e4
LT		 814 switch (c->processor_id & 0xff00) {
815 case PRID_IMP_SB1:
816 c->cputype = CPU_SB1;
cea7e2df 817 __cpu_name[cpu] = "SiByte SB1";
1da177e4 818 /* FPU in pass1 is known to have issues. */
aa32374a 819 if ((c->processor_id & 0xff) < 0x02)
010b853b 820 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1da177e4 821 break;
93ce2f52
AI		 822 case PRID_IMP_SB1A:
823 c->cputype = CPU_SB1A;
cea7e2df 824 __cpu_name[cpu] = "SiByte SB1A";
93ce2f52 825 break;
1da177e4
LT		 826 }
827}
828
cea7e2df 829static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1da177e4 830{
4194318c 831 decode_configs(c);
1da177e4
LT		 832 switch (c->processor_id & 0xff00) {
833 case PRID_IMP_SR71000:
834 c->cputype = CPU_SR71000;
cea7e2df 835 __cpu_name[cpu] = "Sandcraft SR71000";
1da177e4
LT		 836 c->scache.ways = 8;
837 c->tlbsize = 64;
838 break;
839 }
840}
841
cea7e2df 842static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
bdf21b18
PP		 843{
844 decode_configs(c);
845 switch (c->processor_id & 0xff00) {
846 case PRID_IMP_PR4450:
847 c->cputype = CPU_PR4450;
cea7e2df 848 __cpu_name[cpu] = "Philips PR4450";
e7958bb9 849 c->isa_level = MIPS_CPU_ISA_M32R1;
bdf21b18 850 break;
bdf21b18
PP		 851 }
852}
853
cea7e2df 854static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1c0c13eb
AJ		 855{
856 decode_configs(c);
857 switch (c->processor_id & 0xff00) {
858 case PRID_IMP_BCM3302:
859 c->cputype = CPU_BCM3302;
cea7e2df 860 __cpu_name[cpu] = "Broadcom BCM3302";
1c0c13eb
AJ		 861 break;
862 case PRID_IMP_BCM4710:
863 c->cputype = CPU_BCM4710;
cea7e2df 864 __cpu_name[cpu] = "Broadcom BCM4710";
1c0c13eb
AJ		 865 break;
866 }
867}
868
0dd4781b
DD		 869static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
870{
871 decode_configs(c);
872 switch (c->processor_id & 0xff00) {
873 case PRID_IMP_CAVIUM_CN38XX:
874 case PRID_IMP_CAVIUM_CN31XX:
875 case PRID_IMP_CAVIUM_CN30XX:
876 case PRID_IMP_CAVIUM_CN58XX:
877 case PRID_IMP_CAVIUM_CN56XX:
878 case PRID_IMP_CAVIUM_CN50XX:
879 case PRID_IMP_CAVIUM_CN52XX:
880 c->cputype = CPU_CAVIUM_OCTEON;
881 __cpu_name[cpu] = "Cavium Octeon";
882 break;
883 default:
884 printk(KERN_INFO "Unknown Octeon chip!\n");
885 c->cputype = CPU_UNKNOWN;
886 break;
887 }
888}
889
9966db25
RB		 890const char *__cpu_name[NR_CPUS];
891
234fcd14 892__cpuinit void cpu_probe(void)
1da177e4
LT		 893{
894 struct cpuinfo_mips *c = &current_cpu_data;
9966db25 895 unsigned int cpu = smp_processor_id();
1da177e4
LT		 896
897 c->processor_id = PRID_IMP_UNKNOWN;
898 c->fpu_id = FPIR_IMP_NONE;
899 c->cputype = CPU_UNKNOWN;
900
901 c->processor_id = read_c0_prid();
902 switch (c->processor_id & 0xff0000) {
903 case PRID_COMP_LEGACY:
cea7e2df 904 cpu_probe_legacy(c, cpu);
1da177e4
LT		 905 break;
906 case PRID_COMP_MIPS:
cea7e2df 907 cpu_probe_mips(c, cpu);
1da177e4
LT		 908 break;
909 case PRID_COMP_ALCHEMY:
cea7e2df 910 cpu_probe_alchemy(c, cpu);
1da177e4
LT		 911 break;
912 case PRID_COMP_SIBYTE:
cea7e2df 913 cpu_probe_sibyte(c, cpu);
1da177e4 914 break;
1c0c13eb 915 case PRID_COMP_BROADCOM:
cea7e2df 916 cpu_probe_broadcom(c, cpu);
1c0c13eb 917 break;
1da177e4 918 case PRID_COMP_SANDCRAFT:
cea7e2df 919 cpu_probe_sandcraft(c, cpu);
1da177e4 920 break;
a92b0588 921 case PRID_COMP_NXP:
cea7e2df 922 cpu_probe_nxp(c, cpu);
a3dddd56 923 break;
0dd4781b
DD		 924 case PRID_COMP_CAVIUM:
925 cpu_probe_cavium(c, cpu);
926 break;
1da177e4 927 }
dec8b1ca 928
cea7e2df
RB		 929 BUG_ON(!__cpu_name[cpu]);
930 BUG_ON(c->cputype == CPU_UNKNOWN);
931
dec8b1ca
FBH		 932 /*
933 * Platform code can force the cpu type to optimize code
934 * generation. In that case be sure the cpu type is correctly
935 * manually setup otherwise it could trigger some nasty bugs.
936 */
937 BUG_ON(current_cpu_type() != c->cputype);
938
4194318c 939 if (c->options & MIPS_CPU_FPU) {
1da177e4 940 c->fpu_id = cpu_get_fpu_id();
4194318c 941
e7958bb9 942 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
b4672d37
RB		 943 c->isa_level == MIPS_CPU_ISA_M32R2 ||
944 c->isa_level == MIPS_CPU_ISA_M64R1 ||
945 c->isa_level == MIPS_CPU_ISA_M64R2) {
4194318c
RB		 946 if (c->fpu_id & MIPS_FPIR_3D)
947 c->ases |= MIPS_ASE_MIPS3D;
948 }
949 }
9966db25 950
f6771dbb
RB		 951 if (cpu_has_mips_r2)
952 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
953 else
954 c->srsets = 1;
1da177e4
LT		 955}
956
234fcd14 957__cpuinit void cpu_report(void)
1da177e4
LT		 958{
959 struct cpuinfo_mips *c = &current_cpu_data;
960
9966db25
RB		 961 printk(KERN_INFO "CPU revision is: %08x (%s)\n",
962 c->processor_id, cpu_name_string());
1da177e4 963 if (c->options & MIPS_CPU_FPU)
9966db25 964 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1da177e4 965}
Linux 6.x block layer and io_uring tree(s)