[linux-2.6-block.git] / arch / mips / kernel / cevt-smtc.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2007 MIPS Technologies, Inc.
 * Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org>
 * Copyright (C) 2008 Kevin D. Kissell, Paralogos sarl
 */
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/percpu.h>
#include <linux/smp.h>

#include <asm/smtc_ipi.h>
#include <asm/time.h>
#include <asm/cevt-r4k.h>

/*
 * Variant clock event timer support for SMTC on MIPS 34K, 1004K
 * or other MIPS MT cores.
 *
 * Notes on SMTC Support:
 *
 * SMTC has multiple microthread TCs pretending to be Linux CPUs.
 * But there's only one Count/Compare pair per VPE, and Compare
 * interrupts are taken opportunisitically by available TCs
 * bound to the VPE with the Count register.  The new timer
 * framework provides for global broadcasts, but we really
 * want VPE-level multicasts for best behavior. So instead
 * of invoking the high-level clock-event broadcast code,
 * this version of SMTC support uses the historical SMTC
 * multicast mechanisms "under the hood", appearing to the
 * generic clock layer as if the interrupts are per-CPU.
 *
 * The approach taken here is to maintain a set of NR_CPUS
 * virtual timers, and track which "CPU" needs to be alerted
 * at each event.
 *
 * It's unlikely that we'll see a MIPS MT core with more than
 * 2 VPEs, but we *know* that we won't need to handle more
 * VPEs than we have "CPUs".  So NCPUs arrays of NCPUs elements
 * is always going to be overkill, but always going to be enough.
 */

unsigned long smtc_nexttime[NR_CPUS][NR_CPUS];
static int smtc_nextinvpe[NR_CPUS];

/*
 * Timestamps stored are absolute values to be programmed
 * into Count register.  Valid timestamps will never be zero.
 * If a Zero Count value is actually calculated, it is converted
 * to be a 1, which will introduce 1 or two CPU cycles of error
 * roughly once every four billion events, which at 1000 HZ means
 * about once every 50 days.  If that's actually a problem, one
 * could alternate squashing 0 to 1 and to -1.
 */

#define MAKEVALID(x) (((x) == 0L) ? 1L : (x))
#define ISVALID(x) ((x) != 0L)

/*
 * Time comparison is subtle, as it's really truncated
 * modular arithmetic.
 */

#define IS_SOONER(a, b, reference) \
    (((a) - (unsigned long)(reference)) < ((b) - (unsigned long)(reference)))

/*
 * CATCHUP_INCREMENT, used when the function falls behind the counter.
 * Could be an increasing function instead of a constant;
 */

#define CATCHUP_INCREMENT 64

static int mips_next_event(unsigned long delta,
				struct clock_event_device *evt)
{
	unsigned long flags;
	unsigned int mtflags;
	unsigned long timestamp, reference, previous;
	unsigned long nextcomp = 0L;
	int vpe = current_cpu_data.vpe_id;
	int cpu = smp_processor_id();
	local_irq_save(flags);
	mtflags = dmt();

	/*
	 * Maintain the per-TC virtual timer
	 * and program the per-VPE shared Count register
	 * as appropriate here...
	 */
	reference = (unsigned long)read_c0_count();
	timestamp = MAKEVALID(reference + delta);
	/*
	 * To really model the clock, we have to catch the case
	 * where the current next-in-VPE timestamp is the old
	 * timestamp for the calling CPE, but the new value is
	 * in fact later.  In that case, we have to do a full
	 * scan and discover the new next-in-VPE CPU id and
	 * timestamp.
	 */
	previous = smtc_nexttime[vpe][cpu];
	if (cpu == smtc_nextinvpe[vpe] && ISVALID(previous)
	    && IS_SOONER(previous, timestamp, reference)) {
		int i;
		int soonest = cpu;

		/*
		 * Update timestamp array here, so that new
		 * value gets considered along with those of
		 * other virtual CPUs on the VPE.
		 */
		smtc_nexttime[vpe][cpu] = timestamp;
		for_each_online_cpu(i) {
			if (ISVALID(smtc_nexttime[vpe][i])
			    && IS_SOONER(smtc_nexttime[vpe][i],
				smtc_nexttime[vpe][soonest], reference)) {
				    soonest = i;
			}
		}
		smtc_nextinvpe[vpe] = soonest;
		nextcomp = smtc_nexttime[vpe][soonest];
	/*
	 * Otherwise, we don't have to process the whole array rank,
	 * we just have to see if the event horizon has gotten closer.
	 */
	} else {
		if (!ISVALID(smtc_nexttime[vpe][smtc_nextinvpe[vpe]]) ||
		    IS_SOONER(timestamp,
			smtc_nexttime[vpe][smtc_nextinvpe[vpe]], reference)) {
			    smtc_nextinvpe[vpe] = cpu;
			    nextcomp = timestamp;
		}
		/*
		 * Since next-in-VPE may me the same as the executing
		 * virtual CPU, we update the array *after* checking
		 * its value.
		 */
		smtc_nexttime[vpe][cpu] = timestamp;
	}

	/*
	 * It may be that, in fact, we don't need to update Compare,
	 * but if we do, we want to make sure we didn't fall into
	 * a crack just behind Count.
	 */
	if (ISVALID(nextcomp)) {
		write_c0_compare(nextcomp);
		ehb();
		/*
		 * We never return an error, we just make sure
		 * that we trigger the handlers as quickly as
		 * we can if we fell behind.
		 */
		while ((nextcomp - (unsigned long)read_c0_count())
			> (unsigned long)LONG_MAX) {
			nextcomp += CATCHUP_INCREMENT;
			write_c0_compare(nextcomp);
			ehb();
		}
	}
	emt(mtflags);
	local_irq_restore(flags);
	return 0;
}


void smtc_distribute_timer(int vpe)
{
	unsigned long flags;
	unsigned int mtflags;
	int cpu;
	struct clock_event_device *cd;
	unsigned long nextstamp = 0L;
	unsigned long reference;


repeat:
	for_each_online_cpu(cpu) {
	    /*
	     * Find virtual CPUs within the current VPE who have
	     * unserviced timer requests whose time is now past.
	     */
	    local_irq_save(flags);
	    mtflags = dmt();
	    if (cpu_data[cpu].vpe_id == vpe &&
		ISVALID(smtc_nexttime[vpe][cpu])) {
		reference = (unsigned long)read_c0_count();
		if ((smtc_nexttime[vpe][cpu] - reference)
			 > (unsigned long)LONG_MAX) {
			    smtc_nexttime[vpe][cpu] = 0L;
			    emt(mtflags);
			    local_irq_restore(flags);
			    /*
			     * We don't send IPIs to ourself.
			     */
			    if (cpu != smp_processor_id()) {
				smtc_send_ipi(cpu, SMTC_CLOCK_TICK, 0);
			    } else {
				cd = &per_cpu(mips_clockevent_device, cpu);
				cd->event_handler(cd);
			    }
		} else {
			/* Local to VPE but Valid Time not yet reached. */
			if (!ISVALID(nextstamp) ||
			    IS_SOONER(smtc_nexttime[vpe][cpu], nextstamp,
			    reference)) {
				smtc_nextinvpe[vpe] = cpu;
				nextstamp = smtc_nexttime[vpe][cpu];
			}
			emt(mtflags);
			local_irq_restore(flags);
		}
	    } else {
		emt(mtflags);
		local_irq_restore(flags);

	    }
	}
	/* Reprogram for interrupt at next soonest timestamp for VPE */
	if (ISVALID(nextstamp)) {
		write_c0_compare(nextstamp);
		ehb();
		if ((nextstamp - (unsigned long)read_c0_count())
			> (unsigned long)LONG_MAX)
				goto repeat;
	}
}


irqreturn_t c0_compare_interrupt(int irq, void *dev_id)
{
	int cpu = smp_processor_id();

	/* If we're running SMTC, we've got MIPS MT and therefore MIPS32R2 */
	handle_perf_irq(1);

	if (read_c0_cause() & (1 << 30)) {
		/* Clear Count/Compare Interrupt */
		write_c0_compare(read_c0_compare());
		smtc_distribute_timer(cpu_data[cpu].vpe_id);
	}
	return IRQ_HANDLED;
}


int __cpuinit smtc_clockevent_init(void)
{
	uint64_t mips_freq = mips_hpt_frequency;
	unsigned int cpu = smp_processor_id();
	struct clock_event_device *cd;
	unsigned int irq;
	int i;
	int j;

	if (!cpu_has_counter || !mips_hpt_frequency)
		return -ENXIO;
	if (cpu == 0) {
		for (i = 0; i < num_possible_cpus(); i++) {
			smtc_nextinvpe[i] = 0;
			for (j = 0; j < num_possible_cpus(); j++)
				smtc_nexttime[i][j] = 0L;
		}
		/*
		 * SMTC also can't have the usablility test
		 * run by secondary TCs once Compare is in use.
		 */
		if (!c0_compare_int_usable())
			return -ENXIO;
	}

	/*
	 * With vectored interrupts things are getting platform specific.
	 * get_c0_compare_int is a hook to allow a platform to return the
	 * interrupt number of it's liking.
	 */
	irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
	if (get_c0_compare_int)
		irq = get_c0_compare_int();

	cd = &per_cpu(mips_clockevent_device, cpu);

	cd->name		= "MIPS";
	cd->features		= CLOCK_EVT_FEAT_ONESHOT;

	/* Calculate the min / max delta */
	cd->mult	= div_sc((unsigned long) mips_freq, NSEC_PER_SEC, 32);
	cd->shift		= 32;
	cd->max_delta_ns	= clockevent_delta2ns(0x7fffffff, cd);
	cd->min_delta_ns	= clockevent_delta2ns(0x300, cd);

	cd->rating		= 300;
	cd->irq			= irq;
	cd->cpumask		= cpumask_of(cpu);
	cd->set_next_event	= mips_next_event;
	cd->set_mode		= mips_set_clock_mode;
	cd->event_handler	= mips_event_handler;

	clockevents_register_device(cd);

	/*
	 * On SMTC we only want to do the data structure
	 * initialization and IRQ setup once.
	 */
	if (cpu)
		return 0;
	/*
	 * And we need the hwmask associated with the c0_compare
	 * vector to be initialized.
	 */
	irq_hwmask[irq] = (0x100 << cp0_compare_irq);
	if (cp0_timer_irq_installed)
		return 0;

	cp0_timer_irq_installed = 1;

	setup_irq(irq, &c0_compare_irqaction);

	return 0;
}
Commit	Line	Data
8531a35e KK	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 2007 MIPS Technologies, Inc.
	7	* Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org>
	8	* Copyright (C) 2008 Kevin D. Kissell, Paralogos sarl
	9	*/
	10	#include <linux/clockchips.h>
	11	#include <linux/interrupt.h>
	12	#include <linux/percpu.h>
631330f5	13	#include <linux/smp.h>
8531a35e KK	14
	15	#include <asm/smtc_ipi.h>
	16	#include <asm/time.h>
	17	#include <asm/cevt-r4k.h>
	18
	19	/*
	20	* Variant clock event timer support for SMTC on MIPS 34K, 1004K
	21	* or other MIPS MT cores.
	22	*
	23	* Notes on SMTC Support:
	24	*
	25	* SMTC has multiple microthread TCs pretending to be Linux CPUs.
	26	* But there's only one Count/Compare pair per VPE, and Compare
	27	* interrupts are taken opportunisitically by available TCs
	28	* bound to the VPE with the Count register. The new timer
	29	* framework provides for global broadcasts, but we really
	30	* want VPE-level multicasts for best behavior. So instead
	31	* of invoking the high-level clock-event broadcast code,
	32	* this version of SMTC support uses the historical SMTC
	33	* multicast mechanisms "under the hood", appearing to the
	34	* generic clock layer as if the interrupts are per-CPU.
	35	*
	36	* The approach taken here is to maintain a set of NR_CPUS
	37	* virtual timers, and track which "CPU" needs to be alerted
	38	* at each event.
	39	*
	40	* It's unlikely that we'll see a MIPS MT core with more than
	41	* 2 VPEs, but we know that we won't need to handle more
	42	* VPEs than we have "CPUs". So NCPUs arrays of NCPUs elements
	43	* is always going to be overkill, but always going to be enough.
	44	*/
	45
	46	unsigned long smtc_nexttime[NR_CPUS][NR_CPUS];
	47	static int smtc_nextinvpe[NR_CPUS];
	48
	49	/*
	50	* Timestamps stored are absolute values to be programmed
	51	* into Count register. Valid timestamps will never be zero.
	52	* If a Zero Count value is actually calculated, it is converted
	53	* to be a 1, which will introduce 1 or two CPU cycles of error
	54	* roughly once every four billion events, which at 1000 HZ means
	55	* about once every 50 days. If that's actually a problem, one
	56	* could alternate squashing 0 to 1 and to -1.
	57	*/
	58
	59	#define MAKEVALID(x) (((x) == 0L) ? 1L : (x))
	60	#define ISVALID(x) ((x) != 0L)
	61
	62	/*
	63	* Time comparison is subtle, as it's really truncated
	64	* modular arithmetic.
	65	*/
	66
	67	#define IS_SOONER(a, b, reference) \
	68	(((a) - (unsigned long)(reference)) < ((b) - (unsigned long)(reference)))
	69
	70	/*
	71	* CATCHUP_INCREMENT, used when the function falls behind the counter.
	72	* Could be an increasing function instead of a constant;
	73	*/
	74
	75	#define CATCHUP_INCREMENT 64
	76
	77	static int mips_next_event(unsigned long delta,
78	struct clock_event_device *evt)
79	{
80	unsigned long flags;
81	unsigned int mtflags;
82	unsigned long timestamp, reference, previous;
83	unsigned long nextcomp = 0L;
84	int vpe = current_cpu_data.vpe_id;
85	int cpu = smp_processor_id();
86	local_irq_save(flags);
87	mtflags = dmt();
88
89	/*
90	* Maintain the per-TC virtual timer
91	* and program the per-VPE shared Count register
92	* as appropriate here...
93	*/
94	reference = (unsigned long)read_c0_count();
95	timestamp = MAKEVALID(reference + delta);
96	/*
97	* To really model the clock, we have to catch the case
98	* where the current next-in-VPE timestamp is the old
99	* timestamp for the calling CPE, but the new value is
100	* in fact later. In that case, we have to do a full
101	* scan and discover the new next-in-VPE CPU id and
102	* timestamp.
103	*/
104	previous = smtc_nexttime[vpe][cpu];
105	if (cpu == smtc_nextinvpe[vpe] && ISVALID(previous)
106	&& IS_SOONER(previous, timestamp, reference)) {
107	int i;
108	int soonest = cpu;
109
110	/*
111	* Update timestamp array here, so that new
112	* value gets considered along with those of
113	* other virtual CPUs on the VPE.
114	*/
115	smtc_nexttime[vpe][cpu] = timestamp;
116	for_each_online_cpu(i) {
117	if (ISVALID(smtc_nexttime[vpe][i])
118	&& IS_SOONER(smtc_nexttime[vpe][i],
119	smtc_nexttime[vpe][soonest], reference)) {
120	soonest = i;
121	}
122	}
123	smtc_nextinvpe[vpe] = soonest;
124	nextcomp = smtc_nexttime[vpe][soonest];
125	/*
126	* Otherwise, we don't have to process the whole array rank,
127	* we just have to see if the event horizon has gotten closer.
128	*/
129	} else {
130	if (!ISVALID(smtc_nexttime[vpe][smtc_nextinvpe[vpe]]) \|\|
131	IS_SOONER(timestamp,
132	smtc_nexttime[vpe][smtc_nextinvpe[vpe]], reference)) {
133	smtc_nextinvpe[vpe] = cpu;
134	nextcomp = timestamp;
135	}
136	/*
137	* Since next-in-VPE may me the same as the executing
138	* virtual CPU, we update the array after checking
139	* its value.
140	*/
141	smtc_nexttime[vpe][cpu] = timestamp;
142	}
143
144	/*
145	* It may be that, in fact, we don't need to update Compare,
146	* but if we do, we want to make sure we didn't fall into
147	* a crack just behind Count.
148	*/
149	if (ISVALID(nextcomp)) {
150	write_c0_compare(nextcomp);
151	ehb();
152	/*
153	* We never return an error, we just make sure
154	* that we trigger the handlers as quickly as
155	* we can if we fell behind.
156	*/
157	while ((nextcomp - (unsigned long)read_c0_count())
158	> (unsigned long)LONG_MAX) {
159	nextcomp += CATCHUP_INCREMENT;
160	write_c0_compare(nextcomp);
161	ehb();
162	}
163	}
164	emt(mtflags);
165	local_irq_restore(flags);
166	return 0;
167	}
168
169
170	void smtc_distribute_timer(int vpe)
171	{
172	unsigned long flags;
173	unsigned int mtflags;
174	int cpu;
175	struct clock_event_device *cd;
176	unsigned long nextstamp = 0L;
177	unsigned long reference;
178
179
180	repeat:
181	for_each_online_cpu(cpu) {
182	/*
183	* Find virtual CPUs within the current VPE who have
184	* unserviced timer requests whose time is now past.
185	*/
186	local_irq_save(flags);
187	mtflags = dmt();
188	if (cpu_data[cpu].vpe_id == vpe &&
189	ISVALID(smtc_nexttime[vpe][cpu])) {
190	reference = (unsigned long)read_c0_count();
191	if ((smtc_nexttime[vpe][cpu] - reference)
192	> (unsigned long)LONG_MAX) {
193	smtc_nexttime[vpe][cpu] = 0L;
194	emt(mtflags);
195	local_irq_restore(flags);
196	/*
197	* We don't send IPIs to ourself.
198	*/
199	if (cpu != smp_processor_id()) {
200	smtc_send_ipi(cpu, SMTC_CLOCK_TICK, 0);
201	} else {
202	cd = &per_cpu(mips_clockevent_device, cpu);
203	cd->event_handler(cd);
204	}
205	} else {
206	/* Local to VPE but Valid Time not yet reached. */
207	if (!ISVALID(nextstamp) \|\|
208	IS_SOONER(smtc_nexttime[vpe][cpu], nextstamp,
209	reference)) {
210	smtc_nextinvpe[vpe] = cpu;
211	nextstamp = smtc_nexttime[vpe][cpu];
212	}
213	emt(mtflags);
214	local_irq_restore(flags);
215	}
216	} else {
217	emt(mtflags);
218	local_irq_restore(flags);
219
220	}
221	}
222	/* Reprogram for interrupt at next soonest timestamp for VPE */
223	if (ISVALID(nextstamp)) {
224	write_c0_compare(nextstamp);
225	ehb();
226	if ((nextstamp - (unsigned long)read_c0_count())
227	> (unsigned long)LONG_MAX)
228	goto repeat;
229	}
230	}
231
232
233	irqreturn_t c0_compare_interrupt(int irq, void *dev_id)
234	{
235	int cpu = smp_processor_id();
236
237	/* If we're running SMTC, we've got MIPS MT and therefore MIPS32R2 */
238	handle_perf_irq(1);
239
240	if (read_c0_cause() & (1 << 30)) {
241	/* Clear Count/Compare Interrupt */
242	write_c0_compare(read_c0_compare());
243	smtc_distribute_timer(cpu_data[cpu].vpe_id);
244	}
245	return IRQ_HANDLED;
246	}
247
248
bcf11801	249	int __cpuinit smtc_clockevent_init(void)
8531a35e KK	250	{
	251	uint64_t mips_freq = mips_hpt_frequency;
	252	unsigned int cpu = smp_processor_id();
	253	struct clock_event_device *cd;
	254	unsigned int irq;
	255	int i;
	256	int j;
	257
	258	if (!cpu_has_counter \|\| !mips_hpt_frequency)
	259	return -ENXIO;
	260	if (cpu == 0) {
	261	for (i = 0; i < num_possible_cpus(); i++) {
	262	smtc_nextinvpe[i] = 0;
	263	for (j = 0; j < num_possible_cpus(); j++)
	264	smtc_nexttime[i][j] = 0L;
	265	}
	266	/*
	267	* SMTC also can't have the usablility test
	268	* run by secondary TCs once Compare is in use.
	269	*/
	270	if (!c0_compare_int_usable())
	271	return -ENXIO;
	272	}
	273
	274	/*
	275	* With vectored interrupts things are getting platform specific.
	276	* get_c0_compare_int is a hook to allow a platform to return the
	277	* interrupt number of it's liking.
	278	*/
	279	irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
	280	if (get_c0_compare_int)
	281	irq = get_c0_compare_int();
	282
	283	cd = &per_cpu(mips_clockevent_device, cpu);
	284
	285	cd->name = "MIPS";
	286	cd->features = CLOCK_EVT_FEAT_ONESHOT;
	287
	288	/* Calculate the min / max delta */
	289	cd->mult = div_sc((unsigned long) mips_freq, NSEC_PER_SEC, 32);
	290	cd->shift = 32;
	291	cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd);
	292	cd->min_delta_ns = clockevent_delta2ns(0x300, cd);
	293
	294	cd->rating = 300;
	295	cd->irq = irq;
320ab2b0	296	cd->cpumask = cpumask_of(cpu);
8531a35e KK	297	cd->set_next_event = mips_next_event;
	298	cd->set_mode = mips_set_clock_mode;
	299	cd->event_handler = mips_event_handler;
	300
	301	clockevents_register_device(cd);
	302
	303	/*
	304	* On SMTC we only want to do the data structure
	305	* initialization and IRQ setup once.
	306	*/
	307	if (cpu)
	308	return 0;
	309	/*
	310	* And we need the hwmask associated with the c0_compare
	311	* vector to be initialized.
	312	*/
	313	irq_hwmask[irq] = (0x100 << cp0_compare_irq);
	314	if (cp0_timer_irq_installed)
	315	return 0;
	316
	317	cp0_timer_irq_installed = 1;
	318
	319	setup_irq(irq, &c0_compare_irqaction);
	320
	321	return 0;
	322	}