Commit | Line | Data |
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42f77542 RB |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 2007 MIPS Technologies, Inc. | |
7 | * Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org> | |
8 | */ | |
9 | #include <linux/clockchips.h> | |
10 | #include <linux/interrupt.h> | |
11 | #include <linux/percpu.h> | |
631330f5 | 12 | #include <linux/smp.h> |
ca4d3e67 | 13 | #include <linux/irq.h> |
42f77542 RB |
14 | |
15 | #include <asm/time.h> | |
8531a35e KK |
16 | #include <asm/cevt-r4k.h> |
17 | ||
42f77542 | 18 | static int mips_next_event(unsigned long delta, |
70342287 | 19 | struct clock_event_device *evt) |
42f77542 RB |
20 | { |
21 | unsigned int cnt; | |
22 | int res; | |
23 | ||
42f77542 RB |
24 | cnt = read_c0_count(); |
25 | cnt += delta; | |
26 | write_c0_compare(cnt); | |
5878fc93 | 27 | res = ((int)(read_c0_count() - cnt) >= 0) ? -ETIME : 0; |
42f77542 RB |
28 | return res; |
29 | } | |
30 | ||
8531a35e KK |
31 | void mips_set_clock_mode(enum clock_event_mode mode, |
32 | struct clock_event_device *evt) | |
42f77542 RB |
33 | { |
34 | /* Nothing to do ... */ | |
35 | } | |
36 | ||
8531a35e KK |
37 | DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device); |
38 | int cp0_timer_irq_installed; | |
42f77542 | 39 | |
19971c0b JH |
40 | /* |
41 | * Possibly handle a performance counter interrupt. | |
42 | * Return true if the timer interrupt should not be checked | |
43 | */ | |
44 | static inline int handle_perf_irq(int r2) | |
45 | { | |
46 | /* | |
47 | * The performance counter overflow interrupt may be shared with the | |
48 | * timer interrupt (cp0_perfcount_irq < 0). If it is and a | |
49 | * performance counter has overflowed (perf_irq() == IRQ_HANDLED) | |
50 | * and we can't reliably determine if a counter interrupt has also | |
51 | * happened (!r2) then don't check for a timer interrupt. | |
52 | */ | |
53 | return (cp0_perfcount_irq < 0) && | |
54 | perf_irq() == IRQ_HANDLED && | |
55 | !r2; | |
56 | } | |
57 | ||
8531a35e | 58 | irqreturn_t c0_compare_interrupt(int irq, void *dev_id) |
42f77542 | 59 | { |
54dac950 | 60 | const int r2 = cpu_has_mips_r2_r6; |
42f77542 RB |
61 | struct clock_event_device *cd; |
62 | int cpu = smp_processor_id(); | |
63 | ||
64 | /* | |
65 | * Suckage alert: | |
66 | * Before R2 of the architecture there was no way to see if a | |
67 | * performance counter interrupt was pending, so we have to run | |
68 | * the performance counter interrupt handler anyway. | |
69 | */ | |
70 | if (handle_perf_irq(r2)) | |
71 | goto out; | |
72 | ||
73 | /* | |
70342287 | 74 | * The same applies to performance counter interrupts. But with the |
42f77542 RB |
75 | * above we now know that the reason we got here must be a timer |
76 | * interrupt. Being the paranoiacs we are we check anyway. | |
77 | */ | |
3ba5040a | 78 | if (!r2 || (read_c0_cause() & CAUSEF_TI)) { |
8531a35e KK |
79 | /* Clear Count/Compare Interrupt */ |
80 | write_c0_compare(read_c0_compare()); | |
42f77542 RB |
81 | cd = &per_cpu(mips_clockevent_device, cpu); |
82 | cd->event_handler(cd); | |
7dfe8198 JH |
83 | } else { |
84 | return IRQ_NONE; | |
42f77542 RB |
85 | } |
86 | ||
87 | out: | |
88 | return IRQ_HANDLED; | |
89 | } | |
90 | ||
8531a35e | 91 | struct irqaction c0_compare_irqaction = { |
42f77542 | 92 | .handler = c0_compare_interrupt, |
7dfe8198 JH |
93 | /* |
94 | * IRQF_SHARED: The timer interrupt may be shared with other interrupts | |
95 | * such as perf counter and FDC interrupts. | |
96 | */ | |
97 | .flags = IRQF_PERCPU | IRQF_TIMER | IRQF_SHARED, | |
42f77542 RB |
98 | .name = "timer", |
99 | }; | |
100 | ||
42f77542 | 101 | |
8531a35e | 102 | void mips_event_handler(struct clock_event_device *dev) |
42f77542 RB |
103 | { |
104 | } | |
105 | ||
106 | /* | |
107 | * FIXME: This doesn't hold for the relocated E9000 compare interrupt. | |
108 | */ | |
109 | static int c0_compare_int_pending(void) | |
110 | { | |
ae58d882 | 111 | /* When cpu_has_mips_r2, this checks Cause.TI instead of Cause.IP7 */ |
010c108d | 112 | return (read_c0_cause() >> cp0_compare_irq_shift) & (1ul << CAUSEB_IP); |
42f77542 RB |
113 | } |
114 | ||
8531a35e KK |
115 | /* |
116 | * Compare interrupt can be routed and latched outside the core, | |
4f1a1eb5 AC |
117 | * so wait up to worst case number of cycle counter ticks for timer interrupt |
118 | * changes to propagate to the cause register. | |
8531a35e | 119 | */ |
4f1a1eb5 | 120 | #define COMPARE_INT_SEEN_TICKS 50 |
8531a35e KK |
121 | |
122 | int c0_compare_int_usable(void) | |
42f77542 | 123 | { |
3a6c43a7 | 124 | unsigned int delta; |
42f77542 RB |
125 | unsigned int cnt; |
126 | ||
9843b030 SL |
127 | #ifdef CONFIG_KVM_GUEST |
128 | return 1; | |
129 | #endif | |
130 | ||
42f77542 | 131 | /* |
70342287 | 132 | * IP7 already pending? Try to clear it by acking the timer. |
42f77542 RB |
133 | */ |
134 | if (c0_compare_int_pending()) { | |
4f1a1eb5 AC |
135 | cnt = read_c0_count(); |
136 | write_c0_compare(cnt); | |
137 | back_to_back_c0_hazard(); | |
138 | while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS)) | |
139 | if (!c0_compare_int_pending()) | |
140 | break; | |
42f77542 RB |
141 | if (c0_compare_int_pending()) |
142 | return 0; | |
143 | } | |
144 | ||
3a6c43a7 AN |
145 | for (delta = 0x10; delta <= 0x400000; delta <<= 1) { |
146 | cnt = read_c0_count(); | |
147 | cnt += delta; | |
148 | write_c0_compare(cnt); | |
4f1a1eb5 | 149 | back_to_back_c0_hazard(); |
3a6c43a7 AN |
150 | if ((int)(read_c0_count() - cnt) < 0) |
151 | break; | |
152 | /* increase delta if the timer was already expired */ | |
153 | } | |
42f77542 | 154 | |
c637fecb | 155 | while ((int)(read_c0_count() - cnt) <= 0) |
42f77542 RB |
156 | ; /* Wait for expiry */ |
157 | ||
4f1a1eb5 AC |
158 | while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS)) |
159 | if (c0_compare_int_pending()) | |
160 | break; | |
42f77542 RB |
161 | if (!c0_compare_int_pending()) |
162 | return 0; | |
4f1a1eb5 AC |
163 | cnt = read_c0_count(); |
164 | write_c0_compare(cnt); | |
165 | back_to_back_c0_hazard(); | |
166 | while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS)) | |
167 | if (!c0_compare_int_pending()) | |
168 | break; | |
42f77542 RB |
169 | if (c0_compare_int_pending()) |
170 | return 0; | |
171 | ||
172 | /* | |
173 | * Feels like a real count / compare timer. | |
174 | */ | |
175 | return 1; | |
176 | } | |
177 | ||
078a55fc | 178 | int r4k_clockevent_init(void) |
42f77542 | 179 | { |
42f77542 RB |
180 | unsigned int cpu = smp_processor_id(); |
181 | struct clock_event_device *cd; | |
38760d40 | 182 | unsigned int irq; |
42f77542 | 183 | |
22df3f53 | 184 | if (!cpu_has_counter || !mips_hpt_frequency) |
5aa85c9f | 185 | return -ENXIO; |
42f77542 | 186 | |
42f77542 | 187 | if (!c0_compare_int_usable()) |
5aa85c9f | 188 | return -ENXIO; |
42f77542 | 189 | |
38760d40 RB |
190 | /* |
191 | * With vectored interrupts things are getting platform specific. | |
192 | * get_c0_compare_int is a hook to allow a platform to return the | |
193 | * interrupt number of it's liking. | |
194 | */ | |
195 | irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; | |
196 | if (get_c0_compare_int) | |
197 | irq = get_c0_compare_int(); | |
198 | ||
42f77542 RB |
199 | cd = &per_cpu(mips_clockevent_device, cpu); |
200 | ||
201 | cd->name = "MIPS"; | |
5977d682 | 202 | cd->features = CLOCK_EVT_FEAT_ONESHOT | |
d8107efd PB |
203 | CLOCK_EVT_FEAT_C3STOP | |
204 | CLOCK_EVT_FEAT_PERCPU; | |
42f77542 | 205 | |
4d2b1125 DD |
206 | clockevent_set_clock(cd, mips_hpt_frequency); |
207 | ||
42f77542 | 208 | /* Calculate the min / max delta */ |
42f77542 RB |
209 | cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd); |
210 | cd->min_delta_ns = clockevent_delta2ns(0x300, cd); | |
211 | ||
212 | cd->rating = 300; | |
213 | cd->irq = irq; | |
320ab2b0 | 214 | cd->cpumask = cpumask_of(cpu); |
42f77542 | 215 | cd->set_next_event = mips_next_event; |
8531a35e | 216 | cd->set_mode = mips_set_clock_mode; |
42f77542 RB |
217 | cd->event_handler = mips_event_handler; |
218 | ||
219 | clockevents_register_device(cd); | |
220 | ||
aea68639 | 221 | if (cp0_timer_irq_installed) |
5aa85c9f | 222 | return 0; |
38760d40 RB |
223 | |
224 | cp0_timer_irq_installed = 1; | |
225 | ||
38760d40 | 226 | setup_irq(irq, &c0_compare_irqaction); |
5aa85c9f RB |
227 | |
228 | return 0; | |
42f77542 | 229 | } |
8531a35e | 230 |