[linux-block.git] / arch / mips / kernel / cevt-bcm1480.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright (C) 2000,2001,2004 Broadcom Corporation
 */
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/percpu.h>
#include <linux/smp.h>
#include <linux/irq.h>

#include <asm/addrspace.h>
#include <asm/io.h>
#include <asm/time.h>

#include <asm/sibyte/bcm1480_regs.h>
#include <asm/sibyte/sb1250_regs.h>
#include <asm/sibyte/bcm1480_int.h>
#include <asm/sibyte/bcm1480_scd.h>

#include <asm/sibyte/sb1250.h>

#define IMR_IP2_VAL	K_BCM1480_INT_MAP_I0
#define IMR_IP3_VAL	K_BCM1480_INT_MAP_I1
#define IMR_IP4_VAL	K_BCM1480_INT_MAP_I2

/*
 * The general purpose timer ticks at 1MHz independent if
 * the rest of the system
 */

static int sibyte_set_periodic(struct clock_event_device *evt)
{
	unsigned int cpu = smp_processor_id();
	void __iomem *cfg, *init;

	cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
	init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));

	__raw_writeq(0, cfg);
	__raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, init);
	__raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, cfg);
	return 0;
}

static int sibyte_shutdown(struct clock_event_device *evt)
{
	unsigned int cpu = smp_processor_id();
	void __iomem *cfg;

	cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));

	/* Stop the timer until we actually program a shot */
	__raw_writeq(0, cfg);
	return 0;
}

static int sibyte_next_event(unsigned long delta, struct clock_event_device *cd)
{
	unsigned int cpu = smp_processor_id();
	void __iomem *cfg, *init;

	cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
	init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));

	__raw_writeq(0, cfg);
	__raw_writeq(delta - 1, init);
	__raw_writeq(M_SCD_TIMER_ENABLE, cfg);

	return 0;
}

static irqreturn_t sibyte_counter_handler(int irq, void *dev_id)
{
	unsigned int cpu = smp_processor_id();
	struct clock_event_device *cd = dev_id;
	void __iomem *cfg;
	unsigned long tmode;

	if (clockevent_state_periodic(cd))
		tmode = M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS;
	else
		tmode = 0;

	/* ACK interrupt */
	cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
	____raw_writeq(tmode, cfg);

	cd->event_handler(cd);

	return IRQ_HANDLED;
}

static DEFINE_PER_CPU(struct clock_event_device, sibyte_hpt_clockevent);
static DEFINE_PER_CPU(struct irqaction, sibyte_hpt_irqaction);
static DEFINE_PER_CPU(char [18], sibyte_hpt_name);

void sb1480_clockevent_init(void)
{
	unsigned int cpu = smp_processor_id();
	unsigned int irq = K_BCM1480_INT_TIMER_0 + cpu;
	struct irqaction *action = &per_cpu(sibyte_hpt_irqaction, cpu);
	struct clock_event_device *cd = &per_cpu(sibyte_hpt_clockevent, cpu);
	unsigned char *name = per_cpu(sibyte_hpt_name, cpu);

	BUG_ON(cpu > 3);	/* Only have 4 general purpose timers */

	sprintf(name, "bcm1480-counter-%d", cpu);
	cd->name		= name;
	cd->features		= CLOCK_EVT_FEAT_PERIODIC |
				  CLOCK_EVT_FEAT_ONESHOT;
	clockevent_set_clock(cd, V_SCD_TIMER_FREQ);
	cd->max_delta_ns	= clockevent_delta2ns(0x7fffff, cd);
	cd->max_delta_ticks	= 0x7fffff;
	cd->min_delta_ns	= clockevent_delta2ns(2, cd);
	cd->min_delta_ticks	= 2;
	cd->rating		= 200;
	cd->irq			= irq;
	cd->cpumask		= cpumask_of(cpu);
	cd->set_next_event	= sibyte_next_event;
	cd->set_state_shutdown	= sibyte_shutdown;
	cd->set_state_periodic	= sibyte_set_periodic;
	cd->set_state_oneshot	= sibyte_shutdown;
	clockevents_register_device(cd);

	bcm1480_mask_irq(cpu, irq);

	/*
	 * Map the timer interrupt to IP[4] of this cpu
	 */
	__raw_writeq(IMR_IP4_VAL,
		     IOADDR(A_BCM1480_IMR_REGISTER(cpu,
			R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + (irq << 3)));

	bcm1480_unmask_irq(cpu, irq);

	action->handler = sibyte_counter_handler;
	action->flags	= IRQF_PERCPU | IRQF_TIMER;
	action->name	= name;
	action->dev_id	= cd;

	irq_set_affinity(irq, cpumask_of(cpu));
	setup_irq(irq, action);
}
Commit	Line	Data
1a59d1b8	1	// SPDX-License-Identifier: GPL-2.0-or-later
217dd11e RB	2	/*
217dd11e RB	3	* Copyright (C) 2000,2001,2004 Broadcom Corporation
217dd11e RB	4	*/
	5	#include <linux/clockchips.h>
	6	#include <linux/interrupt.h>
	7	#include <linux/percpu.h>
631330f5	8	#include <linux/smp.h>
ca4d3e67	9	#include <linux/irq.h>
217dd11e RB	10
	11	#include <asm/addrspace.h>
	12	#include <asm/io.h>
	13	#include <asm/time.h>
	14
	15	#include <asm/sibyte/bcm1480_regs.h>
	16	#include <asm/sibyte/sb1250_regs.h>
	17	#include <asm/sibyte/bcm1480_int.h>
	18	#include <asm/sibyte/bcm1480_scd.h>
	19
	20	#include <asm/sibyte/sb1250.h>
	21
	22	#define IMR_IP2_VAL K_BCM1480_INT_MAP_I0
	23	#define IMR_IP3_VAL K_BCM1480_INT_MAP_I1
	24	#define IMR_IP4_VAL K_BCM1480_INT_MAP_I2
	25
	26	/*
	27	* The general purpose timer ticks at 1MHz independent if
	28	* the rest of the system
	29	*/
1edf907a VK	30
1edf907a VK	31	static int sibyte_set_periodic(struct clock_event_device *evt)
217dd11e RB	32	{
	33	unsigned int cpu = smp_processor_id();
	34	void __iomem cfg, init;
	35
	36	cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
	37	init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
	38
1edf907a VK	39	__raw_writeq(0, cfg);
	40	__raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, init);
	41	__raw_writeq(M_SCD_TIMER_ENABLE \| M_SCD_TIMER_MODE_CONTINUOUS, cfg);
	42	return 0;
	43	}
	44
	45	static int sibyte_shutdown(struct clock_event_device *evt)
	46	{
	47	unsigned int cpu = smp_processor_id();
	48	void __iomem *cfg;
	49
	50	cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
	51
	52	/* Stop the timer until we actually program a shot */
	53	__raw_writeq(0, cfg);
	54	return 0;
217dd11e RB	55	}
	56
	57	static int sibyte_next_event(unsigned long delta, struct clock_event_device *cd)
	58	{
	59	unsigned int cpu = smp_processor_id();
	60	void __iomem cfg, init;
	61
	62	cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
	63	init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
	64
8dfa741f	65	__raw_writeq(0, cfg);
217dd11e RB	66	__raw_writeq(delta - 1, init);
	67	__raw_writeq(M_SCD_TIMER_ENABLE, cfg);
	68
	69	return 0;
	70	}
	71
	72	static irqreturn_t sibyte_counter_handler(int irq, void *dev_id)
	73	{
	74	unsigned int cpu = smp_processor_id();
	75	struct clock_event_device *cd = dev_id;
	76	void __iomem *cfg;
	77	unsigned long tmode;
	78
1edf907a	79	if (clockevent_state_periodic(cd))
217dd11e RB	80	tmode = M_SCD_TIMER_ENABLE \| M_SCD_TIMER_MODE_CONTINUOUS;
	81	else
	82	tmode = 0;
	83
	84	/* ACK interrupt */
	85	cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
	86	____raw_writeq(tmode, cfg);
	87
	88	cd->event_handler(cd);
	89
	90	return IRQ_HANDLED;
	91	}
	92
	93	static DEFINE_PER_CPU(struct clock_event_device, sibyte_hpt_clockevent);
	94	static DEFINE_PER_CPU(struct irqaction, sibyte_hpt_irqaction);
	95	static DEFINE_PER_CPU(char [18], sibyte_hpt_name);
	96
078a55fc	97	void sb1480_clockevent_init(void)
217dd11e RB	98	{
	99	unsigned int cpu = smp_processor_id();
	100	unsigned int irq = K_BCM1480_INT_TIMER_0 + cpu;
	101	struct irqaction *action = &per_cpu(sibyte_hpt_irqaction, cpu);
	102	struct clock_event_device *cd = &per_cpu(sibyte_hpt_clockevent, cpu);
	103	unsigned char *name = per_cpu(sibyte_hpt_name, cpu);
	104
	105	BUG_ON(cpu > 3); /* Only have 4 general purpose timers */
	106
	107	sprintf(name, "bcm1480-counter-%d", cpu);
	108	cd->name = name;
	109	cd->features = CLOCK_EVT_FEAT_PERIODIC \|
	110	CLOCK_EVT_FEAT_ONESHOT;
	111	clockevent_set_clock(cd, V_SCD_TIMER_FREQ);
	112	cd->max_delta_ns = clockevent_delta2ns(0x7fffff, cd);
e4db9253	113	cd->max_delta_ticks = 0x7fffff;
62247753	114	cd->min_delta_ns = clockevent_delta2ns(2, cd);
e4db9253	115	cd->min_delta_ticks = 2;
217dd11e RB	116	cd->rating = 200;
217dd11e RB	117	cd->irq = irq;
320ab2b0	118	cd->cpumask = cpumask_of(cpu);
217dd11e	119	cd->set_next_event = sibyte_next_event;
1edf907a VK	120	cd->set_state_shutdown = sibyte_shutdown;
	121	cd->set_state_periodic = sibyte_set_periodic;
	122	cd->set_state_oneshot = sibyte_shutdown;
217dd11e RB	123	clockevents_register_device(cd);
	124
	125	bcm1480_mask_irq(cpu, irq);
	126
	127	/*
	128	* Map the timer interrupt to IP[4] of this cpu
	129	*/
	130	__raw_writeq(IMR_IP4_VAL,
	131	IOADDR(A_BCM1480_IMR_REGISTER(cpu,
	132	R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + (irq << 3)));
	133
	134	bcm1480_unmask_irq(cpu, irq);
	135
70342287	136	action->handler = sibyte_counter_handler;
8b5690f8	137	action->flags = IRQF_PERCPU \| IRQF_TIMER;
217dd11e RB	138	action->name = name;
217dd11e RB	139	action->dev_id = cd;
07a80e49	140
0de26520	141	irq_set_affinity(irq, cpumask_of(cpu));
217dd11e RB	142	setup_irq(irq, action);
217dd11e RB	143	}