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Merge tag 'mm-hotfixes-stable-2025-07-11-16-16' of git://git.kernel.org/pub/scm/linux...
[linux-2.6-block.git] / arch / mips / include / asm / pgtable.h
CommitLineData
1da177e4
LT		 1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003 Ralf Baechle
7 */
8#ifndef _ASM_PGTABLE_H
9#define _ASM_PGTABLE_H
10
5bbea36a 11#include <linux/mm_types.h>
970d032f 12#include <linux/mmzone.h>
875d43e7 13#ifdef CONFIG_32BIT
1da177e4
LT		 14#include <asm/pgtable-32.h>
15#endif
875d43e7 16#ifdef CONFIG_64BIT
1da177e4
LT		 17#include <asm/pgtable-64.h>
18#endif
19
82f4f66d 20#include <asm/cmpxchg.h>
f10fae02 21#include <asm/io.h>
1da177e4 22#include <asm/pgtable-bits.h>
446f062b 23#include <asm/cpu-features.h>
1da177e4 24
8c65b4a6
TS		 25struct mm_struct;
26struct vm_area_struct;
27
41bb1a9b
TB		 28#define PAGE_SHARED vm_get_page_prot(VM_READ|VM_WRITE|VM_SHARED)
29
1da177e4 30#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \
35133692 31 _PAGE_GLOBAL | _page_cachable_default)
e2a9e5ad
PB		 32#define PAGE_KERNEL_NC __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \
33 _PAGE_GLOBAL | _CACHE_CACHABLE_NONCOHERENT)
1da177e4
LT		 34#define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \
35 __WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED)
36
37/*
6dd9344c
DD		 38 * If _PAGE_NO_EXEC is not defined, we can't do page protection for
39 * execute, and consider it to be the same as read. Also, write
40 * permissions imply read permissions. This is the closest we can get
41 * by reasonable means..
1da177e4 42 */
1da177e4 43
35133692 44extern unsigned long _page_cachable_default;
a2fa4ced 45extern void __update_cache(unsigned long address, pte_t pte);
1da177e4
LT		 46
47/*
48 * ZERO_PAGE is a global shared page that is always zero; used
49 * for zero-mapped memory areas etc..
50 */
51
52extern unsigned long empty_zero_page;
53extern unsigned long zero_page_mask;
54
55#define ZERO_PAGE(vaddr) \
99e3b942 56 (virt_to_page((void *)(empty_zero_page + (((unsigned long)(vaddr)) & zero_page_mask))))
816422ad 57#define __HAVE_COLOR_ZERO_PAGE
62eede62 58
1da177e4
LT		 59extern void paging_init(void);
60
61/*
62 * Conversion functions: convert a page and protection to a page entry,
63 * and a page entry and page directory to the page they refer to.
64 */
c9d06962 65#define pmd_phys(pmd) virt_to_phys((void *)pmd_val(pmd))
970d032f 66
177bd2a9
MWO		 67static inline unsigned long pmd_pfn(pmd_t pmd)
68{
15fa3e8e 69 return pmd_val(pmd) >> PFN_PTE_SHIFT;
177bd2a9
MWO		 70}
71
f69fa4c8
ZZ		 72#ifndef CONFIG_MIPS_HUGE_TLB_SUPPORT
73#define pmd_page(pmd) (pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT))
74#endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
970d032f 75
46a82b2d 76#define pmd_page_vaddr(pmd) pmd_val(pmd)
1da177e4 77
f1014d1b
MC		 78#define htw_stop() \
79do { \
cabcff9b 80 unsigned long __flags; \
ed4cbc81 81 \
461d1597 82 if (cpu_has_htw) { \
cabcff9b 83 local_irq_save(__flags); \
ed4cbc81
MC		 84 if(!raw_current_cpu_data.htw_seq++) { \
85 write_c0_pwctl(read_c0_pwctl() & \
86 ~(1 << MIPS_PWCTL_PWEN_SHIFT)); \
87 back_to_back_c0_hazard(); \
88 } \
cabcff9b 89 local_irq_restore(__flags); \
461d1597 90 } \
f1014d1b
MC		 91} while(0)
92
93#define htw_start() \
94do { \
cabcff9b 95 unsigned long __flags; \
ed4cbc81 96 \
f1014d1b 97 if (cpu_has_htw) { \
cabcff9b 98 local_irq_save(__flags); \
ed4cbc81
MC		 99 if (!--raw_current_cpu_data.htw_seq) { \
100 write_c0_pwctl(read_c0_pwctl() | \
101 (1 << MIPS_PWCTL_PWEN_SHIFT)); \
102 back_to_back_c0_hazard(); \
103 } \
cabcff9b 104 local_irq_restore(__flags); \
f1014d1b
MC		 105 } \
106} while(0)
107
34adb28d 108#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
6e953891 109
7b2cb64f
PB		 110#ifdef CONFIG_XPA
111# define pte_none(pte) (!(((pte).pte_high) & ~_PAGE_GLOBAL))
112#else
113# define pte_none(pte) (!(((pte).pte_low | (pte).pte_high) & ~_PAGE_GLOBAL))
114#endif
115
6e953891 116#define pte_present(pte) ((pte).pte_low & _PAGE_PRESENT)
37d22a0d 117#define pte_no_exec(pte) ((pte).pte_low & _PAGE_NO_EXEC)
6e953891 118
1da177e4
LT		 119static inline void set_pte(pte_t *ptep, pte_t pte)
120{
121 ptep->pte_high = pte.pte_high;
122 smp_wmb();
123 ptep->pte_low = pte.pte_low;
1da177e4 124
7b2cb64f 125#ifdef CONFIG_XPA
c5b36783 126 if (pte.pte_high & _PAGE_GLOBAL) {
7b2cb64f
PB		 127#else
128 if (pte.pte_low & _PAGE_GLOBAL) {
129#endif
1da177e4
LT		 130 pte_t *buddy = ptep_buddy(ptep);
131 /*
132 * Make sure the buddy is global too (if it's !none,
133 * it better already be global)
134 */
7b2cb64f 135 if (pte_none(*buddy)) {
97f2645f 136 if (!IS_ENABLED(CONFIG_XPA))
7b2cb64f 137 buddy->pte_low |= _PAGE_GLOBAL;
6e953891 138 buddy->pte_high |= _PAGE_GLOBAL;
7b2cb64f 139 }
1da177e4
LT		 140 }
141}
1da177e4
LT		 142
143static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
144{
6e953891
SS		 145 pte_t null = __pte(0);
146
fde3538a 147 htw_stop();
1da177e4 148 /* Preserve global status for the pair */
97f2645f 149 if (IS_ENABLED(CONFIG_XPA)) {
7b2cb64f
PB		 150 if (ptep_buddy(ptep)->pte_high & _PAGE_GLOBAL)
151 null.pte_high = _PAGE_GLOBAL;
152 } else {
153 if (ptep_buddy(ptep)->pte_low & _PAGE_GLOBAL)
154 null.pte_low = null.pte_high = _PAGE_GLOBAL;
155 }
6e953891 156
15fa3e8e 157 set_pte(ptep, null);
fde3538a 158 htw_start();
1da177e4
LT		 159}
160#else
6e953891
SS		 161
162#define pte_none(pte) (!(pte_val(pte) & ~_PAGE_GLOBAL))
163#define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
37d22a0d 164#define pte_no_exec(pte) (pte_val(pte) & _PAGE_NO_EXEC)
6e953891 165
1da177e4
LT		 166/*
167 * Certain architectures need to do special things when pte's
168 * within a page table are directly modified. Thus, the following
169 * hook is made available.
170 */
171static inline void set_pte(pte_t *ptep, pte_t pteval)
172{
173 *ptep = pteval;
54746829 174#if !defined(CONFIG_CPU_R3K_TLB)
1da177e4
LT		 175 if (pte_val(pteval) & _PAGE_GLOBAL) {
176 pte_t *buddy = ptep_buddy(ptep);
177 /*
178 * Make sure the buddy is global too (if it's !none,
179 * it better already be global)
180 */
c7e2d71d
PB		 181# if defined(CONFIG_PHYS_ADDR_T_64BIT) && !defined(CONFIG_CPU_MIPS32)
182 cmpxchg64(&buddy->pte, 0, _PAGE_GLOBAL);
183# else
82f4f66d 184 cmpxchg(&buddy->pte, 0, _PAGE_GLOBAL);
c7e2d71d 185# endif
1da177e4
LT		 186 }
187#endif
188}
1da177e4
LT		 189
190static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
191{
fde3538a 192 htw_stop();
54746829 193#if !defined(CONFIG_CPU_R3K_TLB)
1da177e4
LT		 194 /* Preserve global status for the pair */
195 if (pte_val(*ptep_buddy(ptep)) & _PAGE_GLOBAL)
15fa3e8e 196 set_pte(ptep, __pte(_PAGE_GLOBAL));
1da177e4
LT		 197 else
198#endif
15fa3e8e 199 set_pte(ptep, __pte(0));
fde3538a 200 htw_start();
1da177e4
LT		 201}
202#endif
203
15fa3e8e
MWO		 204static inline void set_ptes(struct mm_struct *mm, unsigned long addr,
205 pte_t *ptep, pte_t pte, unsigned int nr)
37d22a0d 206{
15fa3e8e
MWO		 207 unsigned int i;
208 bool do_sync = false;
37d22a0d 209
15fa3e8e
MWO		 210 for (i = 0; i < nr; i++) {
211 if (!pte_present(pte))
212 continue;
213 if (pte_present(ptep[i]) &&
214 (pte_pfn(ptep[i]) == pte_pfn(pte)))
215 continue;
216 do_sync = true;
217 }
37d22a0d 218
15fa3e8e
MWO		 219 if (do_sync)
220 __update_cache(addr, pte);
37d22a0d 221
15fa3e8e
MWO		 222 for (;;) {
223 set_pte(ptep, pte);
224 if (--nr == 0)
225 break;
226 ptep++;
227 pte = __pte(pte_val(pte) + (1UL << PFN_PTE_SHIFT));
228 }
37d22a0d 229}
15fa3e8e 230#define set_ptes set_ptes
37d22a0d 231
1da177e4 232/*
c6e8b587 233 * (pmds are folded into puds so this doesn't get actually called,
1da177e4
LT		 234 * but the define is needed for a generic inline function.)
235 */
236#define set_pmd(pmdptr, pmdval) do { *(pmdptr) = (pmdval); } while(0)
c6e8b587 237
325f8a0a 238#ifndef __PAGETABLE_PMD_FOLDED
c6e8b587
RB		 239/*
240 * (puds are folded into pgds so this doesn't get actually called,
241 * but the define is needed for a generic inline function.)
242 */
243#define set_pud(pudptr, pudval) do { *(pudptr) = (pudval); } while(0)
244#endif
1da177e4 245
5ff97472
RB		 246#define PGD_T_LOG2 (__builtin_ffs(sizeof(pgd_t)) - 1)
247#define PMD_T_LOG2 (__builtin_ffs(sizeof(pmd_t)) - 1)
248#define PTE_T_LOG2 (__builtin_ffs(sizeof(pte_t)) - 1)
1da177e4 249
9975e77d
RB		 250/*
251 * We used to declare this array with size but gcc 3.3 and older are not able
252 * to find that this expression is a constant, so the size is dropped.
253 */
254extern pgd_t swapper_pg_dir[];
1da177e4 255
78e7c5af
AK		 256/*
257 * Platform specific pte_special() and pte_mkspecial() definitions
258 * are required only when ARCH_HAS_PTE_SPECIAL is enabled.
259 */
260#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL)
261#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
262static inline int pte_special(pte_t pte)
263{
264 return pte.pte_low & _PAGE_SPECIAL;
265}
266
267static inline pte_t pte_mkspecial(pte_t pte)
268{
269 pte.pte_low |= _PAGE_SPECIAL;
270 return pte;
271}
272#else
273static inline int pte_special(pte_t pte)
274{
275 return pte_val(pte) & _PAGE_SPECIAL;
276}
277
278static inline pte_t pte_mkspecial(pte_t pte)
279{
280 pte_val(pte) |= _PAGE_SPECIAL;
281 return pte;
282}
283#endif
284#endif /* CONFIG_ARCH_HAS_PTE_SPECIAL */
285
1da177e4
LT		 286/*
287 * The following only work if pte_present() is true.
288 * Undefined behaviour if not..
289 */
34adb28d 290#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
6e953891
SS		 291static inline int pte_write(pte_t pte) { return pte.pte_low & _PAGE_WRITE; }
292static inline int pte_dirty(pte_t pte) { return pte.pte_low & _PAGE_MODIFIED; }
293static inline int pte_young(pte_t pte) { return pte.pte_low & _PAGE_ACCESSED; }
6e953891 294
1da177e4
LT		 295static inline pte_t pte_wrprotect(pte_t pte)
296{
c5b36783 297 pte.pte_low &= ~_PAGE_WRITE;
97f2645f 298 if (!IS_ENABLED(CONFIG_XPA))
7b2cb64f 299 pte.pte_low &= ~_PAGE_SILENT_WRITE;
6e953891 300 pte.pte_high &= ~_PAGE_SILENT_WRITE;
1da177e4
LT		 301 return pte;
302}
303
1da177e4
LT		 304static inline pte_t pte_mkclean(pte_t pte)
305{
c5b36783 306 pte.pte_low &= ~_PAGE_MODIFIED;
97f2645f 307 if (!IS_ENABLED(CONFIG_XPA))
7b2cb64f 308 pte.pte_low &= ~_PAGE_SILENT_WRITE;
6e953891 309 pte.pte_high &= ~_PAGE_SILENT_WRITE;
1da177e4
LT		 310 return pte;
311}
312
313static inline pte_t pte_mkold(pte_t pte)
314{
c5b36783 315 pte.pte_low &= ~_PAGE_ACCESSED;
97f2645f 316 if (!IS_ENABLED(CONFIG_XPA))
7b2cb64f 317 pte.pte_low &= ~_PAGE_SILENT_READ;
6e953891 318 pte.pte_high &= ~_PAGE_SILENT_READ;
1da177e4
LT		 319 return pte;
320}
321
2f0584f3 322static inline pte_t pte_mkwrite_novma(pte_t pte)
1da177e4 323{
6e953891 324 pte.pte_low |= _PAGE_WRITE;
7b2cb64f 325 if (pte.pte_low & _PAGE_MODIFIED) {
97f2645f 326 if (!IS_ENABLED(CONFIG_XPA))
7b2cb64f 327 pte.pte_low |= _PAGE_SILENT_WRITE;
6e953891 328 pte.pte_high |= _PAGE_SILENT_WRITE;
7b2cb64f 329 }
1da177e4
LT		 330 return pte;
331}
332
1da177e4
LT		 333static inline pte_t pte_mkdirty(pte_t pte)
334{
6e953891 335 pte.pte_low |= _PAGE_MODIFIED;
7b2cb64f 336 if (pte.pte_low & _PAGE_WRITE) {
97f2645f 337 if (!IS_ENABLED(CONFIG_XPA))
7b2cb64f 338 pte.pte_low |= _PAGE_SILENT_WRITE;
6e953891 339 pte.pte_high |= _PAGE_SILENT_WRITE;
7b2cb64f 340 }
1da177e4
LT		 341 return pte;
342}
343
344static inline pte_t pte_mkyoung(pte_t pte)
345{
6e953891 346 pte.pte_low |= _PAGE_ACCESSED;
7b2cb64f 347 if (!(pte.pte_low & _PAGE_NO_READ)) {
97f2645f 348 if (!IS_ENABLED(CONFIG_XPA))
7b2cb64f 349 pte.pte_low |= _PAGE_SILENT_READ;
6e953891 350 pte.pte_high |= _PAGE_SILENT_READ;
7b2cb64f 351 }
1da177e4
LT		 352 return pte;
353}
354#else
1da177e4
LT		 355static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; }
356static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_MODIFIED; }
357static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
1da177e4
LT		 358
359static inline pte_t pte_wrprotect(pte_t pte)
360{
361 pte_val(pte) &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE);
362 return pte;
363}
364
1da177e4
LT		 365static inline pte_t pte_mkclean(pte_t pte)
366{
77a5c593 367 pte_val(pte) &= ~(_PAGE_MODIFIED | _PAGE_SILENT_WRITE);
1da177e4
LT		 368 return pte;
369}
370
371static inline pte_t pte_mkold(pte_t pte)
372{
77a5c593 373 pte_val(pte) &= ~(_PAGE_ACCESSED | _PAGE_SILENT_READ);
1da177e4
LT		 374 return pte;
375}
376
2f0584f3 377static inline pte_t pte_mkwrite_novma(pte_t pte)
1da177e4
LT		 378{
379 pte_val(pte) |= _PAGE_WRITE;
380 if (pte_val(pte) & _PAGE_MODIFIED)
381 pte_val(pte) |= _PAGE_SILENT_WRITE;
382 return pte;
383}
384
1da177e4
LT		 385static inline pte_t pte_mkdirty(pte_t pte)
386{
2971317a 387 pte_val(pte) |= _PAGE_MODIFIED | _PAGE_SOFT_DIRTY;
1da177e4
LT		 388 if (pte_val(pte) & _PAGE_WRITE)
389 pte_val(pte) |= _PAGE_SILENT_WRITE;
390 return pte;
391}
392
393static inline pte_t pte_mkyoung(pte_t pte)
394{
395 pte_val(pte) |= _PAGE_ACCESSED;
be0c37c9
SH		 396 if (!(pte_val(pte) & _PAGE_NO_READ))
397 pte_val(pte) |= _PAGE_SILENT_READ;
1da177e4
LT		 398 return pte;
399}
dd794392 400
44bf431b
BM		 401#define pte_sw_mkyoung pte_mkyoung
402
05f9883a 403#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
dd794392
DD		 404static inline int pte_huge(pte_t pte) { return pte_val(pte) & _PAGE_HUGE; }
405
406static inline pte_t pte_mkhuge(pte_t pte)
407{
408 pte_val(pte) |= _PAGE_HUGE;
409 return pte;
410}
f69fa4c8
ZZ		 411
412#define pmd_write pmd_write
413static inline int pmd_write(pmd_t pmd)
414{
415 return !!(pmd_val(pmd) & _PAGE_WRITE);
416}
417
f69fa4c8
ZZ		 418static inline struct page *pmd_page(pmd_t pmd)
419{
420 if (pmd_val(pmd) & _PAGE_HUGE)
421 return pfn_to_page(pmd_pfn(pmd));
422
423 return pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT);
424}
05f9883a 425#endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
2971317a
GS		 426
427#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
428static inline bool pte_soft_dirty(pte_t pte)
429{
430 return pte_val(pte) & _PAGE_SOFT_DIRTY;
431}
432#define pte_swp_soft_dirty pte_soft_dirty
433
434static inline pte_t pte_mksoft_dirty(pte_t pte)
435{
436 pte_val(pte) |= _PAGE_SOFT_DIRTY;
437 return pte;
438}
439#define pte_swp_mksoft_dirty pte_mksoft_dirty
440
441static inline pte_t pte_clear_soft_dirty(pte_t pte)
442{
443 pte_val(pte) &= ~(_PAGE_SOFT_DIRTY);
444 return pte;
445}
446#define pte_swp_clear_soft_dirty pte_clear_soft_dirty
447
448#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
449
1da177e4
LT		 450#endif
451
452/*
70342287 453 * Macro to make mark a page protection value as "uncacheable". Note
1da177e4
LT		 454 * that "protection" is really a misnomer here as the protection value
455 * contains the memory attribute bits, dirty bits, and various other
456 * bits as well.
457 */
458#define pgprot_noncached pgprot_noncached
459
460static inline pgprot_t pgprot_noncached(pgprot_t _prot)
461{
462 unsigned long prot = pgprot_val(_prot);
463
464 prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED;
465
466 return __pgprot(prot);
467}
468
c4687b15
AS		 469#define pgprot_writecombine pgprot_writecombine
470
4b050ba7
MC		 471static inline pgprot_t pgprot_writecombine(pgprot_t _prot)
472{
473 unsigned long prot = pgprot_val(_prot);
474
475 /* cpu_data[0].writecombine is already shifted by _CACHE_SHIFT */
476 prot = (prot & ~_CACHE_MASK) | cpu_data[0].writecombine;
477
478 return __pgprot(prot);
479}
480
4dd7683e 481static inline void flush_tlb_fix_spurious_fault(struct vm_area_struct *vma,
99c29133
GS		 482 unsigned long address,
483 pte_t *ptep)
4dd7683e
BM		 484{
485}
486
7df67697
BM		 487#define __HAVE_ARCH_PTE_SAME
488static inline int pte_same(pte_t pte_a, pte_t pte_b)
489{
490 return pte_val(pte_a) == pte_val(pte_b);
491}
492
493#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
494static inline int ptep_set_access_flags(struct vm_area_struct *vma,
495 unsigned long address, pte_t *ptep,
496 pte_t entry, int dirty)
497{
498 if (!pte_same(*ptep, entry))
15fa3e8e 499 set_pte(ptep, entry);
7df67697
BM		 500 /*
501 * update_mmu_cache will unconditionally execute, handling both
502 * the case that the PTE changed and the spurious fault case.
503 */
504 return true;
505}
506
7b2cb64f 507#if defined(CONFIG_XPA)
1da177e4
LT		 508static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
509{
c5b36783 510 pte.pte_low &= (_PAGE_MODIFIED | _PAGE_ACCESSED | _PFNX_MASK);
77a5c593 511 pte.pte_high &= (_PFN_MASK | _CACHE_MASK);
c5b36783 512 pte.pte_low |= pgprot_val(newprot) & ~_PFNX_MASK;
6d037de9 513 pte.pte_high |= pgprot_val(newprot) & ~(_PFN_MASK | _CACHE_MASK);
1da177e4
LT		 514 return pte;
515}
7b2cb64f
PB		 516#elif defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
517static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
518{
519 pte.pte_low &= _PAGE_CHG_MASK;
520 pte.pte_high &= (_PFN_MASK | _CACHE_MASK);
521 pte.pte_low |= pgprot_val(newprot);
522 pte.pte_high |= pgprot_val(newprot) & ~(_PFN_MASK | _CACHE_MASK);
523 return pte;
524}
1da177e4
LT		 525#else
526static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
527{
273b5fa0
BM		 528 pte_val(pte) &= _PAGE_CHG_MASK;
529 pte_val(pte) |= pgprot_val(newprot) & ~_PAGE_CHG_MASK;
530 if ((pte_val(pte) & _PAGE_ACCESSED) && !(pte_val(pte) & _PAGE_NO_READ))
531 pte_val(pte) |= _PAGE_SILENT_READ;
532 return pte;
1da177e4
LT		 533}
534#endif
535
83d3b2b4 536#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
403d1338 537static inline bool pte_swp_exclusive(pte_t pte)
83d3b2b4
DH		 538{
539 return pte.pte_low & _PAGE_SWP_EXCLUSIVE;
540}
541
542static inline pte_t pte_swp_mkexclusive(pte_t pte)
543{
544 pte.pte_low |= _PAGE_SWP_EXCLUSIVE;
545 return pte;
546}
547
548static inline pte_t pte_swp_clear_exclusive(pte_t pte)
549{
550 pte.pte_low &= ~_PAGE_SWP_EXCLUSIVE;
551 return pte;
552}
553#else
403d1338 554static inline bool pte_swp_exclusive(pte_t pte)
83d3b2b4
DH		 555{
556 return pte_val(pte) & _PAGE_SWP_EXCLUSIVE;
557}
558
559static inline pte_t pte_swp_mkexclusive(pte_t pte)
560{
561 pte_val(pte) |= _PAGE_SWP_EXCLUSIVE;
562 return pte;
563}
564
565static inline pte_t pte_swp_clear_exclusive(pte_t pte)
566{
567 pte_val(pte) &= ~_PAGE_SWP_EXCLUSIVE;
568 return pte;
569}
570#endif
1da177e4
LT		 571
572extern void __update_tlb(struct vm_area_struct *vma, unsigned long address,
573 pte_t pte);
1da177e4 574
15fa3e8e
MWO		 575static inline void update_mmu_cache_range(struct vm_fault *vmf,
576 struct vm_area_struct *vma, unsigned long address,
577 pte_t *ptep, unsigned int nr)
578{
579 for (;;) {
580 pte_t pte = *ptep;
581 __update_tlb(vma, address, pte);
582 if (--nr == 0)
583 break;
584 ptep++;
585 address += PAGE_SIZE;
586 }
1da177e4 587}
15fa3e8e
MWO		 588#define update_mmu_cache(vma, address, ptep) \
589 update_mmu_cache_range(NULL, vma, address, ptep, 1)
1da177e4 590
23b1b44e
BL		 591#define update_mmu_tlb_range(vma, address, ptep, nr) \
592 update_mmu_cache_range(NULL, vma, address, ptep, nr)
7df67697 593
970d032f
RB		 594static inline void update_mmu_cache_pmd(struct vm_area_struct *vma,
595 unsigned long address, pmd_t *pmdp)
596{
597 pte_t pte = *(pte_t *)pmdp;
598
599 __update_tlb(vma, address, pte);
600}
601
d3991572
CH		 602/*
603 * Allow physical addresses to be fixed up to help 36-bit peripherals.
604 */
605#ifdef CONFIG_MIPS_FIXUP_BIGPHYS_ADDR
606phys_addr_t fixup_bigphys_addr(phys_addr_t addr, phys_addr_t size);
607int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long vaddr,
608 unsigned long pfn, unsigned long size, pgprot_t prot);
40d158e6 609#define io_remap_pfn_range io_remap_pfn_range
d3991572
CH		 610#else
611#define fixup_bigphys_addr(addr, size) (addr)
612#endif /* CONFIG_MIPS_FIXUP_BIGPHYS_ADDR */
1da177e4 613
970d032f
RB		 614#ifdef CONFIG_TRANSPARENT_HUGEPAGE
615
b6b34b2d
KS		 616/* We don't have hardware dirty/accessed bits, generic_pmdp_establish is fine.*/
617#define pmdp_establish generic_pmdp_establish
618
fd8cfd30 619#define has_transparent_hugepage has_transparent_hugepage
970d032f
RB		 620extern int has_transparent_hugepage(void);
621
622static inline int pmd_trans_huge(pmd_t pmd)
623{
624 return !!(pmd_val(pmd) & _PAGE_HUGE);
625}
626
627static inline pmd_t pmd_mkhuge(pmd_t pmd)
628{
629 pmd_val(pmd) |= _PAGE_HUGE;
630
631 return pmd;
632}
633
970d032f
RB		 634extern void set_pmd_at(struct mm_struct *mm, unsigned long addr,
635 pmd_t *pmdp, pmd_t pmd);
636
970d032f
RB		 637static inline pmd_t pmd_wrprotect(pmd_t pmd)
638{
639 pmd_val(pmd) &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE);
640 return pmd;
641}
642
2f0584f3 643static inline pmd_t pmd_mkwrite_novma(pmd_t pmd)
970d032f
RB		 644{
645 pmd_val(pmd) |= _PAGE_WRITE;
646 if (pmd_val(pmd) & _PAGE_MODIFIED)
647 pmd_val(pmd) |= _PAGE_SILENT_WRITE;
648
649 return pmd;
650}
651
533c67e6 652#define pmd_dirty pmd_dirty
970d032f
RB		 653static inline int pmd_dirty(pmd_t pmd)
654{
655 return !!(pmd_val(pmd) & _PAGE_MODIFIED);
656}
657
658static inline pmd_t pmd_mkclean(pmd_t pmd)
659{
660 pmd_val(pmd) &= ~(_PAGE_MODIFIED | _PAGE_SILENT_WRITE);
661 return pmd;
662}
663
664static inline pmd_t pmd_mkdirty(pmd_t pmd)
665{
2971317a 666 pmd_val(pmd) |= _PAGE_MODIFIED | _PAGE_SOFT_DIRTY;
970d032f
RB		 667 if (pmd_val(pmd) & _PAGE_WRITE)
668 pmd_val(pmd) |= _PAGE_SILENT_WRITE;
669
670 return pmd;
671}
672
6617da8f 673#define pmd_young pmd_young
970d032f
RB		 674static inline int pmd_young(pmd_t pmd)
675{
676 return !!(pmd_val(pmd) & _PAGE_ACCESSED);
677}
678
679static inline pmd_t pmd_mkold(pmd_t pmd)
680{
681 pmd_val(pmd) &= ~(_PAGE_ACCESSED|_PAGE_SILENT_READ);
682
683 return pmd;
684}
685
686static inline pmd_t pmd_mkyoung(pmd_t pmd)
687{
688 pmd_val(pmd) |= _PAGE_ACCESSED;
689
be0c37c9
SH		 690 if (!(pmd_val(pmd) & _PAGE_NO_READ))
691 pmd_val(pmd) |= _PAGE_SILENT_READ;
970d032f
RB		 692
693 return pmd;
694}
695
2971317a
GS		 696#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
697static inline int pmd_soft_dirty(pmd_t pmd)
698{
699 return !!(pmd_val(pmd) & _PAGE_SOFT_DIRTY);
700}
701
702static inline pmd_t pmd_mksoft_dirty(pmd_t pmd)
703{
704 pmd_val(pmd) |= _PAGE_SOFT_DIRTY;
705 return pmd;
706}
707
708static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd)
709{
710 pmd_val(pmd) &= ~(_PAGE_SOFT_DIRTY);
711 return pmd;
712}
713
714#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
715
970d032f
RB		 716static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
717{
88d02a2b 718 pmd_val(pmd) = (pmd_val(pmd) & (_PAGE_CHG_MASK | _PAGE_HUGE)) |
6d037de9 719 (pgprot_val(newprot) & ~_PAGE_CHG_MASK);
970d032f
RB		 720 return pmd;
721}
722
86ec2da0 723static inline pmd_t pmd_mkinvalid(pmd_t pmd)
970d032f
RB		 724{
725 pmd_val(pmd) &= ~(_PAGE_PRESENT | _PAGE_VALID | _PAGE_DIRTY);
726
727 return pmd;
728}
729
730/*
8809aa2d 731 * The generic version pmdp_huge_get_and_clear uses a version of pmd_clear() with a
970d032f
RB		 732 * different prototype.
733 */
8809aa2d
AK		 734#define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
735static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
736 unsigned long address, pmd_t *pmdp)
970d032f
RB		 737{
738 pmd_t old = *pmdp;
739
740 pmd_clear(pmdp);
741
742 return old;
743}
744
745#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
746
501b8104
SP		 747#ifdef _PAGE_HUGE
748#define pmd_leaf(pmd) ((pmd_val(pmd) & _PAGE_HUGE) != 0)
749#define pud_leaf(pud) ((pud_val(pud) & _PAGE_HUGE) != 0)
750#endif
751
446f062b
CH		 752#define gup_fast_permitted(start, end) (!cpu_has_dc_aliases)
753
1da177e4
LT		 754/*
755 * We provide our own get_unmapped area to cope with the virtual aliasing
756 * constraints placed on us by the cache architecture.
757 */
758#define HAVE_ARCH_UNMAPPED_AREA
d0be89f6 759#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
1da177e4 760
1da177e4 761#endif /* _ASM_PGTABLE_H */
Linux 6.x block layer and io_uring tree(s)